Merge "msmzirc : Fix the system partition index value"
diff --git a/platform/msm8909/acpuclock.c b/platform/msm8909/acpuclock.c
index 334a1f3..d483c79 100644
--- a/platform/msm8909/acpuclock.c
+++ b/platform/msm8909/acpuclock.c
@@ -39,24 +39,136 @@
void hsusb_clock_init(void)
{
+ int ret;
+ struct clk *iclk, *cclk;
+ ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_core_clk", 80000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ mdelay(20);
+
+ iclk = clk_get("usb_iface_clk");
+ cclk = clk_get("usb_core_clk");
+
+ clk_disable(iclk);
+ clk_disable(cclk);
+
+ mdelay(20);
+
+ /* Start the block reset for usb */
+ writel(1, USB_HS_BCR);
+
+ mdelay(20);
+
+ /* Take usb block out of reset */
+ writel(0, USB_HS_BCR);
+
+ mdelay(20);
+
+ ret = clk_enable(iclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_enable(cclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
}
void clock_init_mmc(uint32_t interface)
{
+ char clk_name[64];
+ int ret;
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
+ int ret;
+ char clk_name[64];
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
+ else if(freq == MMC_CLK_177MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 177770000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
+ ASSERT(0);
+ }
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret);
+ ASSERT(0);
+ }
}
/* Function to asynchronously reset CE.
@@ -64,17 +176,90 @@
*/
static void ce_async_reset(uint8_t instance)
{
+ /* Start the block reset for CE */
+ writel(1, GCC_CRYPTO_BCR);
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CRYPTO_BCR);
+
+ udelay(2);
}
void clock_ce_enable(uint8_t instance)
{
+ int ret;
+ char clk_name[64];
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ ret = clk_get_set_enable(clk_name, 160000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_src_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_core_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_ahb_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_axi_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ /* Wait for 48 * #pipes cycles.
+ * This is necessary as immediately after an access control reset (boot up)
+ * or a debug re-enable, the Crypto core sequentially clears its internal
+ * pipe key storage memory. If pipe key initialization writes are attempted
+ * during this time, they may be overwritten by the internal clearing logic.
+ */
+ udelay(1);
}
void clock_ce_disable(uint8_t instance)
{
+ struct clk *ahb_clk;
+ struct clk *cclk;
+ struct clk *axi_clk;
+ struct clk *src_clk;
+ char clk_name[64];
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ src_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ahb_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ axi_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ cclk = clk_get(clk_name);
+
+ clk_disable(ahb_clk);
+ clk_disable(axi_clk);
+ clk_disable(cclk);
+ clk_disable(src_clk);
+
+ /* Some delay for the clocks to stabalize. */
+ udelay(1);
}
void clock_config_ce(uint8_t instance)
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index bbe731c..2ba6355 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -82,6 +82,7 @@
#define SPMI_BASE 0x02000000
#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
+#define PMIC_ARB_CORE 0x200F000
#define TLMM_BASE_ADDR 0x1000000
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
@@ -109,6 +110,7 @@
/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x21024)
+#define GPLL0_MODE (CLK_CTL_BASE + 0x21000)
#define GPLL1_STATUS (CLK_CTL_BASE + 0x2001C)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
@@ -142,6 +144,12 @@
#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
+#define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x203C)
+#define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2044)
+#define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x2048)
+#define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x204C)
+#define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x2050)
+#define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x2054)
/* USB */
#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
@@ -238,4 +246,6 @@
#define BOOT_CONFIG_OFFSET 0x0000602C
#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
+/* EBI2 */
+#define TLMM_EBI2_EMMC_GPIO_CFG (TLMM_BASE_ADDR + 0x00111000)
#endif
diff --git a/platform/msm8909/msm8909-clock.c b/platform/msm8909/msm8909-clock.c
index a2af96d..5c0c433 100644
--- a/platform/msm8909/msm8909-clock.c
+++ b/platform/msm8909/msm8909-clock.c
@@ -100,8 +100,8 @@
{
.en_reg = (void *) APCS_GPLL_ENA_VOTE,
.en_mask = BIT(0),
- .status_reg = (void *) GPLL0_STATUS,
- .status_mask = BIT(17),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
.parent = &cxo_clk_src.c,
.c = {
@@ -254,31 +254,31 @@
F_END
};
-static struct rcg_clk blsp1_uart2_apps_clk_src =
+static struct rcg_clk blsp1_uart1_apps_clk_src =
{
- .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+ .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART1_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART1_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART1_APPS_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "blsp1_uart2_apps_clk",
+ .dbg_name = "blsp1_uart1_apps_clk",
.ops = &clk_ops_rcg_mnd,
},
};
-static struct branch_clk gcc_blsp1_uart2_apps_clk =
+static struct branch_clk gcc_blsp1_uart1_apps_clk =
{
- .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
+ .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR,
+ .parent = &blsp1_uart1_apps_clk_src.c,
.c = {
- .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .dbg_name = "gcc_blsp1_uart1_apps_clk",
.ops = &clk_ops_branch,
},
};
@@ -422,8 +422,8 @@
CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
- CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
- CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+ CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c),
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
diff --git a/platform/msm_shared/gpio.c b/platform/msm_shared/gpio.c
index eb569dd..7071a22 100644
--- a/platform/msm_shared/gpio.c
+++ b/platform/msm_shared/gpio.c
@@ -32,7 +32,7 @@
#include <platform/iomap.h>
#include <gpio.h>
-static void tlmm_set_sdc_pins(struct tlmm_cfgs *cfg)
+static void tlmm_set_pins(struct tlmm_cfgs *cfg)
{
uint32_t reg_val;
@@ -57,7 +57,7 @@
uint8_t i;
for (i = 0; i < sz; i++)
- tlmm_set_sdc_pins(&hdrv_cfgs[i]);
+ tlmm_set_pins(&hdrv_cfgs[i]);
}
void tlmm_set_pull_ctrl(struct tlmm_cfgs *pull_cfgs, uint8_t sz)
@@ -65,5 +65,5 @@
uint8_t i;
for (i = 0; i < sz; i++)
- tlmm_set_sdc_pins(&pull_cfgs[i]);
+ tlmm_set_pins(&pull_cfgs[i]);
}
diff --git a/platform/msm_shared/include/gpio.h b/platform/msm_shared/include/gpio.h
index 3606641..b7305b4 100644
--- a/platform/msm_shared/include/gpio.h
+++ b/platform/msm_shared/include/gpio.h
@@ -50,7 +50,7 @@
TLMM_NO_PULL = 0x0,
} tlmm_pull_values;
-/* Bit offsets in the TLMM register */
+/* SDC Bit offsets in the TLMM register */
enum {
SDC1_DATA_HDRV_CTL_OFF = 0,
SDC1_CMD_HDRV_CTL_OFF = 3,
@@ -59,7 +59,25 @@
SDC1_CMD_PULL_CTL_OFF = 11,
SDC1_CLK_PULL_CTL_OFF = 13,
SDC1_RCLK_PULL_CTL_OFF = 15,
-} tlmm_drv_ctrl;
+} tlmm_sdc_drv_ctrl;
+
+/* EBI2 Bit offsets in the TLMM register */
+enum {
+ EBI2_BUSY_HDRV_CTL_OFF = 29,
+ EBI2_WE_HDRV_CTL_OFF = 24,
+ EBI2_OE_HDRV_CTL_OFF = 9,
+ EBI2_CLE_HDRV_CTL_OFF = 19,
+ EBI2_ALE_HDRV_CTL_OFF = 14,
+ EBI2_CS_HDRV_CTL_OFF = 4,
+ EBI2_DATA_HDRV_CTL_OFF = 17,
+ EBI2_BUSY_PULL_CTL_OFF = 27,
+ EBI2_WE_PULL_CTL_OFF = 22,
+ EBI2_OE_PULL_CTL_OFF = 7 ,
+ EBI2_CLE_PULL_CTL_OFF = 17,
+ EBI2_ALE_PULL_CTL_OFF = 12,
+ EBI2_CS_PULL_CTL_OFF = 2,
+ EBI2_DATA_PULL_CTL_OFF = 15,
+} tlmm_ebi2_drv_ctrl;
/* Input for the tlmm config function */
struct tlmm_cfgs {
diff --git a/platform/msm_shared/include/regulator.h b/platform/msm_shared/include/regulator.h
index 4e6c932..9a54063 100644
--- a/platform/msm_shared/include/regulator.h
+++ b/platform/msm_shared/include/regulator.h
@@ -45,6 +45,11 @@
#define KEY_BYPASS_ALLOWED_KEY 0x61707962 //bypa - bypass allowed
#define KEY_CORNER_LEVEL_KEY 0x6E726F63 // corn - coner voltage
#define KEY_ACTIVE_FLOOR 0x636676
+#define GENERIC_DISABLE 0
+#define GENERIC_ENABLE 1
+#define SW_MODE_LDO_IPEAK 1
+#define LDOA_RES_TYPE 0x616F646C //aodl
+#define SMPS_RES_TYPE 0x61706D73 //apms
void regulator_enable();
void regulator_disable();
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 9d9196c..d6e048a 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -19,8 +19,7 @@
ifeq ($(ENABLE_SMD_SUPPORT),1)
OBJS += \
$(LOCAL_DIR)/rpm-smd.o \
- $(LOCAL_DIR)/smd.o \
- $(LOCAL_DIR)/regulator.o
+ $(LOCAL_DIR)/smd.o
endif
ifeq ($(ENABLE_SDHCI_SUPPORT),1)
diff --git a/platform/msm_shared/smd.c b/platform/msm_shared/smd.c
index dfb5b62..6d99088 100644
--- a/platform/msm_shared/smd.c
+++ b/platform/msm_shared/smd.c
@@ -153,10 +153,63 @@
return false;
}
+/* Copy the local buffer to fifo buffer.
+ * Takes care of fifo overlap.
+ * Uses the fifo as circular buffer, if the request data
+ * exceeds the max size of the buffer start from the beginning.
+ */
+static void memcpy_to_fifo(smd_channel_info_t *ch_ptr, uint32_t *src, size_t len)
+{
+ uint32_t write_index = ch_ptr->port_info->ch0.write_index;
+ uint32_t *dest = (uint32_t *)(ch_ptr->send_buf + write_index);
+
+ while(len)
+ {
+ *dest++ = *src++;
+ write_index += 4;
+ len -= 4;
+
+ if (write_index >= ch_ptr->fifo_size)
+ {
+ write_index = 0;
+ dest = (uint32_t *)(ch_ptr->send_buf + write_index);
+ }
+ }
+ ch_ptr->port_info->ch0.write_index = write_index;
+}
+
+/* Copy the fifo buffer to a local destination.
+ * Takes care of fifo overlap.
+ * If the response data is split across with some part at
+ * end of fifo and some at the beginning of the fifo
+ */
+void memcpy_from_fifo(smd_channel_info_t *ch_ptr, uint32_t *dest, size_t len)
+{
+ uint32_t read_index = ch_ptr->port_info->ch1.read_index;
+ uint32_t *src = (uint32_t *)(ch_ptr->recv_buf + read_index);
+
+ while(len)
+ {
+ *dest++ = *src++;
+ read_index += 4;
+ len -= 4;
+
+ if (read_index >= ch_ptr->fifo_size)
+ {
+ read_index = 0;
+ src = (uint32_t *) (ch_ptr->recv_buf + read_index);
+ }
+ }
+
+ ch_ptr->port_info->ch1.read_index = read_index;
+}
+
uint8_t* smd_read(smd_channel_info_t *ch, uint32_t *len, int ch_type)
{
smd_pkt_hdr smd_hdr;
uint32_t size = 0;
+ /* Response as per the current design does not exceed 20 bytes */
+ uint32_t response[5];
/* Read the indices from smem */
ch->port_info = smem_get_alloc_entry(SMEM_SMD_BASE_ID + ch->alloc_entry.cid,
@@ -172,20 +225,12 @@
{
/* Get the update info from memory */
arch_invalidate_cache_range((addr_t) ch->port_info, size);
-
- if ((ch->port_info->ch1.read_index + sizeof(smd_pkt_hdr)) >= ch->fifo_size)
- {
- dprintf(CRITICAL, "At %d:%s:RX channel read index [%u] is greater than RX fifo size[%u]\n",
- __LINE__,__func__, ch->port_info->ch1.read_index, ch->fifo_size);
- return -1;
- }
}
-
- arch_invalidate_cache_range((addr_t)(ch->recv_buf + ch->port_info->ch1.read_index), sizeof(smd_hdr));
-
/* Copy the smd buffer to local buf */
- memcpy(&smd_hdr, (void*)(ch->recv_buf + ch->port_info->ch1.read_index), sizeof(smd_hdr));
+ memcpy_from_fifo(ch, &smd_hdr, sizeof(smd_hdr));
+
+ arch_invalidate_cache_range((addr_t)&smd_hdr, sizeof(smd_hdr));
*len = smd_hdr.pkt_size;
@@ -194,23 +239,18 @@
{
/* Get the update info from memory */
arch_invalidate_cache_range((addr_t) ch->port_info, size);
-
- if ((ch->port_info->ch1.read_index + sizeof(smd_hdr) + smd_hdr.pkt_size) >= ch->fifo_size)
- {
- dprintf(CRITICAL, "At %d:%s:RX channel read index [%u] is greater than RX fifo size[%u]\n",
- __LINE__,__func__, ch->port_info->ch1.read_index, ch->fifo_size);
- return -1;
- }
}
/* We are good to return the response now */
- return (uint8_t*)(ch->recv_buf + ch->port_info->ch1.read_index + sizeof(smd_hdr));
+ memcpy_from_fifo(ch, response, sizeof(response));
+
+ arch_invalidate_cache_range((addr_t)response, sizeof(response));
+
+ return response;
}
void smd_signal_read_complete(smd_channel_info_t *ch, uint32_t len)
{
- ch->port_info->ch1.read_index += sizeof(smd_pkt_hdr) + len;
-
/* Clear the data_written flag */
ch->port_info->ch1.data_written = 0;
@@ -258,14 +298,9 @@
/*copy the local buf to smd buf */
smd_hdr.pkt_size = len;
- memcpy(ch->send_buf + ch->port_info->ch0.write_index, &smd_hdr, sizeof(smd_hdr));
+ memcpy_to_fifo(ch, (uint32_t *)&smd_hdr, sizeof(smd_hdr));
- memcpy(ch->send_buf + ch->port_info->ch0.write_index + sizeof(smd_hdr), data, len);
-
- arch_invalidate_cache_range((addr_t)ch->send_buf+ch->port_info->ch0.write_index, sizeof(smd_hdr) + len);
-
- /* Update write index */
- ch->port_info->ch0.write_index += sizeof(smd_hdr) + len;
+ memcpy_to_fifo(ch, data, len);
dsb();
diff --git a/platform/msm_shared/smem.c b/platform/msm_shared/smem.c
index 948a256..25628d3 100644
--- a/platform/msm_shared/smem.c
+++ b/platform/msm_shared/smem.c
@@ -87,7 +87,7 @@
size = readl(&ainfo->size);
- if (size != (unsigned)((len + 7) & ~0x00000007))
+ if (size < (unsigned)((len + 7) & ~0x00000007))
return 1;
src = smem_addr + readl(&ainfo->offset);
diff --git a/project/msm8909.mk b/project/msm8909.mk
index 0ffce48..e00fbe2 100644
--- a/project/msm8909.mk
+++ b/project/msm8909.mk
@@ -6,18 +6,25 @@
MODULES += app/aboot
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
+
EMMC_BOOT := 1
-ENABLE_SMD_SUPPORT := 1
+#ENABLE_SMD_SUPPORT := 1
ENABLE_BOOT_CONFIG_SUPPORT := 1
#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_LOG_BUF=1
DEFINES += WITH_DEBUG_UART=1
#DEFINES += WITH_DEBUG_FBCON=1
DEFINES += DEVICE_TREE=1
#DEFINES += MMC_BOOT_BAM=1
#DEFINES += CRYPTO_BAM=1
+DEFINES += SPMI_CORE_V2=1
DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80008000
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index b0eed95..3186c82 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -115,6 +115,7 @@
{ SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
static void set_sdc_power_ctrl(void);
+static void set_ebi2_config(void);
void update_ptable_names(void)
{
@@ -237,17 +238,17 @@
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
- { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
- { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
};
/* Pull configs for sdc pins */
struct tlmm_cfgs sdc1_pull_cfg[] =
{
- { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
- { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
- { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
};
/* Set the drive strength & pull control values */
@@ -255,6 +256,37 @@
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
}
+static void set_ebi2_config()
+{
+ /* Drive strength configs for ebi2 pins */
+ struct tlmm_cfgs ebi2_hdrv_cfg[] =
+ {
+ { EBI2_BUSY_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_WE_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_OE_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_CLE_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_ALE_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_CS_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
+ };
+
+ /* Pull configs for ebi2 pins */
+ struct tlmm_cfgs ebi2_pull_cfg[] =
+ {
+ { EBI2_BUSY_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_WE_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_OE_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_CLE_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_ALE_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_CS_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, TLMM_EBI2_EMMC_GPIO_CFG },
+ { EBI2_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
+ };
+
+ /* Set the drive strength & pull control values */
+ tlmm_set_hdrive_ctrl(ebi2_hdrv_cfg, ARRAY_SIZE(ebi2_hdrv_cfg));
+ tlmm_set_pull_ctrl(ebi2_pull_cfg, ARRAY_SIZE(ebi2_pull_cfg));
+
+}
void target_init(void)
{
uint32_t base_addr;
@@ -266,7 +298,9 @@
target_keystatus();
+#if ENABLE_BOOT_CONFIG_SUPPORT
platform_read_boot_config();
+#endif
if (platform_boot_dev_isemmc()) {
target_sdc_init();
@@ -277,6 +311,7 @@
}
} else {
+ set_ebi2_config();
config.pipes.read_pipe = DATA_PRODUCER_PIPE;
config.pipes.write_pipe = DATA_CONSUMER_PIPE;
config.pipes.cmd_pipe = CMD_PIPE;
@@ -313,7 +348,9 @@
if (target_use_signed_kernel())
target_crypto_init_params();
+#if ENABLE_SMD_SUPPORT
rpm_smd_init();
+#endif
}
void target_serialno(unsigned char *buf)
@@ -595,7 +632,9 @@
if (target_is_ssd_enabled())
clock_ce_disable(CE1_INSTANCE);
+#if ENABLE_SMD_SUPPORT
rpm_smd_uninit();
+#endif
}
/* Do any target specific intialization needed before entering fastboot mode */
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 18c6ab9..d540bd4 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -197,7 +197,7 @@
if (is_cold_boot &&
(!(pon_reason & HARD_RST)) &&
(!(pon_reason & KPDPWR_N)) &&
- ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ ((pon_reason & PON1)))
return 1;
else
return 0;
diff --git a/platform/msm_shared/regulator.c b/target/msm8994/regulator.c
similarity index 94%
rename from platform/msm_shared/regulator.c
rename to target/msm8994/regulator.c
index 440049b..8a8d1e1 100644
--- a/platform/msm_shared/regulator.c
+++ b/target/msm8994/regulator.c
@@ -30,12 +30,6 @@
#include <regulator.h>
#include <rpm-smd.h>
-#define GENERIC_DISABLE 0
-#define GENERIC_ENABLE 1
-#define SW_MODE_LDO_IPEAK 1
-#define LDOA_RES_TYPE 0x616F646C //aodl
-#define SMPS_RES_TYPE 0x61706D73 //apms
-
static uint32_t ldo2[][11]=
{
{
@@ -116,7 +110,6 @@
rpm_send_data(&ldo28[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
}
-
void regulator_disable()
{
diff --git a/target/msm8994/rules.mk b/target/msm8994/rules.mk
index 509c91a..ec35e53 100644
--- a/target/msm8994/rules.mk
+++ b/target/msm8994/rules.mk
@@ -39,3 +39,8 @@
$(LOCAL_DIR)/meminfo.o \
$(LOCAL_DIR)/target_display.o \
$(LOCAL_DIR)/oem_panel.o
+
+ifeq ($(ENABLE_SMD_SUPPORT),1)
+OBJS += \
+ $(LOCAL_DIR)/regulator.o
+endif