arch: arm: Use dsb instruction for data barrier
Use dsb instruction for data barriers for cache clean, invalidate
functions instead of cp15 instruction. With Armv8 by default disables
cp15 barriers, if attempted to execute these cp15 barriers we end up in
undefined behaviour.
Change-Id: I3a6dcd350d07d6dbaaca28e841da6e6ada973cda
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S
index 974fb9b..e67dc65 100644
--- a/arch/arm/cache-ops.S
+++ b/arch/arm/cache-ops.S
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -338,7 +338,7 @@
bhs 0b
mov r0, #0
- mcr p15, 0, r0, c7, c10, 4 // data sync barrier (formerly drain write buffer)
+ dsb
bx lr
@@ -351,7 +351,7 @@
bhs 0b
mov r0, #0
- mcr p15, 0, r0, c7, c10, 4 // data sync barrier (formerly drain write buffer)
+ dsb
bx lr
@@ -364,8 +364,7 @@
subs r1, r1, #CACHE_LINE
bhs 0b
mov r0, #0
- /* data sync barrier (formerly drain write buffer*/
- mcr p15, 0, r0, c7, c10, 4
+ dsb
bx lr
/* void arch_sync_cache_range(addr_t start, size_t len); */