Merge "lib: fdt: add integer overflow checks in fdt header"
diff --git a/AndroidBoot.mk b/AndroidBoot.mk
index 0cb6128..089c4d8 100644
--- a/AndroidBoot.mk
+++ b/AndroidBoot.mk
@@ -3,7 +3,7 @@
ifndef 2ND_TARGET_GCC_VERSION
CROSS_COMPILE := ../../../prebuilts/gcc/linux-x86/arm/arm-eabi-$(TARGET_GCC_VERSION)/bin/arm-eabi-
else
-CROSS_COMPILE := ../../../prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+CROSS_COMPILE := ../../../prebuilts/gcc/linux-x86/arm/arm-eabi-$(2ND_TARGET_GCC_VERSION)/bin/arm-eabi-
endif
# Set flags if we need to include security libs
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
old mode 100755
new mode 100644
index 3b5092d..5d036f5
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -328,11 +328,13 @@
if (cmdline_len > 0) {
const char *src;
- unsigned char *dst = (unsigned char*) malloc((cmdline_len + 4) & (~3));
- ASSERT(dst != NULL);
+ unsigned char *dst;
+
+ cmdline_final = (unsigned char*) malloc((cmdline_len + 4) & (~3));
+ ASSERT(cmdline_final != NULL);
+ dst = cmdline_final;
/* Save start ptr for debug print */
- cmdline_final = dst;
if (have_cmdline) {
src = cmdline;
while ((*dst++ = *src++));
@@ -471,7 +473,7 @@
if (boot_dev_buf)
free(boot_dev_buf);
- dprintf(INFO, "cmdline: %s\n", cmdline_final);
+ dprintf(INFO, "cmdline: %s\n", cmdline_final ? cmdline_final : "");
return cmdline_final;
}
@@ -592,6 +594,7 @@
generate_atags(tags, final_cmdline, ramdisk, ramdisk_size);
#endif
+ free(final_cmdline);
/* Perform target specific cleanup */
target_uninit();
@@ -2497,6 +2500,13 @@
memset(display_panel_buf, '\0', MAX_PANEL_BUF_SIZE);
+ /*
+ * Check power off reason if user force reset,
+ * if yes phone will do normal boot.
+ */
+ if (is_user_force_reset())
+ goto normal_boot;
+
/* Check if we should do something other than booting up */
if (keys_get_state(KEY_VOLUMEUP) && keys_get_state(KEY_VOLUMEDOWN))
{
@@ -2532,6 +2542,7 @@
boot_into_fastboot = true;
}
+normal_boot:
if (!boot_into_fastboot)
{
if (target_is_emmc_boot())
diff --git a/app/aboot/rules.mk b/app/aboot/rules.mk
index a26937b..5342d7a 100644
--- a/app/aboot/rules.mk
+++ b/app/aboot/rules.mk
@@ -2,6 +2,8 @@
INCLUDES += -I$(LK_TOP_DIR)/platform/msm_shared/include
+DEFINES += ASSERT_ON_TAMPER=1
+
OBJS += \
$(LOCAL_DIR)/aboot.o \
$(LOCAL_DIR)/fastboot.o \
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index e7d7a0e..38ba3b4 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -37,9 +37,8 @@
static struct mdss_dsi_pll_config pll_data;
-static uint32_t calculate_bitclock(struct msm_panel_info *pinfo)
+static void calculate_bitclock(struct msm_panel_info *pinfo)
{
- uint32_t ret = NO_ERROR;
uint32_t h_period = 0, v_period = 0;
uint32_t width = pinfo->xres;
@@ -67,8 +66,6 @@
pll_data.byte_clock = pll_data.bit_clock >> 3;
pll_data.halfbit_clock = pll_data.bit_clock >> 1;
-
- return ret;
}
static uint32_t calculate_div1()
@@ -140,9 +137,38 @@
pll_data.posdiv3--; /* Register needs one value less */
}
-static uint32_t calculate_vco(uint8_t bpp, uint8_t num_of_lanes)
+static uint32_t calculate_dec_frac_start()
{
- uint32_t ret = NO_ERROR;
+ uint32_t refclk = 19200000;
+ uint32_t vco_rate = pll_data.vco_clock;
+ uint32_t tmp, mod;
+
+ vco_rate /= 2;
+ pll_data.dec_start = vco_rate / refclk;
+ tmp = vco_rate % refclk; /* module, fraction */
+ tmp /= 192;
+ tmp *= 1024;
+ tmp /= 100;
+ tmp *= 1024;
+ tmp /= 1000;
+ pll_data.frac_start = tmp;
+
+ vco_rate *= 2; /* restore */
+ tmp = vco_rate / refclk;/* div 1000 first */
+ mod = vco_rate % refclk;
+ tmp *= 127;
+ mod *= 127;
+ mod /= refclk;
+ tmp += mod;
+ tmp /= 10;
+ pll_data.lock_comp = tmp;
+
+ dprintf(SPEW, "%s: dec_start=%u dec_frac=%u lock_comp=%u\n", __func__,
+ pll_data.dec_start, pll_data.frac_start, pll_data.lock_comp);
+}
+
+static uint32_t calculate_vco_28nm(uint8_t bpp, uint8_t num_of_lanes)
+{
uint8_t counter = 0;
uint32_t temprate = 0;
@@ -172,7 +198,85 @@
/* calculate mnd and div3 for direct and indirect path */
calculate_div3(bpp, num_of_lanes);
- return ret;
+ return NO_ERROR;
+}
+
+static uint32_t calculate_vco_20nm(uint8_t bpp, uint8_t lanes)
+{
+ uint32_t vco, dsi_clk;
+ int mod, ndiv, hr_oclk2, hr_oclk3;
+ int m = 1;
+ int n = 1;
+ int bpp_m = 3; /* bpp = 3 */
+ int bpp_n = 1;
+
+ if (bpp == BITS_18) {
+ bpp_m = 9; /* bpp = 2.25 */
+ bpp_n = 4;
+
+ if (lanes == 2) {
+ m = 2;
+ n = 9;
+ } else if (lanes == 4) {
+ m = 4;
+ n = 9;
+ }
+ } else if (bpp == BITS_16) {
+ bpp_m = 2; /* bpp = 2 */
+ bpp_n = 1;
+ if (lanes == 3) {
+ m = 3;
+ n = 8;
+ }
+ }
+
+ hr_oclk2 = 4;
+
+ /* If bitclock is more than VCO min value */
+ if (pll_data.halfbit_clock >= HALF_VCO_MIN_CLOCK_20NM) {
+ /* Direct Mode */
+ vco = pll_data.halfbit_clock << 1;
+ /* support vco clock to max value only */
+ if (vco > VCO_MAX_CLOCK_20NM)
+ vco = VCO_MAX_CLOCK_20NM;
+
+ pll_data.directpath = 0x0;
+ pll_data.byte_clock = vco / 2 / hr_oclk2;
+ pll_data.lp_div_mux = 0x0;
+ ndiv = 1;
+ hr_oclk3 = hr_oclk2 * m / n * bpp_m / bpp_n / lanes;
+ } else {
+ /* Indirect Mode */
+ mod = VCO_MIN_CLOCK_20NM % (4 * pll_data.halfbit_clock );
+ ndiv = VCO_MIN_CLOCK_20NM / (4 * pll_data.halfbit_clock );
+ if (mod)
+ ndiv += 1;
+
+ vco = pll_data.halfbit_clock * 4 * ndiv;
+ pll_data.lp_div_mux = 0x1;
+ pll_data.directpath = 0x02; /* set bit 1 to enable for
+ indirect path */
+
+ pll_data.byte_clock = vco / 4 / hr_oclk2 / ndiv;
+ hr_oclk3 = hr_oclk2 * m / n * ndiv * 2 * bpp_m / bpp_n / lanes;
+ }
+
+ pll_data.vco_clock = vco;
+ dsi_clk = vco / 2 / hr_oclk3;
+ pll_data.ndiv = ndiv;
+ pll_data.hr_oclk2 = hr_oclk2 - 1; /* strat from 0 */
+ pll_data.hr_oclk3 = hr_oclk3 - 1; /* strat from 0 */
+
+ pll_data.pclk_m = m; /* M */
+ pll_data.pclk_n = ~(n - m); /* ~(N-M) */
+ pll_data.pclk_d = ~n; /* ~N */
+
+ dprintf(SPEW, "%s: oclk2=%d oclk3=%d ndiv=%d vco=%u dsi_clk=%u byte_clk=%u\n",
+ __func__, hr_oclk2, hr_oclk3, ndiv, vco, dsi_clk, pll_data.byte_clock);
+
+ calculate_dec_frac_start();
+
+ return NO_ERROR;
}
uint32_t calculate_clock_config(struct msm_panel_info *pinfo)
@@ -181,7 +285,10 @@
calculate_bitclock(pinfo);
- calculate_vco(pinfo->bpp, pinfo->mipi.num_of_lanes);
+ if (pinfo->mipi.mdss_dsi_phy_db->is_pll_20nm)
+ ret = calculate_vco_20nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
+ else
+ ret = calculate_vco_28nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
pinfo->mipi.dsi_pll_config = &pll_data;
diff --git a/dev/gcdb/display/gcdb_autopll.h b/dev/gcdb/display/gcdb_autopll.h
index 259abd6..ee0070d 100755
--- a/dev/gcdb/display/gcdb_autopll.h
+++ b/dev/gcdb/display/gcdb_autopll.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,6 +43,16 @@
#define HALFBIT_CLOCK3 44000000 /* VCO min clock div by 8 */
#define HALFBIT_CLOCK4 40000000 /* VCO min clock div by 9 */
+#define VCO_MIN_CLOCK_20NM 1000000000
+#define VCO_MAX_CLOCK_20NM 2000000000
+
+#define HALF_VCO_MIN_CLOCK_20NM (VCO_MIN_CLOCK_20NM >> 1)
+
+#define HALFBIT_CLOCK1_20NM 500000000 /* VCO min clock div by 2 */
+#define HALFBIT_CLOCK2_20NM 250000000 /* VCO min clock div by 4 */
+#define HALFBIT_CLOCK3_20NM 125000000 /* VCO min clock div by 8 */
+#define HALFBIT_CLOCK4_20NM 120000000 /* VCO min clock div by 9 */
+
#define BITS_24 24
#define BITS_18 18
#define BITS_16 16
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index da9ffa6..d1695f2 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -90,12 +90,13 @@
return ret;
}
-static int mdss_dsi_panel_power(uint8_t enable)
+static int mdss_dsi_panel_power(uint8_t enable,
+ struct msm_panel_info *pinfo)
{
int ret = NO_ERROR;
if (enable) {
- ret = target_ldo_ctrl(enable);
+ ret = target_ldo_ctrl(enable, pinfo);
if (ret) {
dprintf(CRITICAL, "LDO control enable failed\n");
return ret;
@@ -118,7 +119,7 @@
return ret;
}
- ret = target_ldo_ctrl(enable);
+ ret = target_ldo_ctrl(enable, pinfo);
if (ret) {
dprintf(CRITICAL, "ldo control disable failed\n");
return ret;
@@ -159,7 +160,7 @@
return ret;
}
-bool gcdb_display_cmdline_arg(char *pbuf, uint16_t buf_size)
+bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size)
{
char *dsi_id = NULL;
char *panel_node = NULL;
@@ -171,28 +172,29 @@
int panel_mode = SPLIT_DISPLAY_FLAG | DUAL_PIPE_FLAG | DST_SPLIT_FLAG;
int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
- if (panelstruct.paneldata)
- {
+ if (!strcmp(panel_name, SIM_VIDEO_PANEL)) {
+ dsi_id = SIM_DSI_ID;
+ panel_mode = 0;
+ panel_node = SIM_VIDEO_PANEL_NODE;
+ } else if (!strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL)) {
+ dsi_id = SIM_DSI_ID;
+ panel_mode = 1;
+ panel_node = SIM_DUALDSI_VIDEO_PANEL_NODE;
+ slave_panel_node = SIM_DUALDSI_VIDEO_SLAVE_PANEL_NODE;
+ } else if (panelstruct.paneldata) {
dsi_id = panelstruct.paneldata->panel_controller;
panel_node = panelstruct.paneldata->panel_node_id;
panel_mode = panelstruct.paneldata->panel_operating_mode &
panel_mode;
slave_panel_node = panelstruct.paneldata->slave_panel_node_id;
- }
- else
- {
+ } else {
if (target_is_edp())
- {
default_str = "0:edp:";
- }
else
- {
default_str = "0:dsi:0:";
- }
arg_size = prefix_string_len + strlen(default_str);
- if (buf_size < arg_size)
- {
+ if (buf_size < arg_size) {
dprintf(CRITICAL, "display command line buffer is small\n");
return false;
}
@@ -227,13 +229,10 @@
if (panel_mode)
arg_size += DSI_1_STRING_LEN + slave_panel_node_len;
- if (buf_size < arg_size)
- {
+ if (buf_size < arg_size) {
dprintf(CRITICAL, "display command line buffer is small\n");
ret = false;
- }
- else
- {
+ } else {
strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
pbuf += prefix_string_len;
buf_size -= prefix_string_len;
@@ -299,12 +298,13 @@
return target_edp_panel_disable();
}
-static int mdss_edp_panel_power(uint8_t enable)
+static int mdss_edp_panel_power(uint8_t enable,
+ struct msm_panel_info *pinfo)
{
int ret = NO_ERROR;
if (enable) {
- ret = target_ldo_ctrl(enable);
+ ret = target_ldo_ctrl(enable, pinfo);
if (ret) {
dprintf(CRITICAL, "LDO control enable failed\n");
return ret;
@@ -324,7 +324,7 @@
return ret;
}
- ret = target_ldo_ctrl(enable);
+ ret = target_ldo_ctrl(enable, pinfo);
if (ret) {
dprintf(CRITICAL, "%s: ldo control disable failed\n", __func__);
return ret;
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 5727067..3b112e3 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -54,10 +54,10 @@
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo);
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo);
-int target_ldo_ctrl(uint8_t enable);
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo);
int gcdb_display_init(const char *panel_name, uint32_t rev, void *base);
-bool gcdb_display_cmdline_arg(char *pbuf, uint16_t buf_size);
+bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size);
void gcdb_display_shutdown();
#endif /*_GCDB_DISPLAY_H_ */
diff --git a/dev/gcdb/display/include/display_resource.h b/dev/gcdb/display/include/display_resource.h
index 5caad1e..ce95769 100755
--- a/dev/gcdb/display/include/display_resource.h
+++ b/dev/gcdb/display/include/display_resource.h
@@ -43,6 +43,13 @@
#define LK_OVERRIDE_PANEL_LEN 2
#define NO_PANEL_CONFIG "none"
+#define SIM_VIDEO_PANEL "sim_video_panel"
+#define SIM_DUALDSI_VIDEO_PANEL "sim_dualdsi_video_panel"
+
+#define SIM_DSI_ID "dsi:0:"
+#define SIM_VIDEO_PANEL_NODE "qcom,mdss_dsi_sim_video"
+#define SIM_DUALDSI_VIDEO_PANEL_NODE "qcom,mdss_dsi_sim_video_0"
+#define SIM_DUALDSI_VIDEO_SLAVE_PANEL_NODE "qcom,mdss_dsi_sim_video_1"
/*---------------------------------------------------------------------------*/
/* Structure definition */
diff --git a/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
new file mode 100755
index 0000000..b11b9b4
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
@@ -0,0 +1,237 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_HX8379A_FWVGA_VIDEO_H_
+#define _PANEL_HX8379A_FWVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config hx8379a_fwvga_video_panel_data = {
+ "qcom,mdss_dsi_hx8379a_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8379a_fwvga_video_panel_res = {
+ 480, 854, 100, 94, 40, 0, 6, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8379a_fwvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char hx8379a_fwvga_video_on_cmd0[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB9, 0xFF, 0x83, 0x79,
+};
+
+static char hx8379a_fwvga_video_on_cmd1[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xBA, 0x51, 0x93, 0xFF,
+};
+
+static char hx8379a_fwvga_video_on_cmd2[] = {
+ 0x14, 0x00, 0x39, 0xC0,
+ 0xB1, 0x00, 0x50, 0x24,
+ 0xEA, 0x51, 0x08, 0x11,
+ 0x10, 0xF0, 0x27, 0x2F,
+ 0x9A, 0x1A, 0x42, 0x0B,
+ 0x7A, 0xF1, 0x00, 0xE6,
+};
+
+static char hx8379a_fwvga_video_on_cmd3[] = {
+ 0x0E, 0x00, 0x39, 0xC0,
+ 0xB2, 0x00, 0x00, 0xFE,
+ 0x07, 0x03, 0x19, 0x44,
+ 0x00, 0xFF, 0x07, 0x03,
+ 0x19, 0x20, 0xFF, 0xFF,
+};
+
+static char hx8379a_fwvga_video_on_cmd4[] = {
+ 0x20, 0x00, 0x39, 0xC0,
+ 0xB4, 0x82, 0x08, 0x00,
+ 0x32, 0x10, 0x03, 0x32,
+ 0x13, 0x70, 0x32, 0x10,
+ 0x08, 0x37, 0x01, 0x28,
+ 0x07, 0x37, 0x08, 0x3C,
+ 0x08, 0x3E, 0x3E, 0x08,
+ 0x00, 0x40, 0x08, 0x28,
+ 0x08, 0x30, 0x30, 0x04,
+};
+
+static char hx8379a_fwvga_video_on_cmd5[] = {
+ 0xcc, 0x02, 0x23, 0x80
+};
+
+static char hx8379a_fwvga_video_on_cmd6[] = {
+ 0x30, 0x00, 0x39, 0xC0,
+ 0xD5, 0x00, 0x00, 0x0A,
+ 0x00, 0x01, 0x05, 0x00,
+ 0x03, 0x00, 0x88, 0x88,
+ 0x88, 0x88, 0x23, 0x01,
+ 0x67, 0x45, 0x02, 0x13,
+ 0x88, 0x88, 0x88, 0x88,
+ 0x88, 0x88, 0x88, 0x88,
+ 0x88, 0x88, 0x54, 0x76,
+ 0x10, 0x32, 0x31, 0x20,
+ 0x88, 0x88, 0x88, 0x88,
+ 0x88, 0x88, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+static char hx8379a_fwvga_video_on_cmd7[] = {
+ 0x24, 0x00, 0x39, 0xC0,
+ 0xE0, 0x79, 0x00, 0x0F,
+ 0x14, 0x22, 0x22, 0x39,
+ 0x2F, 0x43, 0x04, 0x0A,
+ 0x12, 0x14, 0x17, 0x15,
+ 0x16, 0x12, 0x16, 0x00,
+ 0x0F, 0x14, 0x22, 0x22,
+ 0x39, 0x2F, 0x43, 0x04,
+ 0x0A, 0x12, 0x14, 0x17,
+ 0x15, 0x16, 0x12, 0x16,
+};
+
+static char hx8379a_fwvga_video_on_cmd8[] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0xB6, 0x00, 0x9C, 0x00,
+ 0x9C, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8379a_fwvga_video_on_cmd9[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char hx8379a_fwvga_video_on_cmd10[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379a_fwvga_video_on_command[] = {
+ {0x8, hx8379a_fwvga_video_on_cmd0, 0x00},
+ {0x8, hx8379a_fwvga_video_on_cmd1, 0x00},
+ {0x18, hx8379a_fwvga_video_on_cmd2, 0x00},
+ {0x14, hx8379a_fwvga_video_on_cmd3, 0x00},
+ {0x24, hx8379a_fwvga_video_on_cmd4, 0x00},
+ {0x04, hx8379a_fwvga_video_on_cmd5, 0x00},
+ {0x34, hx8379a_fwvga_video_on_cmd6, 0x00},
+ {0x28, hx8379a_fwvga_video_on_cmd7, 0x00},
+ {0xc, hx8379a_fwvga_video_on_cmd8, 0x00},
+ {0x4, hx8379a_fwvga_video_on_cmd9, 0x96},
+ {0x4, hx8379a_fwvga_video_on_cmd10, 0x78}
+};
+
+#define HX8379A_FWVGA_VIDEO_ON_COMMAND 11
+
+
+static char hx8379a_fwvga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char hx8379a_fwvga_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379a_fwvga_video_off_command[] = {
+ {0x4, hx8379a_fwvga_videooff_cmd0, 0x32},
+ {0x4, hx8379a_fwvga_videooff_cmd1, 0x78}
+};
+
+#define HX8379A_FWVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state hx8379a_fwvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info hx8379a_fwvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info hx8379a_fwvga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration hx8379a_fwvga_video_lane_config = {
+ 2, 1, 1, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t hx8379a_fwvga_video_timings[] = {
+ 0x8B, 0x1f, 0x14, 0x00, 0x45, 0x4A, 0x19, 0x23, 0x23, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing hx8379a_fwvga_video_timing_info = {
+ 0, 4, 0x04, 0x1d
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence hx8379a_fwvga_video_reset_seq = {
+ {1, 0, 1, }, {20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight hx8379a_fwvga_video_backlight = {
+ 0, 1, 255, 0, 2, 0
+};
+
+#endif /*_PANEL_HX8379A_FWVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
index 34cb79d..72f5a18 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
@@ -2390,470 +2390,470 @@
static struct mipi_dsi_cmd nt35590_720p_cmd_on_command[] = {
-{ 0x8 , nt35590_720p_cmd_on_cmd0},
-{ 0x8 , nt35590_720p_cmd_on_cmd1},
-{ 0x8 , nt35590_720p_cmd_on_cmd2},
-{ 0x8 , nt35590_720p_cmd_on_cmd3},
-{ 0x8 , nt35590_720p_cmd_on_cmd4},
-{ 0x8 , nt35590_720p_cmd_on_cmd5},
-{ 0x8 , nt35590_720p_cmd_on_cmd6},
-{ 0x8 , nt35590_720p_cmd_on_cmd7},
-{ 0x8 , nt35590_720p_cmd_on_cmd8},
-{ 0x8 , nt35590_720p_cmd_on_cmd9},
-{ 0x8 , nt35590_720p_cmd_on_cmd10},
-{ 0x8 , nt35590_720p_cmd_on_cmd11},
-{ 0x8 , nt35590_720p_cmd_on_cmd12},
-{ 0x8 , nt35590_720p_cmd_on_cmd13},
-{ 0x8 , nt35590_720p_cmd_on_cmd14},
-{ 0x8 , nt35590_720p_cmd_on_cmd15},
-{ 0x8 , nt35590_720p_cmd_on_cmd16},
-{ 0x8 , nt35590_720p_cmd_on_cmd17},
-{ 0x8 , nt35590_720p_cmd_on_cmd18},
-{ 0x8 , nt35590_720p_cmd_on_cmd19},
-{ 0x8 , nt35590_720p_cmd_on_cmd20},
-{ 0x8 , nt35590_720p_cmd_on_cmd21},
-{ 0x8 , nt35590_720p_cmd_on_cmd22},
-{ 0x8 , nt35590_720p_cmd_on_cmd23},
-{ 0x8 , nt35590_720p_cmd_on_cmd24},
-{ 0x8 , nt35590_720p_cmd_on_cmd25},
-{ 0x8 , nt35590_720p_cmd_on_cmd26},
-{ 0x8 , nt35590_720p_cmd_on_cmd27},
-{ 0x8 , nt35590_720p_cmd_on_cmd28},
-{ 0x8 , nt35590_720p_cmd_on_cmd29},
-{ 0x8 , nt35590_720p_cmd_on_cmd30},
-{ 0x8 , nt35590_720p_cmd_on_cmd31},
-{ 0x8 , nt35590_720p_cmd_on_cmd32},
-{ 0x8 , nt35590_720p_cmd_on_cmd33},
-{ 0x8 , nt35590_720p_cmd_on_cmd34},
-{ 0x8 , nt35590_720p_cmd_on_cmd35},
-{ 0x8 , nt35590_720p_cmd_on_cmd36},
-{ 0x8 , nt35590_720p_cmd_on_cmd37},
-{ 0x8 , nt35590_720p_cmd_on_cmd38},
-{ 0x8 , nt35590_720p_cmd_on_cmd39},
-{ 0x8 , nt35590_720p_cmd_on_cmd40},
-{ 0x8 , nt35590_720p_cmd_on_cmd41},
-{ 0x8 , nt35590_720p_cmd_on_cmd42},
-{ 0x8 , nt35590_720p_cmd_on_cmd43},
-{ 0x8 , nt35590_720p_cmd_on_cmd44},
-{ 0x8 , nt35590_720p_cmd_on_cmd45},
-{ 0x8 , nt35590_720p_cmd_on_cmd46},
-{ 0x8 , nt35590_720p_cmd_on_cmd47},
-{ 0x8 , nt35590_720p_cmd_on_cmd48},
-{ 0x8 , nt35590_720p_cmd_on_cmd49},
-{ 0x8 , nt35590_720p_cmd_on_cmd50},
-{ 0x8 , nt35590_720p_cmd_on_cmd51},
-{ 0x8 , nt35590_720p_cmd_on_cmd52},
-{ 0x8 , nt35590_720p_cmd_on_cmd53},
-{ 0x8 , nt35590_720p_cmd_on_cmd54},
-{ 0x8 , nt35590_720p_cmd_on_cmd55},
-{ 0x8 , nt35590_720p_cmd_on_cmd56},
-{ 0x8 , nt35590_720p_cmd_on_cmd57},
-{ 0x8 , nt35590_720p_cmd_on_cmd58},
-{ 0x8 , nt35590_720p_cmd_on_cmd59},
-{ 0x8 , nt35590_720p_cmd_on_cmd60},
-{ 0x8 , nt35590_720p_cmd_on_cmd61},
-{ 0x8 , nt35590_720p_cmd_on_cmd62},
-{ 0x8 , nt35590_720p_cmd_on_cmd63},
-{ 0x8 , nt35590_720p_cmd_on_cmd64},
-{ 0x8 , nt35590_720p_cmd_on_cmd65},
-{ 0x8 , nt35590_720p_cmd_on_cmd66},
-{ 0x8 , nt35590_720p_cmd_on_cmd67},
-{ 0x8 , nt35590_720p_cmd_on_cmd68},
-{ 0x8 , nt35590_720p_cmd_on_cmd69},
-{ 0x8 , nt35590_720p_cmd_on_cmd70},
-{ 0x8 , nt35590_720p_cmd_on_cmd71},
-{ 0x8 , nt35590_720p_cmd_on_cmd72},
-{ 0x8 , nt35590_720p_cmd_on_cmd73},
-{ 0x8 , nt35590_720p_cmd_on_cmd74},
-{ 0x8 , nt35590_720p_cmd_on_cmd75},
-{ 0x8 , nt35590_720p_cmd_on_cmd76},
-{ 0x8 , nt35590_720p_cmd_on_cmd77},
-{ 0x8 , nt35590_720p_cmd_on_cmd78},
-{ 0x8 , nt35590_720p_cmd_on_cmd79},
-{ 0x8 , nt35590_720p_cmd_on_cmd80},
-{ 0x8 , nt35590_720p_cmd_on_cmd81},
-{ 0x8 , nt35590_720p_cmd_on_cmd82},
-{ 0x8 , nt35590_720p_cmd_on_cmd83},
-{ 0x8 , nt35590_720p_cmd_on_cmd84},
-{ 0x8 , nt35590_720p_cmd_on_cmd85},
-{ 0x8 , nt35590_720p_cmd_on_cmd86},
-{ 0x8 , nt35590_720p_cmd_on_cmd87},
-{ 0x8 , nt35590_720p_cmd_on_cmd88},
-{ 0x8 , nt35590_720p_cmd_on_cmd89},
-{ 0x8 , nt35590_720p_cmd_on_cmd90},
-{ 0x8 , nt35590_720p_cmd_on_cmd91},
-{ 0x8 , nt35590_720p_cmd_on_cmd92},
-{ 0x8 , nt35590_720p_cmd_on_cmd93},
-{ 0x8 , nt35590_720p_cmd_on_cmd94},
-{ 0x8 , nt35590_720p_cmd_on_cmd95},
-{ 0x8 , nt35590_720p_cmd_on_cmd96},
-{ 0x8 , nt35590_720p_cmd_on_cmd97},
-{ 0x8 , nt35590_720p_cmd_on_cmd98},
-{ 0x8 , nt35590_720p_cmd_on_cmd99},
-{ 0x8 , nt35590_720p_cmd_on_cmd100},
-{ 0x8 , nt35590_720p_cmd_on_cmd101},
-{ 0x8 , nt35590_720p_cmd_on_cmd102},
-{ 0x8 , nt35590_720p_cmd_on_cmd103},
-{ 0x8 , nt35590_720p_cmd_on_cmd104},
-{ 0x8 , nt35590_720p_cmd_on_cmd105},
-{ 0x8 , nt35590_720p_cmd_on_cmd106},
-{ 0x8 , nt35590_720p_cmd_on_cmd107},
-{ 0x8 , nt35590_720p_cmd_on_cmd108},
-{ 0x8 , nt35590_720p_cmd_on_cmd109},
-{ 0x8 , nt35590_720p_cmd_on_cmd110},
-{ 0x8 , nt35590_720p_cmd_on_cmd111},
-{ 0x8 , nt35590_720p_cmd_on_cmd112},
-{ 0x8 , nt35590_720p_cmd_on_cmd113},
-{ 0x8 , nt35590_720p_cmd_on_cmd114},
-{ 0x8 , nt35590_720p_cmd_on_cmd115},
-{ 0x8 , nt35590_720p_cmd_on_cmd116},
-{ 0x8 , nt35590_720p_cmd_on_cmd117},
-{ 0x8 , nt35590_720p_cmd_on_cmd118},
-{ 0x8 , nt35590_720p_cmd_on_cmd119},
-{ 0x8 , nt35590_720p_cmd_on_cmd120},
-{ 0x8 , nt35590_720p_cmd_on_cmd121},
-{ 0x8 , nt35590_720p_cmd_on_cmd122},
-{ 0x8 , nt35590_720p_cmd_on_cmd123},
-{ 0x8 , nt35590_720p_cmd_on_cmd124},
-{ 0x8 , nt35590_720p_cmd_on_cmd125},
-{ 0x8 , nt35590_720p_cmd_on_cmd126},
-{ 0x8 , nt35590_720p_cmd_on_cmd127},
-{ 0x8 , nt35590_720p_cmd_on_cmd128},
-{ 0x8 , nt35590_720p_cmd_on_cmd129},
-{ 0x8 , nt35590_720p_cmd_on_cmd130},
-{ 0x8 , nt35590_720p_cmd_on_cmd131},
-{ 0x8 , nt35590_720p_cmd_on_cmd132},
-{ 0x8 , nt35590_720p_cmd_on_cmd133},
-{ 0x8 , nt35590_720p_cmd_on_cmd134},
-{ 0x8 , nt35590_720p_cmd_on_cmd135},
-{ 0x8 , nt35590_720p_cmd_on_cmd136},
-{ 0x8 , nt35590_720p_cmd_on_cmd137},
-{ 0x8 , nt35590_720p_cmd_on_cmd138},
-{ 0x8 , nt35590_720p_cmd_on_cmd139},
-{ 0x8 , nt35590_720p_cmd_on_cmd140},
-{ 0x8 , nt35590_720p_cmd_on_cmd141},
-{ 0x8 , nt35590_720p_cmd_on_cmd142},
-{ 0x8 , nt35590_720p_cmd_on_cmd143},
-{ 0x8 , nt35590_720p_cmd_on_cmd144},
-{ 0x8 , nt35590_720p_cmd_on_cmd145},
-{ 0x8 , nt35590_720p_cmd_on_cmd146},
-{ 0x8 , nt35590_720p_cmd_on_cmd147},
-{ 0x8 , nt35590_720p_cmd_on_cmd148},
-{ 0x8 , nt35590_720p_cmd_on_cmd149},
-{ 0x8 , nt35590_720p_cmd_on_cmd150},
-{ 0x8 , nt35590_720p_cmd_on_cmd151},
-{ 0x8 , nt35590_720p_cmd_on_cmd152},
-{ 0x8 , nt35590_720p_cmd_on_cmd153},
-{ 0x8 , nt35590_720p_cmd_on_cmd154},
-{ 0x8 , nt35590_720p_cmd_on_cmd155},
-{ 0x8 , nt35590_720p_cmd_on_cmd156},
-{ 0x8 , nt35590_720p_cmd_on_cmd157},
-{ 0x8 , nt35590_720p_cmd_on_cmd158},
-{ 0x8 , nt35590_720p_cmd_on_cmd159},
-{ 0x8 , nt35590_720p_cmd_on_cmd160},
-{ 0x8 , nt35590_720p_cmd_on_cmd161},
-{ 0x8 , nt35590_720p_cmd_on_cmd162},
-{ 0x8 , nt35590_720p_cmd_on_cmd163},
-{ 0x8 , nt35590_720p_cmd_on_cmd164},
-{ 0x8 , nt35590_720p_cmd_on_cmd165},
-{ 0x8 , nt35590_720p_cmd_on_cmd166},
-{ 0x8 , nt35590_720p_cmd_on_cmd167},
-{ 0x8 , nt35590_720p_cmd_on_cmd168},
-{ 0x8 , nt35590_720p_cmd_on_cmd169},
-{ 0x8 , nt35590_720p_cmd_on_cmd170},
-{ 0x8 , nt35590_720p_cmd_on_cmd171},
-{ 0x8 , nt35590_720p_cmd_on_cmd172},
-{ 0x8 , nt35590_720p_cmd_on_cmd173},
-{ 0x8 , nt35590_720p_cmd_on_cmd174},
-{ 0x8 , nt35590_720p_cmd_on_cmd175},
-{ 0x8 , nt35590_720p_cmd_on_cmd176},
-{ 0x8 , nt35590_720p_cmd_on_cmd177},
-{ 0x8 , nt35590_720p_cmd_on_cmd178},
-{ 0x8 , nt35590_720p_cmd_on_cmd179},
-{ 0x8 , nt35590_720p_cmd_on_cmd180},
-{ 0x8 , nt35590_720p_cmd_on_cmd181},
-{ 0x8 , nt35590_720p_cmd_on_cmd182},
-{ 0x8 , nt35590_720p_cmd_on_cmd183},
-{ 0x8 , nt35590_720p_cmd_on_cmd184},
-{ 0x8 , nt35590_720p_cmd_on_cmd185},
-{ 0x8 , nt35590_720p_cmd_on_cmd186},
-{ 0x8 , nt35590_720p_cmd_on_cmd187},
-{ 0x8 , nt35590_720p_cmd_on_cmd188},
-{ 0x8 , nt35590_720p_cmd_on_cmd189},
-{ 0x8 , nt35590_720p_cmd_on_cmd190},
-{ 0x8 , nt35590_720p_cmd_on_cmd191},
-{ 0x8 , nt35590_720p_cmd_on_cmd192},
-{ 0x8 , nt35590_720p_cmd_on_cmd193},
-{ 0x8 , nt35590_720p_cmd_on_cmd194},
-{ 0x8 , nt35590_720p_cmd_on_cmd195},
-{ 0x8 , nt35590_720p_cmd_on_cmd196},
-{ 0x8 , nt35590_720p_cmd_on_cmd197},
-{ 0x8 , nt35590_720p_cmd_on_cmd198},
-{ 0x8 , nt35590_720p_cmd_on_cmd199},
-{ 0x8 , nt35590_720p_cmd_on_cmd200},
-{ 0x8 , nt35590_720p_cmd_on_cmd201},
-{ 0x8 , nt35590_720p_cmd_on_cmd202},
-{ 0x8 , nt35590_720p_cmd_on_cmd203},
-{ 0x8 , nt35590_720p_cmd_on_cmd204},
-{ 0x8 , nt35590_720p_cmd_on_cmd205},
-{ 0x8 , nt35590_720p_cmd_on_cmd206},
-{ 0x8 , nt35590_720p_cmd_on_cmd207},
-{ 0x8 , nt35590_720p_cmd_on_cmd208},
-{ 0x8 , nt35590_720p_cmd_on_cmd209},
-{ 0x8 , nt35590_720p_cmd_on_cmd210},
-{ 0x8 , nt35590_720p_cmd_on_cmd211},
-{ 0x8 , nt35590_720p_cmd_on_cmd212},
-{ 0x8 , nt35590_720p_cmd_on_cmd213},
-{ 0x8 , nt35590_720p_cmd_on_cmd214},
-{ 0x8 , nt35590_720p_cmd_on_cmd215},
-{ 0x8 , nt35590_720p_cmd_on_cmd216},
-{ 0x8 , nt35590_720p_cmd_on_cmd217},
-{ 0x8 , nt35590_720p_cmd_on_cmd218},
-{ 0x8 , nt35590_720p_cmd_on_cmd219},
-{ 0x8 , nt35590_720p_cmd_on_cmd220},
-{ 0x8 , nt35590_720p_cmd_on_cmd221},
-{ 0x8 , nt35590_720p_cmd_on_cmd222},
-{ 0x8 , nt35590_720p_cmd_on_cmd223},
-{ 0x8 , nt35590_720p_cmd_on_cmd224},
-{ 0x8 , nt35590_720p_cmd_on_cmd225},
-{ 0x8 , nt35590_720p_cmd_on_cmd226},
-{ 0x8 , nt35590_720p_cmd_on_cmd227},
-{ 0x8 , nt35590_720p_cmd_on_cmd228},
-{ 0x8 , nt35590_720p_cmd_on_cmd229},
-{ 0x8 , nt35590_720p_cmd_on_cmd230},
-{ 0x8 , nt35590_720p_cmd_on_cmd231},
-{ 0x8 , nt35590_720p_cmd_on_cmd232},
-{ 0x8 , nt35590_720p_cmd_on_cmd233},
-{ 0x8 , nt35590_720p_cmd_on_cmd234},
-{ 0x8 , nt35590_720p_cmd_on_cmd235},
-{ 0x8 , nt35590_720p_cmd_on_cmd236},
-{ 0x8 , nt35590_720p_cmd_on_cmd237},
-{ 0x8 , nt35590_720p_cmd_on_cmd238},
-{ 0x8 , nt35590_720p_cmd_on_cmd239},
-{ 0x8 , nt35590_720p_cmd_on_cmd240},
-{ 0x8 , nt35590_720p_cmd_on_cmd241},
-{ 0x8 , nt35590_720p_cmd_on_cmd242},
-{ 0x8 , nt35590_720p_cmd_on_cmd243},
-{ 0x8 , nt35590_720p_cmd_on_cmd244},
-{ 0x8 , nt35590_720p_cmd_on_cmd245},
-{ 0x8 , nt35590_720p_cmd_on_cmd246},
-{ 0x8 , nt35590_720p_cmd_on_cmd247},
-{ 0x8 , nt35590_720p_cmd_on_cmd248},
-{ 0x8 , nt35590_720p_cmd_on_cmd249},
-{ 0x8 , nt35590_720p_cmd_on_cmd250},
-{ 0x8 , nt35590_720p_cmd_on_cmd251},
-{ 0x8 , nt35590_720p_cmd_on_cmd252},
-{ 0x8 , nt35590_720p_cmd_on_cmd253},
-{ 0x8 , nt35590_720p_cmd_on_cmd254},
-{ 0x8 , nt35590_720p_cmd_on_cmd255},
-{ 0x8 , nt35590_720p_cmd_on_cmd256},
-{ 0x8 , nt35590_720p_cmd_on_cmd257},
-{ 0x8 , nt35590_720p_cmd_on_cmd258},
-{ 0x8 , nt35590_720p_cmd_on_cmd259},
-{ 0x8 , nt35590_720p_cmd_on_cmd260},
-{ 0x8 , nt35590_720p_cmd_on_cmd261},
-{ 0x8 , nt35590_720p_cmd_on_cmd262},
-{ 0x8 , nt35590_720p_cmd_on_cmd263},
-{ 0x8 , nt35590_720p_cmd_on_cmd264},
-{ 0x8 , nt35590_720p_cmd_on_cmd265},
-{ 0x8 , nt35590_720p_cmd_on_cmd266},
-{ 0x8 , nt35590_720p_cmd_on_cmd267},
-{ 0x8 , nt35590_720p_cmd_on_cmd268},
-{ 0x8 , nt35590_720p_cmd_on_cmd269},
-{ 0x8 , nt35590_720p_cmd_on_cmd270},
-{ 0x8 , nt35590_720p_cmd_on_cmd271},
-{ 0x8 , nt35590_720p_cmd_on_cmd272},
-{ 0x8 , nt35590_720p_cmd_on_cmd273},
-{ 0x8 , nt35590_720p_cmd_on_cmd274},
-{ 0x8 , nt35590_720p_cmd_on_cmd275},
-{ 0x8 , nt35590_720p_cmd_on_cmd276},
-{ 0x8 , nt35590_720p_cmd_on_cmd277},
-{ 0x8 , nt35590_720p_cmd_on_cmd278},
-{ 0x8 , nt35590_720p_cmd_on_cmd279},
-{ 0x8 , nt35590_720p_cmd_on_cmd280},
-{ 0x8 , nt35590_720p_cmd_on_cmd281},
-{ 0x8 , nt35590_720p_cmd_on_cmd282},
-{ 0x8 , nt35590_720p_cmd_on_cmd283},
-{ 0x8 , nt35590_720p_cmd_on_cmd284},
-{ 0x8 , nt35590_720p_cmd_on_cmd285},
-{ 0x8 , nt35590_720p_cmd_on_cmd286},
-{ 0x8 , nt35590_720p_cmd_on_cmd287},
-{ 0x8 , nt35590_720p_cmd_on_cmd288},
-{ 0x8 , nt35590_720p_cmd_on_cmd289},
-{ 0x8 , nt35590_720p_cmd_on_cmd290},
-{ 0x8 , nt35590_720p_cmd_on_cmd291},
-{ 0x8 , nt35590_720p_cmd_on_cmd292},
-{ 0x8 , nt35590_720p_cmd_on_cmd293},
-{ 0x8 , nt35590_720p_cmd_on_cmd294},
-{ 0x8 , nt35590_720p_cmd_on_cmd295},
-{ 0x8 , nt35590_720p_cmd_on_cmd296},
-{ 0x8 , nt35590_720p_cmd_on_cmd297},
-{ 0x8 , nt35590_720p_cmd_on_cmd298},
-{ 0x8 , nt35590_720p_cmd_on_cmd299},
-{ 0x8 , nt35590_720p_cmd_on_cmd300},
-{ 0x8 , nt35590_720p_cmd_on_cmd301},
-{ 0x8 , nt35590_720p_cmd_on_cmd302},
-{ 0x8 , nt35590_720p_cmd_on_cmd303},
-{ 0x8 , nt35590_720p_cmd_on_cmd304},
-{ 0x8 , nt35590_720p_cmd_on_cmd305},
-{ 0x8 , nt35590_720p_cmd_on_cmd306},
-{ 0x8 , nt35590_720p_cmd_on_cmd307},
-{ 0x8 , nt35590_720p_cmd_on_cmd308},
-{ 0x8 , nt35590_720p_cmd_on_cmd309},
-{ 0x8 , nt35590_720p_cmd_on_cmd310},
-{ 0x8 , nt35590_720p_cmd_on_cmd311},
-{ 0x8 , nt35590_720p_cmd_on_cmd312},
-{ 0x8 , nt35590_720p_cmd_on_cmd313},
-{ 0x8 , nt35590_720p_cmd_on_cmd314},
-{ 0x8 , nt35590_720p_cmd_on_cmd315},
-{ 0x8 , nt35590_720p_cmd_on_cmd316},
-{ 0x8 , nt35590_720p_cmd_on_cmd317},
-{ 0x8 , nt35590_720p_cmd_on_cmd318},
-{ 0x8 , nt35590_720p_cmd_on_cmd319},
-{ 0x8 , nt35590_720p_cmd_on_cmd320},
-{ 0x8 , nt35590_720p_cmd_on_cmd321},
-{ 0x8 , nt35590_720p_cmd_on_cmd322},
-{ 0x8 , nt35590_720p_cmd_on_cmd323},
-{ 0x8 , nt35590_720p_cmd_on_cmd324},
-{ 0x8 , nt35590_720p_cmd_on_cmd325},
-{ 0x8 , nt35590_720p_cmd_on_cmd326},
-{ 0x8 , nt35590_720p_cmd_on_cmd327},
-{ 0x8 , nt35590_720p_cmd_on_cmd328},
-{ 0x8 , nt35590_720p_cmd_on_cmd329},
-{ 0x8 , nt35590_720p_cmd_on_cmd330},
-{ 0x8 , nt35590_720p_cmd_on_cmd331},
-{ 0x8 , nt35590_720p_cmd_on_cmd332},
-{ 0x8 , nt35590_720p_cmd_on_cmd333},
-{ 0x8 , nt35590_720p_cmd_on_cmd334},
-{ 0x8 , nt35590_720p_cmd_on_cmd335},
-{ 0x8 , nt35590_720p_cmd_on_cmd336},
-{ 0x8 , nt35590_720p_cmd_on_cmd337},
-{ 0x8 , nt35590_720p_cmd_on_cmd338},
-{ 0x8 , nt35590_720p_cmd_on_cmd339},
-{ 0x8 , nt35590_720p_cmd_on_cmd340},
-{ 0x8 , nt35590_720p_cmd_on_cmd341},
-{ 0x8 , nt35590_720p_cmd_on_cmd342},
-{ 0x8 , nt35590_720p_cmd_on_cmd343},
-{ 0x8 , nt35590_720p_cmd_on_cmd344},
-{ 0x8 , nt35590_720p_cmd_on_cmd345},
-{ 0x8 , nt35590_720p_cmd_on_cmd346},
-{ 0x8 , nt35590_720p_cmd_on_cmd347},
-{ 0x8 , nt35590_720p_cmd_on_cmd348},
-{ 0x8 , nt35590_720p_cmd_on_cmd349},
-{ 0x8 , nt35590_720p_cmd_on_cmd350},
-{ 0x8 , nt35590_720p_cmd_on_cmd351},
-{ 0x8 , nt35590_720p_cmd_on_cmd352},
-{ 0x8 , nt35590_720p_cmd_on_cmd353},
-{ 0x8 , nt35590_720p_cmd_on_cmd354},
-{ 0x8 , nt35590_720p_cmd_on_cmd355},
-{ 0x8 , nt35590_720p_cmd_on_cmd356},
-{ 0x8 , nt35590_720p_cmd_on_cmd357},
-{ 0x8 , nt35590_720p_cmd_on_cmd358},
-{ 0x8 , nt35590_720p_cmd_on_cmd359},
-{ 0x8 , nt35590_720p_cmd_on_cmd360},
-{ 0x8 , nt35590_720p_cmd_on_cmd361},
-{ 0x8 , nt35590_720p_cmd_on_cmd362},
-{ 0x8 , nt35590_720p_cmd_on_cmd363},
-{ 0x8 , nt35590_720p_cmd_on_cmd364},
-{ 0x8 , nt35590_720p_cmd_on_cmd365},
-{ 0x8 , nt35590_720p_cmd_on_cmd366},
-{ 0x8 , nt35590_720p_cmd_on_cmd367},
-{ 0x8 , nt35590_720p_cmd_on_cmd368},
-{ 0x8 , nt35590_720p_cmd_on_cmd369},
-{ 0x8 , nt35590_720p_cmd_on_cmd370},
-{ 0x8 , nt35590_720p_cmd_on_cmd371},
-{ 0x8 , nt35590_720p_cmd_on_cmd372},
-{ 0x8 , nt35590_720p_cmd_on_cmd373},
-{ 0x8 , nt35590_720p_cmd_on_cmd374},
-{ 0x8 , nt35590_720p_cmd_on_cmd375},
-{ 0x8 , nt35590_720p_cmd_on_cmd376},
-{ 0x8 , nt35590_720p_cmd_on_cmd377},
-{ 0x8 , nt35590_720p_cmd_on_cmd378},
-{ 0x8 , nt35590_720p_cmd_on_cmd379},
-{ 0x8 , nt35590_720p_cmd_on_cmd380},
-{ 0x8 , nt35590_720p_cmd_on_cmd381},
-{ 0x8 , nt35590_720p_cmd_on_cmd382},
-{ 0x8 , nt35590_720p_cmd_on_cmd383},
-{ 0x8 , nt35590_720p_cmd_on_cmd384},
-{ 0x8 , nt35590_720p_cmd_on_cmd385},
-{ 0x8 , nt35590_720p_cmd_on_cmd386},
-{ 0x8 , nt35590_720p_cmd_on_cmd387},
-{ 0x8 , nt35590_720p_cmd_on_cmd388},
-{ 0x8 , nt35590_720p_cmd_on_cmd389},
-{ 0x8 , nt35590_720p_cmd_on_cmd390},
-{ 0x8 , nt35590_720p_cmd_on_cmd391},
-{ 0x8 , nt35590_720p_cmd_on_cmd392},
-{ 0x8 , nt35590_720p_cmd_on_cmd393},
-{ 0x8 , nt35590_720p_cmd_on_cmd394},
-{ 0x8 , nt35590_720p_cmd_on_cmd395},
-{ 0x8 , nt35590_720p_cmd_on_cmd396},
-{ 0x8 , nt35590_720p_cmd_on_cmd397},
-{ 0x8 , nt35590_720p_cmd_on_cmd398},
-{ 0x8 , nt35590_720p_cmd_on_cmd399},
-{ 0x8 , nt35590_720p_cmd_on_cmd400},
-{ 0x8 , nt35590_720p_cmd_on_cmd401},
-{ 0x8 , nt35590_720p_cmd_on_cmd402},
-{ 0x8 , nt35590_720p_cmd_on_cmd403},
-{ 0x8 , nt35590_720p_cmd_on_cmd404},
-{ 0x8 , nt35590_720p_cmd_on_cmd405},
-{ 0x8 , nt35590_720p_cmd_on_cmd406},
-{ 0x8 , nt35590_720p_cmd_on_cmd407},
-{ 0x8 , nt35590_720p_cmd_on_cmd408},
-{ 0x8 , nt35590_720p_cmd_on_cmd409},
-{ 0x8 , nt35590_720p_cmd_on_cmd410},
-{ 0x8 , nt35590_720p_cmd_on_cmd411},
-{ 0x8 , nt35590_720p_cmd_on_cmd412},
-{ 0x8 , nt35590_720p_cmd_on_cmd413},
-{ 0x8 , nt35590_720p_cmd_on_cmd414},
-{ 0x8 , nt35590_720p_cmd_on_cmd415},
-{ 0x8 , nt35590_720p_cmd_on_cmd416},
-{ 0x8 , nt35590_720p_cmd_on_cmd417},
-{ 0x8 , nt35590_720p_cmd_on_cmd418},
-{ 0x8 , nt35590_720p_cmd_on_cmd419},
-{ 0x8 , nt35590_720p_cmd_on_cmd420},
-{ 0x8 , nt35590_720p_cmd_on_cmd421},
-{ 0x8 , nt35590_720p_cmd_on_cmd422},
-{ 0x8 , nt35590_720p_cmd_on_cmd423},
-{ 0x8 , nt35590_720p_cmd_on_cmd424},
-{ 0x8 , nt35590_720p_cmd_on_cmd425},
-{ 0x8 , nt35590_720p_cmd_on_cmd426},
-{ 0x8 , nt35590_720p_cmd_on_cmd427},
-{ 0x8 , nt35590_720p_cmd_on_cmd428},
-{ 0x8 , nt35590_720p_cmd_on_cmd429},
-{ 0x8 , nt35590_720p_cmd_on_cmd430},
-{ 0x8 , nt35590_720p_cmd_on_cmd431},
-{ 0x8 , nt35590_720p_cmd_on_cmd432},
-{ 0x8 , nt35590_720p_cmd_on_cmd433},
-{ 0x8 , nt35590_720p_cmd_on_cmd434},
-{ 0x8 , nt35590_720p_cmd_on_cmd435},
-{ 0x8 , nt35590_720p_cmd_on_cmd436},
-{ 0x8 , nt35590_720p_cmd_on_cmd437},
-{ 0x8 , nt35590_720p_cmd_on_cmd438},
-{ 0x8 , nt35590_720p_cmd_on_cmd439},
-{ 0x8 , nt35590_720p_cmd_on_cmd440},
-{ 0x8 , nt35590_720p_cmd_on_cmd441},
-{ 0x8 , nt35590_720p_cmd_on_cmd442},
-{ 0x8 , nt35590_720p_cmd_on_cmd443},
-{ 0x8 , nt35590_720p_cmd_on_cmd444},
-{ 0x8 , nt35590_720p_cmd_on_cmd445},
-{ 0x8 , nt35590_720p_cmd_on_cmd446},
-{ 0x8 , nt35590_720p_cmd_on_cmd447},
-{ 0x8 , nt35590_720p_cmd_on_cmd448},
-{ 0x8 , nt35590_720p_cmd_on_cmd449},
-{ 0x8 , nt35590_720p_cmd_on_cmd450},
-{ 0x8 , nt35590_720p_cmd_on_cmd451},
-{ 0x8 , nt35590_720p_cmd_on_cmd452},
-{ 0x8 , nt35590_720p_cmd_on_cmd453},
-{ 0x8 , nt35590_720p_cmd_on_cmd454},
-{ 0x8 , nt35590_720p_cmd_on_cmd455},
-{ 0x8 , nt35590_720p_cmd_on_cmd456},
-{ 0x8 , nt35590_720p_cmd_on_cmd457},
-{ 0x8 , nt35590_720p_cmd_on_cmd458},
-{ 0x8 , nt35590_720p_cmd_on_cmd459},
-{ 0x8 , nt35590_720p_cmd_on_cmd460},
-{ 0x8 , nt35590_720p_cmd_on_cmd461},
-{ 0x8 , nt35590_720p_cmd_on_cmd462},
-{ 0x8 , nt35590_720p_cmd_on_cmd463}
+{ 0x8 , nt35590_720p_cmd_on_cmd0, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd1, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd2, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd3, 0x10},
+{ 0x8 , nt35590_720p_cmd_on_cmd4, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd5, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd6, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd7, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd8, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd9, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd10, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd11, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd12, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd13, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd14, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd15, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd16, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd17, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd18, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd19, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd20, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd21, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd22, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd23, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd24, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd25, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd26, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd27, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd28, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd29, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd30, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd31, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd32, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd33, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd34, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd35, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd36, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd37, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd38, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd39, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd40, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd41, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd42, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd43, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd44, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd45, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd46, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd47, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd48, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd49, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd50, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd51, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd52, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd53, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd54, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd55, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd56, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd57, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd58, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd59, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd60, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd61, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd62, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd63, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd64, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd65, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd66, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd67, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd68, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd69, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd70, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd71, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd72, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd73, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd74, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd75, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd76, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd77, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd78, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd79, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd80, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd81, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd82, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd83, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd84, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd85, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd86, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd87, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd88, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd89, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd90, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd91, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd92, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd93, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd94, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd95, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd96, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd97, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd98, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd99, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd100, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd101, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd102, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd103, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd104, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd105, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd106, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd107, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd108, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd109, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd110, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd111, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd112, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd113, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd114, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd115, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd116, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd117, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd118, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd119, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd120, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd121, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd122, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd123, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd124, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd125, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd126, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd127, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd128, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd129, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd130, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd131, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd132, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd133, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd134, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd135, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd136, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd137, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd138, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd139, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd140, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd141, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd142, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd143, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd144, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd145, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd146, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd147, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd148, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd149, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd150, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd151, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd152, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd153, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd154, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd155, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd156, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd157, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd158, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd159, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd160, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd161, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd162, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd163, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd164, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd165, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd166, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd167, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd168, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd169, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd170, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd171, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd172, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd173, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd174, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd175, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd176, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd177, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd178, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd179, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd180, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd181, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd182, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd183, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd184, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd185, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd186, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd187, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd188, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd189, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd190, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd191, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd192, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd193, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd194, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd195, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd196, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd197, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd198, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd199, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd200, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd201, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd202, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd203, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd204, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd205, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd206, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd207, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd208, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd209, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd210, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd211, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd212, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd213, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd214, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd215, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd216, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd217, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd218, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd219, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd220, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd221, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd222, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd223, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd224, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd225, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd226, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd227, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd228, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd229, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd230, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd231, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd232, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd233, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd234, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd235, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd236, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd237, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd238, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd239, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd240, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd241, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd242, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd243, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd244, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd245, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd246, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd247, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd248, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd249, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd250, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd251, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd252, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd253, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd254, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd255, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd256, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd257, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd258, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd259, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd260, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd261, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd262, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd263, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd264, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd265, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd266, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd267, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd268, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd269, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd270, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd271, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd272, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd273, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd274, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd275, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd276, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd277, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd278, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd279, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd280, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd281, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd282, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd283, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd284, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd285, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd286, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd287, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd288, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd289, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd290, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd291, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd292, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd293, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd294, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd295, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd296, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd297, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd298, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd299, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd300, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd301, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd302, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd303, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd304, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd305, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd306, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd307, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd308, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd309, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd310, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd311, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd312, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd313, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd314, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd315, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd316, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd317, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd318, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd319, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd320, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd321, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd322, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd323, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd324, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd325, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd326, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd327, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd328, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd329, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd330, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd331, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd332, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd333, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd334, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd335, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd336, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd337, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd338, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd339, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd340, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd341, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd342, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd343, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd344, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd345, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd346, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd347, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd348, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd349, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd350, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd351, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd352, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd353, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd354, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd355, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd356, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd357, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd358, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd359, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd360, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd361, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd362, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd363, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd364, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd365, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd366, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd367, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd368, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd369, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd370, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd371, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd372, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd373, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd374, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd375, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd376, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd377, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd378, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd379, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd380, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd381, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd382, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd383, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd384, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd385, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd386, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd387, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd388, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd389, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd390, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd391, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd392, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd393, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd394, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd395, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd396, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd397, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd398, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd399, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd400, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd401, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd402, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd403, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd404, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd405, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd406, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd407, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd408, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd409, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd410, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd411, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd412, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd413, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd414, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd415, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd416, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd417, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd418, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd419, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd420, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd421, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd422, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd423, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd424, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd425, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd426, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd427, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd428, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd429, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd430, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd431, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd432, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd433, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd434, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd435, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd436, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd437, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd438, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd439, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd440, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd441, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd442, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd443, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd444, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd445, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd446, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd447, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd448, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd449, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd450, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd451, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd452, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd453, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd454, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd455, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd456, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd457, 0x64},
+{ 0x8 , nt35590_720p_cmd_on_cmd458, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd459, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd460, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd461, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd462, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd463, 0x78}
};
#define NT35590_720P_CMD_ON_COMMAND 464
diff --git a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
index a25afd8..2cd3d07 100644
--- a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
+++ b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
@@ -541,22 +541,22 @@
static char nt35596_1080p_skuk_video_on_cmd95[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0E, 0xBF, 0xFF, 0xFF,
+ 0x0E, 0xB5, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd96[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0F, 0xC2, 0xFF, 0xFF,
+ 0x0F, 0xB8, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd97[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0B, 0xB3, 0xFF, 0xFF,
+ 0x0B, 0x55, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd98[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0C, 0xB3, 0xFF, 0xFF,
+ 0x0C, 0x55, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd99[] = {
@@ -586,1877 +586,1882 @@
static char nt35596_1080p_skuk_video_on_cmd104[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x75, 0x00, 0xFF, 0xFF,
+ 0xFF, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd105[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x76, 0x00, 0xFF, 0xFF,
+ 0xFB, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd106[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x77, 0x00, 0xFF, 0xFF,
+ 0x75, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd107[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x78, 0x09, 0xFF, 0xFF,
+ 0x76, 0x10, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd108[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x79, 0x00, 0xFF, 0xFF,
+ 0x77, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd109[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7A, 0x1D, 0xFF, 0xFF,
+ 0x78, 0x1D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd110[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7B, 0x00, 0xFF, 0xFF,
+ 0x79, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd111[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7C, 0x2E, 0xFF, 0xFF,
+ 0x7A, 0x32, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd112[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7D, 0x00, 0xFF, 0xFF,
+ 0x7B, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd113[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7E, 0x3D, 0xFF, 0xFF,
+ 0x7C, 0x44, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd114[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7F, 0x00, 0xFF, 0xFF,
+ 0x7D, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd115[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x80, 0x4C, 0xFF, 0xFF,
+ 0x7E, 0x54, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd116[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x81, 0x00, 0xFF, 0xFF,
+ 0x7F, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd117[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x82, 0x59, 0xFF, 0xFF,
+ 0x80, 0x63, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd118[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x83, 0x00, 0xFF, 0xFF,
+ 0x81, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd119[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x84, 0x66, 0xFF, 0xFF,
+ 0x82, 0x71, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd120[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x85, 0x00, 0xFF, 0xFF,
+ 0x83, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd121[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x86, 0x73, 0xFF, 0xFF,
+ 0x84, 0x7D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd122[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x87, 0x00, 0xFF, 0xFF,
+ 0x85, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd123[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x88, 0xA0, 0xFF, 0xFF,
+ 0x86, 0x89, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd124[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x89, 0x00, 0xFF, 0xFF,
+ 0x87, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd125[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8A, 0xC7, 0xFF, 0xFF,
+ 0x88, 0xB2, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd126[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8B, 0x01, 0xFF, 0xFF,
+ 0x89, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd127[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8C, 0x0C, 0xFF, 0xFF,
+ 0x8A, 0xD5, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd128[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8D, 0x01, 0xFF, 0xFF,
+ 0x8B, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd129[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8E, 0x46, 0xFF, 0xFF,
+ 0x8C, 0x0D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd130[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8F, 0x01, 0xFF, 0xFF,
+ 0x8D, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd131[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x90, 0xA4, 0xFF, 0xFF,
+ 0x8E, 0x3B, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd132[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x91, 0x01, 0xFF, 0xFF,
+ 0x8F, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd133[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x92, 0xF1, 0xFF, 0xFF,
+ 0x90, 0x87, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd134[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x93, 0x01, 0xFF, 0xFF,
+ 0x91, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd135[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x94, 0xF3, 0xFF, 0xFF,
+ 0x92, 0xC6, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd136[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x95, 0x02, 0xFF, 0xFF,
+ 0x93, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd137[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x96, 0x36, 0xFF, 0xFF,
+ 0x94, 0xC8, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd138[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x97, 0x02, 0xFF, 0xFF,
+ 0x95, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd139[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x98, 0x7B, 0xFF, 0xFF,
+ 0x96, 0x04, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd140[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x99, 0x02, 0xFF, 0xFF,
+ 0x97, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd141[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9A, 0xA3, 0xFF, 0xFF,
+ 0x98, 0x47, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd142[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9B, 0x02, 0xFF, 0xFF,
+ 0x99, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd143[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9C, 0xD6, 0xFF, 0xFF,
+ 0x9A, 0x72, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd144[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9D, 0x02, 0xFF, 0xFF,
+ 0x9B, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd145[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9E, 0xF9, 0xFF, 0xFF,
+ 0x9C, 0xAC, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd146[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9F, 0x03, 0xFF, 0xFF,
+ 0x9D, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd147[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA0, 0x26, 0xFF, 0xFF,
+ 0x9E, 0xD3, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd148[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA2, 0x03, 0xFF, 0xFF,
+ 0x9F, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd149[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA3, 0x34, 0xFF, 0xFF,
+ 0xA0, 0x07, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd150[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA4, 0x03, 0xFF, 0xFF,
+ 0xA2, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd151[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA5, 0x43, 0xFF, 0xFF,
+ 0xA3, 0x17, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd152[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA6, 0x03, 0xFF, 0xFF,
+ 0xA4, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd153[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA7, 0x55, 0xFF, 0xFF,
+ 0xA5, 0x29, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd154[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA9, 0x03, 0xFF, 0xFF,
+ 0xA6, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd155[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAA, 0x6A, 0xFF, 0xFF,
+ 0xA7, 0x3D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd156[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAB, 0x03, 0xFF, 0xFF,
+ 0xA9, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd157[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAC, 0x81, 0xFF, 0xFF,
+ 0xAA, 0x52, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd158[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAD, 0x03, 0xFF, 0xFF,
+ 0xAB, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd159[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAE, 0x9F, 0xFF, 0xFF,
+ 0xAC, 0x6E, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd160[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAF, 0x03, 0xFF, 0xFF,
+ 0xAD, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd161[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB0, 0xD1, 0xFF, 0xFF,
+ 0xAE, 0x8D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd162[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB1, 0x03, 0xFF, 0xFF,
+ 0xAF, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd163[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB2, 0xFF, 0xFF, 0xFF,
+ 0xB0, 0xB0, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd164[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB3, 0x00, 0xFF, 0xFF,
+ 0xB1, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd165[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB4, 0x00, 0xFF, 0xFF,
+ 0xB2, 0xBF, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd166[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB5, 0x00, 0xFF, 0xFF,
+ 0xB3, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd167[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB6, 0x09, 0xFF, 0xFF,
+ 0xB4, 0x10, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd168[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB7, 0x00, 0xFF, 0xFF,
+ 0xB5, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd169[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB8, 0x1D, 0xFF, 0xFF,
+ 0xB6, 0x1D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd170[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB9, 0x00, 0xFF, 0xFF,
+ 0xB7, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd171[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBA, 0x2E, 0xFF, 0xFF,
+ 0xB8, 0x32, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd172[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBB, 0x00, 0xFF, 0xFF,
+ 0xB9, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd173[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBC, 0x3D, 0xFF, 0xFF,
+ 0xBA, 0x44, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd174[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBD, 0x00, 0xFF, 0xFF,
+ 0xBB, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd175[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBE, 0x4C, 0xFF, 0xFF,
+ 0xBC, 0x54, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd176[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBF, 0x00, 0xFF, 0xFF,
+ 0xBD, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd177[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC0, 0x59, 0xFF, 0xFF,
+ 0xBE, 0x63, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd178[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC1, 0x00, 0xFF, 0xFF,
+ 0xBF, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd179[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC2, 0x66, 0xFF, 0xFF,
+ 0xC0, 0x71, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd180[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC3, 0x00, 0xFF, 0xFF,
+ 0xC1, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd181[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC4, 0x73, 0xFF, 0xFF,
+ 0xC2, 0x7D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd182[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC5, 0x00, 0xFF, 0xFF,
+ 0xC3, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd183[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC6, 0xA0, 0xFF, 0xFF,
+ 0xC4, 0x89, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd184[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC7, 0x00, 0xFF, 0xFF,
+ 0xC5, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd185[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC8, 0xC7, 0xFF, 0xFF,
+ 0xC6, 0xB2, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd186[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC9, 0x01, 0xFF, 0xFF,
+ 0xC7, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd187[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCA, 0x0C, 0xFF, 0xFF,
+ 0xC8, 0xD5, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd188[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCB, 0x01, 0xFF, 0xFF,
+ 0xC9, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd189[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCC, 0x46, 0xFF, 0xFF,
+ 0xCA, 0x0D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd190[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCD, 0x01, 0xFF, 0xFF,
+ 0xCB, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd191[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCE, 0xA4, 0xFF, 0xFF,
+ 0xCC, 0x3B, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd192[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCF, 0x01, 0xFF, 0xFF,
+ 0xCD, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd193[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD0, 0xF1, 0xFF, 0xFF,
+ 0xCE, 0x87, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd194[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD1, 0x01, 0xFF, 0xFF,
+ 0xCF, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd195[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD2, 0xF3, 0xFF, 0xFF,
+ 0xD0, 0xC6, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd196[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD3, 0x02, 0xFF, 0xFF,
+ 0xD1, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd197[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD4, 0x36, 0xFF, 0xFF,
+ 0xD2, 0xC8, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd198[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD5, 0x02, 0xFF, 0xFF,
+ 0xD3, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd199[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD6, 0x7B, 0xFF, 0xFF,
+ 0xD4, 0x04, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd200[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD7, 0x02, 0xFF, 0xFF,
+ 0xD5, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd201[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD8, 0xA3, 0xFF, 0xFF,
+ 0xD6, 0x47, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd202[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD9, 0x02, 0xFF, 0xFF,
+ 0xD7, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd203[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDA, 0xD6, 0xFF, 0xFF,
+ 0xD8, 0x72, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd204[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDB, 0x02, 0xFF, 0xFF,
+ 0xD9, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd205[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDC, 0xF9, 0xFF, 0xFF,
+ 0xDA, 0xAC, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd206[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDD, 0x03, 0xFF, 0xFF,
+ 0xDB, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd207[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDE, 0x26, 0xFF, 0xFF,
+ 0xDC, 0xD3, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd208[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDF, 0x03, 0xFF, 0xFF,
+ 0xDD, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd209[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE0, 0x34, 0xFF, 0xFF,
+ 0xDE, 0x07, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd210[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE1, 0x03, 0xFF, 0xFF,
+ 0xDF, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd211[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE2, 0x43, 0xFF, 0xFF,
+ 0xE0, 0x17, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd212[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE3, 0x03, 0xFF, 0xFF,
+ 0xE1, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd213[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE4, 0x55, 0xFF, 0xFF,
+ 0xE2, 0x29, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd214[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE5, 0x03, 0xFF, 0xFF,
+ 0xE3, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd215[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE6, 0x6A, 0xFF, 0xFF,
+ 0xE4, 0x3D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd216[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE7, 0x03, 0xFF, 0xFF,
+ 0xE5, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd217[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE8, 0x81, 0xFF, 0xFF,
+ 0xE6, 0x52, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd218[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE9, 0x03, 0xFF, 0xFF,
+ 0xE7, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd219[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xEA, 0x9F, 0xFF, 0xFF,
+ 0xE8, 0x6E, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd220[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xEB, 0x03, 0xFF, 0xFF,
+ 0xE9, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd221[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xEC, 0xD1, 0xFF, 0xFF,
+ 0xEA, 0x8D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd222[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xED, 0x03, 0xFF, 0xFF,
+ 0xEB, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd223[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xEE, 0xFF, 0xFF, 0xFF,
+ 0xEC, 0xB0, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd224[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xEF, 0x00, 0xFF, 0xFF,
+ 0xED, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd225[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF0, 0x00, 0xFF, 0xFF,
+ 0xEE, 0xBF, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd226[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF1, 0x00, 0xFF, 0xFF,
+ 0xEF, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd227[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF2, 0x09, 0xFF, 0xFF,
+ 0xF0, 0x10, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd228[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF3, 0x00, 0xFF, 0xFF,
+ 0xF1, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd229[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF4, 0x1D, 0xFF, 0xFF,
+ 0xF2, 0x1D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd230[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF5, 0x00, 0xFF, 0xFF,
+ 0xF3, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd231[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF6, 0x2E, 0xFF, 0xFF,
+ 0xF4, 0x32, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd232[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF7, 0x00, 0xFF, 0xFF,
+ 0xF5, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd233[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF8, 0x3D, 0xFF, 0xFF,
+ 0xF6, 0x44, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd234[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xF9, 0x00, 0xFF, 0xFF,
+ 0xF7, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd235[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xFA, 0x4C, 0xFF, 0xFF,
+ 0xF8, 0x54, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd236[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xFF, 0x02, 0xFF, 0xFF,
+ 0xF9, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd237[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xFB, 0x01, 0xFF, 0xFF,
+ 0xFA, 0x63, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd238[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x00, 0x00, 0xFF, 0xFF,
+ 0xFF, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd239[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x01, 0x59, 0xFF, 0xFF,
+ 0xFB, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd240[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x02, 0x00, 0xFF, 0xFF,
+ 0x00, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd241[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x03, 0x66, 0xFF, 0xFF,
+ 0x01, 0x71, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd242[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x04, 0x00, 0xFF, 0xFF,
+ 0x02, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd243[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x05, 0x73, 0xFF, 0xFF,
+ 0x03, 0x7D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd244[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x06, 0x00, 0xFF, 0xFF,
+ 0x04, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd245[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x07, 0xA0, 0xFF, 0xFF,
+ 0x05, 0x89, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd246[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x08, 0x00, 0xFF, 0xFF,
+ 0x06, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd247[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x09, 0xC7, 0xFF, 0xFF,
+ 0x07, 0xB2, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd248[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0A, 0x01, 0xFF, 0xFF,
+ 0x08, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd249[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0B, 0x0C, 0xFF, 0xFF,
+ 0x09, 0xD5, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd250[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0C, 0x01, 0xFF, 0xFF,
+ 0x0A, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd251[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0D, 0x46, 0xFF, 0xFF,
+ 0x0B, 0x0D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd252[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0E, 0x01, 0xFF, 0xFF,
+ 0x0C, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd253[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x0F, 0xA4, 0xFF, 0xFF,
+ 0x0D, 0x3B, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd254[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x10, 0x01, 0xFF, 0xFF,
+ 0x0E, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd255[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x11, 0xF1, 0xFF, 0xFF,
+ 0x0F, 0x87, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd256[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x12, 0x01, 0xFF, 0xFF,
+ 0x10, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd257[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x13, 0xF3, 0xFF, 0xFF,
+ 0x11, 0xC6, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd258[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x14, 0x02, 0xFF, 0xFF,
+ 0x12, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd259[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x15, 0x36, 0xFF, 0xFF,
+ 0x13, 0xC8, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd260[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x16, 0x02, 0xFF, 0xFF,
+ 0x14, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd261[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x17, 0x7B, 0xFF, 0xFF,
+ 0x15, 0x04, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd262[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x18, 0x02, 0xFF, 0xFF,
+ 0x16, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd263[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x19, 0xA3, 0xFF, 0xFF,
+ 0x17, 0x47, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd264[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x1A, 0x02, 0xFF, 0xFF,
+ 0x18, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd265[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x1B, 0xD6, 0xFF, 0xFF,
+ 0x19, 0x72, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd266[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x1C, 0x02, 0xFF, 0xFF,
+ 0x1A, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd267[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x1D, 0xF9, 0xFF, 0xFF,
+ 0x1B, 0xAC, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd268[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x1E, 0x03, 0xFF, 0xFF,
+ 0x1C, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd269[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x1F, 0x26, 0xFF, 0xFF,
+ 0x1D, 0xD3, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd270[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x20, 0x03, 0xFF, 0xFF,
+ 0x1E, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd271[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x21, 0x34, 0xFF, 0xFF,
+ 0x1F, 0x07, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd272[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x22, 0x03, 0xFF, 0xFF,
+ 0x20, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd273[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x23, 0x43, 0xFF, 0xFF,
+ 0x21, 0x17, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd274[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x24, 0x03, 0xFF, 0xFF,
+ 0x22, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd275[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x25, 0x55, 0xFF, 0xFF,
+ 0x23, 0x29, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd276[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x26, 0x03, 0xFF, 0xFF,
+ 0x24, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd277[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x27, 0x6A, 0xFF, 0xFF,
+ 0x25, 0x3D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd278[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x28, 0x03, 0xFF, 0xFF,
+ 0x26, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd279[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x29, 0x81, 0xFF, 0xFF,
+ 0x27, 0x52, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd280[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x2A, 0x03, 0xFF, 0xFF,
+ 0x28, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd281[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x2B, 0x9F, 0xFF, 0xFF,
+ 0x29, 0x6E, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd282[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x2D, 0x03, 0xFF, 0xFF,
+ 0x2A, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd283[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x2F, 0xD1, 0xFF, 0xFF,
+ 0x2B, 0x8D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd284[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x30, 0x03, 0xFF, 0xFF,
+ 0x2D, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd285[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x31, 0xFF, 0xFF, 0xFF,
+ 0x2F, 0xB0, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd286[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x32, 0x00, 0xFF, 0xFF,
+ 0x30, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd287[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x33, 0x00, 0xFF, 0xFF,
+ 0x31, 0xBF, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd288[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x34, 0x00, 0xFF, 0xFF,
+ 0x32, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd289[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x35, 0x09, 0xFF, 0xFF,
+ 0x33, 0x10, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd290[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x36, 0x00, 0xFF, 0xFF,
+ 0x34, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd291[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x37, 0x1D, 0xFF, 0xFF,
+ 0x35, 0x1D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd292[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x38, 0x00, 0xFF, 0xFF,
+ 0x36, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd293[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x39, 0x2E, 0xFF, 0xFF,
+ 0x37, 0x32, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd294[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x3A, 0x00, 0xFF, 0xFF,
+ 0x38, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd295[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x3B, 0x3D, 0xFF, 0xFF,
+ 0x39, 0x44, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd296[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x3D, 0x00, 0xFF, 0xFF,
+ 0x3A, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd297[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x3F, 0x4C, 0xFF, 0xFF,
+ 0x3B, 0x54, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd298[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x40, 0x00, 0xFF, 0xFF,
+ 0x3D, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd299[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x41, 0x59, 0xFF, 0xFF,
+ 0x3F, 0x63, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd300[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x42, 0x00, 0xFF, 0xFF,
+ 0x40, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd301[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x43, 0x66, 0xFF, 0xFF,
+ 0x41, 0x71, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd302[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x44, 0x00, 0xFF, 0xFF,
+ 0x42, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd303[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x45, 0x73, 0xFF, 0xFF,
+ 0x43, 0x7D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd304[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x46, 0x00, 0xFF, 0xFF,
+ 0x44, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd305[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x47, 0xA0, 0xFF, 0xFF,
+ 0x45, 0x89, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd306[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x48, 0x00, 0xFF, 0xFF,
+ 0x46, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd307[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x49, 0xC7, 0xFF, 0xFF,
+ 0x47, 0xB2, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd308[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x4A, 0x01, 0xFF, 0xFF,
+ 0x48, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd309[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x4B, 0x0C, 0xFF, 0xFF,
+ 0x49, 0xD5, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd310[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x4C, 0x01, 0xFF, 0xFF,
+ 0x4A, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd311[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x4D, 0x46, 0xFF, 0xFF,
+ 0x4B, 0x0D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd312[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x4E, 0x01, 0xFF, 0xFF,
+ 0x4C, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd313[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x4F, 0xA4, 0xFF, 0xFF,
+ 0x4D, 0x3B, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd314[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x50, 0x01, 0xFF, 0xFF,
+ 0x4E, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd315[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x51, 0xF1, 0xFF, 0xFF,
+ 0x4F, 0x87, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd316[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x52, 0x01, 0xFF, 0xFF,
+ 0x50, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd317[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x53, 0xF3, 0xFF, 0xFF,
+ 0x51, 0xC6, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd318[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x54, 0x02, 0xFF, 0xFF,
+ 0x52, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd319[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x55, 0x36, 0xFF, 0xFF,
+ 0x53, 0xC8, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd320[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x56, 0x02, 0xFF, 0xFF,
+ 0x54, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd321[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x58, 0x7B, 0xFF, 0xFF,
+ 0x55, 0x04, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd322[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x59, 0x02, 0xFF, 0xFF,
+ 0x56, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd323[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x5A, 0xA3, 0xFF, 0xFF,
+ 0x58, 0x47, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd324[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x5B, 0x02, 0xFF, 0xFF,
+ 0x59, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd325[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x5C, 0xD6, 0xFF, 0xFF,
+ 0x5A, 0x72, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd326[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x5D, 0x02, 0xFF, 0xFF,
+ 0x5B, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd327[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x5E, 0xF9, 0xFF, 0xFF,
+ 0x5C, 0xAC, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd328[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x5F, 0x03, 0xFF, 0xFF,
+ 0x5D, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd329[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x60, 0x26, 0xFF, 0xFF,
+ 0x5E, 0xD3, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd330[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x61, 0x03, 0xFF, 0xFF,
+ 0x5F, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd331[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x62, 0x34, 0xFF, 0xFF,
+ 0x60, 0x07, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd332[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x63, 0x03, 0xFF, 0xFF,
+ 0x61, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd333[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x64, 0x43, 0xFF, 0xFF,
+ 0x62, 0x17, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd334[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x65, 0x03, 0xFF, 0xFF,
+ 0x63, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd335[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x66, 0x55, 0xFF, 0xFF,
+ 0x64, 0x29, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd336[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x67, 0x03, 0xFF, 0xFF,
+ 0x65, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd337[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x68, 0x6A, 0xFF, 0xFF,
+ 0x66, 0x3D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd338[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x69, 0x03, 0xFF, 0xFF,
+ 0x67, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd339[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x6A, 0x81, 0xFF, 0xFF,
+ 0x68, 0x52, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd340[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x6B, 0x03, 0xFF, 0xFF,
+ 0x69, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd341[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x6C, 0x9F, 0xFF, 0xFF,
+ 0x6A, 0x6E, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd342[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x6D, 0x03, 0xFF, 0xFF,
+ 0x6B, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd343[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x6E, 0xD1, 0xFF, 0xFF,
+ 0x6C, 0x8D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd344[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x6F, 0x03, 0xFF, 0xFF,
+ 0x6D, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd345[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x70, 0xFF, 0xFF, 0xFF,
+ 0x6E, 0xB0, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd346[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x71, 0x00, 0xFF, 0xFF,
+ 0x6F, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd347[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x72, 0x00, 0xFF, 0xFF,
+ 0x70, 0xBF, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd348[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x73, 0x00, 0xFF, 0xFF,
+ 0x71, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd349[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x74, 0x09, 0xFF, 0xFF,
+ 0x72, 0x10, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd350[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x75, 0x00, 0xFF, 0xFF,
+ 0x73, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd351[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x76, 0x1D, 0xFF, 0xFF,
+ 0x74, 0x1D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd352[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x77, 0x00, 0xFF, 0xFF,
+ 0x75, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd353[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x78, 0x2E, 0xFF, 0xFF,
+ 0x76, 0x32, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd354[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x79, 0x00, 0xFF, 0xFF,
+ 0x77, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd355[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7A, 0x3D, 0xFF, 0xFF,
+ 0x78, 0x44, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd356[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7B, 0x00, 0xFF, 0xFF,
+ 0x79, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd357[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7C, 0x4C, 0xFF, 0xFF,
+ 0x7A, 0x54, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd358[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7D, 0x00, 0xFF, 0xFF,
+ 0x7B, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd359[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7E, 0x59, 0xFF, 0xFF,
+ 0x7C, 0x63, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd360[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x7F, 0x00, 0xFF, 0xFF,
+ 0x7D, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd361[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x80, 0x66, 0xFF, 0xFF,
+ 0x7E, 0x71, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd362[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x81, 0x00, 0xFF, 0xFF,
+ 0x7F, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd363[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x82, 0x73, 0xFF, 0xFF,
+ 0x80, 0x7D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd364[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x83, 0x00, 0xFF, 0xFF,
+ 0x81, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd365[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x84, 0xA0, 0xFF, 0xFF,
+ 0x82, 0x89, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd366[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x85, 0x00, 0xFF, 0xFF,
+ 0x83, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd367[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x86, 0xC7, 0xFF, 0xFF,
+ 0x84, 0xB2, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd368[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x87, 0x01, 0xFF, 0xFF,
+ 0x85, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd369[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x88, 0x0C, 0xFF, 0xFF,
+ 0x86, 0xD5, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd370[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x89, 0x01, 0xFF, 0xFF,
+ 0x87, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd371[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8A, 0x46, 0xFF, 0xFF,
+ 0x88, 0x0D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd372[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8B, 0x01, 0xFF, 0xFF,
+ 0x89, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd373[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8C, 0xA4, 0xFF, 0xFF,
+ 0x8A, 0x3B, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd374[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8D, 0x01, 0xFF, 0xFF,
+ 0x8B, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd375[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8E, 0xF1, 0xFF, 0xFF,
+ 0x8C, 0x87, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd376[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x8F, 0x01, 0xFF, 0xFF,
+ 0x8D, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd377[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x90, 0xF3, 0xFF, 0xFF,
+ 0x8E, 0xC6, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd378[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x91, 0x02, 0xFF, 0xFF,
+ 0x8F, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd379[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x92, 0x36, 0xFF, 0xFF,
+ 0x90, 0xC8, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd380[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x93, 0x02, 0xFF, 0xFF,
+ 0x91, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd381[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x94, 0x7B, 0xFF, 0xFF,
+ 0x92, 0x04, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd382[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x95, 0x02, 0xFF, 0xFF,
+ 0x93, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd383[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x96, 0xA3, 0xFF, 0xFF,
+ 0x94, 0x47, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd384[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x97, 0x02, 0xFF, 0xFF,
+ 0x95, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd385[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x98, 0xD6, 0xFF, 0xFF,
+ 0x96, 0x72, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd386[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x99, 0x02, 0xFF, 0xFF,
+ 0x97, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd387[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9A, 0xF9, 0xFF, 0xFF,
+ 0x98, 0xAC, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd388[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9B, 0x03, 0xFF, 0xFF,
+ 0x99, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd389[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9C, 0x26, 0xFF, 0xFF,
+ 0x9A, 0xD3, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd390[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9D, 0x03, 0xFF, 0xFF,
+ 0x9B, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd391[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9E, 0x34, 0xFF, 0xFF,
+ 0x9C, 0x07, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd392[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x9F, 0x03, 0xFF, 0xFF,
+ 0x9D, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd393[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA0, 0x43, 0xFF, 0xFF,
+ 0x9E, 0x17, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd394[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA2, 0x03, 0xFF, 0xFF,
+ 0x9F, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd395[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA3, 0x55, 0xFF, 0xFF,
+ 0xA0, 0x29, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd396[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA4, 0x03, 0xFF, 0xFF,
+ 0xA2, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd397[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA5, 0x6A, 0xFF, 0xFF,
+ 0xA3, 0x3D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd398[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA6, 0x03, 0xFF, 0xFF,
+ 0xA4, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd399[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA7, 0x81, 0xFF, 0xFF,
+ 0xA5, 0x52, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd400[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xA9, 0x03, 0xFF, 0xFF,
+ 0xA6, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd401[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAA, 0x9F, 0xFF, 0xFF,
+ 0xA7, 0x6E, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd402[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAB, 0x03, 0xFF, 0xFF,
+ 0xA9, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd403[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAC, 0xD1, 0xFF, 0xFF,
+ 0xAA, 0x8D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd404[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAD, 0x03, 0xFF, 0xFF,
+ 0xAB, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd405[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAE, 0xFF, 0xFF, 0xFF,
+ 0xAC, 0xB0, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd406[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xAF, 0x00, 0xFF, 0xFF,
+ 0xAD, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd407[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB0, 0x00, 0xFF, 0xFF,
+ 0xAE, 0xBF, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd408[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB1, 0x00, 0xFF, 0xFF,
+ 0xAF, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd409[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB2, 0x09, 0xFF, 0xFF,
+ 0xB0, 0x10, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd410[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB3, 0x00, 0xFF, 0xFF,
+ 0xB1, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd411[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB4, 0x1D, 0xFF, 0xFF,
+ 0xB2, 0x1D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd412[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB5, 0x00, 0xFF, 0xFF,
+ 0xB3, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd413[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB6, 0x2E, 0xFF, 0xFF,
+ 0xB4, 0x32, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd414[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB7, 0x00, 0xFF, 0xFF,
+ 0xB5, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd415[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB8, 0x3D, 0xFF, 0xFF,
+ 0xB6, 0x44, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd416[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xB9, 0x00, 0xFF, 0xFF,
+ 0xB7, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd417[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBA, 0x4C, 0xFF, 0xFF,
+ 0xB8, 0x54, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd418[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBB, 0x00, 0xFF, 0xFF,
+ 0xB9, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd419[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBC, 0x59, 0xFF, 0xFF,
+ 0xBA, 0x63, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd420[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBD, 0x00, 0xFF, 0xFF,
+ 0xBB, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd421[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBE, 0x66, 0xFF, 0xFF,
+ 0xBC, 0x71, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd422[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xBF, 0x00, 0xFF, 0xFF,
+ 0xBD, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd423[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC0, 0x73, 0xFF, 0xFF,
+ 0xBE, 0x7D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd424[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC1, 0x00, 0xFF, 0xFF,
+ 0xBF, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd425[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC2, 0xA0, 0xFF, 0xFF,
+ 0xC0, 0x89, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd426[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC3, 0x00, 0xFF, 0xFF,
+ 0xC1, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd427[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC4, 0xC7, 0xFF, 0xFF,
+ 0xC2, 0xB2, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd428[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC5, 0x01, 0xFF, 0xFF,
+ 0xC3, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd429[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC6, 0x0C, 0xFF, 0xFF,
+ 0xC4, 0xD5, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd430[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC7, 0x01, 0xFF, 0xFF,
+ 0xC5, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd431[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC8, 0x46, 0xFF, 0xFF,
+ 0xC6, 0x0D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd432[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xC9, 0x01, 0xFF, 0xFF,
+ 0xC7, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd433[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCA, 0xA4, 0xFF, 0xFF,
+ 0xC8, 0x3B, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd434[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCB, 0x01, 0xFF, 0xFF,
+ 0xC9, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd435[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCC, 0xF1, 0xFF, 0xFF,
+ 0xCA, 0x87, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd436[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCD, 0x01, 0xFF, 0xFF,
+ 0xCB, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd437[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCE, 0xF3, 0xFF, 0xFF,
+ 0xCC, 0xC6, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd438[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xCF, 0x02, 0xFF, 0xFF,
+ 0xCD, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd439[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD0, 0x36, 0xFF, 0xFF,
+ 0xCE, 0xC8, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd440[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD1, 0x02, 0xFF, 0xFF,
+ 0xCF, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd441[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD2, 0x7B, 0xFF, 0xFF,
+ 0xD0, 0x04, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd442[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD3, 0x02, 0xFF, 0xFF,
+ 0xD1, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd443[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD4, 0xA3, 0xFF, 0xFF,
+ 0xD2, 0x47, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd444[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD5, 0x02, 0xFF, 0xFF,
+ 0xD3, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd445[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD6, 0xD6, 0xFF, 0xFF,
+ 0xD4, 0x72, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd446[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD7, 0x02, 0xFF, 0xFF,
+ 0xD5, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd447[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD8, 0xF9, 0xFF, 0xFF,
+ 0xD6, 0xAC, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd448[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD9, 0x03, 0xFF, 0xFF,
+ 0xD7, 0x02, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd449[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDA, 0x26, 0xFF, 0xFF,
+ 0xD8, 0xD3, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd450[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDB, 0x03, 0xFF, 0xFF,
+ 0xD9, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd451[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDC, 0x34, 0xFF, 0xFF,
+ 0xDA, 0x07, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd452[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDD, 0x03, 0xFF, 0xFF,
+ 0xDB, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd453[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDE, 0x43, 0xFF, 0xFF,
+ 0xDC, 0x17, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd454[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xDF, 0x03, 0xFF, 0xFF,
+ 0xDD, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd455[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE0, 0x55, 0xFF, 0xFF,
+ 0xDE, 0x29, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd456[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE1, 0x03, 0xFF, 0xFF,
+ 0xDF, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd457[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE2, 0x6A, 0xFF, 0xFF,
+ 0xE0, 0x3D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd458[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE3, 0x03, 0xFF, 0xFF,
+ 0xE1, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd459[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE4, 0x81, 0xFF, 0xFF,
+ 0xE2, 0x52, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd460[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE5, 0x03, 0xFF, 0xFF,
+ 0xE3, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd461[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE6, 0x9F, 0xFF, 0xFF,
+ 0xE4, 0x6E, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd462[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE7, 0x03, 0xFF, 0xFF,
+ 0xE5, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd463[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE8, 0xD1, 0xFF, 0xFF,
+ 0xE6, 0x8D, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd464[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xE9, 0x03, 0xFF, 0xFF,
+ 0xE7, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd465[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xEA, 0xFF, 0xFF, 0xFF,
+ 0xE8, 0xB0, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd466[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xFF, 0x04, 0xFF, 0xFF,
+ 0xE9, 0x03, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd467[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x07, 0x00, 0xFF, 0xFF,
+ 0xEA, 0xBF, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd468[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x08, 0x92, 0xFF, 0xFF,
+ 0xFF, 0x04, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd469[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xFF, 0x00, 0xFF, 0xFF,
+ 0x07, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd470[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xFB, 0x01, 0xFF, 0xFF,
+ 0x08, 0x92, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd471[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD3, 0x09, 0xFF, 0xFF,
+ 0xFF, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd472[] = {
0x02, 0x00, 0x29, 0xC0,
- 0xD4, 0x04, 0xFF, 0xFF,
+ 0xFB, 0x01, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd473[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x51, 0x00, 0xFF, 0xFF,
+ 0xD3, 0x09, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd474[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x53, 0x2c, 0xFF, 0xFF,
+ 0xD4, 0x04, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd475[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x55, 0x00, 0xFF, 0xFF,
+ 0x51, 0x7F, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd476[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x11, 0x00, 0xFF, 0xFF,
+ 0x53, 0x2C, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd477[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x29, 0x00, 0xFF, 0xFF,
+ 0x55, 0x00, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd478[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x51, 0x7F, 0xFF, 0xFF,
+ 0x11, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35596_1080p_skuk_video_on_cmd479[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x29, 0x00, 0xFF, 0xFF,
};
static struct mipi_dsi_cmd nt35596_1080p_skuk_video_on_command[] = {
@@ -2549,7 +2554,7 @@
{0x8, nt35596_1080p_skuk_video_on_cmd86, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd87, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd88, 0x00},
- {0x8, nt35596_1080p_skuk_video_on_cmd89, 0x05},
+ {0x8, nt35596_1080p_skuk_video_on_cmd89, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd90, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd91, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd92, 0x00},
@@ -2697,7 +2702,7 @@
{0x8, nt35596_1080p_skuk_video_on_cmd234, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd235, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd236, 0x00},
- {0x8, nt35596_1080p_skuk_video_on_cmd237, 0x05},
+ {0x8, nt35596_1080p_skuk_video_on_cmd237, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd238, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd239, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd240, 0x00},
@@ -2930,18 +2935,19 @@
{0x8, nt35596_1080p_skuk_video_on_cmd467, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd468, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd469, 0x00},
- {0x8, nt35596_1080p_skuk_video_on_cmd470, 0x05},
+ {0x8, nt35596_1080p_skuk_video_on_cmd470, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd471, 0x00},
- {0x8, nt35596_1080p_skuk_video_on_cmd472, 0x00},
+ {0x8, nt35596_1080p_skuk_video_on_cmd472, 0x05},
{0x8, nt35596_1080p_skuk_video_on_cmd473, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd474, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd475, 0x00},
- {0x8, nt35596_1080p_skuk_video_on_cmd476, 0x78},
+ {0x8, nt35596_1080p_skuk_video_on_cmd476, 0x00},
{0x8, nt35596_1080p_skuk_video_on_cmd477, 0x00},
- {0x8, nt35596_1080p_skuk_video_on_cmd478, 0x00}
+ {0x8, nt35596_1080p_skuk_video_on_cmd478, 0x78},
+ {0x8, nt35596_1080p_skuk_video_on_cmd479, 0x00}
};
-#define NT35596_1080P_SKUK_VIDEO_ON_COMMAND 479
+#define NT35596_1080P_SKUK_VIDEO_ON_COMMAND 480
static char nt35596_1080p_skuk_videooff_cmd0[] = {
diff --git a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
index 666d63d..376c681 100644
--- a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
@@ -44,7 +44,7 @@
/* Panel configuration */
/*---------------------------------------------------------------------------*/
static struct panel_config sharp_wqxga_dualdsi_video_panel_data = {
- "qcom,mdss_dsi_sharp_wqxga_dualdsi_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ "qcom,mdss_dsi_sharp_wqxga_video_0", "dsi:0:", "qcom,mdss-dsi-panel",
10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 25, 1, 0,
"qcom,mdss_dsi_sharp_wqxga_video_1"
};
@@ -67,16 +67,16 @@
/* Panel on/off command information */
/*---------------------------------------------------------------------------*/
static char sharp_wqxga_dualdsi_video_on_cmd0[] = {
- 0x11, 0X00, 0x05, 0x80
+ 0x11, 0x00, 0x05, 0x80
};
static char sharp_wqxga_dualdsi_video_on_cmd1[] = {
- 0x29, 0x00, 0x5, 0x80
+ 0x29, 0x00, 0x05, 0x80
};
static struct mipi_dsi_cmd sharp_wqxga_dualdsi_video_on_command[] = {
- {0x4, sharp_wqxga_dualdsi_video_on_cmd0, 0xa0},
- {0x4, sharp_wqxga_dualdsi_video_on_cmd1, 0x02}
+ {0x4, sharp_wqxga_dualdsi_video_on_cmd0, 0x0a},
+ {0x4, sharp_wqxga_dualdsi_video_on_cmd1, 0x0a}
};
#define SHARP_WQXGA_DUALDSI_VIDEO_ON_COMMAND 2
@@ -90,6 +90,12 @@
0x10, 0x00, 0x05, 0x80
};
+static struct mipi_dsi_cmd sharp_wqxga_dualdsi_video_off_command[] = {
+ {0x4, sharp_wqxga_dualdsi_videooff_cmd0, 0x32},
+ {0x4, sharp_wqxga_dualdsi_videooff_cmd1, 0x78}
+};
+
+#define SHARP_WQXGA_DUALDSI_VIDEO_OFF_COMMAND 2
static struct command_state sharp_wqxga_dualdsi_video_state = {
0, 1
@@ -131,17 +137,16 @@
/* Panel reset sequence */
/*---------------------------------------------------------------------------*/
static struct panel_reset_sequence sharp_wqxga_dualdsi_video_reset_seq = {
- {1, 0, 1, }, {2, 5, 120, }, 2
+ {1, 0, 1, }, {10, 10, 120, }, 2
};
/*---------------------------------------------------------------------------*/
/* Backlight setting */
/*---------------------------------------------------------------------------*/
static struct backlight sharp_wqxga_dualdsi_video_backlight = {
- 1, 1, 4095, 100, 1, "PMIC_8941"
+ 1, 1, 4095, 100, 1, "PMIC_8941" /* BL_WLED */
};
#define SHARP_WQXGA_DUALDSI_VIDEO_SIGNATURE 0x210000
-
#endif /*_PANEL_SHARP_WQXGA_DUALDSI_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index 8631279..427a548 100644
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -108,7 +108,7 @@
}
pinfo->bpp = pstruct->color->color_format;
pinfo->clk_rate = pstruct->paneldata->panel_clockrate;
- pinfo->rotation = pstruct->paneldata->panel_orientation;
+ pinfo->orientation = pstruct->paneldata->panel_orientation;
pinfo->mipi.interleave_mode = pstruct->paneldata->interleave_mode;
pinfo->mipi.broadcast = pstruct->paneldata->panel_broadcast_mode;
pinfo->mipi.vc = pstruct->paneldata->dsi_virtualchannel_id;
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 472e69f..8681feb 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -171,6 +171,12 @@
MPP_ENABLE,
};
+enum mvs_en_ctl
+{
+ MVS_DISABLE,
+ MVS_ENABLE,
+};
+
enum mpp_mode
{
MPP_DIGITAL_INPUT,
@@ -190,9 +196,15 @@
enum mpp_mode_en_source_select mode;
};
+struct pm8x41_mvs
+{
+ uint32_t base;
+};
+
#define PM8x41_MMP2_BASE 0xA100
#define PM8x41_MMP3_BASE 0xA200
#define PM8x41_MMP4_BASE 0xA300
+#define PM8x41_MVS1_BASE 0x18400
void pm8x41_lpg_write(uint8_t chan, uint8_t off, uint8_t val);
int pm8x41_gpio_get(uint8_t gpio, uint8_t *status);
@@ -212,6 +224,7 @@
uint32_t pm8x41_get_pwrkey_is_pressed();
void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp);
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
+void pm8x41_enable_mvs(struct pm8x41_mvs *mvs, enum mvs_en_ctl enable);
uint8_t pm8x41_get_is_cold_boot();
void pm8x41_diff_clock_ctrl(uint8_t enable);
void pm8x41_clear_pmic_watchdog(void);
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 9d05219..db4473c 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -99,6 +99,10 @@
#define MPP_MODE_CTL_MODE_SHIFT 4
#define MPP_EN_CTL_ENABLE_SHIFT 7
+/* MVS registers */
+#define MVS_EN_CTL 0x46
+#define MVS_EN_CTL_ENABLE_SHIFT 7
+
void pm8x41_reg_write(uint32_t addr, uint8_t val);
uint8_t pm8x41_reg_read(uint32_t addr);
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 3b9783d..2471d0a 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -397,6 +397,13 @@
return REG_READ(PON_POFF_REASON2);
}
+void pm8x41_enable_mvs(struct pm8x41_mvs *mvs, enum mvs_en_ctl enable)
+{
+ ASSERT(mvs);
+
+ REG_WRITE(mvs->base + MVS_EN_CTL, enable << MVS_EN_CTL_ENABLE_SHIFT);
+}
+
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable)
{
ASSERT(mpp);
diff --git a/include/target.h b/include/target.h
index c7c05db..ba95cbb 100644
--- a/include/target.h
+++ b/include/target.h
@@ -59,6 +59,7 @@
void target_load_ssd_keystore(void);
bool target_is_ssd_enabled(void);
void *target_mmc_device();
+uint32_t is_user_force_reset(void);
bool target_display_panel_node(char *panel_name, char *pbuf,
uint16_t buf_size);
diff --git a/lib/heap/heap.c b/lib/heap/heap.c
index a3a35fb..a4835f9 100644
--- a/lib/heap/heap.c
+++ b/lib/heap/heap.c
@@ -237,6 +237,11 @@
if (alignment & (alignment - 1))
return NULL;
+ if(size > (size + sizeof(struct alloc_struct_begin)))
+ {
+ dprintf(CRITICAL, "invalid input size\n");
+ return NULL;
+ }
// we always put a size field + base pointer + magic in front of the allocation
size += sizeof(struct alloc_struct_begin);
#if DEBUG_HEAP
@@ -258,6 +263,11 @@
alignment = 16;
// add alignment for worst case fit
+ if(size > (size + alignment))
+ {
+ dprintf(CRITICAL, "invalid input alignment\n");
+ return NULL;
+ }
size += alignment;
}
diff --git a/makefile b/makefile
index 40cb9f0..0cf7e7c 100644
--- a/makefile
+++ b/makefile
@@ -63,6 +63,7 @@
# setup toolchain prefix
TOOLCHAIN_PREFIX ?= arm-eabi-
CFLAGS += -fstack-protector-all
+CFLAGS += -fno-strict-overflow
CPPFLAGS := -fno-exceptions -fno-rtti -fno-threadsafe-statics
#CPPFLAGS += -Weffc++
ASMFLAGS := -DASSEMBLY
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index 7f903fb..78c7b64 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -556,6 +556,39 @@
}
}
+void hdmi_clk_enable(void)
+{
+ int ret;
+
+ /* Configure hdmi ahb clock */
+ ret = clk_get_set_enable("hdmi_ahb_clk", 0, 1);
+ if(ret) {
+ dprintf(CRITICAL, "failed to set hdmi_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure hdmi core clock */
+ ret = clk_get_set_enable("hdmi_core_clk", 19200000, 1);
+ if(ret) {
+ dprintf(CRITICAL, "failed to set hdmi_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure hdmi pixel clock */
+ ret = clk_get_set_enable("hdmi_extp_clk", 148500000, 1);
+ if(ret) {
+ dprintf(CRITICAL, "failed to set hdmi_extp_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void hdmi_clk_disable(void)
+{
+ clk_disable(clk_get("hdmi_extp_clk"));
+ clk_disable(clk_get("hdmi_core_clk"));
+ clk_disable(clk_get("hdmi_ahb_clk"));
+}
+
void edp_clk_enable(void)
{
int ret;
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index 08d6d2a..f01aa7e 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -47,6 +47,7 @@
#define gpll0_mm_source_val 5
#define edppll_270_mm_source_val 4
#define edppll_350_mm_source_val 4
+#define hdmipll_mm_source_val 3
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -690,6 +691,69 @@
},
};
+static struct branch_clk mdss_hdmi_ahb_clk = {
+ .cbcr_reg = MDSS_HDMI_AHB_CBCR,
+ .has_sibling = 1,
+ .c = {
+ .dbg_name = "mdss_hdmi_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_hdmi_clk[] = {
+ F_MM( 19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk hdmi_clk_src = {
+ .cmd_reg = HDMI_CMD_RCGR,
+ .cfg_reg = HDMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_hdmi_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "hdmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_hdmi_clk = {
+ .cbcr_reg = MDSS_HDMI_CBCR,
+ .has_sibling = 0,
+ .parent = &hdmi_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_hdmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_extpclk_clk[] = {
+ F_MDSS(148500000, hdmipll, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk extpclk_clk_src = {
+ .cmd_reg = EXTPCLK_CMD_RCGR,
+ .cfg_reg = EXTPCLK_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_extpclk_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "extpclk_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_extpclk_clk = {
+ .cbcr_reg = MDSS_EXTPCLK_CBCR,
+ .has_sibling = 0,
+ .parent = &extpclk_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_extpclk_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = {
F_MM(19200000, cxo, 1, 0, 0),
F_END
@@ -838,6 +902,10 @@
CLK_LOOKUP("edp_pixel_clk", mdss_edppixel_clk.c),
CLK_LOOKUP("edp_link_clk", mdss_edplink_clk.c),
CLK_LOOKUP("edp_aux_clk", mdss_edpaux_clk.c),
+
+ CLK_LOOKUP("hdmi_ahb_clk", mdss_hdmi_ahb_clk.c),
+ CLK_LOOKUP("hdmi_core_clk", mdss_hdmi_clk.c),
+ CLK_LOOKUP("hdmi_extp_clk", mdss_extpclk_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/apq8084/include/platform/clock.h b/platform/apq8084/include/platform/clock.h
index 7f4ebfd..a3bb284 100644
--- a/platform/apq8084/include/platform/clock.h
+++ b/platform/apq8084/include/platform/clock.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -50,6 +50,13 @@
#define MDP_CBCR REG_MM(0x231C)
#define MDP_LUT_CBCR REG_MM(0x2320)
#define MDP_AHB_CBCR REG_MM(0x2308)
+#define MDSS_HDMI_AHB_CBCR REG_MM(0x230C)
+#define MDSS_HDMI_CBCR REG_MM(0x2338)
+#define MDSS_EXTPCLK_CBCR REG_MM(0x2324)
+#define EXTPCLK_CMD_RCGR REG_MM(0x2060)
+#define EXTPCLK_CFG_RCGR REG_MM(0x2064)
+#define HDMI_CMD_RCGR REG_MM(0x2100)
+#define HDMI_CFG_RCGR REG_MM(0x2104)
#define MDP_AXI_CMD_RCGR REG_MM(0x5040)
#define MDP_AXI_CFG_RCGR REG_MM(0x5044)
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index 241285f..6d02af3 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -271,4 +271,26 @@
#define VIDEO_MODE_CTRL 0x010
#define HS_TIMER_CTRL 0x0BC
+/* HDMI reg addresses */
+#define HDMI_BASE 0xFD922100
+#define REG_HDMI(off) (HDMI_BASE + (off))
+
+#define HDMI_USEC_REFTIMER REG_HDMI(0x208)
+#define HDMI_CTRL REG_HDMI(0x000)
+#define HDMI_HPD_INT_STATUS REG_HDMI(0x250)
+#define HDMI_HPD_INT_CTRL REG_HDMI(0x254)
+#define HDMI_HPD_CTRL REG_HDMI(0x258)
+#define HDMI_PHY_CTRL REG_HDMI(0x2D4)
+#define HDMI_TOTAL REG_HDMI(0x2C0)
+#define HDMI_ACTIVE_H REG_HDMI(0x2B4)
+#define HDMI_ACTIVE_V REG_HDMI(0x2B8)
+#define HDMI_V_TOTAL_F2 REG_HDMI(0x2C4)
+#define HDMI_ACTIVE_V_F2 REG_HDMI(0x2BC)
+#define HDMI_FRAME_CTRL REG_HDMI(0x2C8)
+
+#define HDMI_AVI_INFO0 REG_HDMI(0x06C)
+#define HDMI_AVI_INFO1 REG_HDMI(0x070)
+#define HDMI_AVI_INFO2 REG_HDMI(0x074)
+#define HDMI_AVI_INFO3 REG_HDMI(0x078)
+#define HDMI_INFOFRAME_CTRL0 REG_HDMI(0x02C)
#endif
diff --git a/platform/ferrum/platform.c b/platform/ferrum/platform.c
index 1895fe6..3765be4 100644
--- a/platform/ferrum/platform.c
+++ b/platform/ferrum/platform.c
@@ -37,6 +37,7 @@
void platform_early_init(void)
{
+ board_init();
qgic_init();
qtimer_init();
}
diff --git a/platform/msm8916/platform.c b/platform/msm8916/platform.c
index cd428e8..4deaa1b 100644
--- a/platform/msm8916/platform.c
+++ b/platform/msm8916/platform.c
@@ -190,6 +190,7 @@
case MSM8236:
case MSM8636:
case MSM8936:
+ case MSM8239:
ret = 1;
break;
default:
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index 72f4962..cd990f2 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -290,3 +290,183 @@
return;
}
+
+void mdp_gdsc_ctrl(uint8_t enable)
+{
+ uint32_t reg = 0;
+ reg = readl(MDP_GDSCR);
+ if (enable) {
+ if (!(reg & GDSC_POWER_ON_BIT)) {
+ reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK);
+ reg |= GDSC_EN_FEW_WAIT_256_MASK;
+ writel(reg, MDP_GDSCR);
+ while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)));
+ } else {
+ dprintf(INFO, "MDP GDSC already enabled\n");
+ }
+ } else {
+ reg |= BIT(0);
+ writel(reg, MDP_GDSCR);
+ while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT));
+ }
+}
+
+/* Configure MDP clock */
+void mdp_clock_enable(void)
+{
+ int ret;
+
+ /* Set MDP clock to 240MHz */
+ ret = clk_get_set_enable("mdp_ahb_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_mdp_clk_src", 240000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_vsync_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_mdp_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void mdp_clock_disable()
+{
+ clk_disable(clk_get("mdss_vsync_clk"));
+ clk_disable(clk_get("mdss_mdp_clk"));
+ clk_disable(clk_get("mdss_mdp_lut_clk"));
+ clk_disable(clk_get("mdss_mdp_clk_src"));
+ clk_disable(clk_get("mdp_ahb_clk"));
+
+}
+
+void mmss_bus_clock_enable(void)
+{
+ int ret;
+ /* Configure MMSSNOC AXI clock */
+ ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure S0 AXI clock */
+ ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure AXI clock */
+ ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void mmss_bus_clock_disable(void)
+{
+ /* Disable MDSS AXI clock */
+ clk_disable(clk_get("mdss_axi_clk"));
+
+ /* Disable MMSSNOC S0AXI clock */
+ clk_disable(clk_get("mmss_s0_axi_clk"));
+
+ /* Disable MMSSNOC AXI clock */
+ clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
+}
+
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+ uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
+{
+ int ret;
+
+ /* Configure Byte clock -autopll- This will not change because
+ byte clock does not need any divider*/
+ writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(0x1, DSI_BYTE0_CMD_RCGR);
+ writel(0x1, DSI_BYTE0_CBCR);
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ writel(0x1, DSI_PIXEL0_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ if (dual_dsi) {
+ /* Configure Byte 1 clock */
+ writel(0x100, DSI_BYTE1_CFG_RCGR);
+ writel(0x1, DSI_BYTE1_CMD_RCGR);
+ writel(0x1, DSI_BYTE1_CBCR);
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
+ writel(0x1, DSI_PIXEL1_CMD_RCGR);
+ writel(0x1, DSI_PIXEL1_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL1_M);
+ writel(pclk0_n, DSI_PIXEL1_N);
+ writel(pclk0_d, DSI_PIXEL1_D);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+ }
+}
+
+void mmss_dsi_clock_disable(uint32_t dual_dsi)
+{
+ /* Disable ESC clock */
+ clk_disable(clk_get("mdss_esc0_clk"));
+ writel(0x0, DSI_BYTE0_CBCR);
+ writel(0x0, DSI_PIXEL0_CBCR);
+
+ if (dual_dsi) {
+ /* Disable ESC clock */
+ clk_disable(clk_get("mdss_esc1_clk"));
+ writel(0x0, DSI_BYTE1_CBCR);
+ writel(0x0, DSI_PIXEL1_CBCR);
+ }
+}
diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index bad5743..c50fef7 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -34,6 +34,71 @@
#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
+
+#define MDP_GDSCR REG_MM(0x2304)
+#define GDSC_POWER_ON_BIT BIT(31)
+#define GDSC_POWER_ON_STATUS_BIT BIT(29)
+#define GDSC_EN_FEW_WAIT_MASK (0x0F << 16)
+#define GDSC_EN_FEW_WAIT_256_MASK BIT(19)
+
+#define VSYNC_CMD_RCGR REG_MM(0x2080)
+#define VSYNC_CFG_RCGR REG_MM(0x2084)
+#define MDSS_VSYNC_CBCR REG_MM(0x2328)
+#define MDP_CMD_RCGR REG_MM(0x2040)
+#define MDP_CFG_RCGR REG_MM(0x2044)
+#define MDP_CBCR REG_MM(0x231C)
+#define MDP_LUT_CBCR REG_MM(0x2320)
+#define MDP_AHB_CBCR REG_MM(0x2308)
+
+#define MDP_AXI_CMD_RCGR REG_MM(0x5040)
+#define MDP_AXI_CFG_RCGR REG_MM(0x5044)
+
+#define MDP_AXI_CBCR REG_MM(0x2310)
+#define MMSS_S0_AXI_CBCR REG_MM(0x5064)
+#define MMSS_MMSSNOC_AXI_CBCR REG_MM(0x506C)
+
+#define DSI_BYTE0_CMD_RCGR REG_MM(0x2120)
+#define DSI_BYTE0_CFG_RCGR REG_MM(0x2124)
+#define DSI_BYTE0_CBCR REG_MM(0x233C)
+#define DSI_ESC0_CMD_RCGR REG_MM(0x2160)
+#define DSI_ESC0_CFG_RCGR REG_MM(0x2164)
+#define DSI_ESC0_CBCR REG_MM(0x2344)
+#define DSI_PIXEL0_CMD_RCGR REG_MM(0x2000)
+#define DSI_PIXEL0_CFG_RCGR REG_MM(0x2004)
+#define DSI_PIXEL0_CBCR REG_MM(0x2314)
+#define DSI_PIXEL0_M REG_MM(0x2008)
+#define DSI_PIXEL0_N REG_MM(0x200C)
+#define DSI_PIXEL0_D REG_MM(0x2010)
+
+#define DSI0_PHY_PLL_OUT BIT(8)
+#define PIXEL_SRC_DIV_1_5 BIT(1)
+
+#define DSI_BYTE1_CMD_RCGR REG_MM(0x2140)
+#define DSI_BYTE1_CFG_RCGR REG_MM(0x2144)
+#define DSI_BYTE1_CBCR REG_MM(0x2340)
+#define DSI_ESC1_CMD_RCGR REG_MM(0x2180)
+#define DSI_ESC1_CFG_RCGR REG_MM(0x2184)
+#define DSI_ESC1_CBCR REG_MM(0x2348)
+#define DSI_PIXEL1_CMD_RCGR REG_MM(0x2020)
+#define DSI_PIXEL1_CFG_RCGR REG_MM(0x2024)
+#define DSI_PIXEL1_CBCR REG_MM(0x2318)
+#define DSI_PIXEL1_M REG_MM(0x2028)
+#define DSI_PIXEL1_N REG_MM(0x202C)
+#define DSI_PIXEL1_D REG_MM(0x2030)
+
+#define MDSS_EDPPIXEL_CBCR REG_MM(0x232C)
+#define MDSS_EDPLINK_CBCR REG_MM(0x2330)
+#define MDSS_EDPAUX_CBCR REG_MM(0x2334)
+#define EDPPIXEL_M REG_MM(0x20A8)
+#define EDPPIXEL_N REG_MM(0x20AC)
+#define EDPPIXEL_D REG_MM(0x20B0)
+#define EDPPIXEL_CFG_RCGR REG_MM(0x20A4)
+#define EDPPIXEL_CMD_RCGR REG_MM(0x20A0)
+#define EDPLINK_CFG_RCGR REG_MM(0x20C4)
+#define EDPLINK_CMD_RCGR REG_MM(0x20C0)
+#define EDPAUX_CFG_RCGR REG_MM(0x20E4)
+#define EDPAUX_CMD_RCGR REG_MM(0x20E0)
void platform_clock_init(void);
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 2040d4a..aade4bd 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -82,6 +82,11 @@
#define QUSB2_PHY_BASE (PERIPH_SS_BASE + 0x00339000)
#define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4)
+#define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4)
+#define QUSB2PHY_PORT_TUNE1 (QUSB2_PHY_BASE + 0x00000080)
+#define QUSB2PHY_PORT_TUNE2 (QUSB2_PHY_BASE + 0x00000084)
+#define QUSB2PHY_PORT_TUNE3 (QUSB2_PHY_BASE + 0x00000088)
+#define QUSB2PHY_PORT_TUNE4 (QUSB2_PHY_BASE + 0x0000008C)
#define MSM_USB30_BASE 0xF9200000
#define MSM_USB30_QSCRATCH_BASE 0xF92F8800
@@ -209,4 +214,127 @@
#define PLATFORM_QMP_OFFSET 0x8
#define SMEM_TARG_INFO_ADDR 0xFE805FF0
+
+/* MDSS */
+#define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000
+#define MIPI_DSI_BASE (0xFD998000)
+#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
+#define MIPI_DSI1_BASE (0xFD9A0000)
+#define DSI0_PHY_BASE (0xFD998500)
+#define DSI1_PHY_BASE (0xFD9A0500)
+#define DSI0_PLL_BASE (0xFD998300)
+#define DSI1_PLL_BASE (0xFD9A0300)
+#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+
+#define MDP_BASE (0xfd900000)
+
+#define REG_MDP(off) (MDP_BASE + (off))
+#define MDP_HW_REV REG_MDP(0x1000)
+#define MDP_INTR_EN REG_MDP(0x1010)
+#define MDP_INTR_CLEAR REG_MDP(0x1018)
+#define MDP_HIST_INTR_EN REG_MDP(0x101C)
+
+#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
+#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
+#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
+#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
+
+#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
+#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
+
+#define MDP_CTL_0_BASE REG_MDP(0x2000)
+#define MDP_CTL_1_BASE REG_MDP(0x2200)
+
+#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
+#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
+#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
+
+/* can not find following two registers */
+#define MDP_REG_PPB0_CNTL REG_MDP(0x1420)
+#define MDP_REG_PPB0_CONFIG REG_MDP(0x1424)
+
+#define MDP_INTF_0_BASE REG_MDP(0x6b000)
+#define MDP_INTF_1_BASE REG_MDP(0x6b800)
+#define MDP_INTF_2_BASE REG_MDP(0x6c000)
+
+
+#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
+#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
+#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
+#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
+#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
+#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
+#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
+#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
+
+#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
+#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
+
+#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x13d8)
+#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x13dc)
+
+#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
+#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
+#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
+#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
+#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
+#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
+#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
+#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
+#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
+#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
+#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xc80B8)
+#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xc80BC)
+#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
+#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
+#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xc80C8)
+#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xc80CC)
+#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xc8070)
+#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xc8074)
+#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xc80A8)
+
+#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
+#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
+#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
+#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
+#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
+#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
+#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
+#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
+
+#define DMA_CMD_OFFSET 0x048
+#define DMA_CMD_LENGTH 0x04C
+
+#define INT_CTRL 0x110
+#define CMD_MODE_DMA_SW_TRIGGER 0x090
+
+#define EOT_PACKET_CTRL 0x0CC
+#define MISR_CMD_CTRL 0x0A0
+#define MISR_VIDEO_CTRL 0x0A4
+#define VIDEO_MODE_CTRL 0x010
+#define HS_TIMER_CTRL 0x0BC
+
+#define SOFT_RESET 0x118
+#define CLK_CTRL 0x11C
+#define TRIG_CTRL 0x084
+#define CTRL 0x004
+#define COMMAND_MODE_DMA_CTRL 0x03C
+#define COMMAND_MODE_MDP_CTRL 0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
+#define ERR_INT_MASK0 0x10C
+
+#define LANE_SWAP_CTL 0x0B0
+#define TIMING_CTL 0x0C4
+
+#define VIDEO_MODE_ACTIVE_H 0x024
+#define VIDEO_MODE_ACTIVE_V 0x028
+#define VIDEO_MODE_TOTAL 0x02C
+#define VIDEO_MODE_HSYNC 0x030
+#define VIDEO_MODE_VSYNC 0x034
+#define VIDEO_MODE_VSYNC_VPOS 0x038
+
#endif
diff --git a/platform/msm8994/msm8994-clock.c b/platform/msm8994/msm8994-clock.c
index 68343bf..033a88d 100644
--- a/platform/msm8994/msm8994-clock.c
+++ b/platform/msm8994/msm8994-clock.c
@@ -45,6 +45,8 @@
#define mmpll1_mm_source_val 2
#define mmpll3_mm_source_val 3
#define gpll0_mm_source_val 5
+#define edppll_270_mm_source_val 4
+#define edppll_350_mm_source_val 4
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -486,6 +488,273 @@
},
};
+/* Display clocks */
+static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_MM(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mdp_clk[] = {
+ F_MM( 75000000, gpll0, 8, 0, 0),
+ F_MM( 240000000, gpll0, 2.5, 0, 0),
+ F_END
+};
+
+static struct rcg_clk dsi_esc0_clk_src = {
+ .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR,
+ .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_esc0_1_clk,
+
+ .c = {
+ .dbg_name = "dsi_esc0_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct rcg_clk dsi_esc1_clk_src = {
+ .cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_esc1_1_clk,
+
+ .c = {
+ .dbg_name = "dsi_esc1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk vsync_clk_src = {
+ .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR,
+ .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_vsync_clk,
+
+ .c = {
+ .dbg_name = "vsync_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct rcg_clk mdp_axi_clk_src = {
+ .cmd_reg = (uint32_t *) MDP_AXI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) MDP_AXI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mmss_axi_clk,
+
+ .c = {
+ .dbg_name = "mdp_axi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_esc0_clk = {
+ .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR,
+ .parent = &dsi_esc0_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_esc0_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_esc1_clk = {
+ .cbcr_reg = (uint32_t *) DSI_ESC1_CBCR,
+ .parent = &dsi_esc1_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_esc1_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_axi_clk = {
+ .cbcr_reg = (uint32_t *) MDP_AXI_CBCR,
+ .parent = &mdp_axi_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mmss_mmssnoc_axi_clk = {
+ .cbcr_reg = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR,
+ .parent = &mdp_axi_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mmss_mmssnoc_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mmss_s0_axi_clk = {
+ .cbcr_reg = (uint32_t *) MMSS_S0_AXI_CBCR,
+ .parent = &mdp_axi_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mmss_s0_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdp_ahb_clk = {
+ .cbcr_reg = (uint32_t *) MDP_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdp_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk mdss_mdp_clk_src = {
+ .cmd_reg = (uint32_t *) MDP_CMD_RCGR,
+ .cfg_reg = (uint32_t *) MDP_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdp_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "mdss_mdp_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_mdp_clk = {
+ .cbcr_reg = (uint32_t *) MDP_CBCR,
+ .parent = &mdss_mdp_clk_src.c,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdss_mdp_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_mdp_lut_clk = {
+ .cbcr_reg = MDP_LUT_CBCR,
+ .parent = &mdss_mdp_clk_src.c,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdss_mdp_lut_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_vsync_clk = {
+ .cbcr_reg = MDSS_VSYNC_CBCR,
+ .parent = &vsync_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_vsync_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edpaux_clk_src = {
+ .cmd_reg = (uint32_t *) EDPAUX_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_edpaux_clk,
+
+ .c = {
+ .dbg_name = "edpaux_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_edpaux_clk = {
+ .cbcr_reg = MDSS_EDPAUX_CBCR,
+ .parent = &edpaux_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_edpaux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = {
+ F_MDSS(162000000, edppll_270, 2, 0, 0),
+ F_MDSS(270000000, edppll_270, 11, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edplink_clk_src = {
+ .cmd_reg = (uint32_t *)EDPLINK_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_edplink_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "edplink_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
+ F_MDSS(138500000, edppll_350, 2, 0, 0),
+ F_MDSS(350000000, edppll_350, 11, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edppixel_clk_src = {
+ .cmd_reg = (uint32_t *)EDPPIXEL_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_mdss_edppixel_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "edppixel_clk_src",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk mdss_edplink_clk = {
+ .cbcr_reg = (uint32_t *)MDSS_EDPLINK_CBCR,
+ .has_sibling = 0,
+ .parent = &edplink_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_edplink_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_edppixel_clk = {
+ .cbcr_reg = (uint32_t *)MDSS_EDPPIXEL_CBCR,
+ .has_sibling = 0,
+ .parent = &edppixel_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_edppixel_clk",
+ .ops = &clk_ops_branch,
+ },
+};
/* Clock lookup table */
static struct clk_lookup msm_8994_clocks[] =
@@ -510,6 +779,22 @@
CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c),
+
+ /* mdss clocks */
+ CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
+ CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
+ CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c),
+ CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c),
+ CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c),
+ CLK_LOOKUP("mmss_s0_axi_clk", mmss_s0_axi_clk.c),
+ CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c),
+ CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
+ CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
+ CLK_LOOKUP("mdss_mdp_lut_clk", mdss_mdp_lut_clk.c),
+
+ CLK_LOOKUP("edp_pixel_clk", mdss_edppixel_clk.c),
+ CLK_LOOKUP("edp_link_clk", mdss_edplink_clk.c),
+ CLK_LOOKUP("edp_aux_clk", mdss_edpaux_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/msm8994/platform.c b/platform/msm8994/platform.c
index 8c90dc5..f494f3f 100644
--- a/platform/msm8994/platform.c
+++ b/platform/msm8994/platform.c
@@ -66,6 +66,7 @@
platform_clock_init();
qgic_init();
qtimer_init();
+ scm_init();
}
void platform_init(void)
diff --git a/platform/msm8994/rules.mk b/platform/msm8994/rules.mk
index a9fd66f..641e3cd 100644
--- a/platform/msm8994/rules.mk
+++ b/platform/msm8994/rules.mk
@@ -13,6 +13,8 @@
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
MMC_SLOT=$(MMC_SLOT)
+DEFINES += TZ_SAVE_KERNEL_HASH
+
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
DEVS += fbcon
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index 5c7dee8..fdc8553 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -50,6 +50,7 @@
unsigned int board_info_len = 0;
unsigned ret = 0;
unsigned format = 0;
+ unsigned pmic_type = 0;
uint8_t i;
uint16_t format_major = 0;
uint16_t format_minor = 0;
@@ -131,6 +132,17 @@
for (i = 0; i < SMEM_V8_SMEM_MAX_PMIC_DEVICES; i++) {
board.pmic_info[i].pmic_type = board_info_v8.pmic_info[i].pmic_type;
board.pmic_info[i].pmic_version = board_info_v8.pmic_info[i].pmic_version;
+
+ /*
+ * fill in pimc_board_info with pmic type and pmic version information
+ * bit no |31 24 | 23 16 | 15 8 |7 0|
+ * pimc_board_info = |Unused | Major version | Minor version|PMIC_MODEL|
+ *
+ */
+ pmic_type = board_info_v8.pmic_info[i].pmic_type == PMIC_IS_INVALID? 0 : board_info_v8.pmic_info[i].pmic_type;
+
+ board.pmic_info[i].pmic_target = (((board_info_v8.pmic_info[i].pmic_version >> 16) & 0xff) << 16) |
+ ((board_info_v8.pmic_info[i].pmic_version & 0xff) << 8) | (pmic_type & 0xff);
}
if (format_minor == 0x9)
@@ -195,12 +207,21 @@
for (i = 0; i < num_ent && i < SMEM_MAX_PMIC_DEVICES; i++) {
info->pmic_type = board.pmic_info[i].pmic_type;
info->pmic_version = board.pmic_info[i].pmic_version;
+ info->pmic_target = board.pmic_info[i].pmic_target;
info++;
}
return (i--);
}
+uint32_t board_pmic_target(uint8_t num_ent)
+{
+ if (num_ent < SMEM_MAX_PMIC_DEVICES) {
+ return board.pmic_info[num_ent].pmic_target;
+ }
+ return 0;
+}
+
uint32_t board_soc_version()
{
return board.platform_version;
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 0ec55a5..bd24628 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -35,6 +35,8 @@
#include <string.h>
#include <platform.h>
#include <board.h>
+#include <list.h>
+#include <kernel/thread.h>
struct dt_entry_v1
{
@@ -46,8 +48,9 @@
};
static struct dt_mem_node_info mem_node;
-
-static int platform_dt_match(struct dt_entry *cur_dt_entry, struct board_dt_entry *board_dt_data, uint32_t subtype_mask);
+static int platform_dt_absolute_match(struct dt_entry *cur_dt_entry, struct dt_entry_node *dt_list);
+static struct dt_entry *platform_dt_match_best(struct dt_entry_node *dt_list);
+static int update_dtb_entry_node(struct dt_entry_node *dt_list, uint32_t dtb_info);
extern int target_is_emmc_boot(void);
extern uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset);
/* TODO: This function needs to be moved to target layer to check violations
@@ -58,30 +61,66 @@
/* Returns soc version if platform id and hardware id matches
otherwise return 0xFFFFFFFF */
#define INVALID_SOC_REV_ID 0XFFFFFFFF
-static uint32_t dev_tree_compatible(void *dtb)
+
+/* Add function to allocate dt entry list, used for recording
+* the entry which conform to platform_dt_absolute_match()
+*/
+static struct dt_entry_node *dt_entry_list_init(void)
+{
+ struct dt_entry_node *dt_node_member = NULL;
+
+ dt_node_member = (struct dt_entry_node *)
+ malloc(sizeof(struct dt_entry_node));
+
+ ASSERT(dt_node_member);
+
+ list_clear_node(&dt_node_member->node);
+ dt_node_member->dt_entry_m = (struct dt_entry *)
+ malloc(sizeof(struct dt_entry));
+ ASSERT(dt_node_member->dt_entry_m);
+
+ memset(dt_node_member->dt_entry_m ,0 ,sizeof(struct dt_entry));
+ return dt_node_member;
+}
+
+static void insert_dt_entry_in_queue(struct dt_entry_node *dt_list, struct dt_entry_node *dt_node_member)
+{
+ list_add_tail(&dt_list->node, &dt_node_member->node);
+}
+
+static void dt_entry_list_delete(struct dt_entry_node *dt_node_member)
+{
+ if (list_in_list(&dt_node_member->node)) {
+ list_delete(&dt_node_member->node);
+ free(dt_node_member->dt_entry_m);
+ free(dt_node_member);
+ }
+}
+
+static int dev_tree_compatible(void *dtb, uint32_t dtb_size, struct dt_entry_node *dtb_list)
{
int root_offset;
const void *prop = NULL;
const char *plat_prop = NULL;
const char *board_prop = NULL;
+ const char *pmic_prop = NULL;
char *model = NULL;
- struct dt_entry cur_dt_entry;
- struct dt_entry *dt_entry_v2 = NULL;
+ struct dt_entry *cur_dt_entry;
+ struct dt_entry *dt_entry_array = NULL;
struct board_id *board_data = NULL;
struct plat_id *platform_data = NULL;
+ struct pmic_id *pmic_data = NULL;
int len;
int len_board_id;
int len_plat_id;
int min_plat_id_len = 0;
- uint32_t target_variant_id;
+ int len_pmic_id;
uint32_t dtb_ver;
uint32_t num_entries = 0;
- uint32_t i, j, k;
- uint32_t found = 0;
+ uint32_t i, j, k, n;
uint32_t msm_data_count;
uint32_t board_data_count;
- uint32_t soc_rev;
- struct board_dt_entry board_dt_data;
+ uint32_t pmic_data_count;
root_offset = fdt_path_offset(dtb, "/");
if (root_offset < 0)
@@ -93,19 +132,32 @@
ASSERT(model);
strlcpy(model, prop, len);
} else {
- model[0] = '\0';
+ dprintf(INFO, "model does not exist in device tree\n");
}
-
- /* Find the board-id prop from DTB , if board-id is present then
- * the DTB is version 2 */
+ /* Find the pmic-id prop from DTB , if pmic-id is present then
+ * the DTB is version 3, otherwise find the board-id prop from DTB ,
+ * if board-id is present then the DTB is version 2 */
+ pmic_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,pmic-id", &len_pmic_id);
board_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,board-id", &len_board_id);
- if (board_prop)
- {
+ if (pmic_prop && (len_pmic_id > 0) && board_prop && (len_board_id > 0)) {
+ if ((len_pmic_id % PMIC_ID_SIZE) || (len_board_id % BOARD_ID_SIZE))
+ {
+ dprintf(CRITICAL, "qcom,pmic-id(%d) or qcom,board-id(%d) in device tree is not a multiple of (%d %d)\n",
+ len_pmic_id, len_board_id, PMIC_ID_SIZE, BOARD_ID_SIZE);
+ return false;
+ }
+ dtb_ver = DEV_TREE_VERSION_V3;
+ min_plat_id_len = PLAT_ID_SIZE;
+ } else if (board_prop && len_board_id > 0) {
+ if (len_board_id % BOARD_ID_SIZE)
+ {
+ dprintf(CRITICAL, "qcom,board-id in device tree is (%d) not a multiple of (%d)\n",
+ len_board_id, BOARD_ID_SIZE);
+ return false;
+ }
dtb_ver = DEV_TREE_VERSION_V2;
min_plat_id_len = PLAT_ID_SIZE;
- }
- else
- {
+ } else {
dtb_ver = DEV_TREE_VERSION_V1;
min_plat_id_len = DT_ENTRY_V1_SIZE;
}
@@ -127,81 +179,145 @@
* y: variant_id
* z: SOC rev
*/
- if (dtb_ver == DEV_TREE_VERSION_V1)
- {
- while (len_plat_id)
- {
- cur_dt_entry.platform_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->platform_id);
- cur_dt_entry.variant_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->variant_id);
- cur_dt_entry.soc_rev = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->soc_rev);
- cur_dt_entry.board_hw_subtype = board_hardware_subtype();
+ if (dtb_ver == DEV_TREE_VERSION_V1) {
+ cur_dt_entry = (struct dt_entry *)
+ malloc(sizeof(struct dt_entry));
- board_dt_data.target_variant_id = board_hardware_id();
- board_dt_data.platform_variant_id = board_platform_id();
+ if (!cur_dt_entry) {
+ dprintf(CRITICAL, "Out of memory\n");
+ return false;
+ }
+ memset(cur_dt_entry, 0, sizeof(struct dt_entry));
+
+ while (len_plat_id) {
+ cur_dt_entry->platform_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->platform_id);
+ cur_dt_entry->variant_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->variant_id);
+ cur_dt_entry->soc_rev = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->soc_rev);
+ cur_dt_entry->board_hw_subtype =
+ fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->variant_id) >> 0x18;
+ cur_dt_entry->pmic_rev[0] = board_pmic_target(0);
+ cur_dt_entry->pmic_rev[1] = board_pmic_target(1);
+ cur_dt_entry->pmic_rev[2] = board_pmic_target(2);
+ cur_dt_entry->pmic_rev[3] = board_pmic_target(3);
+ cur_dt_entry->offset = (uint32_t)dtb;
+ cur_dt_entry->size = dtb_size;
dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u 0x%x)\n",
*model ? model : "unknown",
- cur_dt_entry.platform_id, cur_dt_entry.variant_id, cur_dt_entry.soc_rev);
+ cur_dt_entry->platform_id, cur_dt_entry->variant_id, cur_dt_entry->soc_rev);
- if (platform_dt_match(&cur_dt_entry, &board_dt_data, 0) == 1)
- {
+ if (platform_dt_absolute_match(cur_dt_entry, dtb_list)) {
+ dprintf(SPEW, "Device tree exact match the board: <%u %u 0x%x> != <%u %u 0x%x>\n",
+ cur_dt_entry->platform_id,
+ cur_dt_entry->variant_id,
+ cur_dt_entry->soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_soc_version());
+
+ } else {
dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u 0x%x> != <%u %u 0x%x>\n",
- cur_dt_entry.platform_id,
- cur_dt_entry.variant_id,
- cur_dt_entry.soc_rev,
- board_platform_id(),
- board_hardware_id(),
- board_soc_version());
+ cur_dt_entry->platform_id,
+ cur_dt_entry->variant_id,
+ cur_dt_entry->soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_soc_version());
plat_prop += DT_ENTRY_V1_SIZE;
len_plat_id -= DT_ENTRY_V1_SIZE;
continue;
}
- else
- {
- found = 1;
- break;
- }
}
+ free(cur_dt_entry);
+
}
/*
- * If DTB Version is '2' then we have split DTB with board & msm data
- * populated saperately in board-id & msm-id prop respectively.
+ * If DTB Version is '3' then we have split DTB with board & msm data & pmic
+ * populated saperately in board-id & msm-id & pmic-id prop respectively.
* Extract the data & prepare a look up table
*/
- else if (dtb_ver == DEV_TREE_VERSION_V2)
- {
+ else if (dtb_ver == DEV_TREE_VERSION_V2 || dtb_ver == DEV_TREE_VERSION_V3) {
board_data_count = (len_board_id / BOARD_ID_SIZE);
msm_data_count = (len_plat_id / PLAT_ID_SIZE);
+ /* If dtb version is v2.0, the pmic_data_count will be <= 0 */
+ pmic_data_count = (len_pmic_id / PMIC_ID_SIZE);
- /* If we are using dtb v2.0, then we have split board & msm data in the DTB */
+ /* If we are using dtb v3.0, then we have split board, msm & pmic data in the DTB
+ * If we are using dtb v2.0, then we have split board & msmdata in the DTB
+ */
board_data = (struct board_id *) malloc(sizeof(struct board_id) * (len_board_id / BOARD_ID_SIZE));
ASSERT(board_data);
platform_data = (struct plat_id *) malloc(sizeof(struct plat_id) * (len_plat_id / PLAT_ID_SIZE));
ASSERT(platform_data);
+ if (dtb_ver == DEV_TREE_VERSION_V3) {
+ pmic_data = (struct pmic_id *) malloc(sizeof(struct pmic_id) * (len_pmic_id / PMIC_ID_SIZE));
+ ASSERT(pmic_data);
+ }
i = 0;
/* Extract board data from DTB */
- for(i = 0 ; i < board_data_count; i++)
- {
+ for(i = 0 ; i < board_data_count; i++) {
board_data[i].variant_id = fdt32_to_cpu(((struct board_id *)board_prop)->variant_id);
board_data[i].platform_subtype = fdt32_to_cpu(((struct board_id *)board_prop)->platform_subtype);
+ /* For V2/V3 version of DTBs we have platform version field as part
+ * of variant ID, in such case the subtype will be mentioned as 0x0
+ * As the qcom, board-id = <0xSSPMPmPH, 0x0>
+ * SS -- Subtype
+ * PM -- Platform major version
+ * Pm -- Platform minor version
+ * PH -- Platform hardware CDP/MTP
+ * In such case to make it compatible with LK algorithm move the subtype
+ * from variant_id to subtype field
+ */
+ if (board_data[i].platform_subtype == 0)
+ board_data[i].platform_subtype =
+ fdt32_to_cpu(((struct board_id *)board_prop)->variant_id) >> 0x18;
+
len_board_id -= sizeof(struct board_id);
board_prop += sizeof(struct board_id);
}
/* Extract platform data from DTB */
- for(i = 0 ; i < msm_data_count; i++)
- {
+ for(i = 0 ; i < msm_data_count; i++) {
platform_data[i].platform_id = fdt32_to_cpu(((struct plat_id *)plat_prop)->platform_id);
platform_data[i].soc_rev = fdt32_to_cpu(((struct plat_id *)plat_prop)->soc_rev);
len_plat_id -= sizeof(struct plat_id);
plat_prop += sizeof(struct plat_id);
}
- /* We need to merge board & platform data into dt entry structure */
- num_entries = msm_data_count * board_data_count;
- dt_entry_v2 = (struct dt_entry*) malloc(sizeof(struct dt_entry) * num_entries);
- ASSERT(dt_entry_v2);
+ if (dtb_ver == DEV_TREE_VERSION_V3 && pmic_prop) {
+ /* Extract pmic data from DTB */
+ for(i = 0 ; i < pmic_data_count; i++) {
+ pmic_data[i].pmic_version[0]= fdt32_to_cpu(((struct pmic_id *)pmic_prop)->pmic_version[0]);
+ pmic_data[i].pmic_version[1]= fdt32_to_cpu(((struct pmic_id *)pmic_prop)->pmic_version[1]);
+ pmic_data[i].pmic_version[2]= fdt32_to_cpu(((struct pmic_id *)pmic_prop)->pmic_version[2]);
+ pmic_data[i].pmic_version[3]= fdt32_to_cpu(((struct pmic_id *)pmic_prop)->pmic_version[3]);
+ len_pmic_id -= sizeof(struct pmic_id);
+ pmic_prop += sizeof(struct pmic_id);
+ }
+
+ /* We need to merge board & platform data into dt entry structure */
+ num_entries = msm_data_count * board_data_count * pmic_data_count;
+ } else {
+ /* We need to merge board & platform data into dt entry structure */
+ num_entries = msm_data_count * board_data_count;
+ }
+
+ if ((((uint64_t)msm_data_count * (uint64_t)board_data_count * (uint64_t)pmic_data_count) !=
+ msm_data_count * board_data_count * pmic_data_count) ||
+ (((uint64_t)msm_data_count * (uint64_t)board_data_count) != msm_data_count * board_data_count)) {
+
+ free(board_data);
+ free(platform_data);
+ if (pmic_data)
+ free(pmic_data);
+ if (model)
+ free(model);
+ return false;
+ }
+
+ dt_entry_array = (struct dt_entry*) malloc(sizeof(struct dt_entry) * num_entries);
+ ASSERT(dt_entry_array);
/* If we have '<X>; <Y>; <Z>' as platform data & '<A>; <B>; <C>' as board data.
* Then dt entry should look like
@@ -211,84 +327,78 @@
*/
i = 0;
k = 0;
- for (i = 0; i < msm_data_count; i++)
- {
- for (j = 0; j < board_data_count; j++)
- {
- dt_entry_v2[k].platform_id = platform_data[i].platform_id;
- dt_entry_v2[k].soc_rev = platform_data[i].soc_rev;
- dt_entry_v2[k].variant_id = board_data[j].variant_id;
- dt_entry_v2[k].board_hw_subtype = board_data[j].platform_subtype;
- k++;
+ n = 0;
+ for (i = 0; i < msm_data_count; i++) {
+ for (j = 0; j < board_data_count; j++) {
+ if (dtb_ver == DEV_TREE_VERSION_V3 && pmic_prop) {
+ for (n = 0; n < pmic_data_count; n++) {
+ dt_entry_array[k].platform_id = platform_data[i].platform_id;
+ dt_entry_array[k].soc_rev = platform_data[i].soc_rev;
+ dt_entry_array[k].variant_id = board_data[j].variant_id;
+ dt_entry_array[k].board_hw_subtype = board_data[j].platform_subtype;
+ dt_entry_array[k].pmic_rev[0]= pmic_data[n].pmic_version[0];
+ dt_entry_array[k].pmic_rev[1]= pmic_data[n].pmic_version[1];
+ dt_entry_array[k].pmic_rev[2]= pmic_data[n].pmic_version[2];
+ dt_entry_array[k].pmic_rev[3]= pmic_data[n].pmic_version[3];
+ dt_entry_array[k].offset = (uint32_t)dtb;
+ dt_entry_array[k].size = dtb_size;
+ k++;
+ }
+
+ } else {
+ dt_entry_array[k].platform_id = platform_data[i].platform_id;
+ dt_entry_array[k].soc_rev = platform_data[i].soc_rev;
+ dt_entry_array[k].variant_id = board_data[j].variant_id;
+ dt_entry_array[k].board_hw_subtype = board_data[j].platform_subtype;
+ dt_entry_array[k].pmic_rev[0]= board_pmic_target(0);
+ dt_entry_array[k].pmic_rev[1]= board_pmic_target(1);
+ dt_entry_array[k].pmic_rev[2]= board_pmic_target(2);
+ dt_entry_array[k].pmic_rev[3]= board_pmic_target(3);
+ dt_entry_array[k].offset = (uint32_t)dtb;
+ dt_entry_array[k].size = dtb_size;
+ k++;
+ }
}
}
- /* Now find the matching entry in the merged list */
- if (board_hardware_id() == HW_PLATFORM_QRD)
- {
- board_dt_data.target_variant_id = board_target_id();
- board_dt_data.platform_variant_id = board_platform_id();
- }
- else
- {
- board_dt_data.target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
- board_dt_data.platform_variant_id = board_platform_id();
- }
-
- for (i=0 ;i < num_entries; i++)
- {
+ for (i=0 ;i < num_entries; i++) {
dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u %u 0x%x)\n",
*model ? model : "unknown",
- dt_entry_v2[i].platform_id, dt_entry_v2[i].variant_id, dt_entry_v2[i].board_hw_subtype, dt_entry_v2[i].soc_rev);
+ dt_entry_array[i].platform_id, dt_entry_array[i].variant_id, dt_entry_array[i].board_hw_subtype, dt_entry_array[i].soc_rev);
- if (platform_dt_match(&dt_entry_v2[i], &board_dt_data, 0xff) == 1)
- {
+ if (platform_dt_absolute_match(&(dt_entry_array[i]), dtb_list)) {
+ dprintf(SPEW, "Device tree exact match the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
+ dt_entry_array[i].platform_id,
+ dt_entry_array[i].variant_id,
+ dt_entry_array[i].soc_rev,
+ dt_entry_array[i].board_hw_subtype,
+ board_platform_id(),
+ board_hardware_id(),
+ board_hardware_subtype(),
+ board_soc_version());
+
+ } else {
dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u %u 0x%x> != <%u %u %u 0x%x>\n",
- dt_entry_v2[i].platform_id,
- dt_entry_v2[i].variant_id,
- dt_entry_v2[i].soc_rev,
- dt_entry_v2[i].board_hw_subtype,
- board_platform_id(),
- board_hardware_id(),
- board_hardware_subtype(),
- board_soc_version());
- continue;
- }
- else
- {
- /* If found a match, return the cur_dt_entry */
- found = 1;
- cur_dt_entry = dt_entry_v2[i];
- break;
+ dt_entry_array[i].platform_id,
+ dt_entry_array[i].variant_id,
+ dt_entry_array[i].soc_rev,
+ dt_entry_array[i].board_hw_subtype,
+ board_platform_id(),
+ board_hardware_id(),
+ board_hardware_subtype(),
+ board_soc_version());
}
}
+
+ free(board_data);
+ free(platform_data);
+ if (pmic_data)
+ free(pmic_data);
+ free(dt_entry_array);
}
-
- if (!found)
- {
- soc_rev = INVALID_SOC_REV_ID;
- goto end;
- }
- else
- soc_rev = cur_dt_entry.soc_rev;
-
- dprintf(INFO, "Device tree's msm_id matches the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
- cur_dt_entry.platform_id,
- cur_dt_entry.variant_id,
- cur_dt_entry.board_hw_subtype,
- cur_dt_entry.soc_rev,
- board_platform_id(),
- board_hardware_id(),
- board_hardware_subtype(),
- board_soc_version());
-
-end:
- free(board_data);
- free(platform_data);
- free(dt_entry_v2);
- free(model);
-
- return soc_rev;
+ if (model)
+ free(model);
+ return true;
}
/*
@@ -306,10 +416,25 @@
{
void *kernel_end = kernel + kernel_size;
uint32_t app_dtb_offset = 0;
- void *dtb;
+ void *dtb = NULL;
void *bestmatch_tag = NULL;
+ struct dt_entry *best_match_dt_entry = NULL;
uint32_t bestmatch_tag_size;
- uint32_t bestmatch_soc_rev_id = INVALID_SOC_REV_ID;
+ struct dt_entry_node *dt_entry_queue = NULL;
+ struct dt_entry_node *dt_node_tmp1 = NULL;
+ struct dt_entry_node *dt_node_tmp2 = NULL;
+
+
+ /* Initialize the dtb entry node*/
+ dt_entry_queue = (struct dt_entry_node *)
+ malloc(sizeof(struct dt_entry_node));
+
+ if (!dt_entry_queue) {
+ dprintf(CRITICAL, "Out of memory\n");
+ return NULL;
+ }
+ list_initialize(&dt_entry_queue->node);
+
memcpy((void*) &app_dtb_offset, (void*) (kernel + DTB_OFFSET), sizeof(uint32_t));
@@ -318,7 +443,6 @@
}
dtb = kernel + app_dtb_offset;
while (((uintptr_t)dtb + sizeof(struct fdt_header)) < (uintptr_t)kernel_end) {
- uint32_t dtb_soc_rev_id;
struct fdt_header dtb_hdr;
uint32_t dtb_size;
@@ -336,34 +460,36 @@
return NULL;
}
- /* now that we know we have a valid DTB, we need to copy
- * it somewhere aligned, like tags */
- memcpy(tags, dtb, dtb_size);
-
- dtb_soc_rev_id = dev_tree_compatible(tags);
- if (dtb_soc_rev_id == board_soc_version()) {
- /* clear out the old DTB magic so kernel doesn't find it */
- *((uint32_t *)(kernel + app_dtb_offset)) = 0;
- return tags;
- } else if ((dtb_soc_rev_id != INVALID_SOC_REV_ID) &&
- (dtb_soc_rev_id < board_soc_version())) {
- /* if current bestmatch is less than new dtb_soc_rev_id then update
- bestmatch_tag */
- if((bestmatch_soc_rev_id == INVALID_SOC_REV_ID) ||
- (bestmatch_soc_rev_id < dtb_soc_rev_id)) {
- bestmatch_tag = dtb;
- bestmatch_tag_size = dtb_size;
- bestmatch_soc_rev_id = dtb_soc_rev_id;
- }
- }
+ dev_tree_compatible(dtb, dtb_size, dt_entry_queue);
/* goto the next device tree if any */
dtb += dtb_size;
}
+ best_match_dt_entry = platform_dt_match_best(dt_entry_queue);
+ if (best_match_dt_entry){
+ bestmatch_tag = (void *)best_match_dt_entry->offset;
+ bestmatch_tag_size = best_match_dt_entry->size;
+ dprintf(INFO, "Best match DTB tags %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+ best_match_dt_entry->platform_id, best_match_dt_entry->variant_id,
+ best_match_dt_entry->board_hw_subtype, best_match_dt_entry->soc_rev,
+ best_match_dt_entry->pmic_rev[0], best_match_dt_entry->pmic_rev[1],
+ best_match_dt_entry->pmic_rev[2], best_match_dt_entry->pmic_rev[3],
+ best_match_dt_entry->offset, best_match_dt_entry->size);
+ dprintf(INFO, "Using pmic info 0x%0x/0x%x/0x%x/0x%0x for device 0x%0x/0x%x/0x%x/0x%0x\n",
+ best_match_dt_entry->pmic_rev[0], best_match_dt_entry->pmic_rev[1],
+ best_match_dt_entry->pmic_rev[2], best_match_dt_entry->pmic_rev[3],
+ board_pmic_target(0), board_pmic_target(1),
+ board_pmic_target(2), board_pmic_target(3));
+ }
+ /* free queue's memory */
+ list_for_every_entry(&dt_entry_queue->node, dt_node_tmp1, dt_node, node) {
+ dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_entry_list_delete(dt_node_tmp1);
+ dt_node_tmp1 = dt_node_tmp2;
+ }
+
if(bestmatch_tag) {
- dprintf(INFO,"DTB found with bestmatch soc rev id 0x%x.Board soc rev id 0x%x\n",
- bestmatch_soc_rev_id, board_soc_version());
memcpy(tags, bestmatch_tag, bestmatch_tag_size);
/* clear out the old DTB magic so kernel doesn't find it */
*((uint32_t *)(kernel + app_dtb_offset)) = 0;
@@ -390,6 +516,8 @@
if (table->version == DEV_TREE_VERSION_V1) {
dt_entry_size = sizeof(struct dt_entry_v1);
} else if (table->version == DEV_TREE_VERSION_V2) {
+ dt_entry_size = sizeof(struct dt_entry_v2);
+ } else if (table->version == DEV_TREE_VERSION_V3) {
dt_entry_size = sizeof(struct dt_entry);
} else {
dprintf(CRITICAL, "ERROR: Unsupported version (%d) in DT table \n",
@@ -410,64 +538,350 @@
return 0;
}
-static int platform_dt_match(struct dt_entry *cur_dt_entry, struct board_dt_entry *board_dt_data, uint32_t subtype_mask)
+static int platform_dt_absolute_match(struct dt_entry *cur_dt_entry, struct dt_entry_node *dt_list)
{
- /*
- * 1. Check if cur_dt_entry has platform_hw_version major & minor present?
- * 2. If present, calculate cur_dt_target_id for the current platform as:
- * 3. bit no |31 24 | 23 16| 15 8 |7 0|
- * 4. |subtype| major | minor |hw_platform|
- */
- uint32_t cur_dt_target_id ;
uint32_t cur_dt_hlos_subtype;
+ uint32_t cur_dt_hw_platform;
+ uint32_t cur_dt_hw_subtype;
+ uint32_t cur_dt_msm_id;
+ dt_node *dt_node_tmp = NULL;
- /*
- * if variant_id has platform_hw_ver has major = 0xff and minor = 0xff,
- * ignore the major & minor versions from the DTB entry
- */
- if ((cur_dt_entry->variant_id & 0xffff00) == 0xffff00)
- cur_dt_target_id = (cur_dt_entry->variant_id & 0xff0000ff) | (board_dt_data->target_variant_id & 0xffff00);
- /*
- * We have a valid platform_hw_version major & minor numbers in the board-id, so
- * use the board-id from the DTB.
- * Note: For some QRD platforms the format used is qcom, board-id = <0xMVmVPT 0xPS>
- * where: MV: platform major ver, mV: platform minor ver, PT: platform type
- * PS: platform subtype, so we need to put PS @ bit 24-31 to be backward compatible.
- */
- else
- cur_dt_target_id = cur_dt_entry->variant_id | ((cur_dt_entry->board_hw_subtype & subtype_mask & 0xff) << 24);
+ /* Platform-id
+ * bit no |31 24|23 16|15 0|
+ * |reserved|foundry-id|msm-id|
+ */
+ cur_dt_msm_id = (cur_dt_entry->platform_id & 0x0000ffff);
+ cur_dt_hw_platform = (cur_dt_entry->variant_id & 0x000000ff);
+ cur_dt_hw_subtype = (cur_dt_entry->board_hw_subtype);
+
+
/* Determine the bits 23:8 to check the DT with the DDR Size */
cur_dt_hlos_subtype = (cur_dt_entry->board_hw_subtype & 0xffff00);
- /* 1. must match the platform_id, platform_hw_id, platform_version
- * 2. soc rev number equal then return 0
- * 3. dt soc rev number less than cdt return -1
- * 4. otherwise return 1
+ /* 1. must match the msm_id, platform_hw_id, platform_subtype and DDR size
+ * soc, board major/minor, pmic major/minor must less than board info
+ * 2. find the matched DTB then return 1
+ * 3. otherwise return 0
*/
+ if((cur_dt_msm_id == (board_platform_id() & 0x0000ffff)) &&
+ (cur_dt_hw_platform == board_hardware_id()) &&
+ (cur_dt_hw_subtype == board_hardware_subtype()) &&
+ (cur_dt_hlos_subtype == target_get_hlos_subtype()) &&
+ (cur_dt_entry->soc_rev <= board_soc_version()) &&
+ ((cur_dt_entry->variant_id & 0x00ffff00) <= (board_target_id() & 0x00ffff00)) &&
+ ((cur_dt_entry->pmic_rev[0] & 0x00ffff00) <= (board_pmic_target(0) & 0x00ffff00)) &&
+ ((cur_dt_entry->pmic_rev[1] & 0x00ffff00) <= (board_pmic_target(1) & 0x00ffff00)) &&
+ ((cur_dt_entry->pmic_rev[2] & 0x00ffff00) <= (board_pmic_target(2) & 0x00ffff00)) &&
+ ((cur_dt_entry->pmic_rev[3] & 0x00ffff00) <= (board_pmic_target(3) & 0x00ffff00))) {
- if((cur_dt_entry->platform_id == board_dt_data->platform_variant_id) &&
- (cur_dt_target_id == board_dt_data->target_variant_id) &&
- (cur_dt_hlos_subtype == target_get_hlos_subtype())) {
- if(cur_dt_entry->soc_rev == board_soc_version()) {
+ dt_node_tmp = dt_entry_list_init();
+ memcpy((char*)dt_node_tmp->dt_entry_m,(char*)cur_dt_entry, sizeof(struct dt_entry));
+
+ dprintf(SPEW, "Add DTB entry %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+ dt_node_tmp->dt_entry_m->platform_id, dt_node_tmp->dt_entry_m->variant_id,
+ dt_node_tmp->dt_entry_m->board_hw_subtype, dt_node_tmp->dt_entry_m->soc_rev,
+ dt_node_tmp->dt_entry_m->pmic_rev[0], dt_node_tmp->dt_entry_m->pmic_rev[1],
+ dt_node_tmp->dt_entry_m->pmic_rev[2], dt_node_tmp->dt_entry_m->pmic_rev[3],
+ dt_node_tmp->dt_entry_m->offset, dt_node_tmp->dt_entry_m->size);
+
+ insert_dt_entry_in_queue(dt_list, dt_node_tmp);
+ return 1;
+ }
+ return 0;
+}
+
+static int platform_dt_absolute_compat_match(struct dt_entry_node *dt_list, uint32_t dtb_info) {
+ struct dt_entry_node *dt_node_tmp1 = NULL;
+ struct dt_entry_node *dt_node_tmp2 = NULL;
+ uint32_t current_info = 0;
+ uint32_t board_info = 0;
+ uint32_t best_info = 0;
+ uint32_t current_pmic_model[4] = {0, 0, 0, 0};
+ uint32_t board_pmic_model[4] = {0, 0, 0, 0};
+ uint32_t best_pmic_model[4] = {0, 0, 0, 0};
+ uint32_t delete_current_dt = 0;
+ uint32_t i;
+
+ /* start to select the exact entry
+ * default to exact match 0, if find current DTB entry info is the same as board info,
+ * then exact match board info.
+ */
+ list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+ if (!dt_node_tmp1){
+ dprintf(SPEW, "Current node is the end\n");
+ break;
+ }
+ switch(dtb_info) {
+ case DTB_FOUNDRY:
+ current_info = ((dt_node_tmp1->dt_entry_m->platform_id) & 0x00ff0000);
+ board_info = board_foundry_id();
+ break;
+ case DTB_PMIC_MODEL:
+ for (i = 0; i < 4; i++) {
+ current_pmic_model[i] = (dt_node_tmp1->dt_entry_m->pmic_rev[i] & 0xff);
+ board_pmic_model[i] = (board_pmic_target(i) & 0xff);
+ }
+ break;
+ default:
+ dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
+ dtb_info);
return 0;
- } else if(cur_dt_entry->soc_rev < board_soc_version()) {
- return -1;
+ }
+
+ if (dtb_info == DTB_PMIC_MODEL) {
+ if ((current_pmic_model[0] == board_pmic_model[0]) &&
+ (current_pmic_model[1] == board_pmic_model[1]) &&
+ (current_pmic_model[2] == board_pmic_model[2]) &&
+ (current_pmic_model[3] == board_pmic_model[3])) {
+
+ for (i = 0; i < 4; i++) {
+ best_pmic_model[i] = current_pmic_model[i];
+ }
+ break;
+ }
+ } else {
+ if (current_info == board_info) {
+ best_info = current_info;
+ break;
+ }
+ }
+ }
+
+ list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+ if (!dt_node_tmp1){
+ dprintf(SPEW, "Current node is the end\n");
+ break;
+ }
+ switch(dtb_info) {
+ case DTB_FOUNDRY:
+ current_info = ((dt_node_tmp1->dt_entry_m->platform_id) & 0x00ff0000);
+ break;
+ case DTB_PMIC_MODEL:
+ for (i = 0; i < 4; i++) {
+ current_pmic_model[i] = (dt_node_tmp1->dt_entry_m->pmic_rev[i] & 0xff);
+ }
+ break;
+ default:
+ dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
+ dtb_info);
+ return 0;
+ }
+
+ if (dtb_info == DTB_PMIC_MODEL) {
+ if ((current_pmic_model[0] != best_pmic_model[0]) ||
+ (current_pmic_model[1] != best_pmic_model[1]) ||
+ (current_pmic_model[2] != best_pmic_model[2]) ||
+ (current_pmic_model[3] != best_pmic_model[3])) {
+
+ delete_current_dt = 1;
+ }
+ } else {
+ if (current_info != best_info) {
+ delete_current_dt = 1;
+ }
+ }
+
+ if (delete_current_dt) {
+ dprintf(SPEW, "Delete don't fit DTB entry %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+ dt_node_tmp1->dt_entry_m->platform_id, dt_node_tmp1->dt_entry_m->variant_id,
+ dt_node_tmp1->dt_entry_m->board_hw_subtype, dt_node_tmp1->dt_entry_m->soc_rev,
+ dt_node_tmp1->dt_entry_m->pmic_rev[0], dt_node_tmp1->dt_entry_m->pmic_rev[1],
+ dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
+ dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
+
+ dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_entry_list_delete(dt_node_tmp1);
+ dt_node_tmp1 = dt_node_tmp2;
+ delete_current_dt = 0;
}
}
return 1;
}
-static int __dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info,
- struct board_dt_entry *board_dt_data, uint32_t subtype_mask)
+static int update_dtb_entry_node(struct dt_entry_node *dt_list, uint32_t dtb_info) {
+ struct dt_entry_node *dt_node_tmp1 = NULL;
+ struct dt_entry_node *dt_node_tmp2 = NULL;
+ uint32_t current_info = 0;
+ uint32_t board_info = 0;
+ uint32_t best_info = 0;
+
+ /* start to select the best entry*/
+ list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+ if (!dt_node_tmp1){
+ dprintf(SPEW, "Current node is the end\n");
+ break;
+ }
+ switch(dtb_info) {
+ case DTB_SOC:
+ current_info = dt_node_tmp1->dt_entry_m->soc_rev;
+ board_info = board_soc_version();
+ break;
+ case DTB_MAJOR_MINOR:
+ current_info = ((dt_node_tmp1->dt_entry_m->variant_id) & 0x00ffff00);
+ board_info = (board_target_id() & 0x00ffff00);
+ break;
+ case DTB_PMIC0:
+ current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[0]) & 0x00ffff00);
+ board_info = (board_pmic_target(0) & 0x00ffff00);
+ break;
+ case DTB_PMIC1:
+ current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[1]) & 0x00ffff00);
+ board_info = (board_pmic_target(1) & 0x00ffff00);
+ break;
+ case DTB_PMIC2:
+ current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[2]) & 0x00ffff00);
+ board_info = (board_pmic_target(2) & 0x00ffff00);
+ break;
+ case DTB_PMIC3:
+ current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[3]) & 0x00ffff00);
+ board_info = (board_pmic_target(3) & 0x00ffff00);
+ break;
+ default:
+ dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
+ dtb_info);
+ return 0;
+ }
+
+ if (current_info == board_info) {
+ best_info = current_info;
+ break;
+ }
+ if ((current_info < board_info) && (current_info > best_info)) {
+ best_info = current_info;
+ }
+ if (current_info < best_info) {
+ dprintf(SPEW, "Delete don't fit DTB entry %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+ dt_node_tmp1->dt_entry_m->platform_id, dt_node_tmp1->dt_entry_m->variant_id,
+ dt_node_tmp1->dt_entry_m->board_hw_subtype, dt_node_tmp1->dt_entry_m->soc_rev,
+ dt_node_tmp1->dt_entry_m->pmic_rev[0], dt_node_tmp1->dt_entry_m->pmic_rev[1],
+ dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
+ dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
+
+ dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_entry_list_delete(dt_node_tmp1);
+ dt_node_tmp1 = dt_node_tmp2;
+ }
+ }
+
+ list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+ if (!dt_node_tmp1){
+ dprintf(SPEW, "Current node is the end\n");
+ break;
+ }
+ switch(dtb_info) {
+ case DTB_SOC:
+ current_info = dt_node_tmp1->dt_entry_m->soc_rev;
+ break;
+ case DTB_MAJOR_MINOR:
+ current_info = ((dt_node_tmp1->dt_entry_m->variant_id) & 0x00ffff00);
+ break;
+ case DTB_PMIC0:
+ current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[0]) & 0x00ffff00);
+ break;
+ case DTB_PMIC1:
+ current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[1]) & 0x00ffff00);
+ break;
+ case DTB_PMIC2:
+ current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[2]) & 0x00ffff00);
+ break;
+ case DTB_PMIC3:
+ current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[3]) & 0x00ffff00);
+ break;
+ default:
+ dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
+ dtb_info);
+ return 0;
+ }
+
+ if (current_info != best_info) {
+ dprintf(SPEW, "Delete don't fit DTB entry %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+ dt_node_tmp1->dt_entry_m->platform_id, dt_node_tmp1->dt_entry_m->variant_id,
+ dt_node_tmp1->dt_entry_m->board_hw_subtype, dt_node_tmp1->dt_entry_m->soc_rev,
+ dt_node_tmp1->dt_entry_m->pmic_rev[0], dt_node_tmp1->dt_entry_m->pmic_rev[1],
+ dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
+ dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
+
+ dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_entry_list_delete(dt_node_tmp1);
+ dt_node_tmp1 = dt_node_tmp2;
+ }
+ }
+ return 1;
+}
+
+static struct dt_entry *platform_dt_match_best(struct dt_entry_node *dt_list)
+{
+ struct dt_entry_node *dt_node_tmp1 = NULL;
+
+ /* check Foundry id
+ * the foundry id must exact match board founddry id, this is compatibility check,
+ * if couldn't find the exact match from DTB, will exact match 0x0.
+ */
+ if (!platform_dt_absolute_compat_match(dt_list, DTB_FOUNDRY))
+ return NULL;
+
+ /* check PMIC model
+ * the PMIC model must exact match board PMIC model, this is compatibility check,
+ * if couldn't find the exact match from DTB, will exact match 0x0.
+ */
+ if (!platform_dt_absolute_compat_match(dt_list, DTB_PMIC_MODEL))
+ return NULL;
+
+ /* check soc version
+ * the suitable soc version must less than or equal to board soc version
+ */
+ if (!update_dtb_entry_node(dt_list, DTB_SOC))
+ return NULL;
+
+ /*check major and minor version
+ * the suitable major&minor version must less than or equal to board major&minor version
+ */
+ if (!update_dtb_entry_node(dt_list, DTB_MAJOR_MINOR))
+ return NULL;
+
+ /*check pmic info
+ * the suitable pmic major&minor info must less than or equal to board pmic major&minor version
+ */
+ if (!update_dtb_entry_node(dt_list, DTB_PMIC0))
+ return NULL;
+ if (!update_dtb_entry_node(dt_list, DTB_PMIC1))
+ return NULL;
+ if (!update_dtb_entry_node(dt_list, DTB_PMIC2))
+ return NULL;
+ if (!update_dtb_entry_node(dt_list, DTB_PMIC3))
+ return NULL;
+
+ list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+ if (!dt_node_tmp1) {
+ dprintf(CRITICAL, "ERROR: Couldn't find the suitable DTB!\n");
+ return NULL;
+ }
+ if (dt_node_tmp1->dt_entry_m)
+ return dt_node_tmp1->dt_entry_m;
+ }
+
+ return NULL;
+}
+
+/* Function to obtain the index information for the correct device tree
+ * based on the platform data.
+ * If a matching device tree is found, the information is returned in the
+ * "dt_entry_info" out parameter and a function value of 0 is returned, otherwise
+ * a non-zero function value is returned.
+ */
+int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info)
{
uint32_t i;
- unsigned char *table_ptr;
+ unsigned char *table_ptr = NULL;
struct dt_entry dt_entry_buf_1;
- struct dt_entry dt_entry_buf_2;
- struct dt_entry *cur_dt_entry;
- struct dt_entry *best_match_dt_entry;
- struct dt_entry_v1 *dt_entry_v1;
+ struct dt_entry *cur_dt_entry = NULL;
+ struct dt_entry *best_match_dt_entry = NULL;
+ struct dt_entry_v1 *dt_entry_v1 = NULL;
+ struct dt_entry_v2 *dt_entry_v2 = NULL;
+ struct dt_entry_node *dt_entry_queue = NULL;
+ struct dt_entry_node *dt_node_tmp1 = NULL;
+ struct dt_entry_node *dt_node_tmp2 = NULL;
uint32_t found = 0;
if (!dt_entry_info) {
@@ -479,7 +893,16 @@
table_ptr = (unsigned char *)table + DEV_TREE_HEADER_SIZE;
cur_dt_entry = &dt_entry_buf_1;
best_match_dt_entry = NULL;
+ dt_entry_queue = (struct dt_entry_node *)
+ malloc(sizeof(struct dt_entry_node));
+ if (!dt_entry_queue) {
+ dprintf(CRITICAL, "Out of memory\n");
+ return -1;
+ }
+
+ list_initialize(&dt_entry_queue->node);
+ dprintf(INFO, "DTB Total entry: %d, DTB version: %d\n", table->num_entries, table->version);
for(i = 0; found == 0 && i < table->num_entries; i++)
{
memset(cur_dt_entry, 0, sizeof(struct dt_entry));
@@ -489,48 +912,74 @@
cur_dt_entry->platform_id = dt_entry_v1->platform_id;
cur_dt_entry->variant_id = dt_entry_v1->variant_id;
cur_dt_entry->soc_rev = dt_entry_v1->soc_rev;
- cur_dt_entry->board_hw_subtype = board_hardware_subtype();
+ cur_dt_entry->board_hw_subtype = (dt_entry_v1->variant_id >> 0x18);
+ cur_dt_entry->pmic_rev[0] = board_pmic_target(0);
+ cur_dt_entry->pmic_rev[1] = board_pmic_target(1);
+ cur_dt_entry->pmic_rev[2] = board_pmic_target(2);
+ cur_dt_entry->pmic_rev[3] = board_pmic_target(3);
cur_dt_entry->offset = dt_entry_v1->offset;
cur_dt_entry->size = dt_entry_v1->size;
table_ptr += sizeof(struct dt_entry_v1);
break;
case DEV_TREE_VERSION_V2:
+ dt_entry_v2 = (struct dt_entry_v2*)table_ptr;
+ cur_dt_entry->platform_id = dt_entry_v2->platform_id;
+ cur_dt_entry->variant_id = dt_entry_v2->variant_id;
+ cur_dt_entry->soc_rev = dt_entry_v2->soc_rev;
+ /* For V2 version of DTBs we have platform version field as part
+ * of variant ID, in such case the subtype will be mentioned as 0x0
+ * As the qcom, board-id = <0xSSPMPmPH, 0x0>
+ * SS -- Subtype
+ * PM -- Platform major version
+ * Pm -- Platform minor version
+ * PH -- Platform hardware CDP/MTP
+ * In such case to make it compatible with LK algorithm move the subtype
+ * from variant_id to subtype field
+ */
+ if (dt_entry_v2->board_hw_subtype == 0)
+ cur_dt_entry->board_hw_subtype = (cur_dt_entry->variant_id >> 0x18);
+ else
+ cur_dt_entry->board_hw_subtype = dt_entry_v2->board_hw_subtype;
+ cur_dt_entry->pmic_rev[0] = board_pmic_target(0);
+ cur_dt_entry->pmic_rev[1] = board_pmic_target(1);
+ cur_dt_entry->pmic_rev[2] = board_pmic_target(2);
+ cur_dt_entry->pmic_rev[3] = board_pmic_target(3);
+ cur_dt_entry->offset = dt_entry_v2->offset;
+ cur_dt_entry->size = dt_entry_v2->size;
+ table_ptr += sizeof(struct dt_entry_v2);
+ break;
+ case DEV_TREE_VERSION_V3:
memcpy(cur_dt_entry, (struct dt_entry *)table_ptr,
sizeof(struct dt_entry));
+ /* For V3 version of DTBs we have platform version field as part
+ * of variant ID, in such case the subtype will be mentioned as 0x0
+ * As the qcom, board-id = <0xSSPMPmPH, 0x0>
+ * SS -- Subtype
+ * PM -- Platform major version
+ * Pm -- Platform minor version
+ * PH -- Platform hardware CDP/MTP
+ * In such case to make it compatible with LK algorithm move the subtype
+ * from variant_id to subtype field
+ */
+ if (cur_dt_entry->board_hw_subtype == 0)
+ cur_dt_entry->board_hw_subtype = (cur_dt_entry->variant_id >> 0x18);
+
table_ptr += sizeof(struct dt_entry);
break;
default:
dprintf(CRITICAL, "ERROR: Unsupported version (%d) in DT table \n",
table->version);
+ free(dt_entry_queue);
return -1;
}
- /* DTBs are stored in the ascending order of soc revision.
- * For eg: Rev0..Rev1..Rev2 & so on.
- * we pickup the DTB with highest soc rev number which is less
- * than or equal to actual hardware
- */
- switch(platform_dt_match(cur_dt_entry, board_dt_data, subtype_mask)) {
- case 0:
- best_match_dt_entry = cur_dt_entry;
- found = 1;
- break;
- case -1:
- if (!best_match_dt_entry) {
- /* copy structure */
- best_match_dt_entry = cur_dt_entry;
- cur_dt_entry = &dt_entry_buf_2;
- } else {
- /* Swap dt_entry buffers */
- struct dt_entry *temp = cur_dt_entry;
- cur_dt_entry = best_match_dt_entry;
- best_match_dt_entry = temp;
- }
- default:
- break;
- }
- }
+ /* DTBs must match the platform_id, platform_hw_id, platform_subtype and DDR size.
+ * The satisfactory DTBs are stored in dt_entry_queue
+ */
+ platform_dt_absolute_match(cur_dt_entry, dt_entry_queue);
+ }
+ best_match_dt_entry = platform_dt_match_best(dt_entry_queue);
if (best_match_dt_entry) {
*dt_entry_info = *best_match_dt_entry;
found = 1;
@@ -540,71 +989,37 @@
dprintf(INFO, "Using DTB entry 0x%08x/%08x/0x%08x/%u for device 0x%08x/%08x/0x%08x/%u\n",
dt_entry_info->platform_id, dt_entry_info->soc_rev,
dt_entry_info->variant_id, dt_entry_info->board_hw_subtype,
- board_dt_data->platform_variant_id, board_soc_version(),
- board_dt_data->target_variant_id, board_hardware_subtype());
+ board_platform_id(), board_soc_version(),
+ board_target_id(), board_hardware_subtype());
+ if (dt_entry_info->pmic_rev[0] == 0 && dt_entry_info->pmic_rev[0] == 0 &&
+ dt_entry_info->pmic_rev[0] == 0 && dt_entry_info->pmic_rev[0] == 0) {
+ dprintf(SPEW, "No maintain pmic info in DTB, device pmic info is 0x%0x/0x%x/0x%x/0x%0x\n",
+ board_pmic_target(0), board_pmic_target(1),
+ board_pmic_target(2), board_pmic_target(3));
+ } else {
+ dprintf(INFO, "Using pmic info 0x%0x/0x%x/0x%x/0x%0x for device 0x%0x/0x%x/0x%x/0x%0x\n",
+ dt_entry_info->pmic_rev[0], dt_entry_info->pmic_rev[1],
+ dt_entry_info->pmic_rev[2], dt_entry_info->pmic_rev[3],
+ board_pmic_target(0), board_pmic_target(1),
+ board_pmic_target(2), board_pmic_target(3));
+ }
return 0;
}
- dprintf(CRITICAL, "INFO: Unable to find suitable device tree for device (0x%08x/0x%08x/0x%08x/%u)\n",
- board_dt_data->platform_variant_id, board_soc_version(),
- board_dt_data->target_variant_id, board_hardware_subtype());
+ dprintf(CRITICAL, "ERROR: Unable to find suitable device tree for device (%u/0x%08x/0x%08x/%u)\n",
+ board_platform_id(), board_soc_version(),
+ board_target_id(), board_hardware_subtype());
+
+ list_for_every_entry(&dt_entry_queue->node, dt_node_tmp1, dt_node, node) {
+ /* free node memory */
+ dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_entry_list_delete(dt_node_tmp1);
+ dt_node_tmp1 = dt_node_tmp2;
+ }
+ free(dt_entry_queue);
return -1;
}
-/* Function to obtain the index information for the correct device tree
- * based on the platform data.
- * If a matching device tree is found, the information is returned in the
- * "dt_entry_info" out parameter and a function value of 0 is returned, otherwise
- * a non-zero function value is returned.
- */
-int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info)
-{
- struct board_dt_entry board_dt_data;
-
- /* 1. Look for new board-id (platform version + hw + subtype) & new msm-id (soc ver + soc id + foundry-id) */
- board_dt_data.target_variant_id = board_target_id();
- /* Platform-id
- * bit no |31 24|23 16|15 0|
- * |reserved|foundry-id|msm-id|
- */
- board_dt_data.platform_variant_id = board_platform_id() | (board_foundry_id() << 16);
- if (__dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0xff) == 0) {
- return 0;
- }
-
- /* 2. Look for new board-id & old msm-id (no foundry-id) */
- board_dt_data.target_variant_id = board_target_id();
- board_dt_data.platform_variant_id = board_platform_id();
- if (__dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0xff) == 0) {
- return 0;
- }
-
- /*
- * for compatible with version 1 and version 2 dtbtool
- * will compare the subtype inside the variant id
- */
-
- /* 3. Look for old board-id (no platform version) & new msm-id (with foundry-id) */
- board_dt_data.target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
- board_dt_data.platform_variant_id = board_platform_id() | (board_foundry_id() << 16);
- if (__dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0xff) == 0) {
- return 0;
- }
- /* 4. Look for old board-id (no platform versions) & old msm-id(no foundry-id) */
- board_dt_data.target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
- board_dt_data.platform_variant_id = board_platform_id();
- if (__dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0xff) == 0) {
- return 0;
- }
-
- /*
- * add compatible with old device selection method which don't compare subtype
- */
- board_dt_data.target_variant_id = board_hardware_id();
- board_dt_data.platform_variant_id = board_platform_id();
- return __dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0);
-}
-
/* Function to add the first RAM partition info to the device tree.
* Note: The function replaces the reg property in the "/memory" node
* with the addr and size provided.
@@ -852,12 +1267,15 @@
}
offset = ret;
- /* Adding the cmdline to the chosen node */
- ret = fdt_appendprop_string(fdt, offset, (const char*)"bootargs", (const void*)cmdline);
- if (ret)
+ if (cmdline)
{
- dprintf(CRITICAL, "ERROR: Cannot update chosen node [bootargs]\n");
- return ret;
+ /* Adding the cmdline to the chosen node */
+ ret = fdt_appendprop_string(fdt, offset, (const char*)"bootargs", (const void*)cmdline);
+ if (ret)
+ {
+ dprintf(CRITICAL, "ERROR: Cannot update chosen node [bootargs]\n");
+ return ret;
+ }
}
if (ramdisk_size) {
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index c73b06f..849b294 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -33,23 +33,6 @@
#include <mipi_dsi.h>
#include <boot_stats.h>
-#ifndef DISPLAY_TYPE_HDMI
-static int hdmi_dtv_init(void)
-{
- return 0;
-}
-
-static int hdmi_dtv_on(void)
-{
- return 0;
-}
-
-static int hdmi_msm_turn_on(void)
-{
- return 0;
-}
-#endif
-
static struct msm_fb_panel_data *panel;
extern int lvds_on(struct msm_fb_panel_data *pdata);
@@ -132,7 +115,7 @@
break;
case HDMI_PANEL:
dprintf(INFO, "Config HDMI PANEL.\n");
- ret = hdmi_dtv_init();
+ ret = mdss_hdmi_config(pinfo, &(panel->fb));
if (ret)
goto msm_display_config_out;
break;
@@ -211,11 +194,11 @@
break;
case HDMI_PANEL:
dprintf(INFO, "Turn on HDMI PANEL.\n");
- ret = hdmi_dtv_on();
+ ret = mdss_hdmi_init();
if (ret)
goto msm_display_on_out;
- ret = hdmi_msm_turn_on();
+ ret = mdss_hdmi_on();
if (ret)
goto msm_display_on_out;
break;
@@ -248,7 +231,7 @@
/* Turn on panel */
if (pdata->power_func)
- ret = pdata->power_func(1);
+ ret = pdata->power_func(1, &(panel->panel_info));
if (ret)
goto msm_display_init_out;
@@ -390,7 +373,7 @@
/* Disable panel */
if (panel->power_func)
- ret = panel->power_func(0);
+ ret = panel->power_func(0, pinfo);
msm_display_off_out:
return ret;
diff --git a/platform/msm_shared/hdmi.c b/platform/msm_shared/hdmi.c
deleted file mode 100644
index 422a506..0000000
--- a/platform/msm_shared/hdmi.c
+++ /dev/null
@@ -1,454 +0,0 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of The Linux Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#include <hdmi.h>
-#include <msm_panel.h>
-#include <platform/timer.h>
-#include <platform/clock.h>
-#include <platform/iomap.h>
-
-#define MDP4_OVERLAYPROC1_BASE 0x18000
-#define MDP4_RGB_BASE 0x40000
-#define MDP4_RGB_OFF 0x10000
-
-struct hdmi_disp_mode_timing_type hdmi_timing_default = {
- .height = 1080,
- .hsync_porch_fp = 88,
- .hsync_width = 44,
- .hsync_porch_bp = 148,
- .width = 1920,
- .vsync_porch_fp = 4,
- .vsync_width = 5,
- .vsync_porch_bp = 36,
- .bpp = 24,
-};
-
-static uint8_t hdmi_msm_avi_iframe_lut[][16] = {
-/* 480p60 480i60 576p50 576i50 720p60 720p50 1080p60 1080i60 1080p50
- 1080i50 1080p24 1080p30 1080p25 640x480p 480p60_16_9 576p50_4_3 */
- {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, /*00*/
- {0x18, 0x18, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
- 0x28, 0x28, 0x28, 0x28, 0x18, 0x28, 0x18}, /*01*/
- {0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
- 0x04, 0x04, 0x04, 0x04, 0x88, 0x00, 0x04}, /*02*/
- {0x02, 0x06, 0x11, 0x15, 0x04, 0x13, 0x10, 0x05, 0x1F,
- 0x14, 0x20, 0x22, 0x21, 0x01, 0x03, 0x11}, /*03*/
- {0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*04*/
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*05*/
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*06*/
- {0xE1, 0xE1, 0x41, 0x41, 0xD1, 0xd1, 0x39, 0x39, 0x39,
- 0x39, 0x39, 0x39, 0x39, 0xe1, 0xE1, 0x41}, /*07*/
- {0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x04, 0x04, 0x04,
- 0x04, 0x04, 0x04, 0x04, 0x01, 0x01, 0x02}, /*08*/
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*09*/
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*10*/
- {0xD1, 0xD1, 0xD1, 0xD1, 0x01, 0x01, 0x81, 0x81, 0x81,
- 0x81, 0x81, 0x81, 0x81, 0x81, 0xD1, 0xD1}, /*11*/
- {0x02, 0x02, 0x02, 0x02, 0x05, 0x05, 0x07, 0x07, 0x07,
- 0x07, 0x07, 0x07, 0x07, 0x02, 0x02, 0x02} /*12*/
-};
-
-void hdmi_msm_set_mode(int on)
-{
- uint32_t val = 0;
- if (on) {
- val |= 0x00000003;
- writel(val, HDMI_CTRL);
- } else {
- val &= ~0x00000002;
- writel(val, HDMI_CTRL);
- }
-}
-
-struct hdmi_disp_mode_timing_type *hdmi_common_init_panel_info()
-{
- return &hdmi_timing_default;
-}
-
-void hdmi_set_fb_addr(void *addr)
-{
- hdmi_timing_default.base = addr;
-}
-
-void hdmi_msm_panel_init(struct msm_panel_info *pinfo)
-{
- if (!pinfo)
- return;
-
- pinfo->xres = hdmi_timing_default.width;
- pinfo->yres = hdmi_timing_default.height;
- pinfo->bpp = hdmi_timing_default.bpp;
- pinfo->type = HDMI_PANEL;
-
- pinfo->hdmi.h_back_porch = hdmi_timing_default.hsync_porch_bp;
- pinfo->hdmi.h_front_porch = hdmi_timing_default.hsync_porch_fp;
- pinfo->hdmi.h_pulse_width = hdmi_timing_default.hsync_width;
- pinfo->hdmi.v_back_porch = hdmi_timing_default.vsync_porch_bp;
- pinfo->hdmi.v_front_porch = hdmi_timing_default.vsync_porch_fp;
- pinfo->hdmi.v_pulse_width = hdmi_timing_default.vsync_width;
-}
-
-void hdmi_frame_ctrl_reg()
-{
- uint32_t hdmi_frame_ctrl;
-
- hdmi_frame_ctrl = ((0 << 31) & 0x80000000);
- hdmi_frame_ctrl |= ((0 << 29) & 0x20000000);
- hdmi_frame_ctrl |= ((0 << 28) & 0x10000000);
- writel(hdmi_frame_ctrl, HDMI_FRAME_CTRL);
-}
-
-void hdmi_video_setup()
-{
- uint32_t hsync_total = 0;
- uint32_t vsync_total = 0;
- uint32_t hsync_start = 0;
- uint32_t hsync_end = 0;
- uint32_t vsync_start = 0;
- uint32_t vsync_end = 0;
- uint32_t hvsync_total = 0;
- uint32_t hsync_active = 0;
- uint32_t vsync_active = 0;
- uint32_t hdmi_frame_ctrl = 0;
- uint32_t val;
- struct hdmi_disp_mode_timing_type *hdmi_timing =
- hdmi_common_init_panel_info();
-
- hsync_total = hdmi_timing->width + hdmi_timing->hsync_porch_fp
- + hdmi_timing->hsync_porch_bp + hdmi_timing->hsync_width - 1;
- vsync_total = hdmi_timing->height + hdmi_timing->vsync_porch_fp
- + hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1;
-
- hvsync_total = (vsync_total << 16) & 0x0FFF0000;
- hvsync_total |= (hsync_total << 0) & 0x00000FFF;
- writel(hvsync_total, HDMI_TOTAL);
-
- hsync_start = hdmi_timing->hsync_porch_bp + hdmi_timing->hsync_width;
- hsync_end = (hsync_total + 1) - hdmi_timing->hsync_porch_fp;
- hsync_active = (hsync_end << 16) & 0x0FFF0000;
- hsync_active |= (hsync_start << 0) & 0x00000FFF;
- writel(hsync_active, HDMI_ACTIVE_HSYNC);
-
- vsync_start =
- hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1;
- vsync_end = vsync_total - hdmi_timing->vsync_porch_fp;
- vsync_active = (vsync_end << 16) & 0x0FFF0000;
- vsync_active |= (vsync_start << 0) & 0x00000FFF;
- writel(vsync_active, HDMI_ACTIVE_VSYNC);
-
- writel(0, HDMI_VSYNC_TOTAL_F2);
- writel(0, HDMI_VSYNC_ACTIVE_F2);
- hdmi_frame_ctrl_reg();
-}
-
-void hdmi_msm_avi_info_frame(void)
-{
- /* two header + length + 13 data */
- uint8_t aviInfoFrame[16];
- uint8_t checksum;
- uint32_t sum;
- uint32_t regVal;
- uint8_t i;
- uint8_t mode = 6; //HDMI_VFRMT_1920x1080p60_16_9
-
- /* InfoFrame Type = 82 */
- aviInfoFrame[0] = 0x82;
- /* Version = 2 */
- aviInfoFrame[1] = 2;
- /* Length of AVI InfoFrame = 13 */
- aviInfoFrame[2] = 13;
-
- /* Data Byte 01: 0 Y1 Y0 A0 B1 B0 S1 S0 */
- aviInfoFrame[3] = hdmi_msm_avi_iframe_lut[0][mode];
-
- /* Setting underscan bit */
- aviInfoFrame[3] |= 0x02;
-
- /* Data Byte 02: C1 C0 M1 M0 R3 R2 R1 R0 */
- aviInfoFrame[4] = hdmi_msm_avi_iframe_lut[1][mode];
- /* Data Byte 03: ITC EC2 EC1 EC0 Q1 Q0 SC1 SC0 */
- aviInfoFrame[5] = hdmi_msm_avi_iframe_lut[2][mode];
- /* Data Byte 04: 0 VIC6 VIC5 VIC4 VIC3 VIC2 VIC1 VIC0 */
- aviInfoFrame[6] = hdmi_msm_avi_iframe_lut[3][mode];
- /* Data Byte 05: 0 0 0 0 PR3 PR2 PR1 PR0 */
- aviInfoFrame[7] = hdmi_msm_avi_iframe_lut[4][mode];
- /* Data Byte 06: LSB Line No of End of Top Bar */
- aviInfoFrame[8] = hdmi_msm_avi_iframe_lut[5][mode];
- /* Data Byte 07: MSB Line No of End of Top Bar */
- aviInfoFrame[9] = hdmi_msm_avi_iframe_lut[6][mode];
- /* Data Byte 08: LSB Line No of Start of Bottom Bar */
- aviInfoFrame[10] = hdmi_msm_avi_iframe_lut[7][mode];
- /* Data Byte 09: MSB Line No of Start of Bottom Bar */
- aviInfoFrame[11] = hdmi_msm_avi_iframe_lut[8][mode];
- /* Data Byte 10: LSB Pixel Number of End of Left Bar */
- aviInfoFrame[12] = hdmi_msm_avi_iframe_lut[9][mode];
- /* Data Byte 11: MSB Pixel Number of End of Left Bar */
- aviInfoFrame[13] = hdmi_msm_avi_iframe_lut[10][mode];
- /* Data Byte 12: LSB Pixel Number of Start of Right Bar */
- aviInfoFrame[14] = hdmi_msm_avi_iframe_lut[11][mode];
- /* Data Byte 13: MSB Pixel Number of Start of Right Bar */
- aviInfoFrame[15] = hdmi_msm_avi_iframe_lut[12][mode];
-
- sum = 0;
- for (i = 0; i < 16; i++)
- sum += aviInfoFrame[i];
- sum &= 0xFF;
- sum = 256 - sum;
- checksum = (uint8_t) sum;
-
- regVal = aviInfoFrame[5];
- regVal = regVal << 8 | aviInfoFrame[4];
- regVal = regVal << 8 | aviInfoFrame[3];
- regVal = regVal << 8 | checksum;
- writel(regVal, MSM_HDMI_BASE + 0x006C);
-
- regVal = aviInfoFrame[9];
- regVal = regVal << 8 | aviInfoFrame[8];
- regVal = regVal << 8 | aviInfoFrame[7];
- regVal = regVal << 8 | aviInfoFrame[6];
- writel(regVal, MSM_HDMI_BASE + 0x0070);
-
- regVal = aviInfoFrame[13];
- regVal = regVal << 8 | aviInfoFrame[12];
- regVal = regVal << 8 | aviInfoFrame[11];
- regVal = regVal << 8 | aviInfoFrame[10];
- writel(regVal, MSM_HDMI_BASE + 0x0074);
-
- regVal = aviInfoFrame[1];
- regVal = regVal << 16 | aviInfoFrame[15];
- regVal = regVal << 8 | aviInfoFrame[14];
- writel(regVal, MSM_HDMI_BASE + 0x0078);
-
- /* INFOFRAME_CTRL0[0x002C] */
- /* 0x3 for AVI InfFrame enable (every frame) */
- writel(readl(0x002C) | 0x00000003L, MSM_HDMI_BASE + 0x002C);
-}
-
-void hdmi_app_clk_init(int on)
-{
- uint32_t val = 0;
- if (on) {
- /* Enable hdmi apps clock */
- val = readl(MISC_CC2_REG);
- val = BIT(11);
- writel(val, MISC_CC2_REG);
- udelay(10);
-
- /* Enable hdmi master clock */
- val = readl(MMSS_AHB_EN_REG);
- val |= BIT(14);
- writel(val, MMSS_AHB_EN_REG);
- udelay(10);
-
- /* Enable hdmi slave clock */
- val = readl(MMSS_AHB_EN_REG);
- val |= BIT(4);
- writel(val, MMSS_AHB_EN_REG);
- udelay(10);
- } else {
- // Disable clocks
- val = readl(MISC_CC2_REG);
- val &= ~(BIT(11));
- writel(val, MISC_CC2_REG);
- udelay(10);
- val = readl(MMSS_AHB_EN_REG);
- val &= ~(BIT(14));
- writel(val, MMSS_AHB_EN_REG);
- udelay(10);
- val = readl(MMSS_AHB_EN_REG);
- val &= ~(BIT(4));
- writel(val, MMSS_AHB_EN_REG);
- udelay(10);
- }
-}
-
-int hdmi_msm_turn_on(void)
-{
- uint32_t hotplug_control;
-
- hdmi_msm_set_mode(0);
-
- hdmi_msm_reset_core(); // Reset the core
- hdmi_msm_init_phy();
-
- // Enable USEC REF timer
- writel(0x0001001B, HDMI_USEC_REFTIMER);
-
- // Write 1 to HDMI_CTRL to enable HDMI
- hdmi_msm_set_mode(1);
-
- // Video setup for HDMI
- hdmi_video_setup();
-
- // AVI info setup
- hdmi_msm_avi_info_frame();
-
- return 0;
-}
-
-int hdmi_dtv_init()
-{
- uint32_t hsync_period;
- uint32_t hsync_ctrl;
- uint32_t hsync_start_x;
- uint32_t hsync_end_x;
- uint32_t display_hctl;
- uint32_t vsync_period;
- uint32_t display_v_start;
- uint32_t display_v_end;
- uint32_t hsync_polarity;
- uint32_t vsync_polarity;
- uint32_t data_en_polarity;
- uint32_t ctrl_polarity;
- uint32_t dtv_border_clr = 0;
- uint32_t dtv_underflow_clr = 0;
- uint32_t active_v_start = 0;
- uint32_t active_v_end = 0;
- uint32_t dtv_hsync_skew = 0;
- uint32_t intf, stage, snum, mask, data;
- unsigned char *rgb_base;
- unsigned char *overlay_base;
- uint32_t val;
-
- struct hdmi_disp_mode_timing_type *timing =
- hdmi_common_init_panel_info();
-
- // MDP E config
- writel((unsigned)timing->base, MDP_BASE + 0xb0008); //FB Address
- writel(((timing->height << 16) | timing->width), MDP_BASE + 0xb0004);
- writel((timing->width * timing->bpp / 8), MDP_BASE + 0xb000c);
- writel(0, MDP_BASE + 0xb0010);
-
- writel(DMA_PACK_PATTERN_RGB | DMA_DSTC0G_8BITS | DMA_DSTC1B_8BITS |
- DMA_DSTC2R_8BITS, MDP_BASE + 0xb0000);
- writel(0xff0000, MDP_BASE + 0xb0070);
- writel(0xff0000, MDP_BASE + 0xb0074);
- writel(0xff0000, MDP_BASE + 0xb0078);
-
- // overlay rgb setup RGB2
- rgb_base = MDP_BASE + MDP4_RGB_BASE;
- rgb_base += (MDP4_RGB_OFF * 1);
- writel(((timing->height << 16) | timing->width), rgb_base + 0x0000);
- writel(0x0, rgb_base + 0x0004);
- writel(((timing->height << 16) | timing->width), rgb_base + 0x0008);
- writel(0x0, rgb_base + 0x000c);
- writel(timing->base, rgb_base + 0x0010); //FB address
- writel((timing->width * timing->bpp / 8), rgb_base + 0x0040);
- writel(0x2443F, rgb_base + 0x0050); //format
- writel(0x20001, rgb_base + 0x0054); //pattern
- writel(0x0, rgb_base + 0x0058);
- writel(0x20000000, rgb_base + 0x005c); //phaseX
- writel(0x20000000, rgb_base + 0x0060); // phaseY
-
- // mdp4 mixer setup MDP4_MIXER1
- data = readl(MDP_BASE + 0x10100);
- stage = 9;
- snum = 12;
- mask = 0x0f;
- mask <<= snum;
- stage <<= snum;
- data &= ~mask;
- data |= stage;
- writel(data, MDP_BASE + 0x10100); // Overlay CFG conf
- data = readl(MDP_BASE + 0x10100);
-
- // Overlay cfg
- overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;
-
- writel(0x0, MDP_BASE + 0x0038); //EXternal interface select
-
- data = ((timing->height << 16) | timing->width);
- writel(data, overlay_base + 0x0008);
- writel(timing->base, overlay_base + 0x000c);
- writel((timing->width * timing->bpp / 8), overlay_base + 0x0010);
- writel(0x10, overlay_base + 0x104);
- writel(0x10, overlay_base + 0x124);
- writel(0x10, overlay_base + 0x144);
- writel(0x01, overlay_base + 0x0004); /* directout */
-
- hsync_period =
- timing->hsync_width + timing->hsync_porch_bp + timing->width +
- timing->hsync_porch_fp;
- hsync_ctrl = (hsync_period << 16) | timing->hsync_width;
- hsync_start_x = timing->hsync_width + timing->hsync_porch_bp;
- hsync_end_x = hsync_period - timing->hsync_porch_fp - 1;
- display_hctl = (hsync_end_x << 16) | hsync_start_x;
-
- vsync_period =
- (timing->vsync_width + timing->vsync_porch_bp + timing->height +
- timing->vsync_porch_fp) * hsync_period;
- display_v_start =
- (timing->vsync_width + timing->vsync_porch_bp) * hsync_period;
- display_v_end =
- vsync_period - (timing->vsync_porch_bp * hsync_period) - 1;
-
- dtv_underflow_clr |= 0x80000000;
- hsync_polarity = 0;
- vsync_polarity = 0;
- data_en_polarity = 0;
- ctrl_polarity =
- (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
-
- writel(hsync_ctrl, MDP_BASE + DTV_BASE + 0x4);
- writel(vsync_period, MDP_BASE + DTV_BASE + 0x8);
- writel(timing->vsync_width * hsync_period,
- MDP_BASE + DTV_BASE + 0xc);
- writel(display_hctl, MDP_BASE + DTV_BASE + 0x18);
- writel(display_v_start, MDP_BASE + DTV_BASE + 0x1c);
- writel(0x25a197, MDP_BASE + DTV_BASE + 0x20);
- writel(dtv_border_clr, MDP_BASE + DTV_BASE + 0x40);
- writel(0x8fffffff, MDP_BASE + DTV_BASE + 0x44);
- writel(dtv_hsync_skew, MDP_BASE + DTV_BASE + 0x48);
- writel(ctrl_polarity, MDP_BASE + DTV_BASE + 0x50);
- writel(0x0, MDP_BASE + DTV_BASE + 0x2c);
- writel(active_v_start, MDP_BASE + DTV_BASE + 0x30);
- writel(active_v_end, MDP_BASE + DTV_BASE + 0x38);
-
- /* Enable DTV block */
- writel(0x01, MDP_BASE + DTV_BASE);
-
- /* Flush mixer/pipes configurations */
- val = BIT(1);
- val |= BIT(5);
- writel(val, MDP_BASE + 0x18000);
-
- return 0;
-}
-
-void hdmi_display_shutdown()
-{
- writel(0x0, MDP_BASE + DTV_BASE);
- writel(0x8, MDP_BASE + 0x0038);
- writel(0x0, MDP_BASE + 0x10100);
-}
diff --git a/platform/msm_shared/hdmi_pll_28nm.c b/platform/msm_shared/hdmi_pll_28nm.c
new file mode 100644
index 0000000..02b69bb
--- /dev/null
+++ b/platform/msm_shared/hdmi_pll_28nm.c
@@ -0,0 +1,260 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <reg.h>
+#include <smem.h>
+#include <bits.h>
+#include <msm_panel.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+
+#define HDMI_PHY_BASE 0xFD922500
+#define HDMI_PLL_BASE 0xFD922700
+
+/* hdmi phy registers */
+#define HDMI_PHY_ANA_CFG0 (0x0000)
+#define HDMI_PHY_ANA_CFG1 (0x0004)
+#define HDMI_PHY_ANA_CFG2 (0x0008)
+#define HDMI_PHY_ANA_CFG3 (0x000C)
+#define HDMI_PHY_PD_CTRL0 (0x0010)
+#define HDMI_PHY_PD_CTRL1 (0x0014)
+#define HDMI_PHY_GLB_CFG (0x0018)
+#define HDMI_PHY_DCC_CFG0 (0x001C)
+#define HDMI_PHY_DCC_CFG1 (0x0020)
+#define HDMI_PHY_TXCAL_CFG0 (0x0024)
+#define HDMI_PHY_TXCAL_CFG1 (0x0028)
+#define HDMI_PHY_TXCAL_CFG2 (0x002C)
+#define HDMI_PHY_TXCAL_CFG3 (0x0030)
+#define HDMI_PHY_BIST_CFG0 (0x0034)
+#define HDMI_PHY_BIST_CFG1 (0x0038)
+#define HDMI_PHY_BIST_PATN0 (0x003C)
+#define HDMI_PHY_BIST_PATN1 (0x0040)
+#define HDMI_PHY_BIST_PATN2 (0x0044)
+#define HDMI_PHY_BIST_PATN3 (0x0048)
+#define HDMI_PHY_STATUS (0x005C)
+
+/* hdmi phy unified pll registers */
+#define HDMI_UNI_PLL_REFCLK_CFG (0x0000)
+#define HDMI_UNI_PLL_POSTDIV1_CFG (0x0004)
+#define HDMI_UNI_PLL_CHFPUMP_CFG (0x0008)
+#define HDMI_UNI_PLL_VCOLPF_CFG (0x000C)
+#define HDMI_UNI_PLL_VREG_CFG (0x0010)
+#define HDMI_UNI_PLL_PWRGEN_CFG (0x0014)
+#define HDMI_UNI_PLL_GLB_CFG (0x0020)
+#define HDMI_UNI_PLL_POSTDIV2_CFG (0x0024)
+#define HDMI_UNI_PLL_POSTDIV3_CFG (0x0028)
+#define HDMI_UNI_PLL_LPFR_CFG (0x002C)
+#define HDMI_UNI_PLL_LPFC1_CFG (0x0030)
+#define HDMI_UNI_PLL_LPFC2_CFG (0x0034)
+#define HDMI_UNI_PLL_SDM_CFG0 (0x0038)
+#define HDMI_UNI_PLL_SDM_CFG1 (0x003C)
+#define HDMI_UNI_PLL_SDM_CFG2 (0x0040)
+#define HDMI_UNI_PLL_SDM_CFG3 (0x0044)
+#define HDMI_UNI_PLL_SDM_CFG4 (0x0048)
+#define HDMI_UNI_PLL_SSC_CFG0 (0x004C)
+#define HDMI_UNI_PLL_SSC_CFG1 (0x0050)
+#define HDMI_UNI_PLL_SSC_CFG2 (0x0054)
+#define HDMI_UNI_PLL_SSC_CFG3 (0x0058)
+#define HDMI_UNI_PLL_LKDET_CFG0 (0x005C)
+#define HDMI_UNI_PLL_LKDET_CFG1 (0x0060)
+#define HDMI_UNI_PLL_LKDET_CFG2 (0x0064)
+#define HDMI_UNI_PLL_CAL_CFG0 (0x006C)
+#define HDMI_UNI_PLL_CAL_CFG1 (0x0070)
+#define HDMI_UNI_PLL_CAL_CFG2 (0x0074)
+#define HDMI_UNI_PLL_CAL_CFG3 (0x0078)
+#define HDMI_UNI_PLL_CAL_CFG4 (0x007C)
+#define HDMI_UNI_PLL_CAL_CFG5 (0x0080)
+#define HDMI_UNI_PLL_CAL_CFG6 (0x0084)
+#define HDMI_UNI_PLL_CAL_CFG7 (0x0088)
+#define HDMI_UNI_PLL_CAL_CFG8 (0x008C)
+#define HDMI_UNI_PLL_CAL_CFG9 (0x0090)
+#define HDMI_UNI_PLL_CAL_CFG10 (0x0094)
+#define HDMI_UNI_PLL_CAL_CFG11 (0x0098)
+#define HDMI_UNI_PLL_STATUS (0x00C0)
+
+#define SW_RESET BIT(2)
+#define SW_RESET_PLL BIT(0)
+
+void hdmi_phy_reset(void)
+{
+ uint32_t phy_reset_polarity = 0x0;
+ uint32_t pll_reset_polarity = 0x0;
+ uint32_t val;
+
+ val = readl(HDMI_PHY_CTRL);
+
+ phy_reset_polarity = val >> 3 & 0x1;
+ pll_reset_polarity = val >> 1 & 0x1;
+
+ if (phy_reset_polarity == 0)
+ writel(val | SW_RESET, HDMI_PHY_CTRL);
+ else
+ writel(val & (~SW_RESET), HDMI_PHY_CTRL);
+
+ if (pll_reset_polarity == 0)
+ writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);
+ else
+ writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);
+
+ if (phy_reset_polarity == 0)
+ writel(val & (~SW_RESET), HDMI_PHY_CTRL);
+ else
+ writel(val | SW_RESET, HDMI_PHY_CTRL);
+
+ if (pll_reset_polarity == 0)
+ writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);
+ else
+ writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);
+}
+
+void hdmi_phy_init(void)
+{
+ writel(0x1B, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG0);
+ writel(0xF2, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG1);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_CFG0);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN0);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN1);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN2);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN3);
+
+ writel(0x20, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL1);
+}
+
+void hdmi_phy_powerdown(void)
+{
+ writel(0x7F, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL0);
+}
+
+static uint32_t hdmi_poll_status(uint32_t addr)
+{
+ uint32_t count;
+
+ for (count = 20; count > 0; count--) {
+ if (readl(addr) & 0x1) {
+ return NO_ERROR;
+ }
+ udelay(100);
+ }
+ return ERR_TIMED_OUT;
+}
+
+void hdmi_vco_disable(void)
+{
+ writel(0x0, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ udelay(5);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_GLB_CFG);
+}
+
+int hdmi_vco_enable(void)
+{
+ /* Global Enable */
+ writel(0x81, HDMI_PHY_BASE + HDMI_PHY_GLB_CFG);
+ /* Power up power gen */
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL0);
+ udelay(350);
+
+ /* PLL Power-Up */
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ udelay(5);
+
+ /* Power up PLL LDO */
+ writel(0x03, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ udelay(350);
+
+ /* PLL Power-Up */
+ writel(0x0F, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ udelay(350);
+
+ /* poll for PLL ready status */
+ if (hdmi_poll_status(HDMI_PLL_BASE + HDMI_UNI_PLL_STATUS)) {
+ dprintf(CRITICAL, "%s: hdmi phy pll failed to Lock\n",
+ __func__);
+ hdmi_vco_disable();
+ return ERROR;
+ }
+
+ udelay(350);
+ /* poll for PHY ready status */
+ if (hdmi_poll_status(HDMI_PHY_BASE + HDMI_PHY_STATUS)) {
+ dprintf(CRITICAL, "%s: hdmi phy failed to Lock\n",
+ __func__);
+ hdmi_vco_disable();
+ return ERROR;
+ }
+
+ return NO_ERROR;
+}
+
+uint32_t hdmi_pll_config(void)
+{
+ writel(0x81, HDMI_PHY_BASE + HDMI_PHY_GLB_CFG);
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_REFCLK_CFG);
+ writel(0x19, HDMI_PLL_BASE + HDMI_UNI_PLL_VCOLPF_CFG);
+ writel(0x0E, HDMI_PLL_BASE + HDMI_UNI_PLL_LPFR_CFG);
+ writel(0x20, HDMI_PLL_BASE + HDMI_UNI_PLL_LPFC1_CFG);
+ writel(0x0D, HDMI_PLL_BASE + HDMI_UNI_PLL_LPFC2_CFG);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG0);
+ writel(0x52, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG1);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG2);
+ writel(0x56, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG3);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG4);
+ writel(0x10, HDMI_PLL_BASE + HDMI_UNI_PLL_LKDET_CFG0);
+ writel(0x1A, HDMI_PLL_BASE + HDMI_UNI_PLL_LKDET_CFG1);
+ writel(0x05, HDMI_PLL_BASE + HDMI_UNI_PLL_LKDET_CFG2);
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_POSTDIV1_CFG);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_POSTDIV2_CFG);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_POSTDIV3_CFG);
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG2);
+ writel(0x60, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG8);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG9);
+ writel(0xE6, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG10);
+ writel(0x02, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG11);
+ writel(0x1F, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL0);
+ udelay(50);
+
+ writel(0x0F, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL1);
+ writel(0x10, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG2);
+ writel(0xDB, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG0);
+ writel(0x43, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG1);
+ writel(0x02, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG2);
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG3);
+ writel(0x04, HDMI_PLL_BASE + HDMI_UNI_PLL_VREG_CFG);
+ writel(0xD0, HDMI_PHY_BASE + HDMI_PHY_DCC_CFG0);
+ writel(0x1A, HDMI_PHY_BASE + HDMI_PHY_DCC_CFG1);
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG0);
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG1);
+ writel(0x02, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG2);
+ writel(0x05, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG3);
+ udelay(200);
+}
+
diff --git a/platform/msm_shared/image_verify.c b/platform/msm_shared/image_verify.c
index 0d280f2..284f8e5 100644
--- a/platform/msm_shared/image_verify.c
+++ b/platform/msm_shared/image_verify.c
@@ -55,6 +55,11 @@
goto cleanup;
}
pub_key = X509_get_pubkey(x509_certificate);
+ if (pub_key == NULL) {
+ dprintf(CRITICAL, "ERROR: Boot Invalid, PUB_KEY is NULL!\n");
+ goto cleanup;
+ }
+
rsa_key = EVP_PKEY_get1_RSA(pub_key);
if (rsa_key == NULL) {
dprintf(CRITICAL, "ERROR: Boot Invalid, RSA_KEY is NULL!\n");
diff --git a/platform/msm_shared/include/board.h b/platform/msm_shared/include/board.h
index 9efde4d..d7e82d5 100644
--- a/platform/msm_shared/include/board.h
+++ b/platform/msm_shared/include/board.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -39,6 +39,7 @@
struct board_pmic_data {
uint32_t pmic_type;
uint32_t pmic_version;
+ uint32_t pmic_target;
};
struct board_data {
@@ -65,6 +66,7 @@
uint32_t board_hardware_subtype(void);
uint32_t board_get_ddr_subtype(void);
uint32_t board_hlos_subtype(void);
+uint32_t board_pmic_target(uint8_t num_ent);
/* DDR Subtype Macros
* Determine the DDR Size on the device and define
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
index ef41046..a6534c0 100644
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -27,6 +27,7 @@
*/
#include <debug.h>
+#include <list.h>
#ifndef __DEVICE_TREE__
#define __DEVICE_TREE__
@@ -36,6 +37,8 @@
#define DEV_TREE_MAGIC_LEN 4
#define DEV_TREE_VERSION_V1 1
#define DEV_TREE_VERSION_V2 2
+#define DEV_TREE_VERSION_V3 3
+
#define DEV_TREE_HEADER_SIZE 12
#define DTB_MAGIC 0xedfe0dd0
@@ -54,6 +57,18 @@
#define DT_ENTRY_V1_SIZE 0xC
#define PLAT_ID_SIZE 0x8
#define BOARD_ID_SIZE 0x8
+#define PMIC_ID_SIZE 0x8
+
+
+struct dt_entry_v2
+{
+ uint32_t platform_id;
+ uint32_t variant_id;
+ uint32_t board_hw_subtype;
+ uint32_t soc_rev;
+ uint32_t offset;
+ uint32_t size;
+};
struct dt_entry
{
@@ -61,6 +76,7 @@
uint32_t variant_id;
uint32_t board_hw_subtype;
uint32_t soc_rev;
+ uint32_t pmic_rev[4];
uint32_t offset;
uint32_t size;
};
@@ -84,6 +100,11 @@
uint32_t platform_subtype;
};
+struct pmic_id
+{
+ uint32_t pmic_version[4];
+};
+
struct dt_mem_node_info
{
uint32_t offset;
@@ -92,17 +113,28 @@
uint32_t size_cell_size;
};
+enum dt_entry_info
+{
+ DTB_FOUNDRY = 0,
+ DTB_SOC,
+ DTB_MAJOR_MINOR,
+ DTB_PMIC0,
+ DTB_PMIC1,
+ DTB_PMIC2,
+ DTB_PMIC3,
+ DTB_PMIC_MODEL,
+};
+
enum dt_err_codes
{
DT_OP_SUCCESS,
DT_OP_FAILURE = -1,
};
-struct board_dt_entry
-{
- uint32_t target_variant_id;
- uint32_t platform_variant_id;
-};
+typedef struct dt_entry_node {
+ struct list_node node;
+ struct dt_entry * dt_entry_m;
+}dt_node;
int dev_tree_validate(struct dt_table *table, unsigned int page_size, uint32_t *dt_hdr_size);
int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info);
diff --git a/platform/msm_shared/include/hdmi.h b/platform/msm_shared/include/hdmi.h
deleted file mode 100644
index 0b4fd5b..0000000
--- a/platform/msm_shared/include/hdmi.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of The Linux Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef __PLATFORM_MSM_SHARED_HDMI_H
-#define __PLATFORM_MSM_SHARED_HDMI_H
-
-#include <reg.h>
-#include <debug.h>
-#include <bits.h>
-#include <dev/fbcon.h>
-#include <target/display.h>
-
-#define MDP_GET_PACK_PATTERN(a,x,y,z,bit) (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
-#define DMA_PACK_ALIGN_LSB 0
-#define DMA_PACK_PATTERN_RGB \
- (MDP_GET_PACK_PATTERN(0,CLR_R,CLR_G,CLR_B,2)<<8)
-#define CLR_G 0x0
-#define CLR_B 0x1
-#define CLR_R 0x2
-#define DMA_DSTC0G_8BITS (BIT(1)|BIT(0))
-#define DMA_DSTC1B_8BITS (BIT(3)|BIT(2))
-#define DMA_DSTC2R_8BITS (BIT(5)|BIT(4))
-#define BM(m, l) (((((uint32_t)-1) << (31-m)) >> (31-m+l)) << l)
-#define BVAL(m, l, val) (((val) << l) & BM(m, l))
-#define CC(m, n) (BVAL((m+1), m, 0x2) * !!(n))
-#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
- (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
- | BVAL(s_msb, s_lsb, s))
-
-extern int pm8901_mpp_enable();
-extern int pm8901_vs_enable();
-extern int pm8058_ldo_set_voltage();
-extern int pm8058_vreg_enable();
-void gpio_tlmm_config(uint32_t gpio, uint8_t func,
- uint8_t dir, uint8_t pull,
- uint8_t drvstr, uint32_t enable);
-
-int hdmi_dtv_on(void);
-void hdmi_msm_set_mode(int on);
-void hdmi_msm_init_phy(void);
-void hdmi_display_shutdown(void);
-void hdmi_msm_reset_core(void);
-void hdmi_set_fb_addr(void *addr);
-
-struct hdmi_disp_mode_timing_type {
- uint32_t height;
- uint32_t hsync_porch_fp;
- uint32_t hsync_width;
- uint32_t hsync_porch_bp;
- uint32_t width;
- uint32_t vsync_porch_fp;
- uint32_t vsync_width;
- uint32_t vsync_porch_bp;
- uint32_t refresh_rate;
- uint32_t bpp;
- void *base;
-};
-#endif /* __PLATFORM_MSM_SHARED_HDMI_H */
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 8207651..8ade9c8 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -78,6 +78,7 @@
#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */
#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */
#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */
+#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */
#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
@@ -96,6 +97,7 @@
#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x12500)
#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x12700)
+#define MDP_INTF_3_TIMING_ENGINE_EN REG_MDP(0x12B00)
#define MDP_CTL_0_BASE REG_MDP(0x600)
#define MDP_CTL_1_BASE REG_MDP(0x700)
@@ -116,6 +118,7 @@
#define MDP_INTF_0_BASE REG_MDP(0x12500)
#define MDP_INTF_1_BASE REG_MDP(0x12700)
#define MDP_INTF_2_BASE REG_MDP(0x12900)
+#define MDP_INTF_3_BASE REG_MDP(0x12B00)
#define MDP_HSYNC_CTL 0x08
#define MDP_VSYNC_PERIOD_F0 0x0C
@@ -147,6 +150,10 @@
#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x0180)
#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x0230)
+/* source pipe opmode bits for flip */
+#define MDSS_MDP_OP_MODE_FLIP_UD BIT(14)
+#define MDSS_MDP_OP_MODE_FLIP_LR BIT(13)
+
#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x02E0)
#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x02E4)
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 000e2b1..2a8e192 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -165,6 +165,7 @@
char bistCtrl[MAX_BIST_CONFIG];
char laneCfg[MAX_LANE_CONFIG];
enum dsi_reg_mode regulator_mode;
+ int is_pll_20nm;
};
typedef struct mdss_dsi_pll_config {
@@ -181,6 +182,15 @@
uint8_t pclk_m;
uint8_t pclk_n;
uint8_t pclk_d;
+
+ /* pll 20nm */
+ uint32_t dec_start;
+ uint32_t frac_start;
+ uint32_t lock_comp;
+ uint8_t hr_oclk2;
+ uint8_t hr_oclk3;
+ uint8_t lp_div_mux;
+ uint8_t ndiv;
};
struct mipi_dsi_cmd {
@@ -219,6 +229,8 @@
int mdss_dsi_config(struct msm_fb_panel_data *panel);
int mdss_dsi_phy_init(struct mipi_dsi_panel_config *,
uint32_t ctl_base, uint32_t phy_base);
+void mdss_dsi_phy_contention_detection(struct mipi_dsi_panel_config *,
+ uint32_t phy_base);
int mdss_dsi_video_mode_config(uint16_t disp_width,
uint16_t disp_height,
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index a480d2c..6befefd 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -195,10 +195,11 @@
uint32_t type;
uint32_t wait_cycle;
uint32_t clk_rate;
- uint32_t rotation;
+ uint32_t orientation;
/* Select pipe type for handoff */
uint32_t pipe_type;
char lowpowerstop;
+ char lcd_reg_en;
struct lcd_panel_info lcd;
struct lcdc_panel_info lcdc;
@@ -224,7 +225,7 @@
int rotate;
/* function entry chain */
- int (*power_func) (int enable);
+ int (*power_func) (int enable, struct msm_panel_info *);
int (*clk_func) (int enable);
int (*bl_func) (int enable);
int (*pll_clk_func) (int enable, struct msm_panel_info *);
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index 1268db9..de046a4 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -29,6 +29,34 @@
#ifndef __SCM_H__
#define __SCM_H__
+/* ARM SCM format support related flags */
+#define SIP_SVC_CALLS 0x02000000
+#define MAKE_SIP_SCM_CMD(svc_id, cmd_id) ((((svc_id << 8) | (cmd_id)) & 0xFFFF) | SIP_SVC_CALLS)
+#define MAKE_SCM_VAR_ARGS(num_args, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, ...) (\
+ (((t0) & 0xff) << 4) | \
+ (((t1) & 0xff) << 6) | \
+ (((t2) & 0xff) << 8) | \
+ (((t3) & 0xff) << 10) | \
+ (((t4) & 0xff) << 12) | \
+ (((t5) & 0xff) << 14) | \
+ (((t6) & 0xff) << 16) | \
+ (((t7) & 0xff) << 18) | \
+ (((t8) & 0xff) << 20) | \
+ (((t9) & 0xff) << 22) | \
+ (num_args & 0xffff))
+#define MAKE_SCM_ARGS(...) MAKE_SCM_VAR_ARGS(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+#define SCM_ATOMIC_BIT BIT(31)
+#define SCM_MAX_ARG_LEN 5
+#define SCM_INDIR_MAX_LEN 10
+
+enum
+{
+ SMC_PARAM_TYPE_VALUE = 0,
+ SMC_PARAM_TYPE_BUFFER_READ,
+ SMC_PARAM_TYPE_BUFFER_READWRITE,
+ SMC_PARAM_TYPE_BUFFER_VALIDATION,
+} scm_arg_type;
+
/* 8 Byte SSD magic number (LE) */
#define DECRYPT_MAGIC_0 0x73737A74
#define DECRYPT_MAGIC_1 0x676D6964
@@ -126,12 +154,62 @@
uint32_t out_buf_size;
}__packed;
+/* SCM support as per ARM spec */
+/*
+ * Structure to define the argument for scm call
+ * x0: is the command ID
+ * x1: Number of argument & type of arguments
+ * : Type can be any of
+ * : SMC_PARAM_TYPE_VALUE 0
+ * : SMC_PARAM_TYPE_BUFFER_READ 1
+ * : SMC_PARAM_TYPE_BUFFER_READWRITE 2
+ * : SMC_PARAM_TYPE_BUFFER_VALIDATION 3
+ * @Note: Number of argument count starts from X2.
+ * x2-x4: Arguments
+ * X5[10]: if the number of argument is more, an indirect
+ * : list can be passed here.
+ */
+typedef struct {
+ uint32_t x0;/* command ID details as per ARMv8 spec :
+ 0:7 command, 8:15 service id
+ 0x02000000: SIP calls
+ 30: SMC32 or SMC64
+ 31: Standard or fast calls*/
+ uint32_t x1; /* # of args and attributes for buffers
+ * 0-3: arg #
+ * 4-5: type of arg1
+ * 6-7: type of arg2
+ * :
+ * :
+ * 20-21: type of arg8
+ * 22-23: type of arg9
+ */
+ uint32_t x2; /* Param1 */
+ uint32_t x3; /* Param2 */
+ uint32_t x4; /* Param3 */
+ uint32_t x5[10]; /* Indirect parameter list */
+ uint32_t atomic; /* To indicate if its standard or fast call */
+} scmcall_arg;
+
+/* Return value for the SCM call:
+ * SCM call returns values in register if its less than
+ * 12 bytes, anything greater need to be input buffer + input len
+ * arguments
+ */
+typedef struct
+{
+ uint32_t x1;
+ uint32_t x2;
+ uint32_t x3;
+} scmcall_ret;
+
/* Service IDs */
#define SCM_SVC_BOOT 0x01
#define TZBSP_SVC_INFO 0x06
#define SCM_SVC_SSD 0x07
#define SVC_MEMORY_PROTECTION 0x0C
#define TZ_SVC_CRYPTO 0x0A
+#define SCM_SVC_INFO 0x06
/*Service specific command IDs */
#define ERR_FATAL_ENABLE 0x0
@@ -151,6 +229,7 @@
#define TZ_INFO_GET_FEATURE_ID 0x03
#define PRNG_CMD_ID 0x01
+#define IS_CALL_AVAIL_CMD 0x01
/* Download Mode specific arguments to be passed to TZ */
#define SCM_EDLOAD_MODE 0x02
@@ -235,6 +314,11 @@
/* API to configure XPU violations as fatal */
int scm_xpu_err_fatal_init();
+/* APIs to support ARM scm standard
+ * Takes arguments : x0-x5 and returns result
+ * in x0-x3*/
+uint32_t scm_call2(scmcall_arg *arg, scmcall_ret *ret);
+
/**
* struct scm_command - one SCM command buffer
* @len: total available memory for command and response
@@ -278,4 +362,8 @@
uint32_t buf_offset;
uint32_t is_complete;
};
+/* Perform any scm init needed before making scm calls
+ * Used for checking if armv8 SCM support present
+ */
+void scm_init();
#endif
diff --git a/platform/msm_shared/jtag.c b/platform/msm_shared/jtag.c
index 0430eaf..cf278f8 100644
--- a/platform/msm_shared/jtag.c
+++ b/platform/msm_shared/jtag.c
@@ -2,6 +2,8 @@
* Copyright (C) 2008 The Android Open Source Project
* All rights reserved.
*
+ * Copyright (C) 2008-2014, The Linux Foundation. All rights reserved.
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -11,6 +13,9 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
@@ -32,10 +37,11 @@
#define STATUS_OKAY 1
#define STATUS_FAIL 2
#define STATUS_PRINT 3
+#define JTAG_CMD_NUM 256
volatile unsigned _jtag_cmd = 0;
volatile unsigned _jtag_msg = 0;
-unsigned char _jtag_cmd_buffer[128];
+unsigned char _jtag_cmd_buffer[JTAG_CMD_NUM];
unsigned char _jtag_msg_buffer[128];
volatile unsigned _jtag_arg0 = 0;
@@ -82,7 +88,7 @@
if (jtag_cmd_pending()) {
do_cmd((const char *)_jtag_cmd_buffer, _jtag_arg0,
_jtag_arg1, _jtag_arg2);
- for (n = 0; n < 256; n++)
+ for (n = 0; n < JTAG_CMD_NUM; n++)
_jtag_cmd_buffer[n] = 0;
_jtag_arg0 = 0;
_jtag_arg1 = 0;
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index 2cde8ea..b53b3d8 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -211,3 +211,18 @@
{
return NO_ERROR;
}
+
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+ return NO_ERROR;
+}
+
+int mdss_hdmi_on(void)
+{
+ return NO_ERROR;
+}
+
+int mdss_hdmi_off(void)
+{
+ return NO_ERROR;
+}
diff --git a/platform/msm_shared/mdp4.c b/platform/msm_shared/mdp4.c
index 7b7c0cf..705819e 100644
--- a/platform/msm_shared/mdp4.c
+++ b/platform/msm_shared/mdp4.c
@@ -423,3 +423,18 @@
{
return NO_ERROR;
}
+
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+ return NO_ERROR;
+}
+
+int mdss_hdmi_on(void)
+{
+ return NO_ERROR;
+}
+
+int mdss_hdmi_off(void)
+{
+ return NO_ERROR;
+}
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index ff260d7..801f7b6 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -127,6 +127,7 @@
{
uint32_t src_size, out_size, stride;
uint32_t fb_off = 0;
+ uint32_t flip_bits = 0;
/* write active region size*/
src_size = (fb->height << 16) + fb->width;
@@ -152,7 +153,15 @@
/* Tight Packing 3bpp 0-Alpha 8-bit R B G */
writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT);
writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN);
- writel(0x00, pipe_base + PIPE_SSPP_SRC_OP_MODE);
+
+ /* bit(0) is set if hflip is required.
+ * bit(1) is set if vflip is required.
+ */
+ if (pinfo->orientation & 0x1)
+ flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR;
+ if (pinfo->orientation & 0x2)
+ flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD;
+ writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE);
}
static void mdss_vbif_setup()
@@ -593,6 +602,41 @@
return 0;
}
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+ int ret = NO_ERROR;
+ struct lcdc_panel_info *lcdc = NULL;
+ uint32_t left_pipe, right_pipe;
+
+ mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE);
+ mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
+
+ mdp_clk_gating_ctrl();
+ mdss_vbif_setup();
+
+ mdss_smp_setup(pinfo, left_pipe, right_pipe);
+
+ mdss_qos_remapper_setup();
+
+ mdss_source_pipe_config(fb, pinfo, left_pipe);
+ if (pinfo->lcdc.dual_pipe)
+ mdss_source_pipe_config(fb, pinfo, right_pipe);
+
+ mdss_layer_mixer_setup(fb, pinfo);
+
+ if (pinfo->lcdc.dual_pipe)
+ writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP);
+ else
+ writel(0x40, MDP_CTL_0_BASE + CTL_TOP);
+
+ writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL);
+ writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
+ writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
+ writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
+
+ return 0;
+}
+
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
@@ -721,6 +765,18 @@
return NO_ERROR;
}
+int mdss_hdmi_on(struct msm_panel_info *pinfo)
+{
+ uint32_t ctl0_reg_val, ctl1_reg_val;
+
+ mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
+ writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
+
+ writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
+
+ return NO_ERROR;
+}
+
int mdp_edp_off(void)
{
if (!target_cont_splash_screen()) {
diff --git a/platform/msm_shared/mdss_hdmi.c b/platform/msm_shared/mdss_hdmi.c
new file mode 100644
index 0000000..c6a5bab
--- /dev/null
+++ b/platform/msm_shared/mdss_hdmi.c
@@ -0,0 +1,315 @@
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <err.h>
+#include <debug.h>
+#include <reg.h>
+#include <msm_panel.h>
+#include <platform/timer.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+static struct msm_fb_panel_data panel;
+
+/* AVI INFOFRAME DATA */
+#define NUM_MODES_AVI 20
+#define AVI_MAX_DATA_BYTES 13
+
+enum {
+ DATA_BYTE_1,
+ DATA_BYTE_2,
+ DATA_BYTE_3,
+ DATA_BYTE_4,
+ DATA_BYTE_5,
+ DATA_BYTE_6,
+ DATA_BYTE_7,
+ DATA_BYTE_8,
+ DATA_BYTE_9,
+ DATA_BYTE_10,
+ DATA_BYTE_11,
+ DATA_BYTE_12,
+ DATA_BYTE_13,
+};
+
+#define IFRAME_PACKET_OFFSET 0x80
+/*
+ * InfoFrame Type Code:
+ * 0x0 - Reserved
+ * 0x1 - Vendor Specific
+ * 0x2 - Auxiliary Video Information
+ * 0x3 - Source Product Description
+ * 0x4 - AUDIO
+ * 0x5 - MPEG Source
+ * 0x6 - NTSC VBI
+ * 0x7 - 0xFF - Reserved
+ */
+#define AVI_IFRAME_TYPE 0x2
+#define AVI_IFRAME_VERSION 0x2
+#define LEFT_SHIFT_BYTE(x) ((x) << 8)
+#define LEFT_SHIFT_WORD(x) ((x) << 16)
+#define LEFT_SHIFT_24BITS(x) ((x) << 24)
+
+struct mdss_hdmi_timing_info {
+ uint32_t video_format;
+ uint32_t active_h;
+ uint32_t front_porch_h;
+ uint32_t pulse_width_h;
+ uint32_t back_porch_h;
+ uint32_t active_low_h;
+ uint32_t active_v;
+ uint32_t front_porch_v;
+ uint32_t pulse_width_v;
+ uint32_t back_porch_v;
+ uint32_t active_low_v;
+ /* Must divide by 1000 to get the actual frequency in MHZ */
+ uint32_t pixel_freq;
+ /* Must divide by 1000 to get the actual frequency in HZ */
+ uint32_t refresh_rate;
+ uint32_t interlaced;
+ uint32_t supported;
+};
+
+#define HDMI_VFRMT_1280x720p60_16_9 4
+#define HDMI_RESOLUTION_DATA HDMI_VFRMT_1280x720p60_16_9##_TIMING
+
+#define HDMI_VFRMT_1280x720p60_16_9_TIMING \
+ {HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, \
+ 720, 5, 5, 20, false, 74250, 60000, false, true}
+
+uint32_t mdss_hdmi_avi_info_db[] = {
+ 0x10, 0x28, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0xD1, 0x02, 0x00, 0x00, 0x01, 0x05};
+
+static int mdss_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ return target_hdmi_panel_clock(enable, pinfo);
+}
+
+static int mdss_hdmi_enable_power(uint8_t enable)
+{
+ int ret = NO_ERROR;
+
+ ret = target_ldo_ctrl(enable);
+ if (ret) {
+ dprintf(CRITICAL, "LDO control enable failed\n");
+ return ret;
+ }
+
+ ret = target_hdmi_regulator_ctrl(enable);
+ if (ret) {
+ dprintf(CRITICAL, "hdmi regulator control enable failed\n");
+ return ret;
+ }
+
+ dprintf(SPEW, "HDMI Panel power %s done\n", enable ? "on" : "off");
+
+ return ret;
+}
+
+static void mdss_hdmi_set_mode(bool on)
+{
+ uint32_t val = 0;
+
+ if (on) {
+ val = 0x3;
+ writel(val, HDMI_CTRL);
+ } else {
+ writel(val, HDMI_CTRL);
+ }
+}
+
+static void mdss_hdmi_panel_init(struct msm_panel_info *pinfo)
+{
+ struct mdss_hdmi_timing_info tinfo = HDMI_RESOLUTION_DATA;
+
+ if (!pinfo)
+ return;
+
+ pinfo->xres = tinfo.active_h;
+ pinfo->yres = tinfo.active_v;
+ pinfo->bpp = 24;
+ pinfo->type = HDMI_PANEL;
+
+ pinfo->lcdc.h_back_porch = tinfo.back_porch_h;
+ pinfo->lcdc.h_front_porch = tinfo.front_porch_h;
+ pinfo->lcdc.h_pulse_width = tinfo.pulse_width_h;
+ pinfo->lcdc.v_back_porch = tinfo.back_porch_v;
+ pinfo->lcdc.v_front_porch = tinfo.front_porch_v;
+ pinfo->lcdc.v_pulse_width = tinfo.pulse_width_v;
+
+ pinfo->lcdc.hsync_skew = 0;
+ pinfo->lcdc.xres_pad = 0;
+ pinfo->lcdc.yres_pad = 0;
+ pinfo->lcdc.dual_pipe = 0;
+}
+
+void mdss_hdmi_display_init(uint32_t rev, void *base)
+{
+ mdss_hdmi_panel_init(&(panel.panel_info));
+
+ panel.clk_func = mdss_hdmi_panel_clock;
+ panel.power_func = mdss_hdmi_enable_power;
+
+ panel.fb.width = panel.panel_info.xres;
+ panel.fb.height = panel.panel_info.yres;
+ panel.fb.stride = panel.panel_info.xres;
+ panel.fb.bpp = panel.panel_info.bpp;
+ panel.fb.format = FB_FORMAT_RGB888;
+
+ panel.fb.base = base;
+ panel.mdp_rev = rev;
+
+ msm_display_init(&panel);
+}
+
+static int mdss_hdmi_video_setup(void)
+{
+ uint32_t total_v = 0;
+ uint32_t total_h = 0;
+ uint32_t start_h = 0;
+ uint32_t end_h = 0;
+ uint32_t start_v = 0;
+ uint32_t end_v = 0;
+
+ struct mdss_hdmi_timing_info tinfo = HDMI_RESOLUTION_DATA;
+
+ total_h = tinfo.active_h + tinfo.front_porch_h +
+ tinfo.back_porch_h + tinfo.pulse_width_h - 1;
+ total_v = tinfo.active_v + tinfo.front_porch_v +
+ tinfo.back_porch_v + tinfo.pulse_width_v - 1;
+ if (((total_v << 16) & 0xE0000000) || (total_h & 0xFFFFE000)) {
+ dprintf(CRITICAL,
+ "%s: total v=%d or h=%d is larger than supported\n",
+ __func__, total_v, total_h);
+ return ERROR;
+ }
+ writel((total_v << 16) | (total_h << 0), HDMI_TOTAL);
+
+ start_h = tinfo.back_porch_h + tinfo.pulse_width_h;
+ end_h = (total_h + 1) - tinfo.front_porch_h;
+ if (((end_h << 16) & 0xE0000000) || (start_h & 0xFFFFE000)) {
+ dprintf(CRITICAL,
+ "%s: end_h=%d or start_h=%d is larger than supported\n",
+ __func__, end_h, start_h);
+ return ERROR;
+ }
+ writel((end_h << 16) | (start_h << 0), HDMI_ACTIVE_H);
+
+ start_v = tinfo.back_porch_v + tinfo.pulse_width_v - 1;
+ end_v = total_v - tinfo.front_porch_v;
+ if (((end_v << 16) & 0xE0000000) || (start_v & 0xFFFFE000)) {
+ dprintf(CRITICAL,
+ "%s: end_v=%d or start_v=%d is larger than supported\n",
+ __func__, end_v, start_v);
+ return ERROR;
+ }
+ writel((end_v << 16) | (start_v << 0), HDMI_ACTIVE_V);
+
+ if (tinfo.interlaced) {
+ writel((total_v + 1) << 0, HDMI_V_TOTAL_F2);
+ writel(((end_v + 1) << 16) | ((start_v + 1) << 0),
+ HDMI_ACTIVE_V_F2);
+ } else {
+ writel(0, HDMI_V_TOTAL_F2);
+ writel(0, HDMI_ACTIVE_V_F2);
+ }
+
+ writel(((tinfo.interlaced << 31) & 0x80000000) |
+ ((tinfo.active_low_h << 29) & 0x20000000) |
+ ((tinfo.active_low_v << 28) & 0x10000000), HDMI_FRAME_CTRL);
+
+ return 0;
+}
+
+void mdss_hdmi_avi_info_frame(void)
+{
+ uint32_t sum;
+ uint32_t reg_val;
+ uint8_t checksum;
+ uint32_t i;
+
+ sum = IFRAME_PACKET_OFFSET + AVI_IFRAME_TYPE +
+ AVI_IFRAME_VERSION + AVI_MAX_DATA_BYTES;
+
+ for (i = 0; i < AVI_MAX_DATA_BYTES; i++)
+ sum += mdss_hdmi_avi_info_db[i];
+
+ sum &= 0xFF;
+ sum = 256 - sum;
+ checksum = (uint8_t) sum;
+
+ reg_val = checksum |
+ LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_1]) |
+ LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[DATA_BYTE_2]) |
+ LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[DATA_BYTE_3]);
+ writel(reg_val, HDMI_AVI_INFO0);
+
+ reg_val = mdss_hdmi_avi_info_db[DATA_BYTE_4] |
+ LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_5]) |
+ LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[DATA_BYTE_6]) |
+ LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[DATA_BYTE_7]);
+ writel(reg_val, HDMI_AVI_INFO1);
+
+ reg_val = mdss_hdmi_avi_info_db[DATA_BYTE_8] |
+ LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_9]) |
+ LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[DATA_BYTE_10]) |
+ LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[DATA_BYTE_11]);
+ writel(reg_val, HDMI_AVI_INFO2);
+
+ reg_val = mdss_hdmi_avi_info_db[DATA_BYTE_12] |
+ LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_13]) |
+ LEFT_SHIFT_24BITS(AVI_IFRAME_VERSION);
+ writel(reg_val, HDMI_AVI_INFO3);
+
+ /* AVI InfFrame enable (every frame) */
+ writel(readl(HDMI_INFOFRAME_CTRL0) | BIT(1) | BIT(0),
+ HDMI_INFOFRAME_CTRL0);
+}
+
+int mdss_hdmi_init(void)
+{
+ uint32_t hotplug_control;
+
+ mdss_hdmi_set_mode(false);
+
+ hdmi_phy_init();
+
+ // Enable USEC REF timer
+ writel(0x0001001B, HDMI_USEC_REFTIMER);
+
+ // Video setup for HDMI
+ mdss_hdmi_video_setup();
+
+ // AVI info setup
+ mdss_hdmi_avi_info_frame();
+
+ // Write 1 to HDMI_CTRL to enable HDMI
+ mdss_hdmi_set_mode(true);
+
+ return 0;
+}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 1c2bb08..7ac614e 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -684,6 +684,8 @@
goto error;
}
+ mdss_dsi_phy_contention_detection(&mipi_pinfo, DSI0_PHY_BASE);
+
if (panel->pre_init_func) {
ret = panel->pre_init_func();
if (ret) {
@@ -802,13 +804,12 @@
mdelay(10);
writel(0x0001, DSI_SOFT_RESET);
writel(0x0000, DSI_SOFT_RESET);
- writel(0x1115501, DSI_INT_CTRL);
writel(0, DSI_CTRL);
}
- writel(0x1115501, DSI_INT_CTRL);
+ writel(0x1115501, MIPI_DSI0_BASE + INT_CTRL);
if (pinfo->mipi.broadcast)
- writel(0x1115501, DSI_INT_CTRL + 0x600);
+ writel(0x1115501, MIPI_DSI1_BASE + INT_CTRL);
return NO_ERROR;
}
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
new file mode 100644
index 0000000..0f7052a
--- /dev/null
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -0,0 +1,294 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <debug.h>
+#include <reg.h>
+#include <err.h>
+#include <smem.h>
+#include <mipi_dsi.h>
+#include <platform/iomap.h>
+
+#define LPFR_LUT_SIZE 10
+
+#define VCO_REF_CLOCK_RATE 19200000
+
+#define FRAC_DIVIDER 10000
+
+#define MMSS_DSI_PHY_PLL_SYS_CLK_CTRL 0x0000
+#define MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN 0x0004
+#define MMSS_DSI_PHY_PLL_CMN_MODE 0x0008
+#define MMSS_DSI_PHY_PLL_IE_TRIM 0x000C
+#define MMSS_DSI_PHY_PLL_IP_TRIM 0x0010
+#define MMSS_DSI_PHY_PLL_PLL_CNTRL 0x0014
+#define MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL 0x0018
+#define MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL 0x001C
+#define MMSS_DSI_PHY_PLL_PLL_PHSEL_DC 0x0020
+#define MMSS_DSI_PHY_PLL_PLL_IP_SETI 0x0024
+#define MMSS_DSI_PHY_PLL_CORE_CLK_IN_SYNC_SEL 0x0028
+#define MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN 0x002C
+
+#define MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN 0x0030
+#define MMSS_DSI_PHY_PLL_PLL_CP_SETI 0x0034
+#define MMSS_DSI_PHY_PLL_PLL_IP_SETP 0x0038
+#define MMSS_DSI_PHY_PLL_PLL_CP_SETP 0x003C
+#define MMSS_DSI_PHY_PLL_ATB_SEL1 0x0040
+#define MMSS_DSI_PHY_PLL_ATB_SEL2 0x0044
+#define MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND 0x0048
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL 0x004C
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL2 0x0050
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL3 0x0054
+#define MMSS_DSI_PHY_PLL_RESETSM_PLL_CAL_COUNT1 0x0058
+#define MMSS_DSI_PHY_PLL_RESETSM_PLL_CAL_COUNT2 0x005C
+#define MMSS_DSI_PHY_PLL_DIV_REF1 0x0060
+#define MMSS_DSI_PHY_PLL_DIV_REF2 0x0064
+#define MMSS_DSI_PHY_PLL_KVCO_COUNT1 0x0068
+#define MMSS_DSI_PHY_PLL_KVCO_COUNT2 0x006C
+#define MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL 0x0070
+#define MMSS_DSI_PHY_PLL_KVCO_CODE 0x0074
+#define MMSS_DSI_PHY_PLL_VREF_CFG1 0x0078
+#define MMSS_DSI_PHY_PLL_VREF_CFG2 0x007C
+#define MMSS_DSI_PHY_PLL_VREF_CFG3 0x0080
+#define MMSS_DSI_PHY_PLL_VREF_CFG4 0x0084
+#define MMSS_DSI_PHY_PLL_VREF_CFG5 0x0088
+#define MMSS_DSI_PHY_PLL_VREF_CFG6 0x008C
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP1 0x0090
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP2 0x0094
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP3 0x0098
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN 0x009C
+
+#define MMSS_DSI_PHY_PLL_BGTC 0x00A0
+#define MMSS_DSI_PHY_PLL_PLL_TEST_UPDN 0x00A4
+#define MMSS_DSI_PHY_PLL_PLL_VCO_TUNE 0x00A8
+#define MMSS_DSI_PHY_PLL_DEC_START1 0x00AC
+#define MMSS_DSI_PHY_PLL_PLL_AMP_OS 0x00B0
+#define MMSS_DSI_PHY_PLL_SSC_EN_CENTER 0x00B4
+#define MMSS_DSI_PHY_PLL_SSC_ADJ_PER1 0x00B8
+#define MMSS_DSI_PHY_PLL_SSC_ADJ_PER2 0x00BC
+#define MMSS_DSI_PHY_PLL_SSC_PER1 0x00C0
+#define MMSS_DSI_PHY_PLL_SSC_PER2 0x00C4
+#define MMSS_DSI_PHY_PLL_SSC_STEP_SIZE1 0x00C8
+#define MMSS_DSI_PHY_PLL_SSC_STEP_SIZE2 0x00CC
+#define MMSS_DSI_PHY_PLL_RES_CODE_UP 0x00D0
+#define MMSS_DSI_PHY_PLL_RES_CODE_DN 0x00D4
+#define MMSS_DSI_PHY_PLL_RES_CODE_UP_OFFSET 0x00D8
+#define MMSS_DSI_PHY_PLL_RES_CODE_DN_OFFSET 0x00DC
+#define MMSS_DSI_PHY_PLL_RES_CODE_START_SEG1 0x00E0
+#define MMSS_DSI_PHY_PLL_RES_CODE_START_SEG2 0x00E4
+#define MMSS_DSI_PHY_PLL_RES_CODE_CAL_CSR 0x00E8
+#define MMSS_DSI_PHY_PLL_RES_CODE 0x00EC
+#define MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL 0x00F0
+#define MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL2 0x00F4
+#define MMSS_DSI_PHY_PLL_RES_TRIM_EN_VCOCALDONE 0x00F8
+#define MMSS_DSI_PHY_PLL_FAUX_EN 0x00FC
+
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START1 0x0100
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START2 0x0104
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START3 0x0108
+#define MMSS_DSI_PHY_PLL_DEC_START2 0x010C
+#define MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN 0x0110
+#define MMSS_DSI_PHY_PLL_PLL_CRCTRL 0x0114
+#define MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL 0x013C
+#define MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL 0x0140
+#define MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER 0x0144
+#define MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER 0x0148
+#define MMSS_DSI_PHY_PLL_PLL_VCO_HIGH 0x014C
+#define MMSS_DSI_PHY_PLL_RESET_SM 0x0150
+
+uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base)
+{
+ uint32_t cnt, status;
+
+ udelay(1000);
+
+ /* check pll lock first */
+ for (cnt = 0; cnt < 5; cnt++) {
+ status = readl(pll_base + MMSS_DSI_PHY_PLL_RESET_SM);
+ dprintf(SPEW, "%s: pll_base=%x cnt=%d status=%x\n",
+ __func__, pll_base, cnt, status);
+ status &= 0x20; /* bit 5 */
+ if (status)
+ break;
+ udelay(5000);
+ }
+
+ if (!status)
+ goto pll_done;
+
+ /* check pll ready */
+ for (cnt = 0; cnt < 5; cnt++) {
+ status = readl(pll_base + MMSS_DSI_PHY_PLL_RESET_SM);
+ dprintf(SPEW, "%s: pll_base=%x cnt=%d status=%x\n",
+ __func__, pll_base, cnt, status);
+ status &= 0x40; /* bit 6 */
+ if (status)
+ break;
+ udelay(5000);
+ }
+
+pll_done:
+ return status;
+}
+
+uint32_t mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base)
+{
+ writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG1);
+ writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG2);
+ writel(0x15, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL);
+
+ writel(0x20, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL);
+ writel(0x07, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL2);
+ writel(0x02, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+}
+
+static void pll_20nm_phy_kvco_config(uint32_t pll_base)
+{
+
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_DIV_REF1);
+ writel(0x01, pll_base + MMSS_DSI_PHY_PLL_DIV_REF2);
+ writel(0x8a, pll_base + MMSS_DSI_PHY_PLL_KVCO_COUNT1);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CODE);
+}
+
+static void pll_20nm_phy_loop_bw_config(uint32_t pll_base)
+{
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_IP_SETI);
+ writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_PLL_CP_SETI);
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_IP_SETP);
+ writel(0x1f, pll_base + MMSS_DSI_PHY_PLL_PLL_CP_SETP);
+ writel(0x77, pll_base + MMSS_DSI_PHY_PLL_PLL_CRCTRL);
+}
+
+static void pll_20nm_phy_config(uint32_t pll_base)
+{
+ writel(0x40, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CMN_MODE);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IE_TRIM);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IP_TRIM);
+ writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL);
+ writel(0x0e, pll_base + MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_DC);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CORE_CLK_IN_SYNC_SEL);
+ writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN);
+ writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL1);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL2);
+ writel(0x4b, pll_base + MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND);
+ udelay(1000);
+
+ pll_20nm_phy_kvco_config(pll_base);
+
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG1);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG2);
+ writel(0x10, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG3);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG4);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_BGTC);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_TEST_UPDN);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCO_TUNE);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_AMP_OS);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_SSC_EN_CENTER);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_UP);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_DN);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_CAL_CSR);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_EN_VCOCALDONE);
+ writel(0x0c, pll_base + MMSS_DSI_PHY_PLL_FAUX_EN);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN);
+
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL);
+ udelay(1000);
+
+ pll_20nm_phy_loop_bw_config(pll_base);
+}
+
+static void mdss_dsi_pll_20nm_disable(uint32_t pll_base)
+{
+ dprintf(SPEW, "Disabling DSI PHY PLL \n");
+ writel(0x042, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x002, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
+ writel(0x002, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+ dmb();
+}
+
+int32_t mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd)
+{
+ uint32_t data;
+
+ mdss_dsi_phy_sw_reset(ctl_base);
+ pll_20nm_phy_config(pll_base);
+
+ /*
+ * For 20nm PHY, DSI PLL 1 drains some current in its reset state.
+ * Need to turn off the DSI1 PLL explicitly.
+ */
+ if (ctl_base == MIPI_DSI0_BASE) {
+ dprintf(SPEW, "Calling disable function for PHY PLL 1 \n");
+ mdss_dsi_pll_20nm_disable(DSI1_PLL_BASE);
+ }
+
+ /* set up divider */
+ data = readl(pll_base + MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
+ data |= 0x080; /* bit 7 */
+ data |= (pd->lp_div_mux << 5);
+ data |= pd->ndiv;
+
+ writel(data, pll_base + MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
+
+ writel(pd->hr_oclk2, pll_base + MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER);
+ writel(pd->hr_oclk3, pll_base + MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER);
+
+ writel(((pd->frac_start & 0x7f) | 0x80),
+ pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START1);
+ writel((((pd->frac_start >> 7) & 0x7f) | 0x80),
+ pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START2);
+ writel((((pd->frac_start >> 14) & 0x3f) | 0x40),
+ pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START3);
+
+ writel(((pd->dec_start & 0x7f) | 0x80),
+ pll_base + MMSS_DSI_PHY_PLL_DEC_START1);
+ writel((((pd->dec_start & 0x80) >> 7) | 0x02),
+ pll_base + MMSS_DSI_PHY_PLL_DEC_START2);
+
+ writel((pd->lock_comp & 0xff),
+ pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP1);
+
+ writel(((pd->lock_comp >> 8) & 0xff),
+ pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP2);
+
+ writel(((pd->lock_comp >> 16) & 0xff),
+ pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP3);
+
+ /*
+ * Make sure that PLL vco configuration is complete
+ * before controlling the state machine.
+ */
+ udelay(1000);
+ dmb();
+}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 1170bb6..cd2d217 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -36,6 +36,23 @@
#define MIPI_DSI1_BASE MIPI_DSI_BASE
#endif
+#define MMSS_DSI_CLKOUT_TIMING_CTRL 0x0c4
+#define MMSS_DSI_PHY_TIMING_CTRL_0 0x0140
+#define MMSS_DSI_PHY_CTRL_0 0x0170
+#define MMSS_DSI_PHY_CTRL_1 0x0174
+#define MMSS_DSI_PHY_CTRL_2 0x0178
+#define MMSS_DSI_PHY_STRENGTH_CTRL_0 0x0184
+#define MMSS_DSI_PHY_STRENGTH_CTRL_1 0x0188
+#define MMSS_DSI_PHY_BIST_CTRL_0 0x01b4
+#define MMSS_DSI_PHY_GLBL_TEST_CTRL 0x01d4
+#define MMSS_DSI_PHY_LDO_CTRL 0x01dc
+
+#define TOTAL_TIMING_CTRL_CONFIG 12
+#define TOTAL_BIST_CTRL_CONFIG 6
+/* 4 data lanes and 1 clock lanes */
+#define TOTAL_LANE_COUNT 5
+#define CONFIG_REG_FOR_EACH_LANE 9
+
static void mipi_dsi_calibration(void)
{
uint32_t i = 0;
@@ -274,7 +291,7 @@
return 0;
}
-int mdss_dsi_phy_init(struct mipi_dsi_panel_config *pinfo,
+static int mdss_dsi_phy_28nm_init(struct mipi_dsi_panel_config *pinfo,
uint32_t ctl_base, uint32_t phy_base)
{
struct mdss_dsi_phy_ctrl *pd;
@@ -310,8 +327,6 @@
/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
writel(0x5f, phy_base + 0x0170);
- /* Strength ctrl 1 */
- writel(pd->strength[1], phy_base + 0x0188);
dmb();
/* 4 lanes + clk lane configuration */
/* lane config n * (0 - 4) & DataPath setup */
@@ -349,3 +364,96 @@
dmb();
}
+
+void mdss_dsi_phy_contention_detection(
+ struct mipi_dsi_panel_config *pinfo,
+ uint32_t phy_base)
+{
+ struct mdss_dsi_phy_ctrl *pd;
+
+ if (mdp_get_revision() == MDP_REV_304)
+ return;
+
+ pd = (pinfo->mdss_dsi_phy_config);
+ writel(pd->strength[1], phy_base + 0x0188);
+ dmb();
+}
+
+static int mdss_dsi_phy_20nm_init(struct mipi_dsi_panel_config *pinfo,
+ uint32_t ctl_base, uint32_t phy_base)
+{
+ struct mdss_dsi_phy_ctrl *pd = pinfo->mdss_dsi_phy_config;
+ uint32_t i, off = 0, ln, offset;
+
+ /* Strength ctrl 0 */
+ writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0);
+
+ if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE)
+ pd->regulator[0] = 0x2; /* LDO mode */
+ mdss_dsi_phy_regulator_init(pd);
+
+ if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE)
+ writel(0x25, phy_base + MMSS_DSI_PHY_LDO_CTRL); /* LDO mode */
+ else
+ writel(0x00, phy_base + MMSS_DSI_PHY_LDO_CTRL); /* DCDC mode */
+
+ off = MMSS_DSI_PHY_TIMING_CTRL_0;
+ for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) {
+ writel(pd->timing[i], phy_base + off);
+ dmb();
+ }
+
+ /* Currently the Phy settings for the DSI 0 is done in clk prepare*/
+ if (phy_base == DSI1_PHY_BASE) {
+ writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1);
+ writel(0x05, phy_base + MMSS_DSI_PHY_CTRL_0);
+ dmb();
+
+ writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0);
+ dmb();
+
+ /* BITCLK_HS_SEL should be set to 0 for left */
+ writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL);
+
+ writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_2);
+ writel(0x02, phy_base + MMSS_DSI_PHY_CTRL_2);
+ writel(0x03, phy_base + MMSS_DSI_PHY_CTRL_2);
+ dmb();
+ }
+
+ writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
+ dmb();
+
+ for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) {
+ off = (ln * 0x40);
+ for (i = 0; i < CONFIG_REG_FOR_EACH_LANE; i++, off += 4) {
+ offset = i + (ln * CONFIG_REG_FOR_EACH_LANE);
+ writel(pd->laneCfg[offset], phy_base + off);
+ dmb();
+ }
+ }
+
+ dmb();
+
+ off = MMSS_DSI_PHY_BIST_CTRL_0;
+ for (i = 0; i < TOTAL_BIST_CTRL_CONFIG; i++, off +=4) {
+ writel(pd->bistCtrl[i], phy_base + off);
+ }
+ dmb();
+
+ writel(0x41b, ctl_base + MMSS_DSI_CLKOUT_TIMING_CTRL);
+ dmb();
+}
+
+int mdss_dsi_phy_init (struct mipi_dsi_panel_config *pinfo,
+ uint32_t ctl_base, uint32_t phy_base)
+{
+ int ret;
+
+ if (pinfo->mdss_dsi_phy_config->is_pll_20nm)
+ ret = mdss_dsi_phy_20nm_init(pinfo, ctl_base, phy_base);
+ else
+ ret = mdss_dsi_phy_28nm_init(pinfo, ctl_base, phy_base);
+
+ return ret;
+}
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index 7b76875..982af7a 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -878,15 +878,27 @@
sdhci_msm_set_mci_clk(host);
clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
}
+
+ /* Execute Tuning for hs200 mode */
+ if ((mmc_ret = sdhci_msm_execute_tuning(host, card, width)))
+ dprintf(CRITICAL, "Tuning for hs200 failed\n");
+
+ /* Once the tuning is executed revert back the clock to 200MHZ
+ * and disable the MCI_CLK divider so that we can use SDHC clock
+ * divider to supply clock to the card
+ */
+ if (host->timing == MMC_HS400_TIMING)
+ {
+ MMC_SAVE_TIMING(host, MMC_HS200_TIMING);
+ sdhci_msm_set_mci_clk(host);
+ clock_config_mmc(host->msm_host->slot, MMC_CLK_192MHZ);
+ }
else
{
/* Save the timing value, before changing the clock */
MMC_SAVE_TIMING(host, MMC_HS200_TIMING);
}
- /* Execute Tuning for hs200 mode */
- if ((mmc_ret = sdhci_msm_execute_tuning(host, card, width)))
- dprintf(CRITICAL, "Tuning for hs200 failed\n");
DBG("\n Enabling HS200 Mode Done\n");
@@ -1034,6 +1046,8 @@
* Enable HS400 mode
*/
sdhci_msm_set_mci_clk(host);
+ /* Set the clock back to 400 MHZ */
+ clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
/* 7. Execute Tuning for hs400 mode */
if ((mmc_ret = sdhci_msm_execute_tuning(host, card, width)))
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index 8e59579..6675d67 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -41,11 +41,28 @@
udelay(10);
writel(val & ~BIT(0), GCC_QUSB2_PHY_BCR);
- /* Deassert POWERDOWN by clearing bit 0 to enable the PHY */
- val = readl(QUSB2PHY_PORT_POWERDOWN);
- writel(val & ~BIT(0), QUSB2PHY_PORT_POWERDOWN);
+ /* set CLAMP_N_EN and stay with disabled USB PHY */
+ writel(0x23, QUSB2PHY_PORT_POWERDOWN);
+
+ /* Set HS impedance to 42ohms */
+ writel(0xA0, QUSB2PHY_PORT_TUNE1);
+
+ /* Set TX current to 19mA, TX SR and TX bias current to 1, 1 */
+ writel(0xA5, QUSB2PHY_PORT_TUNE2);
+
+ /* Increase autocalibration bias circuit settling time
+ * and enable utocalibration */
+ writel(0x81, QUSB2PHY_PORT_TUNE3);
+
+ writel(0x85, QUSB2PHY_PORT_TUNE4);
+ /* Wait for tuning params to take effect right before re-enabling power*/
udelay(10);
- /* set CLAMP_N_EN and FREEZIO_N */
+ /* Disable the PHY */
+ writel(0x23, QUSB2PHY_PORT_POWERDOWN);
+ /* Enable ULPI mode */
+ writel(0x0, QUSB2PHY_PORT_UTMI_CTRL2);
+ /* Enable PHY */
+ /* set CLAMP_N_EN and USB PHY is enabled*/
writel(0x22, QUSB2PHY_PORT_POWERDOWN);
}
diff --git a/platform/msm_shared/rpm-smd.c b/platform/msm_shared/rpm-smd.c
index 17b7ff5..6144fba 100644
--- a/platform/msm_shared/rpm-smd.c
+++ b/platform/msm_shared/rpm-smd.c
@@ -103,9 +103,6 @@
ret = smd_write(&ch, smd_data, len_to_smd, SMD_APPS_RPM);
- /* TODO: Use events */
- mdelay(1);
-
/* Read the response */
ack_msg_len = rpm_recv_data(&rlen);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index fa49ff0..bf6d42e 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -224,6 +224,8 @@
$(LOCAL_DIR)/mipi_dsi.o \
$(LOCAL_DIR)/mipi_dsi_phy.o \
$(LOCAL_DIR)/mipi_dsi_autopll.o \
+ $(LOCAL_DIR)/mdss_hdmi.o \
+ $(LOCAL_DIR)/hdmi_pll_28nm.o \
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
@@ -404,6 +406,7 @@
endif
ifeq ($(PLATFORM),msm8994)
+DEFINES += DISPLAY_TYPE_MDSS=1
OBJS += $(LOCAL_DIR)/qgic.o \
$(LOCAL_DIR)/qtimer.o \
$(LOCAL_DIR)/qtimer_mmap.o \
@@ -431,7 +434,13 @@
$(LOCAL_DIR)/crypto_hash.o \
$(LOCAL_DIR)/crypto5_eng.o \
$(LOCAL_DIR)/crypto5_wrapper.o \
- $(LOCAL_DIR)/qusb2_phy.o
+ $(LOCAL_DIR)/qusb2_phy.o \
+ $(LOCAL_DIR)/mdp5.o \
+ $(LOCAL_DIR)/display.o \
+ $(LOCAL_DIR)/mipi_dsi.o \
+ $(LOCAL_DIR)/mipi_dsi_phy.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll_20nm.o
endif
ifeq ($(PLATFORM),ferrum)
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index b2ebfa3..48f62be 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -50,6 +50,33 @@
SCM_MASK_IRQS | \
((n) & 0xf))
+/* SCM interface as per ARM spec present? */
+bool scm_arm_support;
+
+static void scm_arm_support_available(uint32_t svc_id, uint32_t cmd_id)
+{
+ uint32_t ret;
+ scmcall_arg scm_arg = {0};
+ scmcall_arg scm_ret = {0};
+ /* Make a call to check if SCM call available using new interface,
+ * if this returns 0 then scm implementation as per arm spec
+ * otherwise use the old interface for scm calls
+ */
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_INFO, IS_CALL_AVAIL_CMD);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x1);
+ scm_arg.x2 = MAKE_SIP_SCM_CMD(svc_id, cmd_id);
+
+ ret = scm_call2(&scm_arg, &scm_ret);
+
+ if (!ret)
+ scm_arm_support = true;
+}
+
+
+void scm_init()
+{
+ scm_arm_support_available(SCM_SVC_INFO, IS_CALL_AVAIL_CMD);
+}
/**
* alloc_scm_command() - Allocate an SCM command
@@ -255,17 +282,30 @@
secure_cfg.id = id;
secure_cfg.spare = 0;
+ scmcall_arg scm_arg = {0};
- ret = scm_call(SVC_MEMORY_PROTECTION, IOMMU_SECURE_CFG, &secure_cfg, sizeof(secure_cfg),
- NULL, 0);
+ if(!scm_arm_support)
+ {
+ ret = scm_call(SVC_MEMORY_PROTECTION, IOMMU_SECURE_CFG, &secure_cfg, sizeof(secure_cfg),
+ NULL, 0);
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SVC_MEMORY_PROTECTION, IOMMU_SECURE_CFG);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2);
+ scm_arg.x2 = id;
+ scm_arg.x3 = 0x0; /* Spare unused */
- if (ret) {
+ ret = scm_call2(&scm_arg, NULL);
+ }
+
+ if (ret)
+ {
dprintf(CRITICAL, "Secure Config failed\n");
ret = 1;
}
return ret;
-
}
/* SCM Encrypt Command */
@@ -274,6 +314,12 @@
int ret;
img_req cmd;
+ if (scm_arm_support)
+ {
+ dprintf(INFO, "%s:SCM call is not supported\n",__func__);
+ return -1;
+ }
+
cmd.img_ptr = (uint32*) img_ptr;
cmd.img_len_ptr = img_len_ptr;
@@ -302,6 +348,12 @@
int ret;
img_req cmd;
+ if (scm_arm_support)
+ {
+ dprintf(INFO, "%s:SCM call is not supported\n",__func__);
+ return -1;
+ }
+
cmd.img_ptr = (uint32*) img_ptr;
cmd.img_len_ptr = img_len_ptr;
@@ -332,6 +384,12 @@
ssd_parse_md_rsp parse_rsp;
int prev_len = 0;
+ if (scm_arm_support)
+ {
+ dprintf(INFO, "%s:SCM call is not supported\n",__func__);
+ return -1;
+ }
+
/* Populate meta-data ptr. Here md_len is the meta-data length.
* The Code below follows a growing length approach. First send
* min(img_len_ptr,SSD_HEADER_MIN_SIZE) say 128 bytes for example.
@@ -397,6 +455,12 @@
ssd_decrypt_img_frag_req decrypt_req;
ssd_decrypt_img_frag_rsp decrypt_rsp;
+ if (scm_arm_support)
+ {
+ dprintf(INFO, "%s:SCM call is not supported\n",__func__);
+ return -1;
+ }
+
ret = ssd_image_is_encrypted(img_ptr,img_len_ptr,&ctx_id);
switch(ret)
{
@@ -461,15 +525,30 @@
feature_version_req feature_req;
feature_version_rsp feature_rsp;
int ret = 0;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
feature_req.feature_id = TZBSP_FVER_SSD;
- ret = scm_call(TZBSP_SVC_INFO,
- TZ_INFO_GET_FEATURE_ID,
- &feature_req,
- sizeof(feature_req),
- &feature_rsp,
- sizeof(feature_rsp));
+ if (!scm_arm_support)
+ {
+ ret = scm_call(TZBSP_SVC_INFO,
+ TZ_INFO_GET_FEATURE_ID,
+ &feature_req,
+ sizeof(feature_req),
+ &feature_rsp,
+ sizeof(feature_rsp));
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(TZBSP_SVC_INFO, TZ_INFO_GET_FEATURE_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x1);
+ scm_arg.x2 = feature_req.feature_id;
+
+ ret = scm_call2(&scm_arg, &scm_ret);
+ feature_rsp.version = scm_ret.x1;
+ }
+
if(!ret)
*major = TZBSP_GET_FEATURE_VERSION(feature_rsp.version);
@@ -482,6 +561,12 @@
ssd_protect_keystore_req protect_req;
ssd_protect_keystore_rsp protect_rsp;
+ if (scm_arm_support)
+ {
+ dprintf(INFO, "%s:SCM call is not supported\n",__func__);
+ return -1;
+ }
+
protect_req.keystore_ptr = img_ptr;
protect_req.keystore_len = img_len;
@@ -522,6 +607,12 @@
cmd_buf = (void *)&fuse_id;
cmd_len = sizeof(fuse_id);
+ if (scm_arm_support)
+ {
+ dprintf(INFO, "%s:SCM call is not supported\n",__func__);
+ return;
+ }
+
/*no response */
resp_buf = NULL;
resp_len = 0;
@@ -543,6 +634,13 @@
uint8_t resp_buf;
uint32_t fuse_id = HLOS_IMG_TAMPER_FUSE;
+
+ if (scm_arm_support)
+ {
+ dprintf(INFO, "%s:SCM call is not supported\n",__func__);
+ return;
+ }
+
cmd_buf = (void *)&fuse_id;
cmd_len = sizeof(fuse_id);
@@ -577,6 +675,7 @@
void *resp_buf = NULL;
size_t resp_len = 0;
struct qseecom_save_partition_hash_req req;
+ scmcall_arg scm_arg = {0};
/*no response */
resp_buf = NULL;
@@ -585,12 +684,26 @@
req.partition_id = 0; /* kernel */
memcpy(req.digest, digest, sizeof(req.digest));
- svc_id = SCM_SVC_ES;
- cmd_id = SCM_SAVE_PARTITION_HASH_ID;
- cmd_buf = (void *)&req;
- cmd_len = sizeof(req);
+ if (!scm_arm_support)
+ {
+ svc_id = SCM_SVC_ES;
+ cmd_id = SCM_SAVE_PARTITION_HASH_ID;
+ cmd_buf = (void *)&req;
+ cmd_len = sizeof(req);
- scm_call(svc_id, cmd_id, cmd_buf, cmd_len, resp_buf, resp_len);
+ scm_call(svc_id, cmd_id, cmd_buf, cmd_len, resp_buf, resp_len);
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_ES, SCM_SAVE_PARTITION_HASH_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x3, 0, SMC_PARAM_TYPE_BUFFER_READWRITE);
+ scm_arg.x2 = req.partition_id;
+ scm_arg.x3 = (uint8_t *)&req.digest;
+ scm_arg.x4 = sizeof(req.digest);
+
+ if (scm_call2(&scm_arg, NULL))
+ dprintf(CRITICAL, "Failed to Save kernel hash\n");
+ }
}
/*
@@ -612,6 +725,12 @@
uint32_t chn_id;
}__PACKED switch_ce_chn_buf;
+ if (scm_arm_support)
+ {
+ dprintf(INFO, "%s:SCM call is not supported\n",__func__);
+ return 0;
+ }
+
switch_ce_chn_buf.resource = TZ_RESOURCE_CE_AP;
switch_ce_chn_buf.chn_id = channel;
cmd_buf = (void *)&switch_ce_chn_buf;
@@ -631,6 +750,12 @@
{
int ret = 0;
+ if (scm_arm_support)
+ {
+ dprintf(INFO, "%s:SCM call is not supported\n",__func__);
+ return -1;
+ }
+
ret = scm_call_atomic(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER, 0);
return ret;
@@ -656,17 +781,31 @@
void *cmd_buf;
size_t cmd_len;
static el1_system_param param;
+ scmcall_arg scm_arg = {0};
param.el1_x0 = dtb_offset;
param.el1_elr = kernel_entry;
- /* Command Buffer */
- cmd_buf = (void *)¶m;
- cmd_len = sizeof(el1_system_param);
-
/* Response Buffer = Null as no response expected */
dprintf(INFO, "Jumping to kernel via monitor\n");
- scm_call(svc_id, cmd_id, cmd_buf, cmd_len, NULL, 0);
+
+ if (!scm_arm_support)
+ {
+ /* Command Buffer */
+ cmd_buf = (void *)¶m;
+ cmd_len = sizeof(el1_system_param);
+
+ scm_call(svc_id, cmd_id, cmd_buf, cmd_len, NULL, 0);
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_MILESTONE_32_64_ID, SCM_SVC_MILESTONE_CMD_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2, SMC_PARAM_TYPE_BUFFER_READ);
+ scm_arg.x2 = (void *)¶m;
+ scm_arg.x3 = sizeof(el1_system_param);
+
+ scm_call2(&scm_arg, NULL);
+ }
/* Assert if execution ever reaches here */
dprintf(CRITICAL, "Failed to jump to kernel\n");
@@ -678,19 +817,36 @@
{
int ret;
struct tz_prng_data data;
+ scmcall_arg scm_arg = {0};
- data.out_buf = (uint8_t*) rbuf;
- data.out_buf_size = r_len;
+ if (!scm_arm_support)
+ {
+ data.out_buf = (uint8_t*) rbuf;
+ data.out_buf_size = r_len;
- /*
- * random buffer must be flushed/invalidated before and after TZ call.
- */
- arch_clean_invalidate_cache_range((addr_t) rbuf, r_len);
+ /*
+ * random buffer must be flushed/invalidated before and after TZ call.
+ */
+ arch_clean_invalidate_cache_range((addr_t) rbuf, r_len);
- ret = scm_call(TZ_SVC_CRYPTO, PRNG_CMD_ID, &data, sizeof(data), NULL, 0);
+ ret = scm_call(TZ_SVC_CRYPTO, PRNG_CMD_ID, &data, sizeof(data), NULL, 0);
- /* Invalidate the updated random buffer */
- arch_clean_invalidate_cache_range((addr_t) rbuf, r_len);
+ /* Invalidate the updated random buffer */
+ arch_clean_invalidate_cache_range((addr_t) rbuf, r_len);
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(TZ_SVC_CRYPTO, PRNG_CMD_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE);
+ scm_arg.x2 = (uint8_t *) rbuf;
+ scm_arg.x3 = r_len;
+
+ ret = scm_call2(&scm_arg, NULL);
+ if (!ret)
+ arch_clean_invalidate_cache_range((addr_t) rbuf, r_len);
+ else
+ dprintf(CRITICAL, "Secure canary SCM failed: %x\n", ret);
+ }
return ret;
}
@@ -714,12 +870,26 @@
uint32_t ret = 0;
uint32_t response = 0;
tz_xpu_prot_cmd cmd;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
- cmd.config = ERR_FATAL_ENABLE;
- cmd.spare = 0;
+ if (!scm_arm_support)
+ {
+ cmd.config = ERR_FATAL_ENABLE;
+ cmd.spare = 0;
- ret = scm_call(SVC_MEMORY_PROTECTION, XPU_ERR_FATAL, &cmd, sizeof(cmd), &response,
- sizeof(response));
+ ret = scm_call(SVC_MEMORY_PROTECTION, XPU_ERR_FATAL, &cmd, sizeof(cmd), &response,
+ sizeof(response));
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SVC_MEMORY_PROTECTION, XPU_ERR_FATAL);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2);
+ scm_arg.x2 = ERR_FATAL_ENABLE;
+ scm_arg.x3 = 0x0;
+ ret = scm_call2(&scm_arg, &scm_ret);
+ response = scm_ret.x1;
+ }
if (ret)
dprintf(CRITICAL, "Failed to set XPU violations as fatal errors: %u\n", response);
@@ -728,3 +898,74 @@
return ret;
}
+
+static uint32_t scm_call_a32(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3, uint32_t x4, uint32_t x5, scmcall_ret *ret)
+{
+ register uint32_t r0 __asm__("r0") = x0;
+ register uint32_t r1 __asm__("r1") = x1;
+ register uint32_t r2 __asm__("r2") = x2;
+ register uint32_t r3 __asm__("r3") = x3;
+ register uint32_t r4 __asm__("r4") = x4;
+ register uint32_t r5 __asm__("r5") = x5;
+
+ __asm__ volatile(
+ __asmeq("%0", "r0")
+ __asmeq("%1", "r1")
+ __asmeq("%2", "r2")
+ __asmeq("%3", "r3")
+ __asmeq("%4", "r0")
+ __asmeq("%5", "r1")
+ __asmeq("%6", "r2")
+ __asmeq("%7", "r3")
+ __asmeq("%8", "r4")
+ __asmeq("%9", "r5")
+ "smc #0 @ switch to secure world\n"
+ : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
+ : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), "r" (r5));
+
+ if (ret)
+ {
+ ret->x1 = r1;
+ ret->x2 = r2;
+ ret->x3 = r3;
+ }
+
+ return r0;
+}
+
+uint32_t scm_call2(scmcall_arg *arg, scmcall_ret *ret)
+{
+ uint32_t *indir_arg = NULL;
+ uint32_t x5;
+ int i;
+ uint32_t rc;
+
+ arg->x0 = arg->atomic ? (arg->x0 | SCM_ATOMIC_BIT) : arg->x0;
+ x5 = arg->x5[0];
+
+ if ((arg->x1 & 0xF) > SCM_MAX_ARG_LEN)
+ {
+ indir_arg = memalign(CACHE_LINE, (SCM_INDIR_MAX_LEN * sizeof(uint32_t)));
+ ASSERT(indir_arg);
+
+ for (i = 0 ; i < SCM_INDIR_MAX_LEN; i++)
+ {
+ indir_arg[i] = arg->x5[i];
+ }
+ arch_clean_invalidate_cache_range((addr_t) indir_arg, ROUNDUP((SCM_INDIR_MAX_LEN * sizeof(uint32_t)), CACHE_LINE));
+ x5 = (addr_t) indir_arg;
+ }
+
+ rc = scm_call_a32(arg->x0, arg->x1, arg->x2, arg->x3, arg->x4, x5, ret);
+
+ if (rc)
+ {
+ dprintf(CRITICAL, "SCM call: 0x%x failed with :%x\n", arg->x0, rc);
+ return rc;
+ }
+
+ if (indir_arg)
+ free(indir_arg);
+
+ return 0;
+}
diff --git a/platform/msm_shared/smd.c b/platform/msm_shared/smd.c
index 6377e7e..dfb5b62 100644
--- a/platform/msm_shared/smd.c
+++ b/platform/msm_shared/smd.c
@@ -167,8 +167,20 @@
return -1;
}
- /* Clear the data_written flag */
- ch->port_info->ch1.data_written = 0;
+ /* Wait until the data updated in the smd buffer is equal to smd packet header*/
+ while ((ch->port_info->ch1.write_index - ch->port_info->ch1.read_index) < sizeof(smd_pkt_hdr))
+ {
+ /* Get the update info from memory */
+ arch_invalidate_cache_range((addr_t) ch->port_info, size);
+
+ if ((ch->port_info->ch1.read_index + sizeof(smd_pkt_hdr)) >= ch->fifo_size)
+ {
+ dprintf(CRITICAL, "At %d:%s:RX channel read index [%u] is greater than RX fifo size[%u]\n",
+ __LINE__,__func__, ch->port_info->ch1.read_index, ch->fifo_size);
+ return -1;
+ }
+ }
+
arch_invalidate_cache_range((addr_t)(ch->recv_buf + ch->port_info->ch1.read_index), sizeof(smd_hdr));
@@ -177,6 +189,21 @@
*len = smd_hdr.pkt_size;
+ /* Wait on the data being updated in SMEM before returing the response */
+ while ((ch->port_info->ch1.write_index - ch->port_info->ch1.read_index) < smd_hdr.pkt_size)
+ {
+ /* Get the update info from memory */
+ arch_invalidate_cache_range((addr_t) ch->port_info, size);
+
+ if ((ch->port_info->ch1.read_index + sizeof(smd_hdr) + smd_hdr.pkt_size) >= ch->fifo_size)
+ {
+ dprintf(CRITICAL, "At %d:%s:RX channel read index [%u] is greater than RX fifo size[%u]\n",
+ __LINE__,__func__, ch->port_info->ch1.read_index, ch->fifo_size);
+ return -1;
+ }
+ }
+
+ /* We are good to return the response now */
return (uint8_t*)(ch->recv_buf + ch->port_info->ch1.read_index + sizeof(smd_hdr));
}
@@ -184,10 +211,12 @@
{
ch->port_info->ch1.read_index += sizeof(smd_pkt_hdr) + len;
+ /* Clear the data_written flag */
+ ch->port_info->ch1.data_written = 0;
+
/* Set the data_read flag */
- ch->port_info->ch1.data_read = 1;
+ ch->port_info->ch0.data_read = 1;
ch->port_info->ch0.mask_recv_intr = 1;
- ch->port_info->ch0.state_updated = 1;
dsb();
@@ -244,7 +273,6 @@
ch->port_info->ch0.data_written = 1;
ch->port_info->ch0.mask_recv_intr = 0;
- ch->port_info->ch0.state_updated = 1;
dsb();
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 14925f5..2c3a610 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -375,6 +375,12 @@
FSM9010 = 255,
FSM9016 = 256,
FSM9055 = 257,
+ MSM8209 = 258,
+ MSM8208 = 259,
+ MDM9209 = 260,
+ MDM9309 = 261,
+ MDM9609 = 262,
+ MSM8239 = 263,
};
enum platform {
diff --git a/platform/msmzirc/include/platform/iomap.h b/platform/msmzirc/include/platform/iomap.h
index a401803..f8e9cf3 100644
--- a/platform/msmzirc/include/platform/iomap.h
+++ b/platform/msmzirc/include/platform/iomap.h
@@ -171,6 +171,11 @@
#define QUSB2_PHY_BASE 0x00079000
#define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4)
#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00041028)
+#define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4)
+#define QUSB2PHY_PORT_TUNE1 (QUSB2_PHY_BASE + 0x00000080)
+#define QUSB2PHY_PORT_TUNE2 (QUSB2_PHY_BASE + 0x00000084)
+#define QUSB2PHY_PORT_TUNE3 (QUSB2_PHY_BASE + 0x00000088)
+#define QUSB2PHY_PORT_TUNE4 (QUSB2_PHY_BASE + 0x0000008C)
/* SS QMP (Qulacomm Multi Protocol) */
#define QMP_PHY_BASE 0x78000
diff --git a/project/msm8226.mk b/project/msm8226.mk
index a165ec1..0476594 100644
--- a/project/msm8226.mk
+++ b/project/msm8226.mk
@@ -6,7 +6,12 @@
MODULES += app/aboot
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
+
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
diff --git a/project/msm8916.mk b/project/msm8916.mk
index 0b76b89..201f173 100644
--- a/project/msm8916.mk
+++ b/project/msm8916.mk
@@ -26,7 +26,7 @@
DEFINES += ABOOT_FORCE_TAGS_ADDR=0x81E00000
#Enable the feature of long press power on
-DEFINES += LONG_PRESS_POWER_ON=0
+DEFINES += LONG_PRESS_POWER_ON=1
#Disable thumb mode
ENABLE_THUMB := false
@@ -48,3 +48,6 @@
ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
DEFINES += PON_VIB_SUPPORT=1
endif
+
+#enable user force reset feature
+DEFINES += USER_FORCE_RESET_SUPPORT=1
diff --git a/target/apq8084/include/target/display.h b/target/apq8084/include/target/display.h
index 8d6eb87..38baf50 100644
--- a/target/apq8084/include/target/display.h
+++ b/target/apq8084/include/target/display.h
@@ -106,6 +106,7 @@
#define DISPLAY_CMDLINE_PREFIX " mdss_mdp.panel="
#define MIPI_FB_ADDR 0x03200000
+#define HDMI_FB_ADDR 0x03200000
#define MIPI_HSYNC_PULSE_WIDTH 12
#define MIPI_HSYNC_BACK_PORCH_DCLK 32
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index 3aa2379..a67e97f 100755
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -233,7 +233,7 @@
return NO_ERROR;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ldocounter = 0;
uint32_t pm8x41_ldo_base = 0x13F00;
@@ -289,6 +289,77 @@
return NO_ERROR;
}
+int target_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ uint32_t ret;
+
+ dprintf(SPEW, "%s: target_panel_clock\n", __func__);
+
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mmss_bus_clock_enable();
+ mdp_clock_enable();
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(0);
+ return ret;
+ }
+
+ hdmi_phy_reset();
+ hdmi_pll_config();
+ hdmi_vco_enable();
+ hdmi_clk_enable();
+ } else if(!target_cont_splash_screen()) {
+ /* Disable clocks if continuous splash off */
+ hdmi_clk_disable();
+ hdmi_vco_disable();
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return NO_ERROR;
+}
+
+static void target_hdmi_mvs_enable(bool enable)
+{
+ struct pm8x41_mvs mvs;
+ mvs.base = PM8x41_MVS1_BASE;
+
+ if (enable)
+ pm8x41_enable_mvs(&mvs, MVS_ENABLE);
+ else
+ pm8x41_enable_mvs(&mvs, MVS_DISABLE);
+}
+
+static void target_hdmi_vreg_enable(bool enable)
+{
+ struct pm8x41_mpp mpp;
+ mpp.base = PM8x41_MMP3_BASE;
+
+ if (enable) {
+ mpp.mode = MPP_HIGH;
+ mpp.vin = MPP_VIN2;
+ pm8x41_config_output_mpp(&mpp);
+ pm8x41_enable_mpp(&mpp, MPP_ENABLE);
+ } else {
+ pm8x41_enable_mpp(&mpp, MPP_DISABLE);
+ }
+}
+
+int target_hdmi_regulator_ctrl(bool enable)
+{
+ target_hdmi_mvs_enable(enable);
+ target_hdmi_vreg_enable(enable);
+
+ return 0;
+}
+
void target_edp_panel_init(struct msm_panel_info *pinfo)
{
edp_panel_init(pinfo);
@@ -371,7 +442,7 @@
if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
if (buf_size < (prefix_string_len + LK_OVERRIDE_PANEL_LEN +
- HDMI_CONTROLLER_STRING)) {
+ strlen(HDMI_CONTROLLER_STRING))) {
dprintf(CRITICAL, "command line argument is greater than buffer size\n");
return false;
}
@@ -382,7 +453,7 @@
buf_size -= LK_OVERRIDE_PANEL_LEN;
strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
} else {
- ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+ ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
return ret;
@@ -394,20 +465,21 @@
panel_name += strspn(panel_name, " ");
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+ || (!strcmp(panel_name, SIM_VIDEO_PANEL))
+ || (!strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL))) {
+ dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
+ panel_name);
return;
- }
-
- if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+ } else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
dprintf(INFO, "%s: HDMI is primary\n", __func__);
+ mdss_hdmi_display_init(MDP_REV_50, HDMI_FB_ADDR);
return;
}
ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR);
- if (ret) {
+ if (ret)
msm_display_off();
- }
}
void target_display_shutdown(void)
diff --git a/target/ferrum/init.c b/target/ferrum/init.c
index 5e87b2e..604e0ba 100644
--- a/target/ferrum/init.c
+++ b/target/ferrum/init.c
@@ -170,3 +170,36 @@
{
}
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+ /*
+ * already fill the board->target on board.c
+ */
+}
+
+void target_baseband_detect(struct board_data *board)
+{
+ uint32_t platform;
+
+ platform = board->platform;
+ switch(platform)
+ {
+ case MSM8909:
+ case MSM8209:
+ case MSM8208:
+ board->baseband = BASEBAND_MSM;
+ break;
+
+ case MDM9209:
+ case MDM9309:
+ case MDM9609:
+ board->baseband = BASEBAND_MDM;
+ break;
+
+ default:
+ dprintf(CRITICAL, "Platform type: %u is not supported\n", platform);
+ ASSERT(0);
+ };
+}
+
diff --git a/target/init.c b/target/init.c
index 0d99880..4a896e8 100644
--- a/target/init.c
+++ b/target/init.c
@@ -69,6 +69,11 @@
{
}
+__WEAK uint32_t is_user_force_reset(void)
+{
+ return 0;
+}
+
__WEAK int set_download_mode(enum dload_mode mode)
{
return -1;
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index d21fb94..5265f7d 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -356,7 +356,7 @@
return ret;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ret = NO_ERROR;
uint32_t ldocounter = 0;
@@ -389,7 +389,7 @@
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(pbuf, buf_size);
+ return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
void target_display_init(const char *panel_name)
@@ -398,8 +398,10 @@
uint32_t ret = 0;
uint32_t fb_addr = MIPI_FB_ADDR;
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+ || (!strcmp(panel_name, SIM_VIDEO_PANEL))) {
+ dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
+ panel_name);
return;
}
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index cb9f3ce..0db3e9e 100755
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -135,7 +135,7 @@
return 0;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ldocounter = 0;
uint32_t pm8x41_ldo_base = 0x13F00;
@@ -164,7 +164,7 @@
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(pbuf, buf_size);
+ return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
void target_display_init(const char *panel_name)
diff --git a/target/msm8916/init.c b/target/msm8916/init.c
index 2a33157..bcac813 100644
--- a/target/msm8916/init.c
+++ b/target/msm8916/init.c
@@ -168,6 +168,23 @@
keys_post_event(KEY_VOLUMEUP, 1);
}
+#if USER_FORCE_RESET_SUPPORT
+/* Return 1 if it is a force resin triggered by user. */
+uint32_t is_user_force_reset(void)
+{
+ uint8_t poff_reason1 = pm8x41_get_pon_poff_reason1();
+ uint8_t poff_reason2 = pm8x41_get_pon_poff_reason2();
+
+ dprintf(SPEW, "poff_reason1: %d\n", poff_reason1);
+ dprintf(SPEW, "poff_reason2: %d\n", poff_reason2);
+ if (pm8x41_get_is_cold_boot() && (poff_reason1 == KPDPWR_AND_RESIN ||
+ poff_reason2 == STAGE3))
+ return 1;
+ else
+ return 0;
+}
+#endif
+
void target_init(void)
{
uint32_t base_addr;
@@ -324,6 +341,7 @@
case MSM8236:
case MSM8636:
case MSM8936:
+ case MSM8239:
board->baseband = BASEBAND_MSM;
break;
case APQ8016:
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
index 3dc17df..d97823c 100644
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -50,6 +50,7 @@
#include "include/panel_nt35596_1080p_skuk_video.h"
#include "include/panel_sharp_wqxga_dualdsi_video.h"
#include "include/panel_jdi_fhd_video.h""
+#include "include/panel_hx8379a_fwvga_video.h"
#define DISPLAY_MAX_PANEL_DETECTION 2
#define OTM8019A_FWVGA_VIDEO_PANEL_ON_DELAY 50
@@ -69,6 +70,7 @@
NT35596_1080P_VIDEO_PANEL,
SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
JDI_FHD_VIDEO_PANEL,
+HX8379A_FWVGA_VIDEO_PANEL,
UNKNOWN_PANEL
};
@@ -85,7 +87,8 @@
{"otm1283a_720p_video", OTM1283A_720P_VIDEO_PANEL},
{"nt35596_1080p_video", NT35596_1080P_VIDEO_PANEL},
{"sharp_wqxga_dualdsi_video",SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
- {"jdi_fhd_video", JDI_FHD_VIDEO_PANEL}
+ {"jdi_fhd_video", JDI_FHD_VIDEO_PANEL},
+ {"hx8379a_wvga_video", HX8379A_FWVGA_VIDEO_PANEL},
};
static uint32_t panel_id;
@@ -308,6 +311,26 @@
memcpy(phy_db->timing,
jdi_fhd_video_timings, TIMING_SIZE);
break;
+ case HX8379A_FWVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8379a_fwvga_video_panel_data;
+ panelstruct->panelres = &hx8379a_fwvga_video_panel_res;
+ panelstruct->color = &hx8379a_fwvga_video_color;
+ panelstruct->videopanel = &hx8379a_fwvga_video_video_panel;
+ panelstruct->commandpanel = &hx8379a_fwvga_video_command_panel;
+ panelstruct->state = &hx8379a_fwvga_video_state;
+ panelstruct->laneconfig = &hx8379a_fwvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8379a_fwvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8379a_fwvga_video_reset_seq;
+ panelstruct->backlightinfo = &hx8379a_fwvga_video_backlight;
+ pinfo->mipi.panel_cmds
+ = hx8379a_fwvga_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = HX8379A_FWVGA_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ hx8379a_fwvga_video_timings, TIMING_SIZE);
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -373,6 +396,9 @@
auto_pan_loop++;
break;
case HW_PLATFORM_QRD:
+ target_id = board_target_id();
+ plat_hw_ver_major = ((target_id >> 16) & 0xFF);
+
if (platform_is_msm8939()) {
switch (hw_subtype) {
case HW_PLATFORM_SUBTYPE_SKUK:
@@ -386,17 +412,18 @@
} else {
switch (hw_subtype) {
case HW_PLATFORM_SUBTYPE_SKUH:
- target_id = board_target_id();
- plat_hw_ver_major = ((target_id >> 16) & 0xFF);
-
- /* qrd fan-out hw ? */
+ /* qrd SKUIC */
if ((plat_hw_ver_major >> 4) == 0x1)
panel_id = OTM1283A_720P_VIDEO_PANEL;
else
panel_id = INNOLUX_720P_VIDEO_PANEL;
break;
case HW_PLATFORM_SUBTYPE_SKUI:
- panel_id = OTM8019A_FWVGA_VIDEO_PANEL;
+ /* qrd SKUIC */
+ if ((plat_hw_ver_major >> 4) == 0x1)
+ panel_id = HX8379A_FWVGA_VIDEO_PANEL;
+ else
+ panel_id = OTM8019A_FWVGA_VIDEO_PANEL;
break;
default:
dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index 44c3db3..644b750 100755
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -352,7 +352,7 @@
return ret;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
/*
* The PMIC regulators needed for display are enabled in SBL.
@@ -363,7 +363,7 @@
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(pbuf, buf_size);
+ return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
void target_display_init(const char *panel_name)
@@ -371,8 +371,10 @@
uint32_t panel_loop = 0;
uint32_t ret = 0;
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+ || (!strcmp(panel_name, SIM_VIDEO_PANEL))) {
+ dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
+ panel_name);
return;
}
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 7d985a3..fab0122 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -279,7 +279,7 @@
return NO_ERROR;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ldocounter = 0;
uint32_t pm8x41_ldo_base = 0x13F00;
@@ -382,7 +382,7 @@
buf_size -= LK_OVERRIDE_PANEL_LEN;
strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
} else {
- ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+ ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
return ret;
@@ -399,16 +399,16 @@
panel_name += strspn(panel_name, " ");
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+ || (!strcmp(panel_name, SIM_VIDEO_PANEL))
+ || (!strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL))) {
+ dprintf(INFO, "Selected panel: %s\nSkip panel configuration",
+ panel_name);
return;
- }
-
- if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+ } else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
dprintf(INFO, "%s: HDMI is primary\n", __func__);
return;
}
-
switch (hw_id) {
case HW_PLATFORM_LIQUID:
edp_panel_init(&(panel.panel_info));
diff --git a/target/msm8994/include/target/display.h b/target/msm8994/include/target/display.h
new file mode 100644
index 0000000..8449ee0
--- /dev/null
+++ b/target/msm8994/include/target/display.h
@@ -0,0 +1,112 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_DISPLAY_H
+#define _TARGET_DISPLAY_H
+
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
+
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 78, 3, 1, 0, 1
+};
+
+static struct gpio_pin lcd_reg_en = { /* boost regulator */
+ "pm8994_gpios", 14, 3, 1, 0, 1
+};
+
+static struct gpio_pin bkl_gpio = { /* lcd_bklt_reg_en */
+ "pmi8994_gpios", 2, 3, 1, 0, 1
+};
+
+static struct gpio_pin pwm_gpio = { /* pmi_mpp01, lpg = 0 */
+ "pmi8994_mpps", 1, 0, 1, 0, 1
+};
+/*---------------------------------------------------------------------------*/
+/* LDO configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+ { "vdd", 14, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+ { "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+ { "vdda", 2, 1, 1250000, 100000, 100, 0, 0, 0, 0},
+ { "vcca", 28, 1, 1000000, 10000, 100, 0, 0, 0, 0},
+};
+
+#define TOTAL_LDO_DEFINED 3
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0x77, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x00, 0x00, 0xb1, 0xff, 0x00, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x03, 0x05, 0x03, 0x00, 0x20, 0x07, 0x01
+};
+
+static const char panel_lane_config[] = {
+0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x88,
+0x02, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x01, 0x88,
+0x02, 0x00, 0x00, 0x40, 0x20, 0x00, 0x00, 0x01, 0x88,
+0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x88,
+0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x88
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x5f, 0x00, 0x00, 0x10
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+#define DISPLAY_CMDLINE_PREFIX " mdss_mdp.panel="
+
+#define MIPI_FB_ADDR 0x03400000
+
+#define MIPI_HSYNC_PULSE_WIDTH 16
+#define MIPI_HSYNC_BACK_PORCH_DCLK 32
+#define MIPI_HSYNC_FRONT_PORCH_DCLK 76
+
+#define MIPI_VSYNC_PULSE_WIDTH 2
+#define MIPI_VSYNC_BACK_PORCH_LINES 2
+#define MIPI_VSYNC_FRONT_PORCH_LINES 4
+
+#define PWM_BL_LPG_CHAN_ID 0
+
+#endif
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index cfd665f..4a3a5c2 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -298,6 +298,22 @@
/* This is filled from board.c */
}
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+ switch(board_hardware_id())
+ {
+ case HW_PLATFORM_SURF:
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_FLUID:
+ dprintf(SPEW, "Target_cont_splash=1\n");
+ return 1;
+ default:
+ dprintf(SPEW, "Target_cont_splash=0\n");
+ return 0;
+ }
+}
+
/* Detect the modem type */
void target_baseband_detect(struct board_data *board)
{
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
new file mode 100644
index 0000000..f0d7ba5
--- /dev/null
+++ b/target/msm8994/oem_panel.c
@@ -0,0 +1,226 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+
+#include "include/panel.h"
+#include "panel_display.h"
+
+/*---------------------------------------------------------------------------*/
+/* GCDB Panel Database */
+/*---------------------------------------------------------------------------*/
+#include "include/panel_sharp_wqxga_dualdsi_video.h"
+#include "include/panel_jdi_qhd_dualdsi_video.h"
+#include "include/panel_jdi_qhd_dualdsi_cmd.h"
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+enum {
+SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
+JDI_QHD_DUALDSI_VIDEO_PANEL,
+JDI_QHD_DUALDSI_CMD_PANEL,
+UNKNOWN_PANEL
+};
+
+/*
+ * The list of panels that are supported on this target.
+ * Any panel in this list can be selected using fastboot oem command.
+ */
+static struct panel_list supp_panels[] = {
+ {"sharp_wqxga_dualdsi_video", SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
+ {"jdi_qhd_dualdsi_video", JDI_QHD_DUALDSI_VIDEO_PANEL},
+ {"jdi_qhd_dualdsi_cmd", JDI_QHD_DUALDSI_CMD_PANEL},
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ /* OEM can keep there panel specific on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+int oem_panel_on()
+{
+ /* OEM can keep there panel specific on instructions in this
+ function */
+ if (panel_id == JDI_QHD_DUALDSI_CMD_PANEL) {
+ /* needs extra delay to avoid unexpected artifacts */
+ mdelay(JDI_QHD_DUALDSI_CMD_PANEL_ON_DELAY);
+
+ }
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /* OEM can keep there panel specific off instructions in this
+ function */
+ return NO_ERROR;
+}
+
+static bool init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ int pan_type;
+
+ phy_db->is_pll_20nm = 1;
+
+ switch (panel_id) {
+ case SHARP_WQXGA_DUALDSI_VIDEO_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 0;
+ panelstruct->paneldata = &sharp_wqxga_dualdsi_video_panel_data;
+ panelstruct->paneldata->panel_operating_mode = 11;
+ panelstruct->paneldata->panel_with_enable_gpio = 0;
+ panelstruct->panelres = &sharp_wqxga_dualdsi_video_panel_res;
+ panelstruct->color = &sharp_wqxga_dualdsi_video_color;
+ panelstruct->videopanel = &sharp_wqxga_dualdsi_video_video_panel;
+ panelstruct->commandpanel = &sharp_wqxga_dualdsi_video_command_panel;
+ panelstruct->state = &sharp_wqxga_dualdsi_video_state;
+ panelstruct->laneconfig = &sharp_wqxga_dualdsi_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &sharp_wqxga_dualdsi_video_timing_info;
+ panelstruct->panelresetseq
+ = &sharp_wqxga_dualdsi_video_reset_seq;
+ panelstruct->backlightinfo = &sharp_wqxga_dualdsi_video_backlight;
+ pinfo->mipi.panel_cmds
+ = sharp_wqxga_dualdsi_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = SHARP_WQXGA_DUALDSI_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ sharp_wqxga_dualdsi_video_timings, TIMING_SIZE);
+ break;
+ case JDI_QHD_DUALDSI_VIDEO_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 1;
+ panelstruct->paneldata = &jdi_qhd_dualdsi_video_panel_data;
+ panelstruct->panelres = &jdi_qhd_dualdsi_video_panel_res;
+ panelstruct->color = &jdi_qhd_dualdsi_video_color;
+ panelstruct->videopanel = &jdi_qhd_dualdsi_video_video_panel;
+ panelstruct->commandpanel = &jdi_qhd_dualdsi_video_command_panel;
+ panelstruct->state = &jdi_qhd_dualdsi_video_state;
+ panelstruct->laneconfig = &jdi_qhd_dualdsi_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_qhd_dualdsi_video_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_qhd_dualdsi_video_reset_seq;
+
+ /* force backlight to WLED */
+ panelstruct->backlightinfo = &jdi_qhd_dualdsi_video_backlight;
+ jdi_qhd_dualdsi_video_backlight.bl_interface_type = BL_WLED;
+
+ pinfo->mipi.panel_cmds
+ = jdi_qhd_dualdsi_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = JDI_QHD_DUALDSI_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_qhd_dualdsi_video_timings, TIMING_SIZE);
+ break;
+ case JDI_QHD_DUALDSI_CMD_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 1;
+ panelstruct->paneldata = &jdi_qhd_dualdsi_cmd_panel_data;
+ panelstruct->panelres = &jdi_qhd_dualdsi_cmd_panel_res;
+ panelstruct->color = &jdi_qhd_dualdsi_cmd_color;
+ panelstruct->videopanel = &jdi_qhd_dualdsi_cmd_video_panel;
+ panelstruct->commandpanel = &jdi_qhd_dualdsi_cmd_command_panel;
+ panelstruct->state = &jdi_qhd_dualdsi_cmd_state;
+ panelstruct->laneconfig = &jdi_qhd_dualdsi_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_qhd_dualdsi_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_qhd_dualdsi_cmd_reset_seq;
+
+ /* force backlight to WLED */
+ jdi_qhd_dualdsi_cmd_backlight.bl_interface_type = BL_WLED;
+ panelstruct->backlightinfo = &jdi_qhd_dualdsi_cmd_backlight;
+
+ pinfo->mipi.panel_cmds
+ = jdi_qhd_dualdsi_cmd_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = JDI_QHD_DUALDSI_CMD_ON_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_qhd_dualdsi_cmd_timings, TIMING_SIZE);
+ break;
+ default:
+ case UNKNOWN_PANEL:
+ pan_type = PANEL_TYPE_UNKNOWN;
+ break;
+ }
+ return pan_type;
+}
+
+bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ int32_t panel_override_id;
+
+ if (panel_name) {
+ panel_override_id = panel_name_to_id(supp_panels,
+ ARRAY_SIZE(supp_panels), panel_name);
+
+ if (panel_override_id < 0) {
+ dprintf(CRITICAL, "Not able to search the panel:%s\n",
+ panel_name + strspn(panel_name, " "));
+ } else if (panel_override_id < UNKNOWN_PANEL) {
+ /* panel override using fastboot oem command */
+ panel_id = panel_override_id;
+
+ dprintf(INFO, "OEM panel override:%s\n",
+ panel_name + strspn(panel_name, " "));
+ goto panel_init;
+ }
+ }
+
+ switch (hw_id) {
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_FLUID:
+ case HW_PLATFORM_SURF:
+ panel_id = SHARP_WQXGA_DUALDSI_VIDEO_PANEL;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n"
+ , hw_id);
+ return PANEL_TYPE_UNKNOWN;
+ }
+
+panel_init:
+ return init_panel_data(panelstruct, pinfo, phy_db);
+}
diff --git a/target/msm8994/rules.mk b/target/msm8994/rules.mk
index e098b17..509c91a 100644
--- a/target/msm8994/rules.mk
+++ b/target/msm8994/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8994
@@ -11,7 +12,7 @@
SCRATCH_ADDR := 0x10000000
-DEFINES += DISPLAY_SPLASH_SCREEN=0
+DEFINES += DISPLAY_SPLASH_SCREEN=1
DEFINES += DISPLAY_TYPE_MIPI=1
DEFINES += DISPLAY_TYPE_DSI6G=1
@@ -20,6 +21,7 @@
dev/pmic/pm8x41 \
dev/qpnp_wled \
lib/ptable \
+ dev/gcdb/display \
lib/libfdt
DEFINES += \
@@ -35,3 +37,5 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
new file mode 100644
index 0000000..43612bc
--- /dev/null
+++ b/target/msm8994/target_display.c
@@ -0,0 +1,326 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <smem.h>
+#include <err.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <pm8x41.h>
+#include <pm8x41_wled.h>
+#include <qpnp_wled.h>
+#include <board.h>
+#include <mdp5.h>
+#include <scm.h>
+#include <endian.h>
+#include <platform/gpio.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+#include <target/display.h>
+#include "include/panel.h"
+#include "include/display_resource.h"
+
+#define HFPLL_LDO_ID 12
+
+#define GPIO_STATE_LOW 0
+#define GPIO_STATE_HIGH 2
+#define RESET_GPIO_SEQ_LEN 3
+
+#define PWM_DUTY_US 13
+#define PWM_PERIOD_US 27
+#define PMIC_WLED_SLAVE_ID 3
+#define PMIC_MPP_SLAVE_ID 2
+
+static void dsi_pll_20nm_phy_init( uint32_t pll_base, int off)
+{
+ mdss_dsi_pll_20nm_sw_reset_st_machine(pll_base);
+
+ dmb();
+
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
+ writel(0x80, pll_base + off + 0x0174);
+
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
+ writel(0x00, pll_base + off + 0x0174);
+ udelay(5000);
+ /* Strength ctrl 0 */
+ writel(0x77, pll_base + off + 0x0184);
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
+ writel(0x7f, pll_base + off + 0x0170);
+
+ /* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */
+ writel(0x00, pll_base + off + 0x01d4);
+
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_2 */
+ writel(0x00, pll_base + off + 0x0178);
+}
+
+static uint32_t dsi_pll_20nm_enable_seq(uint32_t pll_base)
+{
+ uint32_t pll_locked;
+
+ /*
+ * PLL power up sequence.
+ * Add necessary delays recommeded by hardware.
+ */
+ writel(0x0D, pll_base + 0x9c); /* MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN */
+ writel(0x07, pll_base + 0x14); /* MMSS_DSI_PHY_PLL_PLL_CNTRL */
+ writel(0x00, pll_base + 0x2c); /* MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN */
+ udelay(500);
+
+ dsi_pll_20nm_phy_init(pll_base, 0x200); /* Ctrl 0 */
+ dmb();
+
+ pll_locked = mdss_dsi_pll_20nm_lock_status(pll_base);
+ if (!pll_locked)
+ dprintf(INFO, "%s: DSI PLL lock failed\n", __func__);
+ else
+ dprintf(INFO, "%s: DSI PLL lock Success\n", __func__);
+
+ return pll_locked;
+}
+
+static int msm8994_wled_backlight_ctrl(uint8_t enable)
+{
+ uint8_t slave_id = 3;
+
+ if (enable) {
+ pm8x41_wled_config_slave_id(slave_id);
+ qpnp_wled_enable_backlight(enable);
+ }
+ qpnp_ibb_enable(enable);
+ return NO_ERROR;
+}
+
+static int msm8994_pwm_backlight_ctrl(uint8_t enable)
+{
+ dprintf(INFO, "%s: NOt implemented\n", __func__);
+ return NO_ERROR;
+}
+
+void lcd_reg_enable(void)
+{
+ struct pm8x41_gpio gpio = {
+ .direction = PM_GPIO_DIR_OUT,
+ .function = PM_GPIO_FUNC_HIGH,
+ .vin_sel = 2, /* VIN_2 */
+ .output_buffer = PM_GPIO_OUT_CMOS,
+ .out_strength = PM_GPIO_OUT_DRIVE_MED,
+ };
+
+ pm8x41_gpio_config(lcd_reg_en.pin_id, &gpio);
+ pm8x41_gpio_set(lcd_reg_en.pin_id, 1);
+}
+
+void lcd_reg_disable(void)
+{
+ pm8x41_gpio_set(lcd_reg_en.pin_id, 0);
+}
+
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
+{
+ uint32_t ret = NO_ERROR;
+ struct pm8x41_mpp mpp;
+ int rc;
+
+ if (!bl) {
+ dprintf(CRITICAL, "backlight structure is not available\n");
+ return ERR_INVALID_ARGS;
+ }
+
+ switch (bl->bl_interface_type) {
+ case BL_WLED:
+ /* Enable MPP4 */
+ pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID);
+ mpp.base = PM8x41_MMP4_BASE;
+ mpp.vin = MPP_VIN2;
+ if (enable) {
+ pm_pwm_enable(false);
+ rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
+ if (rc < 0) {
+ mpp.mode = MPP_HIGH;
+ } else {
+ mpp.mode = MPP_DTEST1;
+ pm_pwm_enable(true);
+ }
+ pm8x41_config_output_mpp(&mpp);
+ pm8x41_enable_mpp(&mpp, MPP_ENABLE);
+ } else {
+ pm_pwm_enable(false);
+ pm8x41_enable_mpp(&mpp, MPP_DISABLE);
+ }
+ /* Need delay before power on regulators */
+ mdelay(20);
+ /* Enable WLED backlight control */
+ ret = msm8994_wled_backlight_ctrl(enable);
+ break;
+ case BL_PWM:
+ ret = msm8994_pwm_backlight_ctrl(enable);
+ break;
+ default:
+ dprintf(CRITICAL, "backlight type:%d not supported\n",
+ bl->bl_interface_type);
+ return ERR_NOT_SUPPORTED;
+ }
+
+ return ret;
+}
+
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ uint32_t ret;
+ struct mdss_dsi_pll_config *pll_data;
+ uint32_t dual_dsi = pinfo->mipi.dual_dsi;
+
+ pll_data = pinfo->mipi.dsi_pll_config;
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mmss_bus_clock_enable();
+ mdp_clock_enable();
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(0);
+ return ret;
+ }
+ mdss_dsi_auto_pll_20nm_config(DSI0_PLL_BASE,
+ MIPI_DSI0_BASE, pll_data);
+ dsi_pll_20nm_enable_seq(DSI0_PLL_BASE);
+ mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
+ pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
+ } else if(!target_cont_splash_screen()) {
+ /* Disable clocks if continuous splash off */
+ mmss_dsi_clock_disable(dual_dsi);
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return NO_ERROR;
+}
+
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
+{
+ uint32_t i = 0;
+
+ if (enable) {
+ gpio_tlmm_config(reset_gpio.pin_id, 0,
+ reset_gpio.pin_direction, reset_gpio.pin_pull,
+ reset_gpio.pin_strength, reset_gpio.pin_state);
+ /* reset */
+ for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
+ if (resetseq->pin_state[i] == GPIO_STATE_LOW)
+ gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
+ else
+ gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
+ mdelay(resetseq->sleep[i]);
+ }
+ } else {
+ gpio_set(reset_gpio.pin_id, 0);
+ }
+
+ return NO_ERROR;
+}
+
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ if (enable) {
+ regulator_enable(); /* L2, L12, L14, and L28 */
+ mdelay(10);
+ qpnp_ibb_enable(true); /* +5V and -5V */
+ mdelay(50);
+
+ if (pinfo->lcd_reg_en)
+ lcd_reg_enable();
+ } else {
+ if (pinfo->lcd_reg_en)
+ lcd_reg_disable();
+
+ regulator_disable();
+ }
+
+ return NO_ERROR;
+}
+
+int target_display_pre_on()
+{
+ writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0);
+ writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1);
+ writel(0xC0000CCD, MDP_CLK_CTRL0);
+ writel(0xD0000CCC, MDP_CLK_CTRL1);
+ writel(0x00CCCCCC, MDP_CLK_CTRL2);
+ writel(0x000000CC, MDP_CLK_CTRL6);
+ writel(0x0CCCC0C0, MDP_CLK_CTRL3);
+ writel(0xCCCCC0C0, MDP_CLK_CTRL4);
+ writel(0xCCCCC0C0, MDP_CLK_CTRL5);
+ writel(0x00CCC000, MDP_CLK_CTRL7);
+
+ writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF0);
+ writel(0x08000808, VBIF_VBIF_IN_RD_LIM_CONF1);
+ writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF2);
+ writel(0x00000808, VBIF_VBIF_IN_RD_LIM_CONF3);
+ writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF0);
+ writel(0x00100000, VBIF_VBIF_IN_WR_LIM_CONF1);
+ writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF2);
+ writel(0x00000000, VBIF_VBIF_IN_WR_LIM_CONF3);
+ writel(0x00013fff, VBIF_VBIF_ABIT_SHORT);
+ writel(0x000000A4, VBIF_VBIF_ABIT_SHORT_CONF);
+ writel(0x00003FFF, VBIF_VBIF_GATE_OFF_WRREQ_EN);
+ writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
+
+ return NO_ERROR;
+}
+
+bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
+{
+ int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
+ bool ret = true;
+
+ ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
+
+ return ret;
+}
+
+void target_display_init(const char *panel_name)
+{
+ if (gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR))
+ msm_display_off();
+}
+
+void target_display_shutdown(void)
+{
+ gcdb_display_shutdown();
+}
diff --git a/target/target_display.c b/target/target_display.c
index bac8a52..a4e15e2 100644
--- a/target/target_display.c
+++ b/target/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -62,6 +62,10 @@
{
return 0;
}
+__WEAK int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ return 0;
+}
__WEAK void target_edp_panel_init(struct msm_panel_info *pinfo)
{
@@ -87,3 +91,17 @@
{
return 0;
}
+
+__WEAK int target_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ return 0;
+}
+
+__WEAK int target_hdmi_regulator_ctrl(bool enable)
+{
+ return 0;
+}
+__WEAK int mdss_hdmi_init(void)
+{
+ return 0;
+}