platform: thulium: Update debug uart instance.
Update debug UART instace as per the HW document update.
Change-Id: Ia5eb455bfc3b9a7fff9309164a0492574b82a9df
diff --git a/platform/thulium/include/platform/iomap.h b/platform/thulium/include/platform/iomap.h
index a11db96..8108fd6 100644
--- a/platform/thulium/include/platform/iomap.h
+++ b/platform/thulium/include/platform/iomap.h
@@ -87,13 +87,13 @@
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
/* UART Clocks */
-#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x17004)
-#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x1C004)
-#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x1C00C)
-#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x1C010)
-#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x1C014)
-#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x1C018)
-#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x1C01C)
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x29004)
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29008)
+#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C)
+#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010)
+#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014)
+#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0x29018)
+#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0x2901C)
/* USB3 clocks */
#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
diff --git a/platform/thulium/thulium-clock.c b/platform/thulium/thulium-clock.c
index b02bec4..ae1d0de 100644
--- a/platform/thulium/thulium-clock.c
+++ b/platform/thulium/thulium-clock.c
@@ -156,31 +156,31 @@
F_END
};
-static struct rcg_clk blsp1_uart2_apps_clk_src =
+static struct rcg_clk blsp2_uart2_apps_clk_src =
{
- .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+ .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "blsp1_uart2_apps_clk",
+ .dbg_name = "blsp2_uart2_apps_clk",
.ops = &clk_ops_rcg_mnd,
},
};
-static struct branch_clk gcc_blsp1_uart2_apps_clk =
+static struct branch_clk gcc_blsp2_uart2_apps_clk =
{
- .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
+ .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
+ .parent = &blsp2_uart2_apps_clk_src.c,
.c = {
- .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .dbg_name = "gcc_blsp2_uart2_apps_clk",
.ops = &clk_ops_branch,
},
};
@@ -398,8 +398,8 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
- CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
- CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+ CLK_LOOKUP("uart8_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart8_core_clk", gcc_blsp2_uart2_apps_clk.c),
/* USB30 clocks */
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
diff --git a/target/thulium/init.c b/target/thulium/init.c
index c1b13bb..50e48d9 100644
--- a/target/thulium/init.c
+++ b/target/thulium/init.c
@@ -75,7 +75,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(2, 0, BLSP1_UART1_BASE);
+ uart_dm_init(8, 0, BLSP2_UART1_BASE);
#endif
}