commit 3640a0a8fc6f35b90d40abbfa2dd86e09a28af86
author Ajay Dudani <adudani@codeaurora.org> Mon Sep 27 10:29:55 2010 -0700
committer Ajay Dudani <adudani@codeaurora.org> Mon Sep 27 10:29:55 2010 -0700
tree cf2d26be537c5e787e1e93573327ddac4d5a1640
parent 8412104f002f9b234b151d30b8eb1083fb6c4576

[msm7630] Initialize CCPR register for L1/L2 cache coherency policy

Change-Id: I8921c3fd59c5e26d7dbc81d0fca6d6d17b5b3135

platform/msm7x30/arch_init.S

diff --git a/platform/msm7x30/arch_init.S b/platform/msm7x30/arch_init.S
index 8933bb1..e0a0053 100644
--- a/platform/msm7x30/arch_init.S
+++ b/platform/msm7x30/arch_init.S
@@ -416,6 +416,12 @@
         DSB
         ISB
 
+        //; Setup CCPR - Cache Coherency Policy Register
+        //; setup CCPR[L1ISHP, L2ISHP] both to 0b00 (no forcing)
+        //; setup CCPR[L1OSHP, L2OSHP] both to 0b10 (force non-cacheable)
+        MOVW   r2, #0x88
+        MCR    p15, 0, r2, c10, c4, 2
+
         //;-------------------------------------------------------------------
         //; There are a number of registers that must be set prior to enabling
         //; the MMU. The DCAR is one of these registers. We are setting