msm8974: usb30 clock and irq

Adds support for usb 3.0 clocks and irq

Change-Id: I776a8ec54d33c889500c6f8bc8d0d7d5572d5569
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index 6131e61..ba3a1ad 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -502,3 +502,25 @@
 	clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
 
 }
+
+/* enables usb30 interface and master clocks */
+void clock_usb30_init(void)
+{
+	int ret;
+
+	/* interface clock */
+	ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* master clock */
+	ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index c96763a..04d620c 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -103,5 +103,6 @@
 void edp_clk_enable(void);
 void clock_ce_enable(uint8_t instance);
 void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
 
 #endif
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index b3edca9..f8143dd 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -85,10 +85,32 @@
 #define BLSP1_UART5_BASE            (PERIPH_SS_BASE + 0x00122000)
 #define MSM_USB_BASE                (PERIPH_SS_BASE + 0x00255000)
 
+#define MSM_USB30_BASE               0xF9200000
+#define MSM_USB30_QSCRATCH_BASE      0xF92F8800
+
 #define CLK_CTL_BASE                0xFC400000
 
 #define GCC_WDOG_DEBUG              (CLK_CTL_BASE +  0x00001780)
 
+/* USB 3.0 clocks */
+#define SYS_NOC_USB3_AXI_CBCR       (CLK_CTL_BASE + 0x0108)
+
+#define GCC_USB_30_BCR               0xFC4003C0
+#define GCC_USB_30_MISC              0xFC4003C4
+
+#define GCC_USB30_MASTER_CBCR        0xFC4003C8
+#define GCC_USB30_SLEEP_CBCR         0xFC4003CC
+#define GCC_USB30_MOCK_UTMI_CBCR     0xFC4003D0
+
+#define GCC_USB30_MASTER_CMD_RCGR    0xFC4003D4
+#define GCC_USB30_MASTER_CFG_RCGR    0xFC4003D8
+#define GCC_USB30_MASTER_M           0xFC4003DC
+#define GCC_USB30_MASTER_N           0xFC4003E0
+#define GCC_USB30_MASTER_D           0xFC4003E4
+
+#define GCC_USB3_PHY_BCR             0xFC4003FC
+
+
 #define USB_HS_BCR                  (CLK_CTL_BASE + 0x480)
 
 #define SPMI_BASE                   0xFC4C0000
diff --git a/platform/msm8974/include/platform/irqs.h b/platform/msm8974/include/platform/irqs.h
index e9b2d06..c0637d0 100644
--- a/platform/msm8974/include/platform/irqs.h
+++ b/platform/msm8974/include/platform/irqs.h
@@ -45,6 +45,7 @@
 
 #define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP      (GIC_SPI_START + 8)
 
+#define USB30_EE1_IRQ                          (GIC_SPI_START + 131)
 #define USB1_HS_BAM_IRQ                        (GIC_SPI_START + 135)
 #define USB1_HS_IRQ                            (GIC_SPI_START + 134)
 #define USB2_IRQ                               (GIC_SPI_START + 141)
diff --git a/platform/msm8974/msm8974-clock.c b/platform/msm8974/msm8974-clock.c
index 991fe17..a646916 100644
--- a/platform/msm8974/msm8974-clock.c
+++ b/platform/msm8974/msm8974-clock.c
@@ -680,6 +680,54 @@
 	},
 };
 
+/* USB 3.0 Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
+{
+	F(125000000, gpll0, 1, 5, 24),
+	F_END
+};
+
+static struct rcg_clk usb30_master_clk_src =
+{
+	.cmd_reg      = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR,
+	.m_reg        = (uint32_t *) GCC_USB30_MASTER_M,
+	.n_reg        = (uint32_t *) GCC_USB30_MASTER_N,
+	.d_reg        = (uint32_t *) GCC_USB30_MASTER_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_usb30_master_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "usb30_master_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+
+static struct branch_clk gcc_usb30_master_clk =
+{
+	.cbcr_reg     = (uint32_t *) GCC_USB30_MASTER_CBCR,
+	.parent       = &usb30_master_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_usb30_master_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sys_noc_usb30_axi_clk =
+{
+	.cbcr_reg     = (uint32_t *) SYS_NOC_USB3_AXI_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sys_noc_usb3_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
 /* Clock lookup table */
 static struct clk_lookup msm_clocks_8974[] =
 {
@@ -722,6 +770,10 @@
 
 	CLK_LOOKUP("edp_pixel_clk",        mdss_edppixel_clk.c),
 	CLK_LOOKUP("edp_link_clk",         mdss_edplink_clk.c),
+
+	/* USB 3.0 */
+	CLK_LOOKUP("usb30_iface_clk",  gcc_sys_noc_usb30_axi_clk.c),
+	CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
 };