Merge "msm8974: Add debug prints before & after display init"
diff --git a/platform/msm8226/acpuclock.c b/platform/msm8226/acpuclock.c
index dc6df81..f1b3d41 100644
--- a/platform/msm8226/acpuclock.c
+++ b/platform/msm8226/acpuclock.c
@@ -38,56 +38,140 @@
void hsusb_clock_init(void)
{
+ int ret;
+ struct clk *iclk, *cclk;
+
+ ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ mdelay(20);
+
+ iclk = clk_get("usb_iface_clk");
+ cclk = clk_get("usb_core_clk");
+
+ /* Disable USB all clock init */
+ writel(0, USB_BOOT_CLOCK_CTL);
+
+ clk_disable(iclk);
+ clk_disable(cclk);
+
+ mdelay(20);
+
+ /* Start the block reset for usb */
+ writel(1, USB_HS_BCR);
+
+ mdelay(20);
+
+ /* Take usb block out of reset */
+ writel(0, USB_HS_BCR);
+
+ mdelay(20);
+
+ ret = clk_enable(iclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_enable(cclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
}
void clock_init_mmc(uint32_t interface)
{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
+ int ret;
uint32_t reg;
+ char clk_name[64];
+
+ snprintf(clk_name, 64, "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
reg = 0;
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
writel(reg, MMC_BOOT_MCI_CLK);
+
+ /* Wait for the MMC_BOOT_MCI_CLK write to go through. */
+ mmc_mclk_reg_wr_delay();
+
+ /* Wait 1 ms to provide the free running SD CLK to the card. */
+ mdelay(1);
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+
+ ret = clk_get_set_enable("uart3_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart3_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("uart3_core_clk", 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart3_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
-/* Function to asynchronously reset CE.
- * Function assumes that all the CE clocks are off.
- */
-static void ce_async_reset(uint8_t instance)
-{
-}
-
-static void clock_ce_enable(uint8_t instance)
-{
-}
-
-static void clock_ce_disable(uint8_t instance)
-{
-}
-
-void clock_config_ce(uint8_t instance)
-{
- /* Need to enable the clock before disabling since the clk_disable()
- * has a check to default to nop when the clk_enable() is not called
- * on that particular clock.
- */
- clock_ce_enable(instance);
-
- clock_ce_disable(instance);
-
- ce_async_reset(instance);
-
- clock_ce_enable(instance);
-}
diff --git a/platform/msm8226/gpio.c b/platform/msm8226/gpio.c
index b19643c..b869367 100644
--- a/platform/msm8226/gpio.c
+++ b/platform/msm8226/gpio.c
@@ -53,11 +53,12 @@
/* Configure gpio for blsp uart 2 */
void gpio_config_uart_dm(uint8_t id)
{
- /* configure rx gpio */
- gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+ /* Configure GPIOs for BLSP1 UART3. */
+ /* configure rx gpio */
+ gpio_tlmm_config(9, 2, GPIO_INPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
- /* configure tx gpio */
- gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ /* configure tx gpio */
+ gpio_tlmm_config(8, 2, GPIO_OUTPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
}
diff --git a/platform/msm8226/include/platform/clock.h b/platform/msm8226/include/platform/clock.h
index 118428a..b549dd1 100644
--- a/platform/msm8226/include/platform/clock.h
+++ b/platform/msm8226/include/platform/clock.h
@@ -40,6 +40,5 @@
void clock_config_mmc(uint32_t interface, uint32_t freq);
void clock_config_uart_dm(uint8_t id);
void hsusb_clock_init(void);
-void clock_config_ce(uint8_t instance);
#endif
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index 9d47d11..7f3d1a1 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -88,15 +88,8 @@
#define MPM2_MPM_CTRL_BASE 0xFC4A1000
#define MPM2_MPM_PS_HOLD 0xFC4AB000
-/* CE 2 */
-#define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080)
-#define GCC_CE2_CMD_RCGR (CLK_CTL_BASE + 0x1090)
-#define GCC_CE2_CFG_RCGR (CLK_CTL_BASE + 0x1094)
-#define GCC_CE2_CBCR (CLK_CTL_BASE + 0x1084)
-#define GCC_CE2_AXI_CBCR (CLK_CTL_BASE + 0x1088)
-#define GCC_CE2_AHB_CBCR (CLK_CTL_BASE + 0x108C)
-
/* GPLL */
+#define GPLL0_MODE CLK_CTL_BASE
#define GPLL0_STATUS (CLK_CTL_BASE + 0x001C)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
@@ -114,12 +107,12 @@
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
-#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
-#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
-#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
-#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714)
-#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718)
-#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C)
+#define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x784)
+#define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x78C)
+#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x790)
+#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x794)
+#define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x798)
+#define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x79C)
/* USB */
#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
diff --git a/platform/msm8226/msm8226-clock.c b/platform/msm8226/msm8226-clock.c
new file mode 100644
index 0000000..9f5818b
--- /dev/null
+++ b/platform/msm8226/msm8226-clock.c
@@ -0,0 +1,289 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val 0
+#define gpll0_source_val 1
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+ .enable = clock_lib2_branch_clk_enable,
+ .disable = clock_lib2_branch_clk_disable,
+ .set_rate = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+ .enable = cxo_clk_enable,
+ .disable = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 600000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F(200000000, gpll0, 3, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 96, 15625),
+ F( 7372800, gpll0, 1, 192, 15625),
+ F(14745600, gpll0, 1, 384, 15625),
+ F(16000000, gpll0, 5, 2, 15),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 5, 1, 5),
+ F(32000000, gpll0, 1, 4, 75),
+ F(40000000, gpll0, 15, 0, 0),
+ F(46400000, gpll0, 1, 29, 375),
+ F(48000000, gpll0, 12.5, 0, 0),
+ F(51200000, gpll0, 1, 32, 375),
+ F(56000000, gpll0, 1, 7, 75),
+ F(58982400, gpll0, 1, 1536, 15625),
+ F(60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk blsp1_uart3_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART3_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART3_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART3_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart3_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart3_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR,
+ .parent = &blsp1_uart3_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart3_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(17),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+ F(75000000, gpll0, 8, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+ .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb_hs_system_clk",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
+ .parent = &usb_hs_system_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_system_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_8226[] =
+{
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+
+ CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c),
+
+ CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
+ CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+};
+
+void platform_clock_init(void)
+{
+ clk_init(msm_clocks_8226, ARRAY_SIZE(msm_clocks_8226));
+}
diff --git a/platform/msm8226/platform.c b/platform/msm8226/platform.c
index 819dea0..1be05ed 100644
--- a/platform/msm8226/platform.c
+++ b/platform/msm8226/platform.c
@@ -29,11 +29,13 @@
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
+#include <platform/clock.h>
#include <qgic.h>
#include <qtimer.h>
void platform_early_init(void)
{
+ platform_clock_init();
qgic_init();
qtimer_init();
}
diff --git a/platform/msm8226/rules.mk b/platform/msm8226/rules.mk
index 30d51bb..6645153 100644
--- a/platform/msm8226/rules.mk
+++ b/platform/msm8226/rules.mk
@@ -18,6 +18,7 @@
OBJS += \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/msm8226-clock.o \
$(LOCAL_DIR)/gpio.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 40f1f30..04caeb1 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -171,6 +171,8 @@
/* Get block size. */
blk_size = flash_block_size();
+ dprintf(INFO, "Add %d flash partitions to dt: start\n", ptable->count);
+
/* Need to add partitions in reverse order since libfdt adds
* new nodes on the top.
* Kernel looks to mount the partitions in the order specified in
@@ -245,6 +247,7 @@
}
dev_tree_add_ptable_nodes_err:
+ dprintf(INFO, "Add %d flash partitions to dt: done\n", ptable->count);
free(ptn_name_array);
return dt_ret;
}
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index fb14720..1a34a0c 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
- * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -1553,7 +1553,7 @@
{
if (count == 0)
{
- dprintf(INFO, "flash_read_image: success (%d errors)\n",
+ dprintf(SPEW, "flash_read_image: success (%d errors)\n",
errors);
return NANDC_RESULT_SUCCESS;
}
diff --git a/target/copper/target_display.c b/target/copper/target_display.c
index 29268c6..1f09bb1 100644
--- a/target/copper/target_display.c
+++ b/target/copper/target_display.c
@@ -136,7 +136,6 @@
dprintf(INFO, "display_init(),target_id=%d.\n", hw_id);
switch (hw_id) {
- case HW_PLATFORM_SURF:
case HW_PLATFORM_MTP:
case HW_PLATFORM_FLUID:
mipi_toshiba_video_720p_init(&(panel.panel_info));
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index bcf6100..758df28 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -45,7 +45,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(1, 0, BLSP1_UART1_BASE);
+ uart_dm_init(1, 0, BLSP1_UART2_BASE);
#endif
}