Merge "msm_shared: add mdp5 edp configuration"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index a006ab1..e1a4274 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -102,6 +102,7 @@
static const char *loglevel = " quiet";
static const char *battchg_pause = " androidboot.mode=charger";
static const char *auth_kernel = " androidboot.authorized_kernel=true";
+static const char *secondary_gpt_enable = " gpt";
static const char *baseband_apq = " androidboot.baseband=apq";
static const char *baseband_msm = " androidboot.baseband=msm";
@@ -200,6 +201,7 @@
int have_cmdline = 0;
unsigned char *cmdline_final = NULL;
int pause_at_bootup = 0;
+ bool gpt_exists = partition_gpt_exists();
if (cmdline && cmdline[0]) {
cmdline_len = strlen(cmdline);
@@ -212,6 +214,9 @@
cmdline_len += strlen(usb_sn_cmdline);
cmdline_len += strlen(sn_buf);
+ if (boot_into_recovery && gpt_exists)
+ cmdline_len += strlen(secondary_gpt_enable);
+
if (boot_into_ffbm) {
cmdline_len += strlen(androidboot_mode);
cmdline_len += strlen(ffbm_mode_string);
@@ -293,6 +298,12 @@
have_cmdline = 1;
while ((*dst++ = *src++));
+ if (boot_into_recovery && gpt_exists) {
+ src = secondary_gpt_enable;
+ if (have_cmdline) --dst;
+ while ((*dst++ = *src++));
+ }
+
if (boot_into_ffbm) {
src = androidboot_mode;
if (have_cmdline) --dst;
@@ -765,7 +776,8 @@
*/
void *dtb;
dtb = dev_tree_appended((void*) hdr->kernel_addr,
- (void *)hdr->tags_addr, hdr->kernel_size);
+ hdr->kernel_size,
+ (void *)hdr->tags_addr);
if (!dtb) {
dprintf(CRITICAL, "ERROR: Appended Device Tree Blob not found\n");
return -1;
@@ -856,7 +868,8 @@
*/
void *dtb;
dtb = dev_tree_appended((void*) hdr->kernel_addr,
- (void *)hdr->tags_addr, hdr->kernel_size);
+ kernel_actual,
+ (void *)hdr->tags_addr);
if (!dtb) {
dprintf(CRITICAL, "ERROR: Appended Device Tree Blob not found\n");
return -1;
@@ -1421,7 +1434,8 @@
*/
if (!dtb_copied) {
void *dtb;
- dtb = dev_tree_appended((void *)hdr->kernel_addr, (void *)hdr->tags_addr, hdr->kernel_size);
+ dtb = dev_tree_appended((void *)hdr->kernel_addr, hdr->kernel_size,
+ (void *)hdr->tags_addr);
if (!dtb) {
fastboot_fail("dtb not found");
return;
diff --git a/dev/gcdb/display/include/panel_hx8394a_720p_video.h b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
new file mode 100644
index 0000000..fd62f1e
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
@@ -0,0 +1,277 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_HX8394A_720P_VIDEO_H_
+
+#define _PANEL_HX8394A_720P_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config hx8394a_720p_video_panel_data = {
+ "hx8394a 720p video mode dsi panel", "mdss_dsi0", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 424000000, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8394a_720p_video_panel_res = {
+ 720, 1280, 79, 59, 60, 0, 7, 10, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8394a_720p_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char hx8394a_720p_video_on_cmd0[] = {
+0x04, 0x00, 0x39, 0xC0,
+0xb9, 0xff, 0x83, 0x94,
+ };
+
+
+static char hx8394a_720p_video_on_cmd1[] = {
+0x05, 0x00, 0x39, 0xC0,
+0xc7, 0x00, 0x10, 0x00,
+0x10, 0xFF, 0xFF, 0xFF, };
+
+
+static char hx8394a_720p_video_on_cmd2[] = {
+0x02, 0x00, 0x39, 0xC0,
+0xbc, 0x07, 0xFF, 0xFF, };
+
+
+static char hx8394a_720p_video_on_cmd3[] = {
+0x02, 0x00, 0x39, 0xC0,
+0xba, 0x13, 0xFF, 0xFF, };
+
+
+static char hx8394a_720p_video_on_cmd4[] = {
+0x10, 0x00, 0x39, 0xC0,
+0xb1, 0x01, 0x00, 0x07,
+0x83, 0x01, 0x12, 0x0f,
+0x32, 0x38, 0x29, 0x29,
+0x50, 0x02, 0x00, 0x00,
+ };
+
+
+static char hx8394a_720p_video_on_cmd5[] = {
+0x07, 0x00, 0x39, 0xC0,
+0xb2, 0x00, 0xc8, 0x09,
+0x05, 0x00, 0x71, 0xFF, };
+
+
+static char hx8394a_720p_video_on_cmd6[] = {
+0x02, 0x00, 0x39, 0xC0,
+0xcc, 0x05, 0xFF, 0xFF, };
+
+
+static char hx8394a_720p_video_on_cmd7[] = {
+0x00, 0x00, 0x05, 0x80 };
+
+
+static char hx8394a_720p_video_on_cmd8[] = {
+0x35, 0x00, 0x39, 0xC0,
+0xd5, 0x00, 0x00, 0x00,
+0x00, 0x0a, 0x00, 0x01,
+0x00, 0x00, 0x00, 0x33,
+0x00, 0x23, 0x45, 0x67,
+0x01, 0x01, 0x23, 0x88,
+0x88, 0x88, 0x88, 0x88,
+0x88, 0x88, 0x99, 0x99,
+0x99, 0x88, 0x88, 0x99,
+0x88, 0x54, 0x32, 0x10,
+0x76, 0x32, 0x10, 0x88,
+0x88, 0x88, 0x88, 0x88,
+0x88, 0x88, 0x99, 0x99,
+0x99, 0x88, 0x88, 0x88,
+0x99, 0xFF, 0xFF, 0xFF, };
+
+
+static char hx8394a_720p_video_on_cmd9[] = {
+0x17, 0x00, 0x39, 0xC0,
+0xb4, 0x80, 0x08, 0x32,
+0x10, 0x00, 0x32, 0x15,
+0x08, 0x32, 0x12, 0x20,
+0x33, 0x05, 0x4c, 0x05,
+0x37, 0x05, 0x3f, 0x1e,
+0x5f, 0x5f, 0x06, 0xFF, };
+
+
+static char hx8394a_720p_video_on_cmd10[] = {
+0x02, 0x00, 0x39, 0xC0,
+0xb6, 0x00, 0xFF, 0xFF, };
+
+
+static char hx8394a_720p_video_on_cmd11[] = {
+0x23, 0x00, 0x39, 0xC0,
+0xe0, 0x01, 0x05, 0x07,
+0x25, 0x35, 0x3f, 0x0b,
+0x32, 0x04, 0x09, 0x0e,
+0x10, 0x13, 0x10, 0x14,
+0x16, 0x1b, 0x01, 0x05,
+0x07, 0x25, 0x35, 0x3f,
+0x0b, 0x32, 0x04, 0x09,
+0x0e, 0x10, 0x13, 0x10,
+0x14, 0x16, 0x1b, 0xFF, };
+
+
+static char hx8394a_720p_video_on_cmd12[] = {
+0x00, 0x00, 0x05, 0x80 };
+
+
+static char hx8394a_720p_video_on_cmd13[] = {
+0x04, 0x00, 0x39, 0xC0,
+0xbf, 0x06, 0x00, 0x10,
+ };
+
+
+static char hx8394a_720p_video_on_cmd14[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char hx8394a_720p_video_on_cmd15[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd hx8394a_720p_video_on_command[] = {
+{ 0x8 , hx8394a_720p_video_on_cmd0},
+{ 0xc , hx8394a_720p_video_on_cmd1},
+{ 0x8 , hx8394a_720p_video_on_cmd2},
+{ 0x8 , hx8394a_720p_video_on_cmd3},
+{ 0x14 , hx8394a_720p_video_on_cmd4},
+{ 0xc , hx8394a_720p_video_on_cmd5},
+{ 0x8 , hx8394a_720p_video_on_cmd6},
+{ 0x4 , hx8394a_720p_video_on_cmd7},
+{ 0x3c , hx8394a_720p_video_on_cmd8},
+{ 0x1c , hx8394a_720p_video_on_cmd9},
+{ 0x8 , hx8394a_720p_video_on_cmd10},
+{ 0x28 , hx8394a_720p_video_on_cmd11},
+{ 0x4 , hx8394a_720p_video_on_cmd12},
+{ 0x8 , hx8394a_720p_video_on_cmd13},
+{ 0x4 , hx8394a_720p_video_on_cmd14},
+{ 0x4 , hx8394a_720p_video_on_cmd15}
+};
+#define HX8394A_720P_VIDEO_ON_COMMAND 16
+
+
+static char hx8394a_720p_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char hx8394a_720p_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd hx8394a_720p_video_off_command[] = {
+{ 0x4 , hx8394a_720p_videooff_cmd0},
+{ 0x4 , hx8394a_720p_videooff_cmd1}
+};
+#define HX8394A_720P_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state hx8394a_720p_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info hx8394a_720p_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info hx8394a_720p_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration hx8394a_720p_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t hx8394a_720p_video_timings[] = {
+ 0x8d, 0x24, 0x19, 0x00, 0x34, 0x34, 0x1d, 0x26, 0x2a, 0x03, 0x04, 0x00
+};
+
+
+
+static struct mipi_dsi_cmd hx8394a_720p_video_rotation[] = {
+
+};
+#define HX8394A_720P_VIDEO_ROTATION 0
+
+
+static struct panel_timing hx8394a_720p_video_timing_info = {
+ 0, 4, 0x1f, 0x2d
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight hx8394a_720p_video_backlight = {
+ 1, 1, 4095, 100, 1, "bl_ctrl_wled"
+};
+
+
+#endif /*_HX8394A_720P_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35521_720p_video.h b/dev/gcdb/display/include/panel_nt35521_720p_video.h
new file mode 100644
index 0000000..e9e4104
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35521_720p_video.h
@@ -0,0 +1,1474 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_NT35521_720P_VIDEO_H_
+
+#define _PANEL_NT35521_720P_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config nt35521_720p_video_panel_data = {
+ "nt35521 720p video mode dsi panel", "mdss_dsi0", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 424000000, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35521_720p_video_panel_res = {
+ 720, 1280, 44, 55, 11, 0, 14, 15, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35521_720p_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char nt35521_720p_video_on_cmd0[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xF0, 0x55, 0xAA, 0x52,
+0x08, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd1[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB1, 0x68, 0x21, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd2[] = {
+0xB5, 0xC8, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd3[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xB6, 0x0F, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd4[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xB8, 0x00, 0x00, 0x0A,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd5[] = {
+0xB9, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd6[] = {
+0xBA, 0x02, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd7[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBB, 0x63, 0x63, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd8[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBC, 0x00, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd9[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xBD, 0x02, 0x7F, 0x0D,
+0x0B, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd10[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xCC, 0x41, 0x36, 0x87,
+0x54, 0x46, 0x65, 0x10,
+0x12, 0x14, 0x10, 0x12,
+0x14, 0x40, 0x08, 0x15,
+0x05, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd11[] = {
+0xD0, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd12[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xD1, 0x00, 0x04, 0x08,
+0x0C, 0x10, 0x14, 0x18,
+0x1C, 0x20, 0x24, 0x28,
+0x2C, 0x30, 0x34, 0x38,
+0x3C, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd13[] = {
+0xD3, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd14[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD6, 0x44, 0x44, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd15[] = {
+0x0D, 0x00, 0x29, 0xC0,
+0xD7, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd16[] = {
+0x0E, 0x00, 0x29, 0xC0,
+0xD8, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd17[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD9, 0x00, 0x28, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd18[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xE5, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd19[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xE6, 0xF3, 0xEC, 0xE7,
+0xDF, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd20[] = {
+0x0B, 0x00, 0x29, 0xC0,
+0xE7, 0xF3, 0xD9, 0xCC,
+0xCD, 0xB3, 0xA6, 0x99,
+0x99, 0x99, 0x95, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd21[] = {
+0x0B, 0x00, 0x29, 0xC0,
+0xE8, 0xF3, 0xD9, 0xCC,
+0xCD, 0xB3, 0xA6, 0x99,
+0x99, 0x99, 0x95, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd22[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xE9, 0x00, 0x04, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd23[] = {
+0xEA, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd24[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xEE, 0x87, 0x78, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd25[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xEF, 0x07, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd26[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xF0, 0x55, 0xAA, 0x52,
+0x08, 0x01, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd27[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB0, 0x0D, 0x0D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd28[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB1, 0x0D, 0x0D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd29[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB3, 0x2D, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd30[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB4, 0x19, 0x19, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd31[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB5, 0x06, 0x06, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd32[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB6, 0x05, 0x05, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd33[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB7, 0x05, 0x05, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd34[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB8, 0x05, 0x05, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd35[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB9, 0x44, 0x44, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd36[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBA, 0x36, 0x36, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd37[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBC, 0x50, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd38[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBD, 0x50, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd39[] = {
+0xBE, 0x39, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd40[] = {
+0xBF, 0x39, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd41[] = {
+0xC0, 0x0C, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd42[] = {
+0xC1, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd43[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC2, 0x19, 0x19, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd44[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC3, 0x0A, 0x0A, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd45[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC4, 0x23, 0x23, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd46[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xC7, 0x00, 0x80, 0x00,
+ };
+
+
+static char nt35521_720p_video_on_cmd47[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xC9, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd48[] = {
+0xCA, 0x01, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd49[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCB, 0x0B, 0x53, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd50[] = {
+0xCC, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd51[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xCD, 0x0B, 0x52, 0x53,
+ };
+
+
+static char nt35521_720p_video_on_cmd52[] = {
+0xCE, 0x44, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd53[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xCF, 0x00, 0x50, 0x50,
+ };
+
+
+static char nt35521_720p_video_on_cmd54[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD0, 0x50, 0x50, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd55[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD1, 0x50, 0x50, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd56[] = {
+0xD2, 0x39, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd57[] = {
+0xD3, 0x39, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd58[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xF0, 0x55, 0xAA, 0x52,
+0x08, 0x02, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd59[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xB0, 0x00, 0xAC, 0x00,
+0xBA, 0x00, 0xD9, 0x00,
+0xED, 0x01, 0x01, 0x01,
+0x1E, 0x01, 0x3A, 0x01,
+0x62, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd60[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xB1, 0x01, 0x85, 0x01,
+0xB8, 0x01, 0xE4, 0x02,
+0x27, 0x02, 0x5B, 0x02,
+0x5D, 0x02, 0x8C, 0x02,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd61[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xB2, 0x02, 0xDF, 0x03,
+0x0C, 0x03, 0x2A, 0x03,
+0x51, 0x03, 0x6D, 0x03,
+0x8D, 0x03, 0xA4, 0x03,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd62[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xB3, 0x03, 0xCC, 0x03,
+0xCC, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd63[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xB4, 0x00, 0xAC, 0x00,
+0xBA, 0x00, 0xD9, 0x00,
+0xED, 0x01, 0x01, 0x01,
+0x1E, 0x01, 0x3A, 0x01,
+0x62, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd64[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xB5, 0x01, 0x85, 0x01,
+0xB8, 0x01, 0xE4, 0x02,
+0x27, 0x02, 0x5B, 0x02,
+0x5D, 0x02, 0x8C, 0x02,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd65[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xB6, 0x02, 0xDF, 0x03,
+0x0C, 0x03, 0x2A, 0x03,
+0x51, 0x03, 0x6D, 0x03,
+0x8D, 0x03, 0xA4, 0x03,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd66[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xB7, 0x03, 0xCC, 0x03,
+0xCC, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd67[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xB8, 0x00, 0xAC, 0x00,
+0xBA, 0x00, 0xD9, 0x00,
+0xED, 0x01, 0x01, 0x01,
+0x1E, 0x01, 0x3A, 0x01,
+0x62, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd68[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xB9, 0x01, 0x85, 0x01,
+0xB8, 0x01, 0xE4, 0x02,
+0x27, 0x02, 0x5B, 0x02,
+0x5D, 0x02, 0x8C, 0x02,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd69[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xBA, 0x02, 0xDF, 0x03,
+0x0C, 0x03, 0x2A, 0x03,
+0x51, 0x03, 0x6D, 0x03,
+0x8D, 0x03, 0xA4, 0x03,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd70[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xBB, 0x03, 0xCC, 0x03,
+0xCC, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd71[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xBC, 0x00, 0xAC, 0x00,
+0xBA, 0x00, 0xD9, 0x00,
+0xED, 0x01, 0x01, 0x01,
+0x1E, 0x01, 0x3A, 0x01,
+0x62, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd72[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xBD, 0x01, 0x85, 0x01,
+0xB8, 0x01, 0xE4, 0x02,
+0x27, 0x02, 0x5B, 0x02,
+0x5D, 0x02, 0x8C, 0x02,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd73[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xBE, 0x02, 0xDF, 0x03,
+0x0C, 0x03, 0x2A, 0x03,
+0x51, 0x03, 0x6D, 0x03,
+0x8D, 0x03, 0xA4, 0x03,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd74[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xBF, 0x03, 0xCC, 0x03,
+0xCC, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd75[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xC0, 0x00, 0xAC, 0x00,
+0xBA, 0x00, 0xD9, 0x00,
+0xED, 0x01, 0x01, 0x01,
+0x1E, 0x01, 0x3A, 0x01,
+0x62, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd76[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xC1, 0x01, 0x85, 0x01,
+0xB8, 0x01, 0xE4, 0x02,
+0x27, 0x02, 0x5B, 0x02,
+0x5D, 0x02, 0x8C, 0x02,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd77[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xC2, 0x02, 0xDF, 0x03,
+0x0C, 0x03, 0x2A, 0x03,
+0x51, 0x03, 0x6D, 0x03,
+0x8D, 0x03, 0xA4, 0x03,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd78[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xC3, 0x03, 0xCC, 0x03,
+0xCC, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd79[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xC4, 0x00, 0xAC, 0x00,
+0xBA, 0x00, 0xD9, 0x00,
+0xED, 0x01, 0x01, 0x01,
+0x1E, 0x01, 0x3A, 0x01,
+0x62, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd80[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xC5, 0x01, 0x85, 0x01,
+0xB8, 0x01, 0xE4, 0x02,
+0x27, 0x02, 0x5B, 0x02,
+0x5D, 0x02, 0x8C, 0x02,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd81[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xC6, 0x02, 0xDF, 0x03,
+0x0C, 0x03, 0x2A, 0x03,
+0x51, 0x03, 0x6D, 0x03,
+0x8D, 0x03, 0xA4, 0x03,
+0xBE, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd82[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xC7, 0x03, 0xCC, 0x03,
+0xCC, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd83[] = {
+0xEE, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd84[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xF0, 0x55, 0xAA, 0x52,
+0x08, 0x03, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd85[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB0, 0x00, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd86[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB1, 0x00, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd87[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB2, 0x03, 0x00, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd88[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB3, 0x03, 0x00, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd89[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB4, 0x03, 0x00, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd90[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB5, 0x03, 0x00, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd91[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB6, 0x03, 0x00, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd92[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB7, 0x03, 0x00, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd93[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB8, 0x03, 0x00, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd94[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB9, 0x03, 0x00, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd95[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xBA, 0x35, 0x10, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd96[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xBB, 0x35, 0x10, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd97[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xBC, 0x35, 0x10, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd98[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xBD, 0x35, 0x10, 0x00,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd99[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xC0, 0x00, 0x34, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd100[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xC1, 0x00, 0x34, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd101[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xC2, 0x00, 0x34, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd102[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xC3, 0x00, 0x34, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd103[] = {
+0xC4, 0x40, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd104[] = {
+0xC5, 0x40, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd105[] = {
+0xC6, 0x40, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd106[] = {
+0xC7, 0x40, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd107[] = {
+0xEF, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd108[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xF0, 0x55, 0xAA, 0x52,
+0x08, 0x05, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd109[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB0, 0x1B, 0x10, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd110[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB1, 0x1B, 0x10, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd111[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB2, 0x1B, 0x10, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd112[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB3, 0x1B, 0x10, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd113[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB4, 0x1B, 0x10, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd114[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB5, 0x1B, 0x10, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd115[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB6, 0x1B, 0x10, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd116[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB7, 0x1B, 0x10, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd117[] = {
+0xB8, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd118[] = {
+0xB9, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd119[] = {
+0xBA, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd120[] = {
+0xBB, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd121[] = {
+0xBC, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd122[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xBD, 0x03, 0x03, 0x03,
+0x00, 0x01, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd123[] = {
+0xC0, 0x03, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd124[] = {
+0xC1, 0x05, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd125[] = {
+0xC2, 0x03, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd126[] = {
+0xC3, 0x05, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd127[] = {
+0xC4, 0x80, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd128[] = {
+0xC5, 0xA2, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd129[] = {
+0xC6, 0x80, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd130[] = {
+0xC7, 0xA2, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd131[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC8, 0x01, 0x20, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd132[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC9, 0x00, 0x20, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd133[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCA, 0x01, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd134[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCB, 0x00, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd135[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xCC, 0x00, 0x00, 0x01,
+ };
+
+
+static char nt35521_720p_video_on_cmd136[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xCD, 0x00, 0x00, 0x01,
+ };
+
+
+static char nt35521_720p_video_on_cmd137[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xCE, 0x00, 0x00, 0x01,
+ };
+
+
+static char nt35521_720p_video_on_cmd138[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xCF, 0x00, 0x00, 0x01,
+ };
+
+
+static char nt35521_720p_video_on_cmd139[] = {
+0xD0, 0x00, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd140[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD1, 0x03, 0x00, 0x00,
+0x07, 0x10, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd141[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD2, 0x13, 0x00, 0x00,
+0x07, 0x11, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd142[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD3, 0x23, 0x00, 0x00,
+0x07, 0x10, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd143[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD4, 0x33, 0x00, 0x00,
+0x07, 0x11, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd144[] = {
+0xE5, 0x06, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd145[] = {
+0xE6, 0x06, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd146[] = {
+0xE7, 0x06, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd147[] = {
+0xE8, 0x06, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd148[] = {
+0xE9, 0x06, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd149[] = {
+0xEA, 0x06, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd150[] = {
+0xEB, 0x06, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd151[] = {
+0xEC, 0x06, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd152[] = {
+0xED, 0x31, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd153[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xF0, 0x55, 0xAA, 0x52,
+0x08, 0x06, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd154[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB0, 0x10, 0x11, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd155[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB1, 0x12, 0x13, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd156[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB2, 0x08, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd157[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB3, 0x2D, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd158[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB4, 0x2D, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd159[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB5, 0x34, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd160[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB6, 0x2D, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd161[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB7, 0x34, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd162[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB8, 0x02, 0x0A, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd163[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB9, 0x00, 0x08, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd164[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBA, 0x09, 0x01, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd165[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBB, 0x0B, 0x03, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd166[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBC, 0x34, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd167[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBD, 0x34, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd168[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBE, 0x2D, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd169[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xBF, 0x34, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd170[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC0, 0x2D, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd171[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC1, 0x01, 0x09, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd172[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC2, 0x19, 0x18, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd173[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC3, 0x17, 0x16, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd174[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC4, 0x19, 0x18, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd175[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC5, 0x17, 0x16, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd176[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC6, 0x01, 0x09, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd177[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC7, 0x2D, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd178[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC8, 0x2D, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd179[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC9, 0x34, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd180[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCA, 0x2D, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd181[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCB, 0x34, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd182[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCC, 0x0B, 0x03, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd183[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCD, 0x09, 0x01, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd184[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCE, 0x00, 0x08, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd185[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCF, 0x02, 0x0A, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd186[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD0, 0x34, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd187[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD1, 0x34, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd188[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD2, 0x2D, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd189[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD3, 0x34, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd190[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD4, 0x2D, 0x2D, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd191[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD5, 0x08, 0x00, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd192[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD6, 0x10, 0x11, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd193[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD7, 0x12, 0x13, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd194[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD8, 0x55, 0x55, 0x55,
+0x55, 0x55, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd195[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD9, 0x55, 0x55, 0x55,
+0x55, 0x55, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd196[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xE5, 0x34, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd197[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xE6, 0x34, 0x34, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd198[] = {
+0xE7, 0x05, 0x23, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd199[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xF0, 0x55, 0xAA, 0x52,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd200[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd201[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+static char nt35521_720p_video_on_cmd202[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xF0, 0x55, 0xAA, 0x52,
+0x08, 0x01, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd203[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xF0, 0x55, 0xAA, 0x52,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35521_720p_video_on_cmd204[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x53, 0x2C, 0xFF, 0xFF, };
+
+
+
+
+static struct mipi_dsi_cmd nt35521_720p_video_on_command[] = {
+{ 0xc , nt35521_720p_video_on_cmd0},
+{ 0x8 , nt35521_720p_video_on_cmd1},
+{ 0x4 , nt35521_720p_video_on_cmd2},
+{ 0x8 , nt35521_720p_video_on_cmd3},
+{ 0xc , nt35521_720p_video_on_cmd4},
+{ 0x4 , nt35521_720p_video_on_cmd5},
+{ 0x4 , nt35521_720p_video_on_cmd6},
+{ 0x8 , nt35521_720p_video_on_cmd7},
+{ 0x8 , nt35521_720p_video_on_cmd8},
+{ 0xc , nt35521_720p_video_on_cmd9},
+{ 0x18 , nt35521_720p_video_on_cmd10},
+{ 0x4 , nt35521_720p_video_on_cmd11},
+{ 0x18 , nt35521_720p_video_on_cmd12},
+{ 0x4 , nt35521_720p_video_on_cmd13},
+{ 0x8 , nt35521_720p_video_on_cmd14},
+{ 0x14 , nt35521_720p_video_on_cmd15},
+{ 0x14 , nt35521_720p_video_on_cmd16},
+{ 0x8 , nt35521_720p_video_on_cmd17},
+{ 0x8 , nt35521_720p_video_on_cmd18},
+{ 0xc , nt35521_720p_video_on_cmd19},
+{ 0x10 , nt35521_720p_video_on_cmd20},
+{ 0x10 , nt35521_720p_video_on_cmd21},
+{ 0x8 , nt35521_720p_video_on_cmd22},
+{ 0x4 , nt35521_720p_video_on_cmd23},
+{ 0xc , nt35521_720p_video_on_cmd24},
+{ 0x8 , nt35521_720p_video_on_cmd25},
+{ 0xc , nt35521_720p_video_on_cmd26},
+{ 0x8 , nt35521_720p_video_on_cmd27},
+{ 0x8 , nt35521_720p_video_on_cmd28},
+{ 0x8 , nt35521_720p_video_on_cmd29},
+{ 0x8 , nt35521_720p_video_on_cmd30},
+{ 0x8 , nt35521_720p_video_on_cmd31},
+{ 0x8 , nt35521_720p_video_on_cmd32},
+{ 0x8 , nt35521_720p_video_on_cmd33},
+{ 0x8 , nt35521_720p_video_on_cmd34},
+{ 0x8 , nt35521_720p_video_on_cmd35},
+{ 0x8 , nt35521_720p_video_on_cmd36},
+{ 0x8 , nt35521_720p_video_on_cmd37},
+{ 0x8 , nt35521_720p_video_on_cmd38},
+{ 0x4 , nt35521_720p_video_on_cmd39},
+{ 0x4 , nt35521_720p_video_on_cmd40},
+{ 0x4 , nt35521_720p_video_on_cmd41},
+{ 0x4 , nt35521_720p_video_on_cmd42},
+{ 0x8 , nt35521_720p_video_on_cmd43},
+{ 0x8 , nt35521_720p_video_on_cmd44},
+{ 0x8 , nt35521_720p_video_on_cmd45},
+{ 0x8 , nt35521_720p_video_on_cmd46},
+{ 0xc , nt35521_720p_video_on_cmd47},
+{ 0x4 , nt35521_720p_video_on_cmd48},
+{ 0x8 , nt35521_720p_video_on_cmd49},
+{ 0x4 , nt35521_720p_video_on_cmd50},
+{ 0x8 , nt35521_720p_video_on_cmd51},
+{ 0x4 , nt35521_720p_video_on_cmd52},
+{ 0x8 , nt35521_720p_video_on_cmd53},
+{ 0x8 , nt35521_720p_video_on_cmd54},
+{ 0x8 , nt35521_720p_video_on_cmd55},
+{ 0x4 , nt35521_720p_video_on_cmd56},
+{ 0x4 , nt35521_720p_video_on_cmd57},
+{ 0xc , nt35521_720p_video_on_cmd58},
+{ 0x18 , nt35521_720p_video_on_cmd59},
+{ 0x18 , nt35521_720p_video_on_cmd60},
+{ 0x18 , nt35521_720p_video_on_cmd61},
+{ 0xc , nt35521_720p_video_on_cmd62},
+{ 0x18 , nt35521_720p_video_on_cmd63},
+{ 0x18 , nt35521_720p_video_on_cmd64},
+{ 0x18 , nt35521_720p_video_on_cmd65},
+{ 0xc , nt35521_720p_video_on_cmd66},
+{ 0x18 , nt35521_720p_video_on_cmd67},
+{ 0x18 , nt35521_720p_video_on_cmd68},
+{ 0x18 , nt35521_720p_video_on_cmd69},
+{ 0xc , nt35521_720p_video_on_cmd70},
+{ 0x18 , nt35521_720p_video_on_cmd71},
+{ 0x18 , nt35521_720p_video_on_cmd72},
+{ 0x18 , nt35521_720p_video_on_cmd73},
+{ 0xc , nt35521_720p_video_on_cmd74},
+{ 0x18 , nt35521_720p_video_on_cmd75},
+{ 0x18 , nt35521_720p_video_on_cmd76},
+{ 0x18 , nt35521_720p_video_on_cmd77},
+{ 0xc , nt35521_720p_video_on_cmd78},
+{ 0x18 , nt35521_720p_video_on_cmd79},
+{ 0x18 , nt35521_720p_video_on_cmd80},
+{ 0x18 , nt35521_720p_video_on_cmd81},
+{ 0xc , nt35521_720p_video_on_cmd82},
+{ 0x4 , nt35521_720p_video_on_cmd83},
+{ 0xc , nt35521_720p_video_on_cmd84},
+{ 0x8 , nt35521_720p_video_on_cmd85},
+{ 0x8 , nt35521_720p_video_on_cmd86},
+{ 0xc , nt35521_720p_video_on_cmd87},
+{ 0xc , nt35521_720p_video_on_cmd88},
+{ 0xc , nt35521_720p_video_on_cmd89},
+{ 0xc , nt35521_720p_video_on_cmd90},
+{ 0xc , nt35521_720p_video_on_cmd91},
+{ 0xc , nt35521_720p_video_on_cmd92},
+{ 0xc , nt35521_720p_video_on_cmd93},
+{ 0xc , nt35521_720p_video_on_cmd94},
+{ 0xc , nt35521_720p_video_on_cmd95},
+{ 0xc , nt35521_720p_video_on_cmd96},
+{ 0xc , nt35521_720p_video_on_cmd97},
+{ 0xc , nt35521_720p_video_on_cmd98},
+{ 0xc , nt35521_720p_video_on_cmd99},
+{ 0xc , nt35521_720p_video_on_cmd100},
+{ 0xc , nt35521_720p_video_on_cmd101},
+{ 0xc , nt35521_720p_video_on_cmd102},
+{ 0x4 , nt35521_720p_video_on_cmd103},
+{ 0x4 , nt35521_720p_video_on_cmd104},
+{ 0x4 , nt35521_720p_video_on_cmd105},
+{ 0x4 , nt35521_720p_video_on_cmd106},
+{ 0x4 , nt35521_720p_video_on_cmd107},
+{ 0xc , nt35521_720p_video_on_cmd108},
+{ 0x8 , nt35521_720p_video_on_cmd109},
+{ 0x8 , nt35521_720p_video_on_cmd110},
+{ 0x8 , nt35521_720p_video_on_cmd111},
+{ 0x8 , nt35521_720p_video_on_cmd112},
+{ 0x8 , nt35521_720p_video_on_cmd113},
+{ 0x8 , nt35521_720p_video_on_cmd114},
+{ 0x8 , nt35521_720p_video_on_cmd115},
+{ 0x8 , nt35521_720p_video_on_cmd116},
+{ 0x4 , nt35521_720p_video_on_cmd117},
+{ 0x4 , nt35521_720p_video_on_cmd118},
+{ 0x4 , nt35521_720p_video_on_cmd119},
+{ 0x4 , nt35521_720p_video_on_cmd120},
+{ 0x4 , nt35521_720p_video_on_cmd121},
+{ 0xc , nt35521_720p_video_on_cmd122},
+{ 0x4 , nt35521_720p_video_on_cmd123},
+{ 0x4 , nt35521_720p_video_on_cmd124},
+{ 0x4 , nt35521_720p_video_on_cmd125},
+{ 0x4 , nt35521_720p_video_on_cmd126},
+{ 0x4 , nt35521_720p_video_on_cmd127},
+{ 0x4 , nt35521_720p_video_on_cmd128},
+{ 0x4 , nt35521_720p_video_on_cmd129},
+{ 0x4 , nt35521_720p_video_on_cmd130},
+{ 0x8 , nt35521_720p_video_on_cmd131},
+{ 0x8 , nt35521_720p_video_on_cmd132},
+{ 0x8 , nt35521_720p_video_on_cmd133},
+{ 0x8 , nt35521_720p_video_on_cmd134},
+{ 0x8 , nt35521_720p_video_on_cmd135},
+{ 0x8 , nt35521_720p_video_on_cmd136},
+{ 0x8 , nt35521_720p_video_on_cmd137},
+{ 0x8 , nt35521_720p_video_on_cmd138},
+{ 0x4 , nt35521_720p_video_on_cmd139},
+{ 0xc , nt35521_720p_video_on_cmd140},
+{ 0xc , nt35521_720p_video_on_cmd141},
+{ 0xc , nt35521_720p_video_on_cmd142},
+{ 0xc , nt35521_720p_video_on_cmd143},
+{ 0x4 , nt35521_720p_video_on_cmd144},
+{ 0x4 , nt35521_720p_video_on_cmd145},
+{ 0x4 , nt35521_720p_video_on_cmd146},
+{ 0x4 , nt35521_720p_video_on_cmd147},
+{ 0x4 , nt35521_720p_video_on_cmd148},
+{ 0x4 , nt35521_720p_video_on_cmd149},
+{ 0x4 , nt35521_720p_video_on_cmd150},
+{ 0x4 , nt35521_720p_video_on_cmd151},
+{ 0x4 , nt35521_720p_video_on_cmd152},
+{ 0xc , nt35521_720p_video_on_cmd153},
+{ 0x8 , nt35521_720p_video_on_cmd154},
+{ 0x8 , nt35521_720p_video_on_cmd155},
+{ 0x8 , nt35521_720p_video_on_cmd156},
+{ 0x8 , nt35521_720p_video_on_cmd157},
+{ 0x8 , nt35521_720p_video_on_cmd158},
+{ 0x8 , nt35521_720p_video_on_cmd159},
+{ 0x8 , nt35521_720p_video_on_cmd160},
+{ 0x8 , nt35521_720p_video_on_cmd161},
+{ 0x8 , nt35521_720p_video_on_cmd162},
+{ 0x8 , nt35521_720p_video_on_cmd163},
+{ 0x8 , nt35521_720p_video_on_cmd164},
+{ 0x8 , nt35521_720p_video_on_cmd165},
+{ 0x8 , nt35521_720p_video_on_cmd166},
+{ 0x8 , nt35521_720p_video_on_cmd167},
+{ 0x8 , nt35521_720p_video_on_cmd168},
+{ 0x8 , nt35521_720p_video_on_cmd169},
+{ 0x8 , nt35521_720p_video_on_cmd170},
+{ 0x8 , nt35521_720p_video_on_cmd171},
+{ 0x8 , nt35521_720p_video_on_cmd172},
+{ 0x8 , nt35521_720p_video_on_cmd173},
+{ 0x8 , nt35521_720p_video_on_cmd174},
+{ 0x8 , nt35521_720p_video_on_cmd175},
+{ 0x8 , nt35521_720p_video_on_cmd176},
+{ 0x8 , nt35521_720p_video_on_cmd177},
+{ 0x8 , nt35521_720p_video_on_cmd178},
+{ 0x8 , nt35521_720p_video_on_cmd179},
+{ 0x8 , nt35521_720p_video_on_cmd180},
+{ 0x8 , nt35521_720p_video_on_cmd181},
+{ 0x8 , nt35521_720p_video_on_cmd182},
+{ 0x8 , nt35521_720p_video_on_cmd183},
+{ 0x8 , nt35521_720p_video_on_cmd184},
+{ 0x8 , nt35521_720p_video_on_cmd185},
+{ 0x8 , nt35521_720p_video_on_cmd186},
+{ 0x8 , nt35521_720p_video_on_cmd187},
+{ 0x8 , nt35521_720p_video_on_cmd188},
+{ 0x8 , nt35521_720p_video_on_cmd189},
+{ 0x8 , nt35521_720p_video_on_cmd190},
+{ 0x8 , nt35521_720p_video_on_cmd191},
+{ 0x8 , nt35521_720p_video_on_cmd192},
+{ 0x8 , nt35521_720p_video_on_cmd193},
+{ 0xc , nt35521_720p_video_on_cmd194},
+{ 0xc , nt35521_720p_video_on_cmd195},
+{ 0x8 , nt35521_720p_video_on_cmd196},
+{ 0x8 , nt35521_720p_video_on_cmd197},
+{ 0x4 , nt35521_720p_video_on_cmd198},
+{ 0xc , nt35521_720p_video_on_cmd199},
+{ 0x4 , nt35521_720p_video_on_cmd200},
+{ 0x4 , nt35521_720p_video_on_cmd201},
+{ 0xc , nt35521_720p_video_on_cmd202},
+{ 0xc , nt35521_720p_video_on_cmd203},
+{ 0x8 , nt35521_720p_video_on_cmd204}
+};
+#define NT35521_720P_VIDEO_ON_COMMAND 205
+
+
+static char nt35521_720p_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char nt35521_720p_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd nt35521_720p_video_off_command[] = {
+{ 0x4 , nt35521_720p_videooff_cmd0},
+{ 0x4 , nt35521_720p_videooff_cmd1}
+};
+#define NT35521_720P_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state nt35521_720p_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info nt35521_720p_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info nt35521_720p_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration nt35521_720p_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t nt35521_720p_video_timings[] = {
+ 0x93, 0x1F, 0x17, 0x00, 0x2F, 0x2E, 0x1C, 0x21, 0x26, 0x03, 0x04, 0x00
+};
+
+
+
+static struct mipi_dsi_cmd nt35521_720p_video_rotation[] = {
+
+};
+#define NT35521_720P_VIDEO_ROTATION 0
+
+
+static struct panel_timing nt35521_720p_video_timing_info = {
+ 0, 4, 0x20, 0x2D
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight nt35521_720p_video_backlight = {
+ 1, 1, 255, 100, 2, "PMIC_8941"
+};
+
+
+#endif /*_NT35521_720P_VIDEO_H_*/
diff --git a/dev/gcdb/display/oem_panel.c b/dev/gcdb/display/oem_panel.c
index bacea0f..b1e19e9 100755
--- a/dev/gcdb/display/oem_panel.c
+++ b/dev/gcdb/display/oem_panel.c
@@ -43,7 +43,9 @@
#include "include/panel_toshiba_720p_video.h"
#include "include/panel_nt35590_720p_video.h"
#include "include/panel_nt35590_720p_cmd.h"
+#include "include/panel_hx8394a_720p_video.h"
#include "include/panel_nt35596_1080p_video.h"
+#include "include/panel_nt35521_720p_video.h"
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -52,7 +54,9 @@
TOSHIBA_720P_VIDEO_PANEL,
NT35590_720P_CMD_PANEL,
NT35590_720P_VIDEO_PANEL,
-NT35596_1080P_VIDEO_PANEL
+NT35596_1080P_VIDEO_PANEL,
+HX8394A_720P_VIDEO_PANEL,
+NT35521_720P_VIDEO_PANEL
};
static uint32_t panel_id;
@@ -134,6 +138,43 @@
memcpy(phy_db->timing,
nt35590_720p_video_timings, TIMING_SIZE);
break;
+ case NT35521_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &nt35521_720p_video_panel_data;
+ panelstruct->panelres = &nt35521_720p_video_panel_res;
+ panelstruct->color = &nt35521_720p_video_color;
+ panelstruct->videopanel = &nt35521_720p_video_video_panel;
+ panelstruct->commandpanel = &nt35521_720p_video_command_panel;
+ panelstruct->state = &nt35521_720p_video_state;
+ panelstruct->laneconfig = &nt35521_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35521_720p_video_timing_info;
+ panelstruct->backlightinfo = &nt35521_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = nt35521_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = NT35521_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ nt35521_720p_video_timings, TIMING_SIZE);
+ break;
+ case HX8394A_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8394a_720p_video_panel_data;
+ panelstruct->panelres = &hx8394a_720p_video_panel_res;
+ panelstruct->color = &hx8394a_720p_video_color;
+ panelstruct->videopanel = &hx8394a_720p_video_video_panel;
+ panelstruct->commandpanel = &hx8394a_720p_video_command_panel;
+ panelstruct->state = &hx8394a_720p_video_state;
+ panelstruct->laneconfig = &hx8394a_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8394a_720p_video_timing_info;
+ panelstruct->backlightinfo = &hx8394a_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = hx8394a_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = HX8394A_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ hx8394a_720p_video_timings, TIMING_SIZE);
+ break;
+
case NT35590_720P_CMD_PANEL:
panelstruct->paneldata = &nt35590_720p_cmd_panel_data;
panelstruct->panelres = &nt35590_720p_cmd_panel_res;
@@ -179,6 +220,7 @@
{
uint32_t hw_id = board_hardware_id();
uint32_t platformid = board_platform_id();
+ uint32_t target_id = board_target_id();
switch (platformid) {
case MSM8974:
@@ -194,10 +236,29 @@
return false;
}
break;
- case MSM8226:
+ case MSM8826:
case MSM8626:
+ case MSM8226:
+ case MSM8926:
+ case MSM8126:
+ case MSM8326:
+ case APQ8026:
switch (hw_id) {
case HW_PLATFORM_QRD:
+ if (board_hardware_subtype() == 2) {
+ panel_id = NT35521_720P_VIDEO_PANEL;
+ } else {
+ if (((target_id >> 16) & 0xFF) == 0x1) //EVT
+ panel_id = NT35590_720P_VIDEO_PANEL;
+ else if (((target_id >> 16) & 0xFF) == 0x2) //DVT
+ panel_id = HX8394A_720P_VIDEO_PANEL;
+ else {
+ dprintf(CRITICAL, "Not supported device, target_id=%x\n"
+ , target_id);
+ return false;
+ }
+ }
+ break;
case HW_PLATFORM_MTP:
case HW_PLATFORM_SURF:
panel_id = NT35590_720P_VIDEO_PANEL;
@@ -208,6 +269,10 @@
return false;
}
break;
+ default:
+ dprintf(CRITICAL, "GCDB:Display: Platform id:%d not supported\n"
+ , platformid);
+ return false;
}
init_panel_data(panelstruct, pinfo, phy_db);
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
old mode 100755
new mode 100644
index 7f78122..da69f20
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -184,21 +184,14 @@
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
- switch (pinfo->mipi.num_of_lanes) {
- case 1:
- lane_enable = 0x1; /*1 lane only */
- break;
- case 2:
- lane_enable = 0x3; /* 2 lanes only */
- break;
- case 3:
- lane_enable = 0x7; /* 3 lanes only */
- break;
- case 4:
- default:
- lane_enable = 0xf; /* 4 lanes */
- break;
- }
+ if (pinfo->mipi.data_lane0)
+ lane_enable |= (1 << 0);
+ if (pinfo->mipi.data_lane1)
+ lane_enable |= (1 << 1);
+ if (pinfo->mipi.data_lane2)
+ lane_enable |= (1 << 2);
+ if (pinfo->mipi.data_lane3)
+ lane_enable |= (1 << 3);
ret = mdss_dsi_video_mode_config((panel_width + plcdc->xres_pad),
(pinfo->yres + plcdc->yres_pad),
@@ -245,11 +238,24 @@
struct lcdc_panel_info *plcdc)
{
int ret = NO_ERROR;
+ uint8_t lane_en = 0;
+ uint8_t ystride = pinfo->bpp / 8;
+
+ if (pinfo->mipi.data_lane0)
+ lane_en |= (1 << 0);
+ if (pinfo->mipi.data_lane1)
+ lane_en |= (1 << 1);
+ if (pinfo->mipi.data_lane2)
+ lane_en |= (1 << 2);
+ if (pinfo->mipi.data_lane3)
+ lane_en |= (1 << 3);
ret = mdss_dsi_cmd_mode_config((pinfo->xres + plcdc->xres_pad),
(pinfo->yres + plcdc->yres_pad),
(pinfo->xres), (pinfo->yres),
- pinfo->mipi.dst_format, pinfo->mipi.traffic_mode);
+ pinfo->mipi.dst_format,
+ ystride, lane_en,
+ pinfo->mipi.interleave_mode);
return ret;
}
diff --git a/dev/panel/msm/mipi_nt35590_cmd_720p.c b/dev/panel/msm/mipi_nt35590_cmd_720p.c
index 41c6220..6629aa6 100644
--- a/dev/panel/msm/mipi_nt35590_cmd_720p.c
+++ b/dev/panel/msm/mipi_nt35590_cmd_720p.c
@@ -2385,7 +2385,9 @@
(pinfo->xres),
(pinfo->yres),
pinfo->mipi.dst_format,
- pinfo->mipi.traffic_mode);
+ pinfo->bpp / 8,
+ 0xf,
+ pinfo->mipi.interleave_mode);
return ret;
}
diff --git a/dev/panel/msm/mipi_truly_cmd_wvga.c b/dev/panel/msm/mipi_truly_cmd_wvga.c
new file mode 100644
index 0000000..b1f6c31
--- /dev/null
+++ b/dev/panel/msm/mipi_truly_cmd_wvga.c
@@ -0,0 +1,314 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <sys/types.h>
+#include <err.h>
+#include <reg.h>
+#include <debug.h>
+#include <target/display.h>
+#include <platform/iomap.h>
+
+#define WVGA_MIPI_FB_WIDTH 480
+#define WVGA_MIPI_FB_HEIGHT 800
+
+#define TRULY_PANEL_FRAME_RATE 60
+#define TRULY_PANEL_NUM_OF_LANES 2
+#define TRULY_PANEL_LANE_SWAP 0
+#define TRULY_PANEL_T_CLK_PRE 0x41b
+#define TRULY_PANEL_T_CLK_POST 0x0
+#define TRULY_PANEL_BPP 24
+#define TRULY_PANEL_CLK_RATE 499000000
+
+static char disp_on0[4] = {
+ 0x01, 0x00, 0x05, 0x80
+};
+static char disp_on1[4] = {
+ 0xB0, 0x04, 0x23, 0x80
+};
+static char disp_on2[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB3, 0x02, 0x00, 0xFF
+};
+static char disp_on3[4] = {
+ 0xBD, 0x00, 0x23, 0x80
+};
+static char disp_on4[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC0, 0x18, 0x66, 0xFF
+};
+static char disp_on5[20] = {
+ 0x10, 0x00, 0x29, 0xC0,
+ 0xC1, 0x23, 0x31, 0x99,
+ 0x21, 0x20, 0x00, 0x30,
+ 0x28, 0x0C, 0x0C, 0x00,
+ 0x00, 0x00, 0x21, 0x01
+};
+static char disp_on6[12] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xC2, 0x00, 0x06, 0x06,
+ 0x01, 0x03, 0x00, 0xFF
+};
+static char disp_on7[32] = {
+ 0x19, 0x00, 0x29, 0xC0,
+ 0xC8, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0xFF, 0xFF, 0xFF
+};
+static char disp_on8[32] = {
+ 0x19, 0x00, 0x29, 0xC0,
+ 0xC9, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0xFF, 0xFF, 0xFF
+};
+static char disp_on9[32] = {
+ 0x19, 0x00, 0x29, 0xC0,
+ 0xCA, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0xFF, 0xFF, 0xFF
+};
+static char disp_on10[24] = {
+ 0x11, 0x00, 0x29, 0xC0,
+ 0xD0, 0x29, 0x03, 0xce,
+ 0xa6, 0x00, 0x43, 0x20,
+ 0x10, 0x01, 0x00, 0x01,
+ 0x01, 0x00, 0x03, 0x01,
+ 0x00, 0xFF, 0xFF, 0xFF
+};
+static char disp_on11[12] = {
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xD1, 0x18, 0x0C, 0x23,
+ 0x03, 0x75, 0x02, 0x50
+};
+static char disp_on12[4] = {
+ 0xD3, 0x11, 0x23, 0x80
+};
+static char disp_on13[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD5, 0x2A, 0x2A, 0xFF
+};
+static char disp_on14[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xDE, 0x01, 0x51, 0xFF
+};
+static char disp_on15[4] = {
+ 0xE6, 0x51, 0x23, 0x80
+};
+static char disp_on16[4] = {
+ 0xFA, 0x03, 0x23, 0x80
+};
+static char disp_on17[4] = {
+ 0xD6, 0x28, 0x23, 0x80
+};
+static char disp_on18[4] = {
+ 0x36, 0x41, 0x15, 0x80
+};
+static char disp_on19[12] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0x2A, 0x00, 0x00, 0x01,
+ 0xDF, 0xFF, 0xFF, 0xFF
+};
+static char disp_on20[12] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0x2B, 0x00, 0x00, 0x03,
+ 0x1F, 0xFF, 0xFF, 0xFF
+};
+static char disp_on21[4] = {
+ 0x35, 0x00, 0x15, 0x80
+};
+static char disp_on22[8] = {
+ 0x03, 0x00, 0x39, 0xc0,
+ 0x44, 0x00, 0x50, 0xFF
+};
+static char disp_on23[4] = {
+ 0x3A, 0x77, 0x15, 0x80
+};
+static char disp_on24[4] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+static char disp_on25[4] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd truly_wvga_panel_cmd_mode_cmds[] = {
+ {sizeof(disp_on0), (char *)disp_on0},
+ {sizeof(disp_on1), (char *)disp_on1},
+ {sizeof(disp_on2), (char *)disp_on2},
+ {sizeof(disp_on3), (char *)disp_on3},
+ {sizeof(disp_on4), (char *)disp_on4},
+ {sizeof(disp_on5), (char *)disp_on5},
+ {sizeof(disp_on6), (char *)disp_on6},
+ {sizeof(disp_on7), (char *)disp_on7},
+ {sizeof(disp_on8), (char *)disp_on8},
+ {sizeof(disp_on9), (char *)disp_on9},
+ {sizeof(disp_on10), (char *)disp_on10},
+ {sizeof(disp_on11), (char *)disp_on11},
+ {sizeof(disp_on12), (char *)disp_on12},
+ {sizeof(disp_on13), (char *)disp_on13},
+ {sizeof(disp_on14), (char *)disp_on14},
+ {sizeof(disp_on15), (char *)disp_on15},
+ {sizeof(disp_on16), (char *)disp_on16},
+ {sizeof(disp_on17), (char *)disp_on17},
+ {sizeof(disp_on18), (char *)disp_on18},
+ {sizeof(disp_on19), (char *)disp_on19},
+ {sizeof(disp_on20), (char *)disp_on20},
+ {sizeof(disp_on21), (char *)disp_on21},
+ {sizeof(disp_on22), (char *)disp_on22},
+ {sizeof(disp_on23), (char *)disp_on23},
+ {sizeof(disp_on24), (char *)disp_on24},
+ {sizeof(disp_on25), (char *)disp_on25},
+};
+
+int mipi_truly_cmd_wvga_config(void *pdata)
+{
+ int ret = NO_ERROR;
+ /* 2 Lanes -- Enables Data Lane0, 1 */
+ unsigned char lane_en = 0x3;
+ unsigned long low_pwr_stop_mode = 0;
+
+ /* Needed or else will have blank line at top of display */
+ unsigned char eof_bllp_pwr = 0x9;
+
+ unsigned char interleav = 0;
+ struct lcdc_panel_info *lcdc = NULL;
+ struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
+
+ if (pinfo == NULL)
+ return ERR_INVALID_ARGS;
+
+ lcdc = &(pinfo->lcdc);
+ if (lcdc == NULL)
+ return ERR_INVALID_ARGS;
+
+ ret = mdss_dsi_cmd_mode_config((pinfo->xres + lcdc->xres_pad),
+ (pinfo->yres + lcdc->yres_pad),
+ (pinfo->xres),
+ (pinfo->yres),
+ pinfo->mipi.dst_format,
+ pinfo->bpp / 8,
+ lane_en,
+ 0);
+
+ return ret;
+}
+
+int mipi_truly_cmd_wvga_on()
+{
+ int ret = NO_ERROR;
+ return ret;
+}
+
+int mipi_truly_cmd_wvga_off()
+{
+ int ret = NO_ERROR;
+ return ret;
+}
+
+static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
+ /* regulator */
+ {0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
+ /* timing */
+ {0x5d, 0x12, 0x0c, 0x00, 0x33, 0x38,
+ 0x10, 0x16, 0x1e, 0x03, 0x04, 0x00},
+ /* phy ctrl */
+ {0x7f, 0x00, 0x00, 0x00},
+ /* strength */
+ {0xff, 0x06},
+ /* bist */
+ {0x03, 0x03, 0x00, 0x00, 0x0f, 0x00},
+ /* lane config */
+ {0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00},
+};
+
+void mipi_truly_cmd_wvga_init(struct msm_panel_info *pinfo)
+{
+ if (!pinfo)
+ return;
+
+ pinfo->xres = WVGA_MIPI_FB_WIDTH;
+ pinfo->yres = WVGA_MIPI_FB_HEIGHT;
+ pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK;
+ pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK;
+ pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH;
+ pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES;
+ pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES;
+ pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH;
+ pinfo->mipi.num_of_lanes = TRULY_PANEL_NUM_OF_LANES;
+ pinfo->mipi.frame_rate = TRULY_PANEL_FRAME_RATE;
+
+ pinfo->type = MIPI_CMD_PANEL;
+ pinfo->wait_cycle = 0;
+ pinfo->bpp = TRULY_PANEL_BPP;
+ pinfo->clk_rate = TRULY_PANEL_CLK_RATE;
+
+ pinfo->mipi.mode = DSI_CMD_MODE;
+ pinfo->mipi.traffic_mode = 1;
+ pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
+ pinfo->mipi.vc = 0;
+ pinfo->mipi.lane_swap = TRULY_PANEL_LANE_SWAP;
+ pinfo->mipi.data_lane0 = TRUE;
+ pinfo->mipi.data_lane1 = TRUE;
+ pinfo->mipi.data_lane2 = FALSE;
+ pinfo->mipi.data_lane3 = FALSE;
+ pinfo->mipi.t_clk_post = TRULY_PANEL_T_CLK_POST;
+ pinfo->mipi.t_clk_pre = TRULY_PANEL_T_CLK_PRE;
+ pinfo->mipi.stream = 0;
+ pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
+ pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
+
+ pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
+ pinfo->mipi.tx_eot_append = TRUE;
+
+ pinfo->mipi.panel_cmds = truly_wvga_panel_cmd_mode_cmds;
+ pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(truly_wvga_panel_cmd_mode_cmds);
+
+ pinfo->on = mipi_truly_cmd_wvga_on;
+ pinfo->off = mipi_truly_cmd_wvga_off;
+ pinfo->config = mipi_truly_cmd_wvga_config;
+
+ return;
+}
diff --git a/dev/panel/msm/mipi_truly_video_wvga.c b/dev/panel/msm/mipi_truly_video_wvga.c
index 4e6f416..fa757fe 100644
--- a/dev/panel/msm/mipi_truly_video_wvga.c
+++ b/dev/panel/msm/mipi_truly_video_wvga.c
@@ -74,7 +74,7 @@
};
static char disp_on6[12] = {
0x07, 0x00, 0x29, 0xC0,
- 0xC2, 0x10, 0x06, 0x06,
+ 0xC2, 0x00, 0x06, 0x06,
0x01, 0x03, 0x00, 0xFF
};
static char disp_on7[32] = {
@@ -129,7 +129,7 @@
};
static char disp_on14[8] = {
0x03, 0x00, 0x29, 0xC0,
- 0xDE, 0x01, 0x41, 0xFF
+ 0xDE, 0x01, 0x51, 0xFF
};
static char disp_on15[4] = {
0xE6, 0x51, 0x23, 0x80
@@ -254,7 +254,7 @@
static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* regulator */
- {0x09, 0x08, 0x05, 0x00, 0x20, 0x03},
+ {0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
/* timing */
{0x5d, 0x12, 0x0c, 0x00, 0x33, 0x38,
0x10, 0x16, 0x1e, 0x03, 0x04, 0x00},
diff --git a/dev/panel/msm/rules.mk b/dev/panel/msm/rules.mk
index b3bdac3..faf378d 100644
--- a/dev/panel/msm/rules.mk
+++ b/dev/panel/msm/rules.mk
@@ -35,5 +35,6 @@
ifeq ($(PLATFORM),msm8610)
OBJS += \
- $(LOCAL_DIR)/mipi_truly_video_wvga.o
+ $(LOCAL_DIR)/mipi_truly_video_wvga.o \
+ $(LOCAL_DIR)/mipi_truly_cmd_wvga.o
endif
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 45f3bc7..b230549 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -61,6 +61,7 @@
#define PON_PSHOLD_WARM_RESET 0x1
#define PON_PSHOLD_SHUTDOWN 0x4
+#define PON_PSHOLD_HARD_RESET 0x7
enum PM8X41_VERSIONS
{
@@ -70,6 +71,7 @@
/*Target power on reasons*/
+#define HARD_RST 1
#define DC_CHG 8
#define USB_CHG 16
#define PON1 32
diff --git a/dev/pmic/pm8x41/include/pm8x41_adc.h b/dev/pmic/pm8x41/include/pm8x41_adc.h
index e2d6c65..3180899 100644
--- a/dev/pmic/pm8x41/include/pm8x41_adc.h
+++ b/dev/pmic/pm8x41/include/pm8x41_adc.h
@@ -103,6 +103,7 @@
#define VREF_125_CHAN_ID 10
#define GND_REF_CHAN_ID 14
#define VDD_VADC_CHAN_ID 15
+#define MPP_8_CHAN_ID 39
#define VADC_BAT_CHAN_ID 49
/* Calibration type */
@@ -155,6 +156,43 @@
#define BOOT_DONE 1
#define BOOT_DONE_BIT 7
+
+/* MPP defines */
+#define MPP_REG_BASE 0xA000
+#define MPP_REG_RANGE 0x100
+#define MPP_MAX_NUM 0x7
+
+#define MPP_MODE_AIN 0x4
+#define MPP_MASTER_ENABLE 0x1
+#define MPP_AIN_ROUTE_AMUX3 0x3
+
+/* control register base address offsets */
+#define Q_REG_MODE_CTL 0x40
+#define Q_REG_DIG_VIN_CTL 0x41
+#define Q_REG_DIG_PULL_CTL 0x42
+#define Q_REG_DIG_IN_CTL 0x43
+#define Q_REG_DIG_OUT_CTL 0x45
+#define Q_REG_EN_CTL 0x46
+#define Q_REG_AOUT_CTL 0x48
+#define Q_REG_AIN_CTL 0x4A
+#define Q_REG_SINK_CTL 0x4C
+
+/* control reg: mode */
+#define Q_REG_OUT_INVERT_SHIFT 0
+#define Q_REG_OUT_INVERT_MASK 0x1
+#define Q_REG_SRC_SEL_SHIFT 1
+#define Q_REG_SRC_SEL_MASK 0xE
+#define Q_REG_MODE_SEL_SHIFT 4
+#define Q_REG_MODE_SEL_MASK 0x70
+
+/* control reg: en */
+#define Q_REG_MASTER_EN_SHIFT 7
+#define Q_REG_MASTER_EN_MASK 0x80
+
+/* control reg: ana_in */
+#define Q_REG_AIN_ROUTE_SHIFT 0
+#define Q_REG_AIN_ROUTE_MASK 0x7
+
/* Function declations */
uint32_t pm8x41_adc_channel_read(uint16_t ch_num);
int pm8x41_iusb_max_config(uint32_t current);
@@ -167,4 +205,7 @@
uint32_t pm8x41_get_batt_voltage();
/* API: Get Voltage based State of Charge */
uint32_t pm8x41_get_voltage_based_soc(uint32_t cutoff_vol, uint32_t vdd_max);
+/* API: Set the MMP pin as ADC */
+void pm8x41_enable_mpp_as_adc(uint16_t mpp_num);
+
#endif /* _PM8X41_ADC_H_ */
diff --git a/dev/pmic/pm8x41/include/pm8x41_wled.h b/dev/pmic/pm8x41/include/pm8x41_wled.h
index b357794..0ef9091 100644
--- a/dev/pmic/pm8x41/include/pm8x41_wled.h
+++ b/dev/pmic/pm8x41/include/pm8x41_wled.h
@@ -30,7 +30,7 @@
#include <debug.h>
#include <reg.h>
-#define PM_WLED_BASE 0x1D800
+#define PM_WLED_BASE 0x0D800
#define PM_WLED_CTNL_REG(n) (PM_WLED_BASE + n)
#define PM_WLED_LED_CTNL_REG(n) (PM_WLED_BASE + 0x60 + (n-1)*10)
@@ -57,7 +57,7 @@
#define PM_WLED_LED3_ILED_SYNC_MASK BIT(0)
#define PM_WLED_ENABLE_MODULE_MASK BIT(7)
-
+#define DEFAULT_SLAVE_ID 0x1
struct pm8x41_wled_data{
uint8_t mod_scheme;
uint16_t led1_brightness;
@@ -72,3 +72,4 @@
void pm8x41_wled_iled_sync_control(uint8_t enable);
void pm8x41_wled_sink_control(uint8_t enable);
void pm8x41_wled_enable(uint8_t enable);
+void pm8x41_wled_config_slave_id(uint8_t slave_id);
diff --git a/dev/pmic/pm8x41/pm8x41_adc.c b/dev/pmic/pm8x41/pm8x41_adc.c
index cf6dfa9..6e4aa29 100644
--- a/dev/pmic/pm8x41/pm8x41_adc.c
+++ b/dev/pmic/pm8x41/pm8x41_adc.c
@@ -41,6 +41,7 @@
static struct adc_conf adc_data[] = {
CHAN_INIT(VADC_USR1_BASE, VADC_BAT_CHAN_ID, VADC_MODE_NORMAL, VADC_DECIM_RATIO_VAL, HW_SET_DELAY_100US, FAST_AVG_SAMP_1, CALIB_RATIO),
CHAN_INIT(VADC_USR1_BASE, VADC_BAT_VOL_CHAN_ID, VADC_MODE_NORMAL, VADC_DECIM_RATIO_VAL, HW_SET_DELAY_100US, FAST_AVG_SAMP_1, CALIB_ABS),
+ CHAN_INIT(VADC_USR1_BASE, MPP_8_CHAN_ID, VADC_MODE_NORMAL, VADC_DECIM_RATIO_VAL, HW_SET_DELAY_100US, FAST_AVG_SAMP_1, CALIB_ABS),
};
@@ -383,3 +384,31 @@
return vol_soc;
}
+
+/*
+ * API: pm8x41_enable_mpp_as_adc
+ * Configurate the MPP pin as the ADC feature.
+ */
+void pm8x41_enable_mpp_as_adc(uint16_t mpp_num)
+{
+ uint32_t val;
+ if(mpp_num > MPP_MAX_NUM)
+ {
+ dprintf(CRITICAL, "Error: The MPP pin number is unavailable\n");
+ return;
+ }
+ /* set the MPP mode as AIN */
+ val = (MPP_MODE_AIN << Q_REG_MODE_SEL_SHIFT) \
+ | (0x1 << Q_REG_OUT_INVERT_SHIFT) \
+ | (0x0 << Q_REG_SRC_SEL_SHIFT);
+ REG_WRITE((MPP_REG_BASE + mpp_num * MPP_REG_RANGE + Q_REG_MODE_CTL), val);
+
+ /* Enable the MPP */
+ val = (MPP_MASTER_ENABLE << Q_REG_MASTER_EN_SHIFT);
+ REG_WRITE((MPP_REG_BASE + mpp_num * MPP_REG_RANGE + Q_REG_EN_CTL), val);
+
+ /* AIN route to AMUX8 */
+ val = (MPP_AIN_ROUTE_AMUX3 << Q_REG_AIN_ROUTE_SHIFT);
+ REG_WRITE((MPP_REG_BASE + mpp_num * MPP_REG_RANGE + Q_REG_AIN_CTL), val);
+
+}
diff --git a/dev/pmic/pm8x41/pm8x41_wled.c b/dev/pmic/pm8x41/pm8x41_wled.c
index fd8b48f..8c37e12 100644
--- a/dev/pmic/pm8x41/pm8x41_wled.c
+++ b/dev/pmic/pm8x41/pm8x41_wled.c
@@ -31,6 +31,25 @@
#include <pm8x41_hw.h>
#include <pm8x41_wled.h>
+static uint8_t wled_slave_id;
+
+static void wled_reg_write(uint32_t addr, uint8_t val)
+{
+ uint32_t new_addr;
+ if (wled_slave_id) {
+ new_addr = addr + (wled_slave_id << 16);
+ REG_WRITE(new_addr, val);
+ } else {
+ new_addr = addr + (DEFAULT_SLAVE_ID << 16);
+ REG_WRITE(new_addr, val);
+ }
+}
+
+void pm8x41_wled_config_slave_id(uint8_t slave_id)
+{
+ wled_slave_id = slave_id;
+}
+
void pm8x41_wled_config(struct pm8x41_wled_data *wled_ctrl) {
if (!wled_ctrl) {
@@ -38,20 +57,20 @@
return;
}
- REG_WRITE(PM_WLED_MODULATION_SCHEME, wled_ctrl->mod_scheme);
+ wled_reg_write(PM_WLED_MODULATION_SCHEME, wled_ctrl->mod_scheme);
- REG_WRITE(PM_WLED_LED1_BRIGHTNESS_LSB, (wled_ctrl->led1_brightness & 0xFF));
- REG_WRITE(PM_WLED_LED1_BRIGHTNESS_MSB, ((wled_ctrl->led1_brightness >> 8) & 0xFF));
- REG_WRITE(PM_WLED_LED2_BRIGHTNESS_LSB, (wled_ctrl->led2_brightness & 0xFF));
- REG_WRITE(PM_WLED_LED2_BRIGHTNESS_MSB, ((wled_ctrl->led2_brightness >> 8) & 0xFF));
- REG_WRITE(PM_WLED_LED3_BRIGHTNESS_LSB, (wled_ctrl->led3_brightness & 0xFF));
- REG_WRITE(PM_WLED_LED3_BRIGHTNESS_MSB, ((wled_ctrl->led3_brightness >> 8) & 0xFF));
+ wled_reg_write(PM_WLED_LED1_BRIGHTNESS_LSB, (wled_ctrl->led1_brightness & 0xFF));
+ wled_reg_write(PM_WLED_LED1_BRIGHTNESS_MSB, ((wled_ctrl->led1_brightness >> 8) & 0xFF));
+ wled_reg_write(PM_WLED_LED2_BRIGHTNESS_LSB, (wled_ctrl->led2_brightness & 0xFF));
+ wled_reg_write(PM_WLED_LED2_BRIGHTNESS_MSB, ((wled_ctrl->led2_brightness >> 8) & 0xFF));
+ wled_reg_write(PM_WLED_LED3_BRIGHTNESS_LSB, (wled_ctrl->led3_brightness & 0xFF));
+ wled_reg_write(PM_WLED_LED3_BRIGHTNESS_MSB, ((wled_ctrl->led3_brightness >> 8) & 0xFF));
- REG_WRITE(PM_WLED_MAX_DUTY_CYCLE, wled_ctrl->max_duty_cycle);
- REG_WRITE(PM_WLED_OVP, wled_ctrl->ovp);
- REG_WRITE(LEDn_FULL_SCALE_CURRENT(1), wled_ctrl->full_current_scale);
- REG_WRITE(LEDn_FULL_SCALE_CURRENT(2), wled_ctrl->full_current_scale);
- REG_WRITE(LEDn_FULL_SCALE_CURRENT(3), wled_ctrl->full_current_scale);
+ wled_reg_write(PM_WLED_MAX_DUTY_CYCLE, wled_ctrl->max_duty_cycle);
+ wled_reg_write(PM_WLED_OVP, wled_ctrl->ovp);
+ wled_reg_write(LEDn_FULL_SCALE_CURRENT(1), wled_ctrl->full_current_scale);
+ wled_reg_write(LEDn_FULL_SCALE_CURRENT(2), wled_ctrl->full_current_scale);
+ wled_reg_write(LEDn_FULL_SCALE_CURRENT(3), wled_ctrl->full_current_scale);
dprintf(SPEW, "WLED Configuration Success.\n");
@@ -67,7 +86,7 @@
PM_WLED_LED3_SINK_MASK;
}
- REG_WRITE(PM_WLED_CURRENT_SINK, value);
+ wled_reg_write(PM_WLED_CURRENT_SINK, value);
dprintf(SPEW, "WLED Sink Success\n");
@@ -83,7 +102,7 @@
PM_WLED_LED1_ILED_SYNC_MASK;
}
- REG_WRITE(PM_WLED_ILED_SYNC_BIT, value);
+ wled_reg_write(PM_WLED_ILED_SYNC_BIT, value);
dprintf(SPEW, "WLED ILED Sync Success\n");
@@ -96,7 +115,7 @@
if (enable)
value = PM_WLED_ENABLE_MODULE_MASK;
- REG_WRITE(PM_WLED_ENABLE, value);
+ wled_reg_write(PM_WLED_ENABLE, value);
dprintf(SPEW, "WLED Enable Success\n");
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index ea8bbeb..5418229 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -128,6 +128,17 @@
#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+/* SDCC2 */
+#define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x508)
+#define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x510) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x514) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x518) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */
+
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
#define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x784)
@@ -144,9 +155,11 @@
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
/* SDHCI */
-#define SDCC_MCI_HC_MODE (PERIPH_SS_BASE + 0x00024078)
-#define SDCC_HC_PWRCTL_MASK_REG (PERIPH_SS_BASE + 0x000240E0)
-#define SDCC_HC_PWRCTL_CTL_REG (PERIPH_SS_BASE + 0x000240E8)
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
/* DRV strength for sdcc */
#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
diff --git a/platform/msm8226/include/platform/irqs.h b/platform/msm8226/include/platform/irqs.h
index 2e29d3a..c3abd2f 100644
--- a/platform/msm8226/include/platform/irqs.h
+++ b/platform/msm8226/include/platform/irqs.h
@@ -47,7 +47,9 @@
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
#define USB1_HS_IRQ (GIC_SPI_START + 134)
-#define SDCC_PWRCTRL_IRQ (GIC_SPI_START + 138)
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+#define SDCC3_PWRCTL_IRQ (GIC_SPI_START + 224)
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
diff --git a/platform/msm8226/msm8226-clock.c b/platform/msm8226/msm8226-clock.c
index bd0a265..4c4758d 100644
--- a/platform/msm8226/msm8226-clock.c
+++ b/platform/msm8226/msm8226-clock.c
@@ -166,6 +166,46 @@
},
};
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC2_M,
+ .n_reg = (uint32_t *) SDCC2_N,
+ .d_reg = (uint32_t *) SDCC2_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc2_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR,
+ .parent = &sdcc2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* UART Clocks */
static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
{
@@ -487,6 +527,9 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+ CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+ CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+
CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c),
diff --git a/platform/msm8610/acpuclock.c b/platform/msm8610/acpuclock.c
index f1dcba7..4376e68 100644
--- a/platform/msm8610/acpuclock.c
+++ b/platform/msm8610/acpuclock.c
@@ -121,9 +121,6 @@
snprintf(clk_name, 64, "sdc%u_core_clk", interface);
- /* Disalbe MCI_CLK before changing the sdcc clock */
- mmc_boot_mci_clk_disable();
-
if(freq == MMC_CLK_400KHZ)
{
ret = clk_get_set_enable(clk_name, 400000, 1);
@@ -132,6 +129,10 @@
{
ret = clk_get_set_enable(clk_name, 50000000, 1);
}
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
else
{
dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
@@ -143,9 +144,6 @@
dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
ASSERT(0);
}
-
- /* Enable MCI CLK */
- mmc_boot_mci_clk_enable();
}
/* Configure UART clock based on the UART block id*/
diff --git a/platform/msm8610/include/platform/gpio.h b/platform/msm8610/include/platform/gpio.h
index 02bc2e7..fe7cb8a 100644
--- a/platform/msm8610/include/platform/gpio.h
+++ b/platform/msm8610/include/platform/gpio.h
@@ -30,6 +30,7 @@
#define __PLATFORM_MSM8610_GPIO_H
#include <bits.h>
+#include <gpio.h>
/* GPIO TLMM: Direction */
#define GPIO_INPUT 0
diff --git a/platform/msm8610/include/platform/iomap.h b/platform/msm8610/include/platform/iomap.h
index 79344d7..f9f1c27 100644
--- a/platform/msm8610/include/platform/iomap.h
+++ b/platform/msm8610/include/platform/iomap.h
@@ -60,9 +60,11 @@
#define MSM_SDC1_BAM_BASE (PERIPH_SS_BASE + 0x00004000)
#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
#define MSM_SDC1_DML_BASE (PERIPH_SS_BASE + 0x00024800)
+#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
#define MSM_SDC2_BAM_BASE (PERIPH_SS_BASE + 0x00084000)
#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
#define MSM_SDC2_DML_BASE (PERIPH_SS_BASE + 0x000A4800)
+#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000)
#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000)
@@ -209,6 +211,17 @@
#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+/* SDCC2 */
+#define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x508)
+#define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x510) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x514) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x518) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */
+
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
@@ -224,4 +237,13 @@
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
+/* DRV strength for sdcc */
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
+
+/* SDHCI */
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
#endif
diff --git a/platform/msm8610/include/platform/irqs.h b/platform/msm8610/include/platform/irqs.h
index 6cecf4e..9c96345 100644
--- a/platform/msm8610/include/platform/irqs.h
+++ b/platform/msm8610/include/platform/irqs.h
@@ -47,6 +47,9 @@
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
#define USB1_HS_IRQ (GIC_SPI_START + 134)
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
diff --git a/platform/msm8610/msm8610-clock.c b/platform/msm8610/msm8610-clock.c
index a9b13b8..95cb4d3 100644
--- a/platform/msm8610/msm8610-clock.c
+++ b/platform/msm8610/msm8610-clock.c
@@ -166,6 +166,48 @@
},
};
+/* SDCC2 clocks */
+
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC2_M,
+ .n_reg = (uint32_t *) SDCC2_N,
+ .d_reg = (uint32_t *) SDCC2_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc2_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR,
+ .parent = &sdcc2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* UART Clocks */
static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
{
@@ -413,6 +455,9 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+ CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+ CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+
CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index d817506..b3edca9 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -139,6 +139,17 @@
#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+/* SDCC2 */
+#define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x508)
+#define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x510) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x514) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x518) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */
+
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
@@ -208,7 +219,9 @@
#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
/* SDHCI */
-#define SDCC_MCI_HC_MODE (PERIPH_SS_BASE + 0x00024078)
-#define SDCC_HC_PWRCTL_MASK_REG (PERIPH_SS_BASE + 0x000240E0)
-#define SDCC_HC_PWRCTL_CTL_REG (PERIPH_SS_BASE + 0x000240E8)
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
#endif
diff --git a/platform/msm8974/include/platform/irqs.h b/platform/msm8974/include/platform/irqs.h
index 56ef1cb..e9b2d06 100644
--- a/platform/msm8974/include/platform/irqs.h
+++ b/platform/msm8974/include/platform/irqs.h
@@ -66,5 +66,8 @@
((GIC_SPI_START + 95) + qup_id):\
((GIC_SPI_START + 101) + qup_id))
-#define SDCC_PWRCTRL_IRQ (GIC_SPI_START + 138)
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+#define SDCC3_PWRCTL_IRQ (GIC_SPI_START + 224)
+#define SDCC4_PWRCTL_IRQ (GIC_SPI_START + 227)
#endif /* __IRQS_COPPER_H */
diff --git a/platform/msm8974/msm8974-clock.c b/platform/msm8974/msm8974-clock.c
index cb12667..991fe17 100644
--- a/platform/msm8974/msm8974-clock.c
+++ b/platform/msm8974/msm8974-clock.c
@@ -168,6 +168,46 @@
},
};
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC2_M,
+ .n_reg = (uint32_t *) SDCC2_N,
+ .d_reg = (uint32_t *) SDCC2_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc2_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR,
+ .parent = &sdcc2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* UART Clocks */
static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
{
@@ -646,6 +686,9 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+ CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+ CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+
CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
diff --git a/platform/msm_shared/bam.c b/platform/msm_shared/bam.c
index bd7a595..5deaecf 100644
--- a/platform/msm_shared/bam.c
+++ b/platform/msm_shared/bam.c
@@ -79,6 +79,7 @@
enum p_int_type interrupt)
{
uint32_t val;
+ uint32_t bamsts;
while (1)
{
@@ -90,8 +91,12 @@
} while (!((val & 0x7FFF) & (1 << bam->pipe[pipe_num].pipe_num)));
/* Check the reason for this BAM interrupt */
- if (readl(BAM_IRQ_STTS(bam->base)))
+ bamsts = readl(BAM_IRQ_STTS(bam->base));
+ if (bamsts)
+ {
+ dprintf(CRITICAL,"ERROR:BAM_IRQ_STTS %u \n", bamsts);
goto bam_wait_int_error;
+ }
/* Check the interrupt type */
/* Read interrupt status register */
@@ -109,17 +114,11 @@
writel (val, BAM_P_IRQ_CLRn(bam->pipe[pipe_num].pipe_num, bam->base));
return BAM_RESULT_SUCCESS;
}
- else if (val & P_TRNSFR_END_EN_MASK)
- {
- dprintf(CRITICAL,
- "Trasfer end signalled before the last descc was processed\n");
- goto bam_wait_int_error;
- }
}
bam_wait_int_error:
- dprintf(CRITICAL, "Unexpected interrupt\n");
+ dprintf(CRITICAL, "Unexpected interrupt : val %u\n", val);
return BAM_RESULT_FAILURE;
}
@@ -128,7 +127,7 @@
{
uint32_t int_mask = P_ERR_EN_MASK | P_OUT_OF_DESC_EN_MASK |
- P_PRCSD_DESC_EN_MASK | P_TRNSFR_END_EN_MASK;
+ P_PRCSD_DESC_EN_MASK;
uint32_t val;
/* Leave BAM error interrupts disabled. */
@@ -223,6 +222,9 @@
/* Initialize FIFO offset for the first read */
bam->pipe[pipe_num].fifo.offset = BAM_DESC_SIZE;
+ writel(P_ENABLE | readl(BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base)),
+ BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base));
+
/* Everything is set.
* Flag pipe init done.
*/
@@ -243,9 +245,9 @@
/* Pipe event threshold register is not relevant in sys modes */
/* Enable pipe in system mode and set the direction */
- writel(P_SYS_MODE_MASK | P_ENABLE |
- (bam->pipe[pipe_num].trans_type << P_DIRECTION_SHIFT),
- BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base));
+ writel(P_SYS_MODE_MASK | bam->pipe[pipe_num].lock_grp << P_LOCK_GRP_SHIFT |
+ (bam->pipe[pipe_num].trans_type << P_DIRECTION_SHIFT),
+ BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base));
/* Mark the pipe FIFO as uninitialized. */
bam->pipe[pipe_num].initialized = 0;
diff --git a/platform/msm_shared/crypto5_eng.c b/platform/msm_shared/crypto5_eng.c
index 669d6ac..ed5c8ad 100644
--- a/platform/msm_shared/crypto5_eng.c
+++ b/platform/msm_shared/crypto5_eng.c
@@ -256,6 +256,7 @@
dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].trans_type = BAM2SYS;
dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.size = params->read_fifo_size;
dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.head = crypto_allocate_fifo(params->read_fifo_size);
+ dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].lock_grp = params->pipes.read_pipe_grp;
/* Set Write pipe params. */
dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].pipe_num = params->pipes.write_pipe;
@@ -263,6 +264,7 @@
dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].trans_type = SYS2BAM;
dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.size = params->write_fifo_size;
dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.head = crypto_allocate_fifo(params->write_fifo_size);
+ dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].lock_grp = params->pipes.write_pipe_grp;
dev->bam.threshold = CRYPTO_MAX_THRESHOLD;
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index ee0582d..6b596fa 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -52,6 +52,75 @@
*/
extern int check_aboot_addr_range_overlap(uint32_t start, uint32_t size);
+struct msm_id
+{
+ uint32_t platform_id;
+ uint32_t hardware_id;
+ uint32_t soc_rev;
+};
+
+/* Returns soc version if platform id and hardware id matches
+ otherwise return 0xFFFFFFFF */
+#define INVALID_SOC_REV_ID 0XFFFFFFFF
+static uint32_t dev_tree_compatible(void *dtb)
+{
+ int root_offset;
+ const void *prop;
+ char model[128];
+ struct msm_id msm_id;
+ int len;
+
+ root_offset = fdt_path_offset(dtb, "/");
+ if (root_offset < 0)
+ return false;
+
+ prop = fdt_getprop(dtb, root_offset, "model", &len);
+ if (prop && len > 0) {
+ memcpy(model, prop, MIN((int)sizeof(model), len));
+ model[sizeof(model) - 1] = '\0';
+ } else {
+ model[0] = '\0';
+ }
+
+ prop = fdt_getprop(dtb, root_offset, "qcom,msm-id", &len);
+ if (!prop || len <= 0) {
+ dprintf(INFO, "qcom,msm-id entry not found\n");
+ return false;
+ } else if (len < (int)sizeof(struct msm_id)) {
+ dprintf(INFO, "qcom,msm-id entry size mismatch (%d != %d)\n",
+ len, sizeof(struct msm_id));
+ return false;
+ }
+ msm_id.platform_id = fdt32_to_cpu(((const struct msm_id *)prop)->platform_id);
+ msm_id.hardware_id = fdt32_to_cpu(((const struct msm_id *)prop)->hardware_id);
+ msm_id.soc_rev = fdt32_to_cpu(((const struct msm_id *)prop)->soc_rev);
+
+ dprintf(INFO, "Found an appended flattened device tree (%s - %d %d 0x%x)\n",
+ *model ? model : "unknown",
+ msm_id.platform_id, msm_id.hardware_id, msm_id.soc_rev);
+
+ if (msm_id.platform_id != board_platform_id() ||
+ msm_id.hardware_id != board_hardware_id()) {
+ dprintf(INFO, "Device tree's msm_id doesn't match the board: <%d %d 0x%x> != <%d %d 0x%x>\n",
+ msm_id.platform_id,
+ msm_id.hardware_id,
+ msm_id.soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_soc_version());
+ return INVALID_SOC_REV_ID;
+ }
+
+ dprintf(INFO, "Device tree's msm_id matchs the board: <%d %d 0x%x> != <%d %d 0x%x>\n",
+ msm_id.platform_id,
+ msm_id.hardware_id,
+ msm_id.soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_soc_version());
+ return msm_id.soc_rev;
+}
+
/*
* Will relocate the DTB to the tags addr if the device tree is found and return
* its address
@@ -63,46 +132,66 @@
* Return Value: DTB address : If appended device tree is found
* 'NULL' : Otherwise
*/
-void *dev_tree_appended(void *kernel, void *tags, uint32_t kernel_size)
+void *dev_tree_appended(void *kernel, uint32_t kernel_size, void *tags)
{
+ void *kernel_end = kernel + kernel_size;
uint32_t app_dtb_offset = 0;
- uint32_t size;
+ void *dtb;
+ void *bestmatch_tag = NULL;
+ uint32_t bestmatch_tag_size;
+ uint32_t bestmatch_soc_rev_id = INVALID_SOC_REV_ID;
memcpy((void*) &app_dtb_offset, (void*) (kernel + DTB_OFFSET), sizeof(uint32_t));
- /*
- * Check if we have valid offset for the DTB, if not return error.
- * If the kernel image does not have appeneded device tree, DTB offset
- * might contain some random address which is not accessible & cause
- * data abort. If kernel start + dtb offset address exceed the total
- * size of the kernel, then we dont have an appeneded DTB.
- */
- if (app_dtb_offset < kernel_size)
- {
- if (!fdt_check_header((void*) (kernel + app_dtb_offset)))
- {
- void *dtb;
- int rc;
+ dtb = kernel + app_dtb_offset;
+ while (dtb + sizeof(struct fdt_header) < kernel_end) {
+ uint32_t dtb_soc_rev_id;
+ struct fdt_header dtb_hdr;
+ uint32_t dtb_size;
- dprintf(INFO, "Found Appeneded Flattened Device tree\n");
- dtb = kernel + app_dtb_offset;
- size = fdt_totalsize(dtb);
- if (check_aboot_addr_range_overlap(tags, size))
- {
- dprintf(CRITICAL, "Appended dtb aboot overlap check failed.\n");
- return NULL;
- }
- rc = fdt_open_into(dtb, tags, size);
- if (rc == 0)
- {
- /* clear out the old DTB magic so kernel doesn't find it */
- *((uint32_t *)dtb) = 0;
- return tags;
+ /* the DTB could be unaligned, so extract the header,
+ * and operate on it separately */
+ memcpy(&dtb_hdr, dtb, sizeof(struct fdt_header));
+ if (fdt_check_header((const void *)&dtb_hdr) != 0 ||
+ (dtb + fdt_totalsize((const void *)&dtb_hdr) > kernel_end))
+ break;
+ dtb_size = fdt_totalsize(&dtb_hdr);
+
+ /* now that we know we have a valid DTB, we need to copy
+ * it somewhere aligned, like tags */
+ memcpy(tags, dtb, dtb_size);
+
+ dtb_soc_rev_id = dev_tree_compatible(tags);
+ if (dtb_soc_rev_id == board_soc_version()) {
+ /* clear out the old DTB magic so kernel doesn't find it */
+ *((uint32_t *)(kernel + app_dtb_offset)) = 0;
+ return tags;
+ } else if ((dtb_soc_rev_id != INVALID_SOC_REV_ID) &&
+ (dtb_soc_rev_id < board_soc_version())) {
+ /* if current bestmatch is less than new dtb_soc_rev_id then update
+ bestmatch_tag */
+ if((bestmatch_soc_rev_id == INVALID_SOC_REV_ID) ||
+ (bestmatch_soc_rev_id < dtb_soc_rev_id)) {
+ bestmatch_tag = dtb;
+ bestmatch_tag_size = dtb_size;
+ bestmatch_soc_rev_id = dtb_soc_rev_id;
}
}
+
+ /* goto the next device tree if any */
+ dtb += dtb_size;
}
- else
- dprintf(CRITICAL, "DTB offset is incorrect, kernel image does not have appended DTB\n");
+
+ if(bestmatch_tag) {
+ dprintf(INFO,"DTB found with bestmatch soc rev id 0x%x.Board soc rev id 0x%x\n",
+ bestmatch_soc_rev_id, board_soc_version());
+ memcpy(tags, bestmatch_tag, bestmatch_tag_size);
+ /* clear out the old DTB magic so kernel doesn't find it */
+ *((uint32_t *)(kernel + app_dtb_offset)) = 0;
+ return tags;
+ }
+
+ dprintf(CRITICAL, "DTB offset is incorrect, kernel image does not have appended DTB\n");
return NULL;
}
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
old mode 100755
new mode 100644
index 026142c..3768ca8
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -112,8 +112,8 @@
break;
case MIPI_CMD_PANEL:
dprintf(INFO, "Config MIPI_CMD_PANEL.\n");
-
- if (mdp_get_revision() == MDP_REV_50)
+ mdp_rev = mdp_get_revision();
+ if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304)
ret = mdss_dsi_config(panel);
else
ret = mipi_config(panel);
@@ -150,6 +150,7 @@
int msm_display_on()
{
int ret = NO_ERROR;
+ int mdp_rev;
struct msm_panel_info *pinfo;
if (!panel)
@@ -183,7 +184,8 @@
ret = mdp_dma_on();
if (ret)
goto msm_display_on_out;
- if (mdp_get_revision() != MDP_REV_50) {
+ mdp_rev = mdp_get_revision();
+ if (mdp_rev != MDP_REV_50 && mdp_rev != MDP_REV_304) {
ret = mipi_cmd_trigger();
if (ret)
goto msm_display_on_out;
@@ -283,7 +285,7 @@
ret = mdp_dsi_video_off();
if (ret)
goto msm_display_off_out;
- ret = mipi_dsi_off();
+ ret = mipi_dsi_off(pinfo);
if (ret)
goto msm_display_off_out;
break;
@@ -292,7 +294,7 @@
ret = mdp_dsi_cmd_off();
if (ret)
goto msm_display_off_out;
- ret = mipi_dsi_off();
+ ret = mipi_dsi_off(pinfo);
if (ret)
goto msm_display_off_out;
break;
diff --git a/platform/msm_shared/include/bam.h b/platform/msm_shared/include/bam.h
index 099b1b6..ae673ab 100644
--- a/platform/msm_shared/include/bam.h
+++ b/platform/msm_shared/include/bam.h
@@ -81,6 +81,7 @@
#define P_SYS_MODE_MASK (1 << 5)
/* 1: Producer mode 0: Consumer mode */
#define P_DIRECTION_SHIFT 3
+#define P_LOCK_GRP_SHIFT 16
#define P_ENABLE (1 << 1)
#define BAM_P_RSTn(n, x) (0x00001000 + 0x4 + 0x1000 * (n) + (x))
@@ -198,6 +199,7 @@
uint8_t spi_num;
uint8_t int_mode;
uint8_t initialized;
+ uint8_t lock_grp;
};
/* Structure to define a BAM instance being used
diff --git a/platform/msm_shared/include/crypto5_eng.h b/platform/msm_shared/include/crypto5_eng.h
index 958fa1a..872f46e 100644
--- a/platform/msm_shared/include/crypto5_eng.h
+++ b/platform/msm_shared/include/crypto5_eng.h
@@ -103,6 +103,8 @@
{
uint8_t read_pipe;
uint8_t write_pipe;
+ uint8_t read_pipe_grp;
+ uint8_t write_pipe_grp;
};
struct output_dump
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
index d0b0ca8..2a8ee01 100644
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -70,5 +70,5 @@
int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info);
int update_device_tree(void *, const char *, void *, unsigned);
int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint32_t size, uint32_t addr);
-void *dev_tree_appended(void *kernel, void *tags, uint32_t kernel_size);
+void *dev_tree_appended(void *kernel, uint32_t kernel_size, void *tags);
#endif
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 6a00efa..4f90f96 100755
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -1000,7 +1000,7 @@
unsigned char eof_bllp_pwr,
unsigned char interleav);
int mipi_dsi_on();
-int mipi_dsi_off();
+int mipi_dsi_off(struct msm_panel_info *pinfo);
int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count);
int mipi_dsi_cmds_rx(char **rp, int len);
#endif
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index 6aa323d..79d3965 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -143,6 +143,44 @@
#define MMC_ADDR_OUT_OF_RANGE(resp) ((resp >> 31) & 0x01)
+/* SD card related Macros */
+/* Arguments for commands */
+#define MMC_SD_HC_VOLT_SUPPLIED 0x000001AA
+#define MMC_SD_OCR 0x00FF8000
+#define MMC_SD_HC_HCS 0x40000000
+#define MMC_SD_DEV_READY 0x80000000
+#define MMC_CARD_TYPE_SDHC 0x1
+#define MMC_CARD_TYPE_STD_SD 0x0
+#define SD_CARD_RCA 0x0
+#define MMC_SD_SWITCH_HS 0x80FFFFF1
+
+#define SD_CMD8_MAX_RETRY 0x3
+#define SD_ACMD41_MAX_RETRY 0x14
+
+/* SCR(SD Card Register) related */
+#define SD_SCR_BUS_WIDTH 16
+#define SD_SCR_SD_SPEC 24
+#define SD_SCR_SD_SPEC3 15
+#define SD_SCR_BUS_WIDTH_MASK 0xf0000
+#define SD_SCR_SD_SPEC_MASK 0x0f000000
+#define SD_SCR_SD_SPEC3_MASK 0x8000
+#define SD_SCR_CMD23_SUPPORT BIT(1)
+#define SD_SCR_WIDTH_4BIT BIT(2)
+
+/* SSR related macros */
+#define MMC_SD_AU_SIZE_BIT 428
+#define MMC_SD_AU_SIZE_LEN 4
+#define MMC_SD_ERASE_SIZE_BIT 408
+#define MMC_SD_ERASE_SIZE_LEN 16
+
+/* Commands for SD card */
+#define CMD8_SEND_IF_COND 8
+#define ACMD6_SET_BUS_WIDTH 6
+#define ACMD13_SEND_SD_STATUS 13
+#define ACMD41_SEND_OP_COND 41
+#define ACMD51_READ_CARD_SCR 51
+#define CMD55_APP_CMD 55
+
/* Can be used to unpack array of upto 32 bits data */
#define UNPACK_BITS(array, start, len, size_of) \
({ \
@@ -156,6 +194,20 @@
unpck & mask; \
})
+#define swap_endian32(x) \
+ ((uint32_t)( \
+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
+ (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \
+ (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \
+ (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24) ))
+
+
+#define MMC_CARD_SD(card) ((card->type == MMC_CARD_TYPE_SDHC) || \
+ (card->type == MMC_CARD_TYPE_STD_SD))
+
+#define MMC_CARD_MMC(card) ((card->type == MMC_TYPE_STD_MMC) || \
+ (card->type == MMC_TYPE_MMCHC))
+
/* CSD Register.
* Note: not all the fields have been defined here
*/
@@ -196,6 +248,20 @@
uint32_t year; /* 4 bits manufacturing year */
};
+/* SCR register for SD card */
+struct mmc_sd_scr {
+ uint32_t bus_widths; /* Bus width support, 8 or 1 bit */
+ uint32_t sd_spec; /* sd spec version */
+ uint32_t sd3_spec; /* sd spec 3 version */
+ uint32_t cmd23_support; /* cmd23 supported or not */
+};
+
+/* SD Status Register */
+struct mmc_sd_ssr {
+ uint32_t au_size; /* Allocation unit (AU) size */
+ uint32_t num_aus; /* Number of AUs */
+};
+
/* mmc card register */
struct mmc_card {
uint32_t rca; /* Relative addres of the card*/
@@ -205,14 +271,19 @@
uint32_t status; /* Card status */
uint8_t *ext_csd; /* Ext CSD for the card info */
uint32_t raw_csd[4]; /* Raw CSD for the card */
+ uint32_t raw_scr[2]; /* SCR for SD card */
struct mmc_cid cid; /* CID structure */
struct mmc_csd csd; /* CSD structure */
+ struct mmc_sd_scr scr; /* SCR structure */
+ struct mmc_sd_ssr ssr; /* SSR Register */
};
/* mmc device config data */
struct mmc_config_data {
uint8_t slot; /* Sdcc slot used */
- uint32_t base; /* Based address for the sdcc */
+ uint8_t pwr_irq; /* Power Irq from card to host */
+ uint32_t sdhc_base; /* Base address for the sdhc */
+ uint32_t pwrctl_base; /* Base address for power control registers */
uint16_t bus_width; /* Bus width used */
uint32_t max_clk_rate; /* Max clock rate supported */
};
diff --git a/platform/msm_shared/include/partition_parser.h b/platform/msm_shared/include/partition_parser.h
index 0508e00..25a73ca 100644
--- a/platform/msm_shared/include/partition_parser.h
+++ b/platform/msm_shared/include/partition_parser.h
@@ -162,6 +162,7 @@
unsigned long long partition_get_offset(int index);
unsigned int partition_read_table();
unsigned int write_partition(unsigned size, unsigned char *partition);
+bool partition_gpt_exists();
/* For Debugging */
void partition_dump(void);
diff --git a/platform/msm_shared/include/qpic_nand.h b/platform/msm_shared/include/qpic_nand.h
index abc2bb9..0676301 100644
--- a/platform/msm_shared/include/qpic_nand.h
+++ b/platform/msm_shared/include/qpic_nand.h
@@ -325,6 +325,9 @@
unsigned read_pipe;
unsigned write_pipe;
unsigned cmd_pipe;
+ uint8_t read_pipe_grp;
+ uint8_t write_pipe_grp;
+ uint8_t cmd_pipe_grp;
};
/* Structure to define the initial nand config */
diff --git a/platform/msm_shared/include/sdhci.h b/platform/msm_shared/include/sdhci.h
index 20861fc..ef48d1d 100644
--- a/platform/msm_shared/include/sdhci.h
+++ b/platform/msm_shared/include/sdhci.h
@@ -31,6 +31,7 @@
#include <reg.h>
#include <bits.h>
+#include <kernel/event.h>
/*
* Capabilities for the host controller
@@ -55,6 +56,7 @@
struct sdhci_host {
uint32_t base; /* Base address for the host */
uint32_t cur_clk_rate; /* Running clock rate */
+ event_t* sdhc_event; /* Event for power control irqs */
struct host_caps caps; /* Host capabilities */
};
@@ -79,6 +81,7 @@
uint32_t resp[4]; /* 128 bit response value */
uint32_t trans_mode; /* Transfer mode, read/write */
uint32_t cmd_retry; /* Retry the command, if card is busy */
+ uint32_t cmd23_support; /* If card supports cmd23 */
struct mmc_data data; /* Data pointer */
};
@@ -239,6 +242,7 @@
#define SDHCI_BLK_CNT_EN BIT(1)
#define SDHCI_DMA_EN BIT(0)
#define SDHCI_AUTO_CMD23_EN BIT(3)
+#define SDHCI_AUTO_CMD12_EN BIT(2)
#define SDHCI_ADMA_32BIT BIT(4)
/*
diff --git a/platform/msm_shared/include/sdhci_msm.h b/platform/msm_shared/include/sdhci_msm.h
new file mode 100644
index 0000000..1d77823
--- /dev/null
+++ b/platform/msm_shared/include/sdhci_msm.h
@@ -0,0 +1,43 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SDHCI_MSM_H__
+#define __SDHCI_MSM_H__
+
+#include <kernel/event.h>
+
+struct sdhci_msm_data
+{
+ uint32_t pwrctl_base;
+ uint32_t pwr_irq;
+ event_t* sdhc_event;
+};
+
+void sdhci_msm_init(struct sdhci_msm_data *data);
+
+#endif
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index dae558b..169dce5 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -165,7 +165,7 @@
int mdp_dma_on()
{
int ret = 0;
-
+ mdelay(100);
writel(0x00000001, MDP_DMA_P_START);
return ret;
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index bbda314..6b6e6c6 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -951,7 +951,6 @@
unsigned char eof_bllp_pwr,
unsigned char interleav)
{
-
int status = 0;
/* disable mdp first */
@@ -1033,16 +1032,27 @@
uint16_t img_width,
uint16_t img_height,
uint16_t dst_format,
- uint16_t traffic_mode)
+ uint8_t ystride,
+ uint8_t lane_en,
+ uint8_t interleav)
{
- uint8_t DST_FORMAT;
- uint8_t TRAFIC_MODE;
- uint8_t DLNx_EN;
- // video mode data ctrl
- int status = 0;
- uint8_t interleav = 0;
- uint8_t ystride = 0x03;
- // disable mdp first
+ uint16_t dst_fmt = 0;
+
+ switch (dst_format) {
+ case DSI_VIDEO_DST_FORMAT_RGB565:
+ dst_fmt = DSI_CMD_DST_FORMAT_RGB565;
+ break;
+ case DSI_VIDEO_DST_FORMAT_RGB666:
+ case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE:
+ dst_fmt = DSI_CMD_DST_FORMAT_RGB666;
+ break;
+ case DSI_VIDEO_DST_FORMAT_RGB888:
+ dst_fmt = DSI_CMD_DST_FORMAT_RGB888;
+ break;
+ default:
+ dprintf(CRITICAL, "unsupported dst format\n");
+ return ERROR;
+ }
#if (DISPLAY_TYPE_MDSS == 1)
writel(0x00000000, DSI_CLK_CTRL);
@@ -1061,16 +1071,7 @@
writel(0x02020202, DSI_INT_CTRL);
- DST_FORMAT = 8; // RGB888
- dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n");
-
- DLNx_EN = 0xf; // 4 lane with clk programming
- dprintf(SPEW, "Data Lane: 4 lane\n");
-
- TRAFIC_MODE = 0; // non burst mode with sync pulses
- dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
-
- writel(DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL);
+ writel(dst_fmt, DSI_COMMAND_MODE_MDP_CTRL);
writel((img_width * ystride + 1) << 16 | 0x0039,
DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
writel((img_width * ystride + 1) << 16 | 0x0039,
@@ -1080,13 +1081,13 @@
writel(img_height << 16 | img_width,
DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
- writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105,
+ writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105,
DSI_CTRL);
writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
writel(0x10000000, DSI_MISR_CMD_CTRL);
#endif
- return NO_ERROR;
+ return 0;
}
int mipi_dsi_cmd_mode_config(unsigned short disp_width,
@@ -1175,7 +1176,7 @@
return ret;
}
-int mipi_dsi_off()
+int mipi_dsi_off(struct msm_panel_info *pinfo)
{
if(!target_cont_splash_screen())
{
@@ -1189,6 +1190,8 @@
}
writel(0x1115501, DSI_INT_CTRL);
+ if (pinfo->mipi.broadcast)
+ writel(0x1115501, DSI_INT_CTRL + 0x600);
return NO_ERROR;
}
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index e6bac4e..5616956 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -255,8 +255,13 @@
}
/* 6 enable seq for 8226 target */
- else if (platformid == MSM8226 ||
- platformid == MSM8626) {
+ else if (platformid == MSM8826 ||
+ platformid == MSM8626 ||
+ platformid == MSM8226 ||
+ platformid == MSM8926 ||
+ platformid == MSM8126 ||
+ platformid == MSM8326 ||
+ platformid == APQ8026) {
if (dsi_pll_enable_seq_m()) {
} else if (dsi_pll_enable_seq_d()) {
} else if (dsi_pll_enable_seq_d()) {
@@ -267,7 +272,7 @@
dprintf(CRITICAL, "Not able to enable the pll\n");
}
} else {
- dprintf(CRITICAL, "Target not supported\n");
+ dprintf(CRITICAL, "Target not supported in auto PLL\n");
}
}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index ff7b443..e3a4527 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -408,6 +408,8 @@
writel(0x5F, ctl_base + off + (4 * 0));
off = 0x500;
+ /* use LDO mode */
+ writel(0x25, ctl_base + 0x4B0);
for (i = 0; i < 5; i++)
writel(pd->regulator[i], ctl_base + off + (4 * i));
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index d4b0bd4..8dae760 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -32,6 +32,7 @@
#include <reg.h>
#include <mmc_sdhci.h>
#include <sdhci.h>
+#include <sdhci_msm.h>
#include <partition_parser.h>
#include <platform/iomap.h>
#include <platform/timer.h>
@@ -85,8 +86,7 @@
mmc_csd.cmmc_structure = UNPACK_BITS(raw_csd, 126, 2, mmc_sizeof);
- if ((card->type == MMC_TYPE_SDHC)
- || (card->type == MMC_TYPE_STD_SD)) {
+ if (MMC_CARD_SD(card)) {
/* Parse CSD according to SD card spec. */
/* CSD register is little bit differnet for CSD version 2.0 High
@@ -133,7 +133,7 @@
mmc_csd.temp_wp = UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof);
/* Calculate the card capcity */
- card->capacity = (1 + mmc_csd.c_size) * 512 * 1024;
+ card->capacity = (unsigned long long) (1 + mmc_csd.c_size) * 512 * 1024;
} else {
/* CSD Version 1.0 */
mmc_csd.card_cmd_class = UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof);
@@ -177,7 +177,7 @@
/* Calculate the card capacity */
mmc_temp = (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size + 1);
- card->capacity = mmc_temp * mmc_csd.read_blk_len;
+ card->capacity = (unsigned long long)mmc_temp * mmc_csd.read_blk_len;
}
} else {
/* Parse CSD according to MMC card spec. */
@@ -213,7 +213,7 @@
if (mmc_csd.c_size != 0xFFF) {
/* For cards less than or equal to 2GB */
mmc_temp = (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size + 1);
- card->capacity = mmc_temp * mmc_csd.read_blk_len;
+ card->capacity = (unsigned long long) mmc_temp * mmc_csd.read_blk_len;
} else {
/* For cards greater than 2GB, Ext CSD register's SEC_COUNT
* is used to calculate the size.
@@ -224,7 +224,6 @@
| (card->ext_csd[MMC_SEC_COUNT3] << MMC_SEC_COUNT3_SHIFT)
| (card->ext_csd[MMC_SEC_COUNT2] << MMC_SEC_COUNT2_SHIFT)
| card->ext_csd[MMC_SEC_COUNT1];
-
card->capacity = sec_count * MMC_BLK_SZ;
}
}
@@ -234,22 +233,22 @@
sizeof(struct mmc_csd));
dprintf(SPEW, "Decoded CSD fields:\n");
- dprintf(SPEW, "cmmc_structure: %d\n", mmc_csd.cmmc_structure);
+ dprintf(SPEW, "cmmc_structure: %u\n", mmc_csd.cmmc_structure);
dprintf(SPEW, "card_cmd_class: %x\n", mmc_csd.card_cmd_class);
- dprintf(SPEW, "write_blk_len: %d\n", mmc_csd.write_blk_len);
- dprintf(SPEW, "read_blk_len: %d\n", mmc_csd.read_blk_len);
- dprintf(SPEW, "r2w_factor: %d\n", mmc_csd.r2w_factor);
- dprintf(SPEW, "sector_size: %d\n", mmc_csd.sector_size);
- dprintf(SPEW, "c_size_mult:%d\n", mmc_csd.c_size_mult);
- dprintf(SPEW, "c_size: %d\n", mmc_csd.c_size);
- dprintf(SPEW, "nsac_clk_cycle: %d\n", mmc_csd.nsac_clk_cycle);
- dprintf(SPEW, "taac_ns: %d\n", mmc_csd.taac_ns);
- dprintf(SPEW, "tran_speed: %d kbps\n", mmc_csd.tran_speed);
- dprintf(SPEW, "erase_blk_len: %d\n", mmc_csd.erase_blk_len);
- dprintf(SPEW, "read_blk_misalign: %d\n", mmc_csd.read_blk_misalign);
- dprintf(SPEW, "write_blk_misalign: %d\n", mmc_csd.write_blk_misalign);
- dprintf(SPEW, "read_blk_partial: %d\n", mmc_csd.read_blk_partial);
- dprintf(SPEW, "write_blk_partial: %d\n", mmc_csd.write_blk_partial);
+ dprintf(SPEW, "write_blk_len: %u\n", mmc_csd.write_blk_len);
+ dprintf(SPEW, "read_blk_len: %u\n", mmc_csd.read_blk_len);
+ dprintf(SPEW, "r2w_factor: %u\n", mmc_csd.r2w_factor);
+ dprintf(SPEW, "sector_size: %u\n", mmc_csd.sector_size);
+ dprintf(SPEW, "c_size_mult:%u\n", mmc_csd.c_size_mult);
+ dprintf(SPEW, "c_size: %u\n", mmc_csd.c_size);
+ dprintf(SPEW, "nsac_clk_cycle: %u\n", mmc_csd.nsac_clk_cycle);
+ dprintf(SPEW, "taac_ns: %u\n", mmc_csd.taac_ns);
+ dprintf(SPEW, "tran_speed: %u kbps\n", mmc_csd.tran_speed);
+ dprintf(SPEW, "erase_blk_len: %u\n", mmc_csd.erase_blk_len);
+ dprintf(SPEW, "read_blk_misalign: %u\n", mmc_csd.read_blk_misalign);
+ dprintf(SPEW, "write_blk_misalign: %u\n", mmc_csd.write_blk_misalign);
+ dprintf(SPEW, "read_blk_partial: %u\n", mmc_csd.read_blk_partial);
+ dprintf(SPEW, "write_blk_partial: %u\n", mmc_csd.write_blk_partial);
dprintf(SPEW, "Card Capacity: %llu Bytes\n", card->capacity);
return 0;
@@ -274,8 +273,7 @@
mmc_sizeof = sizeof(uint32_t) * 8;
- if ((card->type == MMC_TYPE_SDHC) ||
- (card->type == MMC_TYPE_STD_SD)) {
+ if (MMC_CARD_SD(card)) {
mmc_cid.mid = UNPACK_BITS(raw_cid, 120, 8, mmc_sizeof);
mmc_cid.oid = UNPACK_BITS(raw_cid, 104, 16, mmc_sizeof);
@@ -289,7 +287,7 @@
mmc_cid.pnm[6] = 0;
mmc_cid.prv = UNPACK_BITS(raw_cid, 56, 8, mmc_sizeof);
- mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 31, mmc_sizeof);
+ mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 32, mmc_sizeof);
mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof);
mmc_cid.year = UNPACK_BITS(raw_cid, 12, 8, mmc_sizeof);
mmc_cid.year += 2000;
@@ -304,7 +302,7 @@
mmc_cid.pnm[6] = 0;
mmc_cid.prv = UNPACK_BITS(raw_cid, 48, 8, mmc_sizeof);
- mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 31, mmc_sizeof);
+ mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 32, mmc_sizeof);
mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof);
mmc_cid.year = UNPACK_BITS(raw_cid, 12, 4, mmc_sizeof);
mmc_cid.year += 1997;
@@ -467,8 +465,7 @@
/* CMD3 Format:
* [31:0] stuff bits
*/
- if (card->type == MMC_TYPE_SDHC ||
- card->type == MMC_TYPE_STD_SD) {
+ if (MMC_CARD_SD(card)) {
cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR;
cmd.argument = 0;
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
@@ -535,14 +532,13 @@
/*
* Function: mmc select card
- * Arg : host, card structure & RCA
+ * Arg : host, card structure
* Return : 0 on Success, 1 on Failure
* Flow : Selects a card by sending CMD7 to the card with its RCA.
* If RCA field is set as 0 ( or any other address ),
* the card will be de-selected. (CMD7)
*/
-static uint32_t mmc_select_card(struct sdhci_host *host, struct mmc_card *card,
- uint32_t rca)
+static uint32_t mmc_select_card(struct sdhci_host *host, struct mmc_card *card)
{
struct mmc_command cmd;
uint32_t mmc_arg = 0;
@@ -554,16 +550,15 @@
* [31:16] RCA
* [15:0] stuff bits
*/
- mmc_arg |= rca << 16;
+ mmc_arg |= card->rca << 16;
cmd.cmd_index = CMD7_SELECT_DESELECT_CARD;
cmd.argument = mmc_arg;
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
/* If we are deselecting card, we do not get response */
- if (rca == card->rca && rca) {
- if (card->type == MMC_TYPE_SDHC ||
- card->type == MMC_TYPE_STD_SD)
+ if (card->rca) {
+ if (MMC_CARD_SD(card))
cmd.resp_type = SDHCI_CMD_RESP_R1B;
else
cmd.resp_type = SDHCI_CMD_RESP_R1;
@@ -896,10 +891,27 @@
struct sdhci_host *host;
struct mmc_config_data *cfg;
+ struct sdhci_msm_data data;
+
+ event_t sdhc_event;
host = &dev->host;
cfg = &dev->config;
+ event_init(&sdhc_event, false, EVENT_FLAG_AUTOUNSIGNAL);
+
+ host->base = cfg->sdhc_base;
+ host->sdhc_event = &sdhc_event;
+
+ data.sdhc_event = &sdhc_event;
+ data.pwrctl_base = cfg->pwrctl_base;
+ data.pwr_irq = cfg->pwr_irq;
+
+ /*
+ * MSM specific sdhc init
+ */
+ sdhci_msm_init(&data);
+
/*
* Initialize the controller, read the host capabilities
* set power on mode
@@ -953,7 +965,7 @@
}
/* Select the card (CMD7) */
- mmc_return = mmc_select_card(host, card, card->rca);
+ mmc_return = mmc_select_card(host, card);
if (mmc_return) {
dprintf(CRITICAL, "Failure selecting the Card with RCA: %x\n",card->rca);
return mmc_return;
@@ -989,6 +1001,7 @@
* Send CMD1 to identify and reject cards that do not match host's VDD range
* profile. Cards sends its OCR register in response.
*/
+
mmc_return = mmc_send_op_cond(host, card);
/* OCR is not received, init could not complete */
@@ -1000,6 +1013,257 @@
return 0;
}
+static uint32_t mmc_send_app_cmd(struct sdhci_host *host, struct mmc_card *card)
+{
+ struct mmc_command cmd = {0};
+
+ cmd.cmd_index = CMD55_APP_CMD;
+ cmd.argument = (card->rca << 16);
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R1;
+
+ if (sdhci_send_command(host, &cmd))
+ {
+ dprintf(CRITICAL, "Failed Sending CMD55\n");
+ return 1;
+ }
+ return 0;
+}
+
+uint32_t mmc_sd_card_init(struct sdhci_host *host, struct mmc_card *card)
+{
+ uint8_t i;
+ uint32_t mmc_ret;
+ struct mmc_command cmd;
+
+ memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
+
+ /* Use the SD card RCA 0x0 during init */
+ card->rca = SD_CARD_RCA;
+
+ /* Send CMD8 for voltage check*/
+ for (i = 0 ;i < SD_CMD8_MAX_RETRY; i++)
+ {
+ cmd.cmd_index = CMD8_SEND_IF_COND;
+ cmd.argument = MMC_SD_HC_VOLT_SUPPLIED;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R7;
+
+ if (sdhci_send_command(host, &cmd))
+ {
+ dprintf(CRITICAL, "The response for CMD8 does not match the supplied value\n");
+ return 1;
+ }
+ else
+ {
+ /* If the command response echos the voltage back */
+ if (cmd.resp[0] == MMC_SD_HC_VOLT_SUPPLIED)
+ break;
+ }
+ /* As per SDCC the spec try for max three times with
+ * 1 ms delay
+ */
+ mdelay(1);
+ }
+
+ if (i == SD_CMD8_MAX_RETRY && (cmd.resp[0] != MMC_SD_HC_VOLT_SUPPLIED))
+ {
+ dprintf(CRITICAL, "Error: CMD8 response timed out\n");
+ return 1;
+ }
+
+ /* Send ACMD41 for OCR */
+ for (i = 0; i < SD_ACMD41_MAX_RETRY; i++)
+ {
+ /* Send APP_CMD before ACMD41*/
+ if (mmc_send_app_cmd(host, card))
+ {
+ dprintf(CRITICAL, "Failed sending App command\n");
+ return 1;
+ }
+
+ /* APP_CMD is successful, send ACMD41 now */
+ cmd.cmd_index = ACMD41_SEND_OP_COND;
+ cmd.argument = MMC_SD_OCR | MMC_SD_HC_HCS;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R3;
+
+ if (sdhci_send_command(host, &cmd))
+ {
+ dprintf(CRITICAL, "Failure sending ACMD41\n");
+ return 1;
+ }
+ else
+ {
+ if (cmd.resp[0] & MMC_SD_DEV_READY)
+ {
+ if (cmd.resp[0] & (1 << 30))
+ card->type = MMC_CARD_TYPE_SDHC;
+ else
+ card->type = MMC_CARD_TYPE_STD_SD;
+
+ break;
+ }
+ }
+ /*
+ * As per SDCC spec try for max 1 second
+ */
+ mdelay(50);
+ }
+
+ if (i == SD_ACMD41_MAX_RETRY && !(cmd.resp[0] & MMC_SD_DEV_READY))
+ {
+ dprintf(CRITICAL, "Error: ACMD41 response timed out\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * Function to read SD card information from SD status
+ */
+static uint32_t mmc_sd_get_card_ssr(struct sdhci_host *host, struct mmc_card *card)
+{
+ BUF_DMA_ALIGN(raw_sd_status, 64);
+ struct mmc_command cmd = {0};
+ uint32_t sd_status[16];
+ uint32_t *status = sd_status;
+ uint32_t au_size;
+ int i;
+ int j;
+
+ if (mmc_send_app_cmd(host, card))
+ {
+ dprintf(CRITICAL, "Failed sending App command\n");
+ return 1;
+ }
+
+ cmd.cmd_index = ACMD13_SEND_SD_STATUS;
+ cmd.argument = 0x0;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R2;
+ cmd.trans_mode = SDHCI_MMC_READ;
+ cmd.data_present = 0x1;
+ cmd.data.data_ptr = raw_sd_status;
+ cmd.data.num_blocks = 0x1;
+ cmd.data.blk_sz = 0x40;
+
+ /* send command */
+ if (sdhci_send_command(host, &cmd))
+ return 1;
+
+ memcpy(sd_status, raw_sd_status, sizeof(sd_status));
+
+ for (i = 15, j = 0; i >=0 ; i--, j++)
+ sd_status[i] = swap_endian32(sd_status[j]);
+
+ au_size = UNPACK_BITS(status, MMC_SD_AU_SIZE_BIT, MMC_SD_AU_SIZE_LEN, 32);
+ /* Card AU size in sectors */
+ card->ssr.au_size = 1 << (au_size + 4);
+ card->ssr.num_aus = UNPACK_BITS(status, MMC_SD_ERASE_SIZE_BIT, MMC_SD_ERASE_SIZE_LEN, 32);
+
+ return 0;
+}
+
+/*
+ * Function to read the SD CARD configuration register
+ */
+static uint32_t mmc_sd_get_card_scr(struct sdhci_host *host, struct mmc_card *card)
+{
+ BUF_DMA_ALIGN(scr_resp, 8);
+ struct mmc_command cmd = {0};
+ uint32_t raw_scr[2];
+
+ /* Now read the SCR register */
+ /* Send APP_CMD before ACMD51*/
+ if (mmc_send_app_cmd(host, card))
+ {
+ dprintf(CRITICAL, "Failed sending App command\n");
+ return 1;
+ }
+
+ cmd.cmd_index = ACMD51_READ_CARD_SCR;
+ cmd.argument = 0x0;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R1;
+ cmd.trans_mode = SDHCI_MMC_READ;
+ cmd.data_present = 0x1;
+ cmd.data.data_ptr = scr_resp;
+ cmd.data.num_blocks = 0x1;
+ cmd.data.blk_sz = 0x8;
+
+ /* send command */
+ if (sdhci_send_command(host, &cmd))
+ return 1;
+
+ memcpy(raw_scr, scr_resp, sizeof(raw_scr));
+
+ card->raw_scr[0] = swap_endian32(raw_scr[0]);
+ card->raw_scr[1] = swap_endian32(raw_scr[1]);
+
+ /*
+ * Parse & Populate the SCR data as per sdcc spec
+ */
+ card->scr.bus_widths = (card->raw_scr[0] & SD_SCR_BUS_WIDTH_MASK) >> SD_SCR_BUS_WIDTH;
+ card->scr.cmd23_support = (card->raw_scr[0] & SD_SCR_CMD23_SUPPORT);
+ card->scr.sd_spec = (card->raw_scr[0] & SD_SCR_SD_SPEC_MASK) >> SD_SCR_SD_SPEC;
+ card->scr.sd3_spec = (card->raw_scr[0] & SD_SCR_SD_SPEC3_MASK) >> SD_SCR_SD_SPEC3;
+
+ return 0;
+}
+
+/*
+ * Function: mmc_set_sd_bus_width
+ * Arg : host, device structure & width
+ * Return : 0 on Success, 1 on Failure
+ * Flow : Set the bus width for the card
+ */
+uint32_t mmc_sd_set_bus_width(struct sdhci_host *host, struct mmc_card *card, uint8_t width)
+{
+ struct mmc_command cmd = {0};
+
+ /* Send APP_CMD before ACMD6*/
+ if (mmc_send_app_cmd(host, card))
+ {
+ dprintf(CRITICAL, "Failed sending App command\n");
+ return 1;
+ }
+
+ cmd.cmd_index = ACMD6_SET_BUS_WIDTH;
+ cmd.argument = (width == DATA_BUS_WIDTH_4BIT) ? (1<<1) : 0;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R1;
+
+ /* send command */
+ if (sdhci_send_command(host, &cmd))
+ return 1;
+
+ return 0;
+}
+
+uint32_t mmc_sd_set_hs(struct sdhci_host *host, struct mmc_card *card)
+{
+ struct mmc_command cmd = {0};
+ BUF_DMA_ALIGN(switch_resp, 64);
+
+ cmd.cmd_index = CMD6_SWITCH_FUNC;
+ cmd.argument = MMC_SD_SWITCH_HS;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R1;
+ cmd.trans_mode = SDHCI_MMC_READ;
+ cmd.data_present = 0x1;
+ cmd.data.data_ptr = switch_resp;
+ cmd.data.num_blocks = 0x1;
+ cmd.data.blk_sz = 0x40;
+
+ /* send command */
+ if (sdhci_send_command(host, &cmd))
+ return 1;
+
+ return 0;
+}
+
/*
* Function: mmc_init_card
* Arg : mmc device structure
@@ -1028,10 +1292,19 @@
/* TODO: Get the OCR params from target */
card->ocr = MMC_OCR_27_36 | MMC_OCR_SEC_MODE;
- /* Reset the card & get the OCR */
+ /* Initialize the internal MMC */
mmc_return = mmc_reset_card_and_send_op(host, card);
if (mmc_return)
- return mmc_return;
+ {
+ dprintf(CRITICAL, "MMC card failed to respond, try for SD card\n");
+ /* Reset the card & get the OCR */
+ mmc_return = mmc_sd_card_init(host, card);
+ if (mmc_return)
+ {
+ dprintf(CRITICAL, "Failed to initialize SD card\n");
+ return mmc_return;
+ }
+ }
/* Identify (CMD2, CMD3 & CMD9) and select the card (CMD7) */
mmc_return = mmc_identify_card(host, card);
@@ -1039,18 +1312,30 @@
return mmc_return;
/* set interface speed */
- mmc_return = mmc_set_hs_interface(host, card);
- if (mmc_return) {
- dprintf(CRITICAL, "Error adjusting interface speed!\n");
- return mmc_return;
+ if (MMC_CARD_SD(card))
+ {
+ mmc_return = mmc_sd_set_hs(host, card);
+ if (mmc_return)
+ {
+ dprintf(CRITICAL, "Failed to set HS for SD card\n");
+ return mmc_return;
+ }
+ }
+ else
+ {
+ mmc_return = mmc_set_hs_interface(host, card);
+ if (mmc_return) {
+ dprintf(CRITICAL, "Error adjusting interface speed!\n");
+ return mmc_return;
+ }
}
/* Set the sdcc clock to 50 MHZ */
sdhci_clk_supply(host, SDHCI_CLK_50MHZ);
/* Now get the extended CSD for the card */
- if ((card->type == MMC_TYPE_STD_MMC) ||
- (card->type == MMC_TYPE_MMCHC)) {
+ if (MMC_CARD_MMC(card))
+ {
/* For MMC cards, also get the extended csd */
mmc_return = mmc_get_ext_csd(host, card);
@@ -1059,6 +1344,21 @@
return mmc_return;
}
}
+ else
+ {
+ /*Read SCR for sd card */
+ if (mmc_sd_get_card_scr(host, card))
+ {
+ dprintf(CRITICAL, "Failure getting card's SCR register\n");
+ return 1;
+ }
+ /* Read SSR for the SD card */
+ if (mmc_sd_get_card_ssr(host, card))
+ {
+ dprintf(CRITICAL, "Failed to get SSR from the card\n");
+ return 1;
+ }
+ }
/* Decode and save the CSD register */
mmc_return = mmc_decode_and_save_csd(card);
@@ -1068,53 +1368,79 @@
}
- /* Set the bus width based on host, target capbilities */
- if (cfg->bus_width == DATA_BUS_WIDTH_8BIT && host->caps.bus_width_8bit)
- bus_width = DATA_BUS_WIDTH_8BIT;
- /*
- * Host contoller by default supports 4 bit & 1 bit mode.
- * No need to check for host support here
- */
- else if (cfg->bus_width == DATA_BUS_WIDTH_4BIT)
- bus_width = DATA_BUS_WIDTH_4BIT;
+ if (MMC_CARD_MMC(card))
+ {
+ /* Set the bus width based on host, target capbilities */
+ if (cfg->bus_width == DATA_BUS_WIDTH_8BIT && host->caps.bus_width_8bit)
+ bus_width = DATA_BUS_WIDTH_8BIT;
+ /*
+ * Host contoller by default supports 4 bit & 1 bit mode.
+ * No need to check for host support here
+ */
+ else if (cfg->bus_width == DATA_BUS_WIDTH_4BIT)
+ bus_width = DATA_BUS_WIDTH_4BIT;
+ else
+ bus_width = DATA_BUS_WIDTH_1BIT;
+
+ /* Set 4/8 bit SDR bus width in controller */
+ mmc_return = sdhci_set_bus_width(host, bus_width);
+
+ if (mmc_return) {
+ dprintf(CRITICAL, "Failed to set bus width for host controller\n");
+ return 1;
+ }
+
+ /* Enable high speed mode in the follwing order:
+ * 1. HS200 mode if supported by host & card
+ * 2. DDR mode host, if supported by host & card
+ * 3. Use normal speed mode with supported bus width
+ */
+ if (mmc_card_supports_hs200_mode(card) && host->caps.sdr50_support) {
+ mmc_return = mmc_set_hs200_mode(host, card, bus_width);
+
+ if (mmc_return) {
+ dprintf(CRITICAL, "Failure to set HS200 mode for Card(RCA:%x)\n",
+ card->rca);
+ return mmc_return;
+ }
+ } else if (mmc_card_supports_ddr_mode(card) && host->caps.ddr_support) {
+ mmc_return = mmc_set_ddr_mode(host, card);
+
+ if (mmc_return) {
+ dprintf(CRITICAL, "Failure to set DDR mode for Card(RCA:%x)\n",
+ card->rca);
+ return mmc_return;
+ }
+ } else {
+ /* Set 4/8 bit bus width for the card */
+ mmc_return = mmc_set_bus_width(host, card, bus_width);
+ if (mmc_return) {
+ dprintf(CRITICAL, "Failure to set wide bus for Card(RCA:%x)\n",
+ card->rca);
+ return mmc_return;
+ }
+ }
+ }
else
+ {
+ /* Check the supported bus width for the card from SCR register */
+ if (card->scr.bus_widths & SD_SCR_WIDTH_4BIT)
+ bus_width = DATA_BUS_WIDTH_4BIT;
+ else
bus_width = DATA_BUS_WIDTH_1BIT;
- /* Set 4/8 bit SDR bus width in controller */
- mmc_return = sdhci_set_bus_width(host, bus_width);
-
- if (mmc_return) {
- dprintf(CRITICAL, "Failed to set bus width for host controller\n");
- return 1;
- }
-
- /* Enable high speed mode in the follwing order:
- * 1. HS200 mode if supported by host & card
- * 2. DDR mode host, if supported by host & card
- * 3. Use normal speed mode with supported bus width
- */
- if (mmc_card_supports_hs200_mode(card) && host->caps.sdr50_support) {
- mmc_return = mmc_set_hs200_mode(host, card, bus_width);
-
- if (mmc_return) {
- dprintf(CRITICAL, "Failure to set HS200 mode for Card(RCA:%x)\n",
- card->rca);
+ mmc_return = mmc_sd_set_bus_width(host, card, bus_width);
+ if (mmc_return)
+ {
+ dprintf(CRITICAL, "Failed to set bus width for the card\n");
return mmc_return;
}
- } else if (mmc_card_supports_ddr_mode(card) && host->caps.ddr_support) {
- mmc_return = mmc_set_ddr_mode(host, card);
- if (mmc_return) {
- dprintf(CRITICAL, "Failure to set DDR mode for Card(RCA:%x)\n",
- card->rca);
- return mmc_return;
- }
- } else {
- /* Set 4/8 bit bus width for the card */
- mmc_return = mmc_set_bus_width(host, card, bus_width);
- if (mmc_return) {
- dprintf(CRITICAL, "Failure to set wide bus for Card(RCA:%x)\n",
- card->rca);
+ /* Set bit SDR bus width in controller */
+ mmc_return = sdhci_set_bus_width(host, bus_width);
+ if (mmc_return)
+ {
+ dprintf(CRITICAL, "Failed to set bus width for host controller\n");
return mmc_return;
}
}
@@ -1174,8 +1500,6 @@
memset((struct mmc_card *)&dev->card, 0, sizeof(struct mmc_card));
- dev->host.base = data->base;
-
/* Initialize the host & clock */
dprintf(SPEW, " Initializing MMC host data structure and clock!\n");
@@ -1227,6 +1551,8 @@
cmd.resp_type = SDHCI_CMD_RESP_R1;
cmd.trans_mode = SDHCI_MMC_READ;
cmd.data_present = 0x1;
+ /* Use CMD23 If card supports cMD23 */
+ cmd.cmd23_support = dev->card.scr.cmd23_support;
cmd.data.data_ptr = dest;
cmd.data.num_blocks = num_blocks;
@@ -1284,6 +1610,8 @@
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
cmd.trans_mode = SDHCI_MMC_WRITE;
+ /* Use CMD23 If card supports cMD23 */
+ cmd.cmd23_support = dev->card.scr.cmd23_support;
cmd.data_present = 0x1;
cmd.data.data_ptr = src;
cmd.data.num_blocks = num_blocks;
@@ -1320,10 +1648,15 @@
static uint32_t mmc_send_erase_grp_start(struct mmc_device *dev, uint32_t erase_start)
{
struct mmc_command cmd;
+ struct mmc_card *card = &dev->card;
memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
- cmd.cmd_index = CMD35_ERASE_GROUP_START;
+ if (MMC_CARD_MMC(card))
+ cmd.cmd_index = CMD35_ERASE_GROUP_START;
+ else
+ cmd.cmd_index = CMD32_ERASE_WR_BLK_START;
+
cmd.argument = erase_start;
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
@@ -1350,10 +1683,15 @@
static uint32_t mmc_send_erase_grp_end(struct mmc_device *dev, uint32_t erase_end)
{
struct mmc_command cmd;
+ struct mmc_card *card = &dev->card;
memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
- cmd.cmd_index = CMD36_ERASE_GROUP_END;
+ if (MMC_CARD_MMC(card))
+ cmd.cmd_index = CMD36_ERASE_GROUP_END;
+ else
+ cmd.cmd_index = CMD33_ERASE_WR_BLK_END;
+
cmd.argument = erase_end;
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
@@ -1433,14 +1771,29 @@
uint32_t blk_end;
uint32_t num_erase_grps;
uint32_t *out;
+ struct mmc_card *card;
+
+
+ card = &dev->card;
/*
- * Calculate the erase unit size as per the emmc specification v4.5
+ * Calculate the erase unit size,
+ * 1. Based on emmc 4.5 spec for emmc card
+ * 2. Use SD Card Status info for SD cards
*/
- if (dev->card.ext_csd[MMC_ERASE_GRP_DEF])
- erase_unit_sz = (MMC_HC_ERASE_MULT * dev->card.ext_csd[MMC_HC_ERASE_GRP_SIZE]) / MMC_BLK_SZ;
+ if (MMC_CARD_MMC(card))
+ {
+ /*
+ * Calculate the erase unit size as per the emmc specification v4.5
+ */
+ if (dev->card.ext_csd[MMC_ERASE_GRP_DEF])
+ erase_unit_sz = (MMC_HC_ERASE_MULT * dev->card.ext_csd[MMC_HC_ERASE_GRP_SIZE]) / MMC_BLK_SZ;
+ else
+ erase_unit_sz = (dev->card.csd.erase_grp_size + 1) * (dev->card.csd.erase_grp_mult + 1);
+ }
else
- erase_unit_sz = (dev->card.csd.erase_grp_size + 1) * (dev->card.csd.erase_grp_mult + 1);
+ erase_unit_sz = dev->card.ssr.au_size * dev->card.ssr.num_aus;
+
/* Convert length in blocks */
len = len / MMC_BLK_SZ;
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index 881d2a0..5cca931 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -59,7 +59,7 @@
unsigned int vfat_count = 0;
struct partition_entry partition_entries[NUM_PARTITIONS];
-unsigned gpt_partitions_exist = 0;
+static unsigned gpt_partitions_exist = 0;
unsigned partition_count = 0;
unsigned int partition_read_table()
@@ -957,3 +957,8 @@
return 0;
}
+
+bool partition_gpt_exists()
+{
+ return (gpt_partitions_exist != 0);
+}
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index 6a386ce..16a498b 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -259,6 +259,7 @@
bam.pipe[DATA_PRODUCER_PIPE_INDEX].trans_type = BAM2SYS;
bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.size = QPIC_BAM_DATA_FIFO_SIZE;
bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.head = data_desc_fifo;
+ bam.pipe[DATA_PRODUCER_PIPE_INDEX].lock_grp = config->pipes.read_pipe_grp;
/* Set Write pipe params. */
bam.pipe[DATA_CONSUMER_PIPE_INDEX].pipe_num = config->pipes.write_pipe;
@@ -266,6 +267,7 @@
bam.pipe[DATA_CONSUMER_PIPE_INDEX].trans_type = SYS2BAM;
bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.size = QPIC_BAM_DATA_FIFO_SIZE;
bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.head = data_desc_fifo;
+ bam.pipe[DATA_CONSUMER_PIPE_INDEX].lock_grp = config->pipes.write_pipe_grp;
/* Set Cmd pipe params. */
bam.pipe[CMD_PIPE_INDEX].pipe_num = config->pipes.cmd_pipe;
@@ -273,6 +275,7 @@
bam.pipe[CMD_PIPE_INDEX].trans_type = BAM2SYS;
bam.pipe[CMD_PIPE_INDEX].fifo.size = QPIC_BAM_CMD_FIFO_SIZE;
bam.pipe[CMD_PIPE_INDEX].fifo.head = cmd_desc_fifo;
+ bam.pipe[CMD_PIPE_INDEX].lock_grp = config->pipes.cmd_pipe_grp;
/* Programs the threshold for BAM transfer
* When this threshold is reached, BAM signals the peripheral via the pipe_bytes_available
diff --git a/platform/msm_shared/qtimer.c b/platform/msm_shared/qtimer.c
index bf9de81..c8d6bd7 100644
--- a/platform/msm_shared/qtimer.c
+++ b/platform/msm_shared/qtimer.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -93,7 +93,7 @@
{
uint64_t ticks;
- ticks = (msecs * ticks_per_sec) / 1000;
+ ticks = ((uint64_t) msecs * ticks_per_sec) / 1000;
delay(ticks);
}
@@ -102,7 +102,7 @@
{
uint64_t ticks;
- ticks = (usecs * ticks_per_sec) / 1000000;
+ ticks = ((uint64_t) usecs * ticks_per_sec) / 1000000;
delay(ticks);
}
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 72982b1..f43f1f6 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -19,6 +19,7 @@
ifeq ($(ENABLE_SDHCI_SUPPORT),1)
OBJS += \
$(LOCAL_DIR)/sdhci.o \
+ $(LOCAL_DIR)/sdhci_msm.o \
$(LOCAL_DIR)/mmc_sdhci.o \
$(LOCAL_DIR)/mmc_wrapper.o
else
@@ -164,7 +165,8 @@
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
- $(LOCAL_DIR)/dev_tree.o
+ $(LOCAL_DIR)/dev_tree.o \
+ $(LOCAL_DIR)/gpio.o
endif
ifeq ($(PLATFORM),msm7x27a)
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 417e0eb..ce54433 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -40,41 +40,6 @@
/*
- * Function: sdhci int handler
- * Arg : Event argument
- * Return : 0
- * Flow: : 1. Read the power control mask register
- * 2. Check if bus is ON
- * 3. Write success to ack regiser
- * Details : This is power control interrupt handler.
- * Once we receive the interrupt, we will ack the power control
- * register that we have successfully completed pmic transactions
- */
-enum handler_return sdhci_int_handler(void *arg)
-{
- uint32_t ack;
- uint32_t status;
-
- /*
- * Read the mask register to check if BUS & IO level
- * interrupts are enabled
- */
- status = readl(SDCC_HC_PWRCTL_MASK_REG);
-
- if (status & (SDCC_HC_BUS_ON | SDCC_HC_BUS_OFF))
- ack = SDCC_HC_BUS_ON_OFF_SUCC;
- if (status & (SDCC_HC_IO_SIG_LOW | SDCC_HC_IO_SIG_HIGH))
- ack |= SDCC_HC_IO_SIG_SUCC;
-
- /* Write success to power control register */
- writel(ack, SDCC_HC_PWRCTL_CTL_REG);
-
- event_signal((event_t *)arg, false);
-
- return 0;
-}
-
-/*
* Function: sdhci error status enable
* Arg : Host structure
* Return : None
@@ -207,7 +172,7 @@
voltage = host->caps.voltage;
voltage <<= SDHCI_BUS_VOL_SEL;
- REG_WRITE8(host, voltage, SDHCI_BUS_PWR_EN);
+ REG_WRITE8(host, voltage, SDHCI_PWR_CTRL_REG);
voltage |= SDHCI_BUS_PWR_EN;
@@ -458,6 +423,8 @@
if (int_status & SDHCI_ERR_INT_STAT_MASK) {
if (sdhci_cmd_err_status(host)) {
dprintf(CRITICAL, "Error: Command completed with errors\n");
+ /* Reset the command & Data line */
+ REG_WRITE8(host, (SOFT_RESET_CMD | SOFT_RESET_DATA), SDHCI_RESET_REG);
return 1;
}
}
@@ -712,10 +679,16 @@
if (cmd->trans_mode == SDHCI_MMC_READ)
trans_mode |= SDHCI_READ_MODE;
- /* Enable auto cmd 23 for multi block transfer */
+ /* Enable auto cmd23 or cmd12 for multi block transfer
+ * based on what command card supports
+ */
if (cmd->data.num_blocks > 1) {
- trans_mode |= SDHCI_TRANS_MULTI | SDHCI_AUTO_CMD23_EN | SDHCI_BLK_CNT_EN;
- REG_WRITE32(host, cmd->data.num_blocks, SDHCI_ARG2_REG);
+ if (cmd->cmd23_support) {
+ trans_mode |= SDHCI_TRANS_MULTI | SDHCI_AUTO_CMD23_EN | SDHCI_BLK_CNT_EN;
+ REG_WRITE32(host, cmd->data.num_blocks, SDHCI_ARG2_REG);
+ }
+ else
+ trans_mode |= SDHCI_TRANS_MULTI | SDHCI_AUTO_CMD12_EN | SDHCI_BLK_CNT_EN;
}
}
@@ -763,20 +736,6 @@
}
/*
- * Function: sdhci mode enable
- * Arg : Flag (0/1)
- * Return : None
- * Flow: : Enable/Disable Sdhci mode
- */
-void sdhci_mode_enable(uint8_t enable)
-{
- if (enable)
- writel(SDHCI_HC_MODE_EN, SDCC_MCI_HC_MODE);
- else
- writel(SDHCI_HC_MODE_DIS, SDCC_MCI_HC_MODE);
-}
-
-/*
* Function: sdhci init
* Arg : Host structure
* Return : None
@@ -791,9 +750,6 @@
void sdhci_init(struct sdhci_host *host)
{
uint32_t caps[2];
- event_t sdhc_event;
-
- event_init(&sdhc_event, false, EVENT_FLAG_AUTOUNSIGNAL);
/*
* Reset the controller
@@ -832,20 +788,11 @@
/* SDR50 mode support */
host->caps.sdr50_support = (caps[1] & SDHCI_SDR50_MODE_MASK) ? 1 : 0;
- /*
- * Register the interrupt handler for pwr irq
- */
- register_int_handler(SDCC_PWRCTRL_IRQ, sdhci_int_handler, &sdhc_event);
- unmask_interrupt(SDCC_PWRCTRL_IRQ);
-
- /* Enable pwr control interrupt */
- writel(SDCC_HC_PWR_CTRL_INT, SDCC_HC_PWRCTL_MASK_REG);
-
/* Set bus power on */
sdhci_set_bus_power_on(host);
/* Wait for power interrupt to be handled */
- event_wait(&sdhc_event);
+ event_wait(host->sdhc_event);
/* Set bus width */
sdhci_set_bus_width(host, SDHCI_BUS_WITDH_1BIT);
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
new file mode 100644
index 0000000..1b6c8b0
--- /dev/null
+++ b/platform/msm_shared/sdhci_msm.c
@@ -0,0 +1,139 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/interrupts.h>
+#include <platform/timer.h>
+#include <target.h>
+#include <string.h>
+#include <stdlib.h>
+#include <bits.h>
+#include <debug.h>
+#include <sdhci.h>
+#include <sdhci_msm.h>
+
+
+/*
+ * Function: sdhci int handler
+ * Arg : MSM specific data for sdhci
+ * Return : 0
+ * Flow: : 1. Read the power control mask register
+ * 2. Check if bus is ON
+ * 3. Write success to ack regiser
+ * Details : This is power control interrupt handler.
+ * Once we receive the interrupt, we will ack the power control
+ * register that we have successfully completed pmic transactions
+ */
+static enum handler_return sdhci_int_handler(struct sdhci_msm_data *data)
+{
+ uint32_t ack;
+ uint32_t status;
+
+ /*
+ * Read the mask register to check if BUS & IO level
+ * interrupts are enabled
+ */
+ status = readl(data->pwrctl_base + SDCC_HC_PWRCTL_MASK_REG);
+
+ if (status & (SDCC_HC_BUS_ON | SDCC_HC_BUS_OFF))
+ ack = SDCC_HC_BUS_ON_OFF_SUCC;
+ if (status & (SDCC_HC_IO_SIG_LOW | SDCC_HC_IO_SIG_HIGH))
+ ack |= SDCC_HC_IO_SIG_SUCC;
+
+ /* Write success to power control register */
+ writel(ack, (data->pwrctl_base + SDCC_HC_PWRCTL_CTL_REG));
+
+ event_signal(data->sdhc_event, false);
+
+ return 0;
+}
+
+/*
+ * Function: sdhci clear pending interrupts
+ * Arg : MSM specific data for sdhci
+ * Return : None
+ * Flow: : Clear pending interrupts
+ */
+static void sdhci_clear_power_ctrl_irq(struct sdhci_msm_data *data)
+{
+ uint32_t irq_ctl;
+ uint32_t irq_stat;
+
+ /*
+ * Read the power control status register to know
+ * the status of BUS & IO_HIGH_V
+ */
+ irq_stat = readl(data->pwrctl_base + SDCC_HC_PWRCTL_STATUS_REG);
+
+ /* Clear the power control status */
+ writel(irq_stat, (data->pwrctl_base + SDCC_HC_PWRCTL_CLEAR_REG));
+
+ /*
+ * Handle the pending irq by ack'ing the bus & IO switch
+ */
+ irq_ctl = readl(data->pwrctl_base + SDCC_HC_PWRCTL_CTL_REG);
+
+ if (irq_stat & (SDCC_HC_BUS_ON | SDCC_HC_BUS_OFF))
+ irq_ctl |= SDCC_HC_BUS_ON_OFF_SUCC;
+ if (irq_stat & (SDCC_HC_IO_SIG_LOW | SDCC_HC_IO_SIG_HIGH))
+ irq_ctl |= SDCC_HC_IO_SIG_SUCC;
+
+ writel(irq_ctl, (data->pwrctl_base + SDCC_HC_PWRCTL_CTL_REG));
+}
+
+/*
+ * Function: sdhci msm init
+ * Arg : MSM specific config data for sdhci
+ * Return : None
+ * Flow: : Enable sdhci mode & do msm specific init
+ */
+void sdhci_msm_init(struct sdhci_msm_data *config)
+{
+ /* Enable sdhc mode */
+ writel(SDHCI_HC_MODE_EN, (config->pwrctl_base + SDCC_MCI_HC_MODE));
+
+ /*
+ * CORE_SW_RST may trigger power irq if previous status of PWRCTL
+ * was either BUS_ON or IO_HIGH. So before we enable the power irq
+ * interrupt in GIC (by registering the interrupt handler), we need to
+ * ensure that any pending power irq interrupt status is acknowledged
+ * otherwise power irq interrupt handler would be fired prematurely.
+ */
+ sdhci_clear_power_ctrl_irq(config);
+
+ /*
+ * Register the interrupt handler for pwr irq
+ */
+ register_int_handler(config->pwr_irq, sdhci_int_handler, (void *)config);
+
+ unmask_interrupt(config->pwr_irq);
+
+ /* Enable pwr control interrupt */
+ writel(SDCC_HC_PWR_CTRL_INT, (config->pwrctl_base + SDCC_HC_PWRCTL_MASK_REG));
+}
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 3782c12..8ebbce8 100755
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -342,6 +342,7 @@
enum platform_subtype {
HW_PLATFORM_SUBTYPE_UNKNOWN = 0,
HW_PLATFORM_SUBTYPE_MDM = 1,
+ HW_PLATFORM_SUBTYPE_8974PRO_PM8084 = 1,
HW_PLATFORM_SUBTYPE_CSFB = 1,
HW_PLATFORM_SUBTYPE_SVLTE1 = 2,
HW_PLATFORM_SUBTYPE_SVLTE2A = 3,
diff --git a/project/msm8610.mk b/project/msm8610.mk
index 8d68d0a..02676ef 100644
--- a/project/msm8610.mk
+++ b/project/msm8610.mk
@@ -7,6 +7,7 @@
MODULES += app/aboot
DEBUG := 1
+ENABLE_SDHCI_SUPPORT := 1
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
@@ -20,3 +21,7 @@
#thumb interworking code for LK. Confirm that the issue
#is with the linker and file a bug report.
ENABLE_THUMB := false
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
diff --git a/target/mdm9625/init.c b/target/mdm9625/init.c
index ab9fd90..77f7331 100644
--- a/target/mdm9625/init.c
+++ b/target/mdm9625/init.c
@@ -54,6 +54,11 @@
#define DATA_PRODUCER_PIPE 1
#define CMD_PIPE 2
+/* NANDc BAM pipe groups */
+#define DATA_PRODUCER_PIPE_GRP 0
+#define DATA_CONSUMER_PIPE_GRP 0
+#define CMD_PIPE_GRP 1
+
/* NANDc EE */
#define QPIC_NAND_EE 0
@@ -122,6 +127,10 @@
config.pipes.write_pipe = DATA_CONSUMER_PIPE;
config.pipes.cmd_pipe = CMD_PIPE;
+ config.pipes.read_pipe_grp = DATA_PRODUCER_PIPE_GRP;
+ config.pipes.write_pipe_grp = DATA_CONSUMER_PIPE_GRP;
+ config.pipes.cmd_pipe_grp = CMD_PIPE_GRP;
+
config.bam_base = MSM_NAND_BAM_BASE;
config.nand_base = MSM_NAND_BASE;
config.ee = QPIC_NAND_EE;
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 4b3b618..dbd12d3 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -28,6 +28,7 @@
#include <debug.h>
#include <platform/iomap.h>
+#include <platform/irqs.h>
#include <reg.h>
#include <target.h>
#include <platform.h>
@@ -55,6 +56,8 @@
#define CRYPTO_ENGINE_FIFO_SIZE 64
#define CRYPTO_ENGINE_READ_PIPE 3
#define CRYPTO_ENGINE_WRITE_PIPE 2
+#define CRYPTO_READ_PIPE_LOCK_GRP 0
+#define CRYPTO_WRITE_PIPE_LOCK_GRP 0
#define CRYPTO_ENGINE_CMD_ARRAY_SIZE 20
#define TLMM_VOL_UP_BTN_GPIO 106
@@ -65,9 +68,15 @@
HW_PLATFORM_SUBTYPE_SKUAB = 3,
};
+static uint32_t mmc_pwrctl_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE };
+
static uint32_t mmc_sdhci_base[] =
{ MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE, MSM_SDC3_SDHCI_BASE };
+static uint32_t mmc_sdc_pwrctl_irq[] =
+ { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ, SDCC3_PWRCTL_IRQ };
+
struct mmc_device *dev;
void target_early_init(void)
@@ -122,9 +131,11 @@
ce_params.bam_base = MSM_CE1_BAM_BASE;
/* Set up BAM config. */
- ce_params.bam_ee = CRYPTO_ENGINE_EE;
- ce_params.pipes.read_pipe = CRYPTO_ENGINE_READ_PIPE;
- ce_params.pipes.write_pipe = CRYPTO_ENGINE_WRITE_PIPE;
+ ce_params.bam_ee = CRYPTO_ENGINE_EE;
+ ce_params.pipes.read_pipe = CRYPTO_ENGINE_READ_PIPE;
+ ce_params.pipes.write_pipe = CRYPTO_ENGINE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CRYPTO_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CRYPTO_WRITE_PIPE_LOCK_GRP;
/* Assign buffer sizes. */
ce_params.num_ce = CRYPTO_ENGINE_CMD_ARRAY_SIZE;
@@ -136,27 +147,30 @@
void target_sdc_init()
{
- struct mmc_config_data config;
+ struct mmc_config_data config = {0};
/*
* Set drive strength & pull ctrl for emmc
*/
set_sdc_power_ctrl();
- /* Enable sdhci mode */
- sdhci_mode_enable(1);
-
config.bus_width = DATA_BUS_WIDTH_8BIT;
config.max_clk_rate = MMC_CLK_200MHZ;
/* Trying Slot 1*/
config.slot = 1;
- config.base = mmc_sdhci_base[config.slot - 1];
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
if (!(dev = mmc_init(&config)))
{
/* Trying Slot 2 next */
config.slot = 2;
- config.base = mmc_sdhci_base[config.slot - 1];
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
if (!(dev = mmc_init(&config))) {
dprintf(CRITICAL, "mmc init failed!");
ASSERT(0);
@@ -348,11 +362,24 @@
unsigned target_pause_for_battery_charge(void)
{
+#if 0
uint8_t pon_reason = pm8x41_get_pon_reason();
uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
- if (is_cold_boot && ((pon_reason == USB_CHG) || (pon_reason == DC_CHG)))
- return 1;
- return 0;
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /* In case of fastboot reboot,adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ return 1;
+ else
+#endif
+ return 0;
}
unsigned target_baseband()
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 2da792e..a30b568 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -43,12 +43,10 @@
#include "include/display_resource.h"
static struct pm8x41_wled_data wled_ctrl = {
- .mod_scheme = 0xC3,
+ .mod_scheme = 0x00,
.led1_brightness = (0x0F << 8) | 0xEF,
- .led2_brightness = (0x0F << 8) | 0xEF,
- .led3_brightness = (0x0F << 8) | 0xEF,
.max_duty_cycle = 0x01,
- .ovp = 0x2,
+ .ovp = 0x0,
.full_current_scale = 0x19
};
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index da32049..92c9855 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -28,6 +28,7 @@
#include <debug.h>
#include <platform/iomap.h>
+#include <platform/irqs.h>
#include <reg.h>
#include <target.h>
#include <platform.h>
@@ -54,9 +55,19 @@
HW_PLATFORM_SUBTYPE_SKUAB = 3,
};
-static uint32_t mmc_sdc_base[] =
+static void set_sdc_power_ctrl(void);
+
+static uint32_t mmc_pwrctl_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE };
+static uint32_t mmc_sdhci_base[] =
+ { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
+
+static uint32_t mmc_sdc_pwrctl_irq[] =
+ { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
+
+struct mmc_device *dev;
+
void target_early_init(void)
{
#if WITH_DEBUG_UART
@@ -98,38 +109,60 @@
keys_post_event(KEY_VOLUMEUP, 1);
}
-void target_init(void)
+void target_sdc_init()
{
- uint32_t base_addr;
- uint8_t slot;
+ struct mmc_config_data config;
- dprintf(INFO, "target_init()\n");
-
- spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
-
- target_keystatus();
+ /* Set drive strength & pull ctrl values */
+ set_sdc_power_ctrl();
/* Display splash screen if enabled */
dprintf(SPEW, "Display Init: Start\n");
display_init();
dprintf(SPEW, "Display Init: Done\n");
- /* Trying Slot 1*/
- slot = 1;
- base_addr = mmc_sdc_base[slot - 1];
- if (mmc_boot_main(slot, base_addr))
+ config.bus_width = DATA_BUS_WIDTH_8BIT;
+ config.max_clk_rate = MMC_CLK_200MHZ;
+
+ /* Try slot 1*/
+ config.slot = 1;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+ if (!(dev = mmc_init(&config)))
{
- /* Trying Slot 2 next */
- slot = 2;
- base_addr = mmc_sdc_base[slot - 1];
+ /* Try slot 2 */
+ config.slot = 2;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
- if (mmc_boot_main(slot, base_addr))
+ if (!(dev = mmc_init(&config)))
{
dprintf(CRITICAL, "mmc init failed!");
ASSERT(0);
}
}
+
+ /* MMC initialization is complete, read the partition table info */
+ if (partition_read_table())
+ {
+ dprintf(CRITICAL, "Error reading the partition table info\n");
+ ASSERT(0);
+ }
+}
+
+void target_init(void)
+{
+ dprintf(INFO, "target_init()\n");
+
+ spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
+
+ target_keystatus();
+
+ target_sdc_init();
}
/* Do any target specific intialization needed before entering fastboot mode */
@@ -295,13 +328,30 @@
return 0;
}
-/*
- * Function to set the capabilities for the host
- */
-void target_mmc_caps(struct mmc_host *host)
+static void set_sdc_power_ctrl()
{
- host->caps.ddr_mode = 0;
- host->caps.hs200_mode = 0;
- host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
- host->caps.hs_clk_rate = MMC_CLK_50MHZ;
+ /* Drive strength configs for sdc pins */
+ struct tlmm_cfgs sdc1_hdrv_cfg[] =
+ {
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ };
+
+ /* Pull configs for sdc pins */
+ struct tlmm_cfgs sdc1_pull_cfg[] =
+ {
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ };
+
+ /* Set the drive strength & pull control values */
+ tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+ tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+}
+
+struct mmc_device *target_mmc_device()
+{
+ return dev;
}
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index 4904848..6316fa8 100644
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -136,7 +136,6 @@
static int msm8610_mipi_panel_power(uint8_t enable)
{
int ret;
- struct pm8x41_ldo ldo4 = LDO(PM8x41_LDO4, NLDO_TYPE);
struct pm8x41_ldo ldo14 = LDO(PM8x41_LDO14, PLDO_TYPE);
struct pm8x41_ldo ldo19 = LDO(PM8x41_LDO19, PLDO_TYPE);
@@ -151,8 +150,6 @@
pm8x41_ldo_control(&ldo14, enable);
pm8x41_ldo_set_voltage(&ldo19, 2850000);
pm8x41_ldo_control(&ldo19, enable);
- pm8x41_ldo_set_voltage(&ldo4, 1200000);
- pm8x41_ldo_control(&ldo4, enable);
/* reset */
msm8610_mdss_mipi_panel_reset(enable);
@@ -162,7 +159,6 @@
pm8x41_ldo_control(&ldo19, enable);
pm8x41_ldo_control(&ldo14, enable);
- pm8x41_ldo_control(&ldo4, enable);
}
return 0;
}
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index 11a9967..b5fbf82 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -28,6 +28,7 @@
#include <debug.h>
#include <platform/iomap.h>
+#include <platform/irqs.h>
#include <platform/gpio.h>
#include <reg.h>
#include <target.h>
@@ -70,6 +71,8 @@
#define CE_FIFO_SIZE 64
#define CE_READ_PIPE 3
#define CE_WRITE_PIPE 2
+#define CE_READ_PIPE_LOCK_GRP 0
+#define CE_WRITE_PIPE_LOCK_GRP 0
#define CE_ARRAY_SIZE 20
#ifdef SSD_ENABLE
@@ -77,6 +80,8 @@
#define SSD_PARTITION_SIZE 8192
#endif
+#define FASTBOOT_MODE 0x77665500
+
#define BOARD_SOC_VERSION1(soc_rev) (soc_rev >= 0x10000 && soc_rev < 0x20000)
#if MMC_SDHCI_SUPPORT
@@ -87,6 +92,9 @@
static uint32_t mmc_sdc_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE };
+static uint32_t mmc_sdc_pwrctl_irq[] =
+ { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ, SDCC3_PWRCTL_IRQ, SDCC4_PWRCTL_IRQ };
+
void target_early_init(void)
{
#if WITH_DEBUG_UART
@@ -174,9 +182,11 @@
ce_params.bam_base = MSM_CE2_BAM_BASE;
/* Set up BAM config. */
- ce_params.bam_ee = CE_EE;
- ce_params.pipes.read_pipe = CE_READ_PIPE;
- ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.bam_ee = CE_EE;
+ ce_params.pipes.read_pipe = CE_READ_PIPE;
+ ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
/* Assign buffer sizes. */
ce_params.num_ce = CE_ARRAY_SIZE;
@@ -198,14 +208,11 @@
}
#if MMC_SDHCI_SUPPORT
-static target_mmc_sdhci_init()
+static void target_mmc_sdhci_init()
{
- struct mmc_config_data config;
+ struct mmc_config_data config = {0};
uint32_t soc_ver = 0;
- /* Enable sdhci mode */
- sdhci_mode_enable(1);
-
soc_ver = board_soc_version();
/*
@@ -228,12 +235,17 @@
/* Trying Slot 1*/
config.slot = 1;
- config.base = mmc_sdhci_base[config.slot - 1];
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_sdc_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
if (!(dev = mmc_init(&config))) {
/* Trying Slot 2 next */
config.slot = 2;
- config.base = mmc_sdhci_base[config.slot - 1];
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_sdc_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
if (!(dev = mmc_init(&config))) {
dprintf(CRITICAL, "mmc init failed!");
ASSERT(0);
@@ -253,8 +265,9 @@
{
return dev;
}
+
#else
-static target_mmc_mci_init()
+static void target_mmc_mci_init()
{
uint32_t base_addr;
uint8_t slot;
@@ -416,10 +429,8 @@
*/
switch(platform_subtype) {
case HW_PLATFORM_SUBTYPE_UNKNOWN:
+ case HW_PLATFORM_SUBTYPE_8974PRO_PM8084:
break;
- case HW_PLATFORM_SUBTYPE_MDM:
- board->baseband = BASEBAND_MDM;
- return;
default:
dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
ASSERT(0);
@@ -489,6 +500,7 @@
void reboot_device(unsigned reboot_reason)
{
uint32_t soc_ver = 0;
+ uint8_t reset_type = 0;
soc_ver = board_soc_version();
@@ -498,11 +510,16 @@
else
writel(reboot_reason, RESTART_REASON_ADDR_V2);
+ if(reboot_reason == FASTBOOT_MODE)
+ reset_type = PON_PSHOLD_WARM_RESET;
+ else
+ reset_type = PON_PSHOLD_HARD_RESET;
+
/* Configure PMIC for warm reset */
if (target_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
- pm8x41_v2_reset_configure(PON_PSHOLD_WARM_RESET);
+ pm8x41_v2_reset_configure(reset_type);
else
- pm8x41_reset_configure(PON_PSHOLD_WARM_RESET);
+ pm8x41_reset_configure(reset_type);
/* Disable Watchdog Debug.
* Required becuase of a H/W bug which causes the system to
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 34650cc..d612015 100644
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -59,6 +59,18 @@
static int msm8974_backlight_on()
{
+ uint32_t platform_id = board_platform_id();
+ uint32_t hardware_id = board_hardware_id();
+ uint8_t slave_id = 1, i;
+ struct board_pmic_data *pmic_info;
+
+ if (platform_id == MSM8974AC)
+ if ((hardware_id == HW_PLATFORM_SURF)
+ || (hardware_id == HW_PLATFORM_MTP)
+ || (hardware_id == HW_PLATFORM_LIQUID))
+ slave_id = 3;
+
+ pm8x41_wled_config_slave_id(slave_id);
pm8x41_wled_config(&wled_ctrl);
pm8x41_wled_sink_control(1);
pm8x41_wled_iled_sync_control(1);
@@ -108,27 +120,40 @@
/* Pull DISP_RST_N high to get panel out of reset */
static void msm8974_mdss_mipi_panel_reset(uint8_t enable)
{
- struct pm8x41_gpio gpio19_param = {
+ uint32_t rst_gpio = 19;
+ uint32_t platform_id = board_platform_id();
+ uint32_t hardware_id = board_hardware_id();
+
+ struct pm8x41_gpio gpio_param = {
.direction = PM_GPIO_DIR_OUT,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = PM_GPIO_OUT_DRIVE_MED,
};
- pm8x41_gpio_config(19, &gpio19_param);
+ if (platform_id == MSM8974AC)
+ if ((hardware_id == HW_PLATFORM_SURF)
+ || (hardware_id == HW_PLATFORM_MTP)
+ || (hardware_id == HW_PLATFORM_LIQUID))
+ rst_gpio = 20;
+
+ dprintf(SPEW, "platform_id: %u, rst_gpio: %u\n",
+ platform_id, rst_gpio);
+
+ pm8x41_gpio_config(rst_gpio, &gpio_param);
if (enable) {
gpio_tlmm_config(58, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
- pm8x41_gpio_set(19, PM_GPIO_FUNC_HIGH);
+ pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_HIGH);
mdelay(2);
- pm8x41_gpio_set(19, PM_GPIO_FUNC_LOW);
+ pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_LOW);
mdelay(5);
- pm8x41_gpio_set(19, PM_GPIO_FUNC_HIGH);
+ pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_HIGH);
mdelay(2);
gpio_set(58, 2);
} else {
- gpio19_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
- pm8x41_gpio_config(19, &gpio19_param);
- pm8x41_gpio_set(19, PM_GPIO_FUNC_LOW);
+ gpio_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
+ pm8x41_gpio_config(rst_gpio, &gpio_param);
+ pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_LOW);
gpio_set(58, 2);
}
}