commit 3fa39aa0c7c716584e72b6844a984544bf287d29
author Linux Build Service Account <lnxbuild@localhost> Tue May 05 22:27:49 2015 -0700
committer Gerrit - the friendly Code Review server <code-review@localhost> Tue May 05 22:27:49 2015 -0700
tree 84c71269a8abe82bf9aa8aa2936629f37d95c659
parent 97c2c6d65736da4eec553cc8cc78165c35e2c0fb
parent 3ccc0552ef942b93863dad3ebe5c9f65869f462a

Merge "target: msm8994: set the correct parent for DSI RCG clocks"

platform/msm8994/acpuclock.c

diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index 0b64ce0..6f4e0f0 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -455,18 +455,18 @@
 	clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
 }
 
-void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t flags,
+void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t flags,
 			uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
 {
 	int ret;
 
 	if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
 		/* Enable DSI0 branch clocks */
-		writel(0x100, DSI_BYTE0_CFG_RCGR);
+		writel(cfg_rcgr, DSI_BYTE0_CFG_RCGR);
 		writel(0x1, DSI_BYTE0_CMD_RCGR);
 		writel(0x1, DSI_BYTE0_CBCR);
 
-		writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+		writel(cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
 		writel(0x1, DSI_PIXEL0_CMD_RCGR);
 		writel(0x1, DSI_PIXEL0_CBCR);
 
@@ -484,11 +484,11 @@
 
 	if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
 		/* Enable DSI1 branch clocks */
-		writel(0x100, DSI_BYTE1_CFG_RCGR);
+		writel(cfg_rcgr, DSI_BYTE1_CFG_RCGR);
 		writel(0x1, DSI_BYTE1_CMD_RCGR);
 		writel(0x1, DSI_BYTE1_CBCR);
 
-		writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
+		writel(cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
 		writel(0x1, DSI_PIXEL1_CMD_RCGR);
 		writel(0x1, DSI_PIXEL1_CBCR);
 

platform/msm8994/include/platform/clock.h

diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index 72d9787..ac611eb 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -79,6 +79,7 @@
 #define DSI_PIXEL0_D                    REG_MM(0x2010)
 
 #define DSI0_PHY_PLL_OUT                BIT(8)
+#define DSI1_PHY_PLL_OUT                BIT(9)
 #define PIXEL_SRC_DIV_1_5               BIT(1)
 
 #define DSI_BYTE1_CMD_RCGR              REG_MM(0x2140)
@@ -122,7 +123,7 @@
 void clock_ce_disable(uint8_t instance);
 void clock_usb30_init(void);
 
-void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t dual_dsi,
 	uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d);
 void mmss_dsi_clock_disable(uint32_t dual_dsi);
 void mmss_bus_clock_enable(void);

target/msm8994/target_display.c

diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 35a7026..1779ea5 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -389,7 +389,7 @@
 {
 	uint32_t ret = NO_ERROR;
 	struct mdss_dsi_pll_config *pll_data;
-	uint32_t flags;
+	uint32_t flags, dsi_phy_pll_out;
 	struct dfps_pll_codes *pll_codes = &pinfo->mipi.pll_codes;
 
 	if (pinfo->dest == DISPLAY_2) {
@@ -437,7 +437,12 @@
 	dprintf(SPEW, "codes %d %d\n", pll_codes->codes[0],
 		pll_codes->codes[1]);
 
-	mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, flags,
+	if (pinfo->mipi.use_dsi1_pll)
+		dsi_phy_pll_out = DSI1_PHY_PLL_OUT;
+	else
+		dsi_phy_pll_out = DSI0_PHY_PLL_OUT;
+
+	mmss_dsi_clock_enable(dsi_phy_pll_out, flags,
 		pll_data->pclk_m,
 		pll_data->pclk_n,
 		pll_data->pclk_d);