Merge "msm_shared: Fix the partition parser logic"
diff --git a/dev/pmic/pm8921/pm8921.c b/dev/pmic/pm8921/pm8921.c
index 231b8b6..cafa6a8 100644
--- a/dev/pmic/pm8921/pm8921.c
+++ b/dev/pmic/pm8921/pm8921.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2013, Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -521,6 +521,24 @@
return ret;
}
+int pm8921_HDMI_Switch(void)
+{
+ int ret = NO_ERROR;
+ uint8_t val;
+
+ /* Value for HDMI MVS 5V Switch */
+ val = 0x068;
+
+ /* Turn on MVS 5V HDMI switch */
+ ret = dev->write(&val, 1, PM8921_MVS_5V_HDMI_SWITCH);
+ if (ret) {
+ dprintf(CRITICAL,
+ "Failed to turn ON MVS 5V hdmi switch ret=%d.\n", ret);
+ }
+
+ return ret;
+}
+
int pm8921_rtc_alarm_disable(void)
{
int rc;
diff --git a/dev/pmic/pm8921/pm8921_hw.h b/dev/pmic/pm8921/pm8921_hw.h
index e75026e..ea3046f 100644
--- a/dev/pmic/pm8921/pm8921_hw.h
+++ b/dev/pmic/pm8921/pm8921_hw.h
@@ -154,6 +154,8 @@
#define PLDO_TYPE 0
#define NLDO_TYPE 1
+#define PM8921_MVS_5V_HDMI_SWITCH 0x70
+
#define LDO(_name, _type, _test_reg, _ctrl_reg) \
{\
.name = _name,\
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index eada6cc..8ed54ba 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -63,6 +63,13 @@
#define PMIC_VERSION_V2 1
+/*Target power on reasons*/
+#define DC_CHG 8
+#define USB_CHG 16
+#define PON1 32
+#define CBLPWR_N 64
+#define KPDPWR_N 128
+
struct pm8x41_gpio {
int direction;
int output_buffer;
@@ -85,6 +92,7 @@
int pm8x41_ldo_set_voltage(const char *, uint32_t);
int pm8x41_ldo_control(const char *, uint8_t);
uint8_t pm8x41_get_pmic_rev();
+uint8_t pm8x41_get_pon_reason();
struct pm8x41_ldo {
const char *name;
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 86cfee5..ff23061 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -56,6 +56,7 @@
/* PON Peripheral registers */
+#define PON_PON_REASON1 0x808
#define PON_INT_RT_STS 0x810
#define PON_INT_SET_TYPE 0x811
#define PON_INT_POLARITY_HIGH 0x812
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 62014ad..64aecae 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -350,3 +350,7 @@
return REG_READ(REVID_REVISION4);
}
+uint8_t pm8x41_get_pon_reason()
+{
+ return REG_READ(PON_PON_REASON1);
+}
diff --git a/platform/msm8960/hdmi_core.c b/platform/msm8960/hdmi_core.c
new file mode 100644
index 0000000..8d6ff34
--- /dev/null
+++ b/platform/msm8960/hdmi_core.c
@@ -0,0 +1,404 @@
+/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <hdmi.h>
+#include <dev/pm8921.h>
+#include <platform/timer.h>
+#include <platform/gpio.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+extern void hdmi_app_clk_init(int);
+extern int hdmi_msm_turn_on();
+
+/* HDMI PLL macros */
+#define HDMI_PHY_PLL_REFCLK_CFG (MSM_HDMI_BASE + 0x00000500)
+#define HDMI_PHY_PLL_CHRG_PUMP_CFG (MSM_HDMI_BASE + 0x00000504)
+#define HDMI_PHY_PLL_LOOP_FLT_CFG0 (MSM_HDMI_BASE + 0x00000508)
+#define HDMI_PHY_PLL_LOOP_FLT_CFG1 (MSM_HDMI_BASE + 0x0000050c)
+#define HDMI_PHY_PLL_IDAC_ADJ_CFG (MSM_HDMI_BASE + 0x00000510)
+#define HDMI_PHY_PLL_I_VI_KVCO_CFG (MSM_HDMI_BASE + 0x00000514)
+#define HDMI_PHY_PLL_PWRDN_B (MSM_HDMI_BASE + 0x00000518)
+#define HDMI_PHY_PLL_SDM_CFG0 (MSM_HDMI_BASE + 0x0000051c)
+#define HDMI_PHY_PLL_SDM_CFG1 (MSM_HDMI_BASE + 0x00000520)
+#define HDMI_PHY_PLL_SDM_CFG2 (MSM_HDMI_BASE + 0x00000524)
+#define HDMI_PHY_PLL_SDM_CFG3 (MSM_HDMI_BASE + 0x00000528)
+#define HDMI_PHY_PLL_SDM_CFG4 (MSM_HDMI_BASE + 0x0000052c)
+#define HDMI_PHY_PLL_SSC_CFG0 (MSM_HDMI_BASE + 0x00000530)
+#define HDMI_PHY_PLL_SSC_CFG1 (MSM_HDMI_BASE + 0x00000534)
+#define HDMI_PHY_PLL_SSC_CFG2 (MSM_HDMI_BASE + 0x00000538)
+#define HDMI_PHY_PLL_SSC_CFG3 (MSM_HDMI_BASE + 0x0000053c)
+#define HDMI_PHY_PLL_LOCKDET_CFG0 (MSM_HDMI_BASE + 0x00000540)
+#define HDMI_PHY_PLL_LOCKDET_CFG1 (MSM_HDMI_BASE + 0x00000544)
+#define HDMI_PHY_PLL_LOCKDET_CFG2 (MSM_HDMI_BASE + 0x00000548)
+#define HDMI_PHY_PLL_VCOCAL_CFG0 (MSM_HDMI_BASE + 0x0000054c)
+#define HDMI_PHY_PLL_VCOCAL_CFG1 (MSM_HDMI_BASE + 0x00000550)
+#define HDMI_PHY_PLL_VCOCAL_CFG2 (MSM_HDMI_BASE + 0x00000554)
+#define HDMI_PHY_PLL_VCOCAL_CFG3 (MSM_HDMI_BASE + 0x00000558)
+#define HDMI_PHY_PLL_VCOCAL_CFG4 (MSM_HDMI_BASE + 0x0000055c)
+#define HDMI_PHY_PLL_VCOCAL_CFG5 (MSM_HDMI_BASE + 0x00000560)
+#define HDMI_PHY_PLL_VCOCAL_CFG6 (MSM_HDMI_BASE + 0x00000564)
+#define HDMI_PHY_PLL_VCOCAL_CFG7 (MSM_HDMI_BASE + 0x00000568)
+#define HDMI_PHY_PLL_DEBUG_SEL (MSM_HDMI_BASE + 0x0000056c)
+#define HDMI_PHY_PLL_PWRDN_B (MSM_HDMI_BASE + 0x00000518)
+#define HDMI_PHY_PLL_STATUS0 (MSM_HDMI_BASE + 0x00000598)
+
+/* HDMI PHY/PLL bit field macros */
+#define SW_RESET BIT(2)
+#define SW_RESET_PLL BIT(0)
+#define PWRDN_B BIT(7)
+
+#define PLL_PWRDN_B BIT(3)
+#define PD_PLL BIT(1)
+
+static unsigned hdmi_pll_on;
+
+void hdmi_msm_init_phy()
+{
+ dprintf(INFO, "phy init\n");
+ uint32_t offset;
+
+ writel(0x1B, HDMI_PHY_REG_0);
+ writel(0xf2, HDMI_PHY_REG_1);
+
+ offset = HDMI_PHY_REG_4;
+ while (offset <= HDMI_PHY_REG_11) {
+ writel(0x0, offset);
+ offset += 0x4;
+ }
+
+ writel(0x20, HDMI_PHY_REG_3);
+}
+
+static void hdmi_gpio_config()
+{
+ writel(0x07, GPIO_CONFIG_ADDR(70));
+ writel(0x07, GPIO_CONFIG_ADDR(71));
+ writel(0x05, GPIO_CONFIG_ADDR(72));
+}
+
+void hdmi_msm_reset_core()
+{
+ uint32_t reg_val = 0;
+
+ // Disable clocks
+ hdmi_app_clk_init(0);
+ udelay(5);
+ // Enable clocks
+ hdmi_app_clk_init(1);
+
+ reg_val = readl(SW_RESET_CORE_REG);
+ reg_val |= BIT(11);
+ writel(reg_val, SW_RESET_CORE_REG);
+ udelay(5);
+ reg_val = readl(SW_RESET_CORE_REG);
+ reg_val &= ~(BIT(11));
+ writel(reg_val, SW_RESET_CORE_REG);
+ udelay(5);
+}
+
+void hdmi_phy_reset(void)
+{
+ uint32_t phy_reset_polarity = 0x0;
+ uint32_t pll_reset_polarity = 0x0;
+
+ uint32_t val = readl(HDMI_PHY_CTRL);
+
+ phy_reset_polarity = val >> 3 & 0x1;
+ pll_reset_polarity = val >> 1 & 0x1;
+
+ if (phy_reset_polarity == 0)
+ writel(val | SW_RESET, HDMI_PHY_CTRL);
+ else
+ writel(val & (~SW_RESET), HDMI_PHY_CTRL);
+
+ if (pll_reset_polarity == 0)
+ writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);
+ else
+ writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);
+
+ udelay(10);
+
+ if (phy_reset_polarity == 0)
+ writel(val & (~SW_RESET), HDMI_PHY_CTRL);
+ else
+ writel(val | SW_RESET, HDMI_PHY_CTRL);
+
+ if (pll_reset_polarity == 0)
+ writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);
+ else
+ writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);
+}
+
+/*
+ * This is the start function which initializes clocks , gpios for hdmi
+ * & powers on the HDMI core
+ */
+void hdmi_power_init()
+{
+ pm8921_low_voltage_switch_enable(lvs_7);
+ apq8064_ext_3p3V_enable();
+ pm8921_HDMI_Switch();
+ hdmi_gpio_config();
+ hdmi_phy_reset();
+ hdmi_msm_set_mode(1);
+}
+
+void hdmi_pll_disable(void)
+{
+ uint32_t val;
+ uint32_t ahb_en_reg, ahb_enabled;
+
+ ahb_en_reg = readl(AHB_EN_REG);
+ ahb_enabled = ahb_en_reg & BIT(4);
+ if (!ahb_enabled) {
+ writel(ahb_en_reg | BIT(4), AHB_EN_REG);
+ udelay(10);
+ }
+
+ val = readl(HDMI_PHY_REG_12);
+ val &= (~PWRDN_B);
+ writel(val, HDMI_PHY_REG_12);
+
+ val = readl(HDMI_PHY_PLL_PWRDN_B);
+ val |= PD_PLL;
+ val &= (~PLL_PWRDN_B);
+ writel(val, HDMI_PHY_PLL_PWRDN_B);
+ /* Make sure HDMI PHY/PLL are powered down */
+ udelay(10);
+
+ if (!ahb_enabled)
+ writel(ahb_en_reg & ~BIT(4), AHB_EN_REG);
+ hdmi_pll_on = 0;
+}
+
+void hdmi_pll_enable(void)
+{
+ uint32_t val;
+ uint32_t ahb_en_reg, ahb_enabled;
+ uint32_t timeout_count;
+ int pll_lock_retry = 10;
+
+ ahb_en_reg = readl(AHB_EN_REG);
+ ahb_enabled = ahb_en_reg & BIT(4);
+ if (!ahb_enabled) {
+ dprintf(INFO, "ahb not enabled\n");
+ writel(ahb_en_reg | BIT(4), AHB_EN_REG);
+ /* Make sure iface clock is enabled before register access */
+ udelay(10);
+ }
+
+ /* Assert PLL S/W reset */
+ writel(0x8D, HDMI_PHY_PLL_LOCKDET_CFG2);
+ writel(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
+ writel(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
+ /* Wait for a short time before de-asserting
+ * to allow the hardware to complete its job.
+ * This much of delay should be fine for hardware
+ * to assert and de-assert.
+ */
+ udelay(10);
+ /* De-assert PLL S/W reset */
+ writel(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
+
+ val = readl(HDMI_PHY_REG_12);
+ val |= BIT(5);
+ /* Assert PHY S/W reset */
+ writel(val, HDMI_PHY_REG_12);
+ val &= ~BIT(5);
+ /* Wait for a short time before de-asserting
+ to allow the hardware to complete its job.
+ This much of delay should be fine for hardware
+ to assert and de-assert. */
+ udelay(10);
+ /* De-assert PHY S/W reset */
+ writel(val, HDMI_PHY_REG_12);
+ writel(0x3f, HDMI_PHY_REG_2);
+
+ val = readl(HDMI_PHY_REG_12);
+ val |= PWRDN_B;
+ writel(val, HDMI_PHY_REG_12);
+ /* Wait 10 us for enabling global power for PHY */
+ udelay(10);
+
+ val = readl(HDMI_PHY_PLL_PWRDN_B);
+ val |= PLL_PWRDN_B;
+ val &= ~PD_PLL;
+ writel(val, HDMI_PHY_PLL_PWRDN_B);
+ writel(0x80, HDMI_PHY_REG_2);
+
+ timeout_count = 1000;
+ while (!(readl(HDMI_PHY_PLL_STATUS0) & BIT(0)) &&
+ timeout_count && pll_lock_retry) {
+ if (--timeout_count == 0) {
+ dprintf(INFO, "PLL not locked, retry\n");
+ /*
+ * PLL has still not locked.
+ * Do a software reset and try again
+ * Assert PLL S/W reset first
+ */
+ writel(0x8D, HDMI_PHY_PLL_LOCKDET_CFG2);
+
+ /* Wait for a short time before de-asserting
+ * to allow the hardware to complete its job.
+ * This much of delay should be fine for hardware
+ * to assert and de-assert.
+ */
+ udelay(10);
+ writel(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
+
+ /*
+ * Wait for a short duration for the PLL calibration
+ * before checking if the PLL gets locked
+ */
+ udelay(350);
+
+ timeout_count = 1000;
+ pll_lock_retry--;
+ }
+ }
+
+ if (!ahb_enabled) {
+ writel(ahb_en_reg & ~BIT(4), AHB_EN_REG);
+ udelay(10);
+ }
+
+ if (!pll_lock_retry) {
+ dprintf(INFO, "%s: HDMI PLL not locked\n", __func__);
+ hdmi_pll_disable();
+ }
+
+ hdmi_pll_on = 1;
+}
+
+
+int hdmi_dtv_on()
+{
+ uint32_t ahb_en_reg = readl(AHB_EN_REG);
+ uint32_t ahb_enabled = ahb_en_reg & BIT(4);
+ uint32_t val, pll_mode, ns_val, pll_config;
+
+ if (!ahb_enabled) {
+ dprintf(INFO, "ahb not enabled, turning on\n");
+ writel(ahb_en_reg | BIT(4), AHB_EN_REG);
+ /* Make sure iface clock is enabled before register access */
+ udelay(10);
+ }
+
+ if (hdmi_pll_on)
+ hdmi_pll_disable();
+
+ /* 1080p60/1080p50 case */
+ writel(0x2, HDMI_PHY_PLL_REFCLK_CFG);
+ writel(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
+ writel(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
+ writel(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
+ writel(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
+ writel(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
+ writel(0xA, HDMI_PHY_PLL_PWRDN_B);
+ writel(0x76, HDMI_PHY_PLL_SDM_CFG0);
+ writel(0x01, HDMI_PHY_PLL_SDM_CFG1);
+ writel(0x4C, HDMI_PHY_PLL_SDM_CFG2);
+ writel(0xC0, HDMI_PHY_PLL_SDM_CFG3);
+ writel(0x00, HDMI_PHY_PLL_SDM_CFG4);
+ writel(0x9A, HDMI_PHY_PLL_SSC_CFG0);
+ writel(0x00, HDMI_PHY_PLL_SSC_CFG1);
+ writel(0x00, HDMI_PHY_PLL_SSC_CFG2);
+ writel(0x00, HDMI_PHY_PLL_SSC_CFG3);
+ writel(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
+ writel(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
+ writel(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
+ writel(0xe6, HDMI_PHY_PLL_VCOCAL_CFG0);
+ writel(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
+ writel(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
+ writel(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
+ writel(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
+ writel(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
+ writel(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
+ writel(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
+
+ udelay(10);
+
+ hdmi_pll_enable();
+
+ if (!ahb_enabled)
+ writel(ahb_en_reg & ~BIT(4), AHB_EN_REG);
+
+ // set M N D
+ ns_val = readl(TV_NS_REG);
+ ns_val |= BIT(7);
+ writel(ns_val, TV_NS_REG);
+
+ writel(0x00, TV_MD_REG);
+
+ val = readl(TV_CC_REG);
+ val &= ~(BM(7, 6));
+ val |= CC(6, 0);
+ writel(val, TV_CC_REG);
+
+ ns_val &= ~BIT(7);
+ writel(ns_val, TV_NS_REG);
+
+ // confiure hdmi_ref clk to run @ 148.5 MHz
+ val = readl(MISC_CC2_REG);
+ val |= BIT(11);
+ writel(val, MISC_CC2_REG);
+
+ // Enable TV src clk
+ writel(0x03, TV_NS_REG);
+
+ // Enable hdmi clk
+ val = readl(TV_CC_REG);
+ val |= BIT(12);
+ writel(val, TV_CC_REG);
+
+ // De-Assert hdmi clk
+ val = readl(SW_RESET_CORE_REG);
+ val |= BIT(1);
+ writel(val, SW_RESET_CORE_REG);
+ udelay(10);
+ val = readl(SW_RESET_CORE_REG);
+ val &= ~(BIT(1));
+ writel(val, SW_RESET_CORE_REG);
+ udelay(10);
+
+ // Root en of tv src clk
+ val = readl(TV_CC_REG);
+ val |= BIT(2);
+ writel(val, TV_CC_REG);
+
+ // enable mdp dtv clk
+ val = readl(TV_CC_REG);
+ val |= BIT(0);
+ writel(val, TV_CC_REG);
+ udelay(10);
+
+ return 0;
+}
+
diff --git a/platform/msm8960/include/platform/clock.h b/platform/msm8960/include/platform/clock.h
index ff73fae..94c4d3d 100644
--- a/platform/msm8960/include/platform/clock.h
+++ b/platform/msm8960/include/platform/clock.h
@@ -1,5 +1,5 @@
/*
- * * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+ * * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -29,6 +29,7 @@
#ifndef __PLATFORM_MSM8960_CLOCK_H
#define __PLATFORM_MSM8960_CLOCK_H
+#define MSM_MMSS_CLK_CTL_SIZE 4096
#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
#define REG(off) (MSM_CLK_CTL_BASE + (off))
@@ -123,6 +124,23 @@
#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
#define DSI1_ESC_NS_REG REG_MM(0x011C)
#define DSI1_ESC_CC_REG REG_MM(0x00CC)
+
+#define MM_PLL1_MODE_REG REG_MM(0x031C)
+#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
+#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
+#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
+#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
+#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
+
+#define MM_PLL2_MODE_REG REG_MM(0x3160)
+#define MM_PLL2_L_VAL_REG REG_MM(0x3164)
+#define MM_PLL2_M_VAL_REG REG_MM(0x3168)
+#define MM_PLL2_N_VAL_REG REG_MM(0x316C)
+#define MM_PLL2_TEST_CTL_REG REG_MM(0x3170)
+#define MM_PLL2_CONFIG_REG REG_MM(0x3174)
+
+#define MMSS_AHB_EN_REG REG_MM(0x08)
+
#define DSI2_ESC_NS_REG REG_MM(0x0150)
#define DSI2_ESC_CC_REG REG_MM(0x013C)
#define DSI_PIXEL_CC_REG REG_MM(0x0130)
diff --git a/platform/msm8960/include/platform/iomap.h b/platform/msm8960/include/platform/iomap.h
index 32167f8..9fc7e25 100644
--- a/platform/msm8960/include/platform/iomap.h
+++ b/platform/msm8960/include/platform/iomap.h
@@ -1,7 +1,7 @@
/* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -66,6 +66,7 @@
#define MSM_GIC_CPU_BASE 0x02002000
#define MSM_VIC_BASE 0x02080000
+#define MSM_TCSR_SIZE 4096
#define MSM_USB_BASE 0x12500000
#define TLMM_BASE_ADDR 0x00800000
@@ -115,7 +116,31 @@
//TODO: Where does this go?
#define MMSS_SFPB_GPREG (0x05700058)
-#define CE1_CRYPTO4_BASE (0x18500000)
-#define CE3_CRYPTO4_BASE (0x11000000)
-#define LCDC_BASE (0x000C0000)
+/* HDMI base addresses */
+#define MSM_HDMI_BASE 0x04A00000
+#define DTV_BASE 0xD0000
+
+#define HDMI_USEC_REFTIMER (MSM_HDMI_BASE + 0x0208)
+#define HDMI_CTRL (MSM_HDMI_BASE + 0x0000)
+#define HDMI_HPD_INT_STATUS (MSM_HDMI_BASE + 0x0250)
+#define HDMI_HPD_INT_CTRL (MSM_HDMI_BASE + 0x0254)
+#define HDMI_HPD_CTRL (MSM_HDMI_BASE + 0x0258)
+#define HDMI_PHY_CTRL (MSM_HDMI_BASE + 0x000002D4)
+#define HDMI_PHY_REG_0 (MSM_HDMI_BASE + 0x00000400)
+#define HDMI_PHY_REG_1 (MSM_HDMI_BASE + 0x00000404)
+#define HDMI_PHY_REG_2 (MSM_HDMI_BASE + 0x00000408)
+#define HDMI_PHY_REG_3 (MSM_HDMI_BASE + 0x0000040c)
+#define HDMI_PHY_REG_4 (MSM_HDMI_BASE + 0x00000410)
+#define HDMI_PHY_REG_9 (MSM_HDMI_BASE + 0x00000424)
+#define HDMI_PHY_REG_11 (MSM_HDMI_BASE + 0x0000042c)
+#define HDMI_PHY_REG_12 (MSM_HDMI_BASE + 0x00000430)
+#define HDMI_TOTAL (MSM_HDMI_BASE + 0x000002C0)
+#define HDMI_ACTIVE_HSYNC (MSM_HDMI_BASE + 0x000002B4)
+#define HDMI_ACTIVE_VSYNC (MSM_HDMI_BASE + 0x000002B8)
+#define HDMI_VSYNC_TOTAL_F2 (MSM_HDMI_BASE + 0x000002C4)
+#define HDMI_VSYNC_ACTIVE_F2 (MSM_HDMI_BASE + 0x000002BC)
+#define HDMI_FRAME_CTRL (MSM_HDMI_BASE + 0x000002C8)
+#define CE1_CRYPTO4_BASE (0x18500000)
+#define CE3_CRYPTO4_BASE (0x11000000)
+#define LCDC_BASE (0x000C0000)
#endif
diff --git a/platform/msm8960/rules.mk b/platform/msm8960/rules.mk
index ccc6833..1950d60 100644
--- a/platform/msm8960/rules.mk
+++ b/platform/msm8960/rules.mk
@@ -20,7 +20,8 @@
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/acpuclock.o \
$(LOCAL_DIR)/gpio.o \
- $(LOCAL_DIR)/clock.o
+ $(LOCAL_DIR)/clock.o \
+ $(LOCAL_DIR)/hdmi_core.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 1165f03..4d7433e 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -95,8 +95,9 @@
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
-#define MPM2_MPM_CTRL_BASE 0xFC4A1000
-#define MPM2_MPM_PS_HOLD 0xFC4AB000
+#define MPM2_MPM_CTRL_BASE 0xFC4A1000
+#define MPM2_MPM_PS_HOLD 0xFC4AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
/* CE 2 */
#define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080)
diff --git a/platform/msm8974/platform.c b/platform/msm8974/platform.c
index 368b590..430116b 100644
--- a/platform/msm8974/platform.c
+++ b/platform/msm8974/platform.c
@@ -69,8 +69,19 @@
dprintf(INFO, "platform_init()\n");
}
+static void platform_print_sclk(void)
+{
+ uint32_t count;
+
+ count = readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+
+ dprintf(INFO, "mpm sclk=(%lu)\n", count);
+}
+
void platform_uninit(void)
{
+ platform_print_sclk();
+
#if DISPLAY_SPLASH_SCREEN
display_shutdown();
#endif
diff --git a/platform/msm8x60/hdmi_core.c b/platform/msm8x60/hdmi_core.c
index 70dce1b..fb4da74 100644
--- a/platform/msm8x60/hdmi_core.c
+++ b/platform/msm8x60/hdmi_core.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -35,7 +35,25 @@
#include <platform/scm-io.h>
extern void hdmi_app_clk_init(int);
-extern void hdmi_msm_turn_on();
+extern int hdmi_msm_turn_on();
+
+#define FB_ADDR 0x43E00000
+
+static struct fbcon_config fb_cfg = {
+ .height = DTV_FB_HEIGHT,
+ .width = DTV_FB_WIDTH,
+ .stride = DTV_FB_WIDTH,
+ .format = DTV_FORMAT_RGB565,
+ .bpp = DTV_BPP,
+ .update_start = NULL,
+ .update_done = NULL,
+ .base = FB_ADDR;
+};
+
+struct fbcon_config *get_fbcon(void)
+{
+ return &fb_cfg;
+}
void hdmi_msm_init_phy()
{
@@ -64,17 +82,6 @@
writel(0x13, HDMI_PHY_REG_12);
}
-void hdmi_frame_ctrl_reg()
-{
- uint32_t hdmi_frame_ctrl;
-
- hdmi_frame_ctrl = ((0 << 31) & 0x80000000);
- hdmi_frame_ctrl |= ((0 << 29) & 0x20000000);
- hdmi_frame_ctrl |= ((0 << 28) & 0x10000000);
- hdmi_frame_ctrl |= (1 << 12);
- writel(hdmi_frame_ctrl, HDMI_FRAME_CTRL);
-}
-
static void hdmi_gpio_config()
{
uint32_t func;
@@ -101,7 +108,7 @@
* This is the start function which initializes clocks , gpios for hdmi
* & powers on the HDMI core
*/
-void hdmi_display_init()
+void hdmi_power_init()
{
// Enable HDMI clocks
hdmi_app_clk_init(1);
@@ -117,7 +124,43 @@
hdmi_msm_turn_on();
}
-void dtv_on()
+static void hdmi_msm_reset_core()
+{
+ uint32_t reg_val = 0;
+ hdmi_msm_set_mode(0);
+ // Disable clocks
+ hdmi_app_clk_init(0);
+ udelay(5);
+ // Enable clocks
+ hdmi_app_clk_init(1);
+
+ reg_val = secure_readl(SW_RESET_CORE_REG);
+ reg_val |= BIT(11);
+ secure_writel(reg_val, SW_RESET_CORE_REG);
+ udelay(5);
+ reg_val = secure_readl(SW_RESET_AHB_REG);
+ reg_val |= BIT(9);
+ secure_writel(reg_val, SW_RESET_AHB_REG);
+ udelay(5);
+ reg_val = secure_readl(SW_RESET_AHB_REG);
+ reg_val |= BIT(9);
+ secure_writel(reg_val, SW_RESET_AHB_REG);
+ udelay(20);
+ reg_val = secure_readl(SW_RESET_CORE_REG);
+ reg_val &= ~(BIT(11));
+ secure_writel(reg_val, SW_RESET_CORE_REG);
+ udelay(5);
+ reg_val = secure_readl(SW_RESET_AHB_REG);
+ reg_val &= ~(BIT(9));
+ secure_writel(reg_val, SW_RESET_AHB_REG);
+ udelay(5);
+ reg_val = secure_readl(SW_RESET_AHB_REG);
+ reg_val &= ~(BIT(9));
+ secure_writel(reg_val, SW_RESET_AHB_REG);
+ udelay(5);
+}
+
+int hdmi_dtv_on()
{
uint32_t val, pll_mode, ns_val, pll_config;
@@ -201,4 +244,6 @@
val |= BIT(0);
secure_writel(val, TV_CC_REG);
udelay(10);
+
+ return 0;
}
diff --git a/platform/msm8x60/platform.c b/platform/msm8x60/platform.c
old mode 100755
new mode 100644
index 16086a9..8c31db6
--- a/platform/msm8x60/platform.c
+++ b/platform/msm8x60/platform.c
@@ -149,10 +149,13 @@
#if DISPLAY_TYPE_HDMI
struct hdmi_disp_mode_timing_type *hdmi_timing;
mdp_clock_init();
- hdmi_display_init();
- hdmi_timing = hdmi_common_init_panel_info();
- fb_cfg = hdmi_dtv_init(hdmi_timing);
+ hdmi_power_init();
+ fb_cfg = get_fbcon();
+ hdmi_set_fb_addr(fb_cfg.base);
fbcon_setup(fb_cfg);
+ hdmi_dtv_init();
+ hdmi_dtv_on();
+ hdmi_msm_turn_on();
#endif
}
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index c005bc9..0bb779e 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -32,6 +32,23 @@
#include <mdp4.h>
#include <mipi_dsi.h>
+#ifndef DISPLAY_TYPE_HDMI
+static int hdmi_dtv_init(void)
+{
+ return 0;
+}
+
+static int hdmi_dtv_on(void)
+{
+ return 0;
+}
+
+static int hdmi_msm_turn_on(void)
+{
+ return 0;
+}
+#endif
+
static struct msm_fb_panel_data *panel;
extern int lvds_on(struct msm_fb_panel_data *pdata);
@@ -105,6 +122,12 @@
if (ret)
goto msm_display_config_out;
break;
+ case HDMI_PANEL:
+ dprintf(INFO, "Config HDMI PANEL.\n");
+ ret = hdmi_dtv_init();
+ if (ret)
+ goto msm_display_config_out;
+ break;
default:
return ERR_INVALID_ARGS;
};
@@ -160,6 +183,17 @@
if (ret)
goto msm_display_on_out;
break;
+ case HDMI_PANEL:
+ dprintf(INFO, "Turn on HDMI PANEL.\n");
+ ret = hdmi_dtv_on();
+ if (ret)
+ goto msm_display_on_out;
+
+ ret = hdmi_msm_turn_on();
+ if (ret)
+ goto msm_display_on_out;
+ break;
+
default:
return ERR_INVALID_ARGS;
};
diff --git a/platform/msm_shared/hdmi.c b/platform/msm_shared/hdmi.c
index f26d36d..422a506 100644
--- a/platform/msm_shared/hdmi.c
+++ b/platform/msm_shared/hdmi.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -27,27 +27,59 @@
*
*/
#include <hdmi.h>
+#include <msm_panel.h>
#include <platform/timer.h>
#include <platform/clock.h>
#include <platform/iomap.h>
-#include <platform/scm-io.h>
#define MDP4_OVERLAYPROC1_BASE 0x18000
#define MDP4_RGB_BASE 0x40000
#define MDP4_RGB_OFF 0x10000
struct hdmi_disp_mode_timing_type hdmi_timing_default = {
- .height = 1080,
+ .height = 1080,
.hsync_porch_fp = 88,
- .hsync_width = 44,
+ .hsync_width = 44,
.hsync_porch_bp = 148,
- .width = 1920,
+ .width = 1920,
.vsync_porch_fp = 4,
- .vsync_width = 5,
+ .vsync_width = 5,
.vsync_porch_bp = 36,
+ .bpp = 24,
};
-static void hdmi_msm_set_mode(int on)
+static uint8_t hdmi_msm_avi_iframe_lut[][16] = {
+/* 480p60 480i60 576p50 576i50 720p60 720p50 1080p60 1080i60 1080p50
+ 1080i50 1080p24 1080p30 1080p25 640x480p 480p60_16_9 576p50_4_3 */
+ {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, /*00*/
+ {0x18, 0x18, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
+ 0x28, 0x28, 0x28, 0x28, 0x18, 0x28, 0x18}, /*01*/
+ {0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+ 0x04, 0x04, 0x04, 0x04, 0x88, 0x00, 0x04}, /*02*/
+ {0x02, 0x06, 0x11, 0x15, 0x04, 0x13, 0x10, 0x05, 0x1F,
+ 0x14, 0x20, 0x22, 0x21, 0x01, 0x03, 0x11}, /*03*/
+ {0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*04*/
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*05*/
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*06*/
+ {0xE1, 0xE1, 0x41, 0x41, 0xD1, 0xd1, 0x39, 0x39, 0x39,
+ 0x39, 0x39, 0x39, 0x39, 0xe1, 0xE1, 0x41}, /*07*/
+ {0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x04, 0x04, 0x04,
+ 0x04, 0x04, 0x04, 0x04, 0x01, 0x01, 0x02}, /*08*/
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*09*/
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*10*/
+ {0xD1, 0xD1, 0xD1, 0xD1, 0x01, 0x01, 0x81, 0x81, 0x81,
+ 0x81, 0x81, 0x81, 0x81, 0x81, 0xD1, 0xD1}, /*11*/
+ {0x02, 0x02, 0x02, 0x02, 0x05, 0x05, 0x07, 0x07, 0x07,
+ 0x07, 0x07, 0x07, 0x07, 0x02, 0x02, 0x02} /*12*/
+};
+
+void hdmi_msm_set_mode(int on)
{
uint32_t val = 0;
if (on) {
@@ -64,6 +96,39 @@
return &hdmi_timing_default;
}
+void hdmi_set_fb_addr(void *addr)
+{
+ hdmi_timing_default.base = addr;
+}
+
+void hdmi_msm_panel_init(struct msm_panel_info *pinfo)
+{
+ if (!pinfo)
+ return;
+
+ pinfo->xres = hdmi_timing_default.width;
+ pinfo->yres = hdmi_timing_default.height;
+ pinfo->bpp = hdmi_timing_default.bpp;
+ pinfo->type = HDMI_PANEL;
+
+ pinfo->hdmi.h_back_porch = hdmi_timing_default.hsync_porch_bp;
+ pinfo->hdmi.h_front_porch = hdmi_timing_default.hsync_porch_fp;
+ pinfo->hdmi.h_pulse_width = hdmi_timing_default.hsync_width;
+ pinfo->hdmi.v_back_porch = hdmi_timing_default.vsync_porch_bp;
+ pinfo->hdmi.v_front_porch = hdmi_timing_default.vsync_porch_fp;
+ pinfo->hdmi.v_pulse_width = hdmi_timing_default.vsync_width;
+}
+
+void hdmi_frame_ctrl_reg()
+{
+ uint32_t hdmi_frame_ctrl;
+
+ hdmi_frame_ctrl = ((0 << 31) & 0x80000000);
+ hdmi_frame_ctrl |= ((0 << 29) & 0x20000000);
+ hdmi_frame_ctrl |= ((0 << 28) & 0x10000000);
+ writel(hdmi_frame_ctrl, HDMI_FRAME_CTRL);
+}
+
void hdmi_video_setup()
{
uint32_t hsync_total = 0;
@@ -107,96 +172,153 @@
hdmi_frame_ctrl_reg();
}
+void hdmi_msm_avi_info_frame(void)
+{
+ /* two header + length + 13 data */
+ uint8_t aviInfoFrame[16];
+ uint8_t checksum;
+ uint32_t sum;
+ uint32_t regVal;
+ uint8_t i;
+ uint8_t mode = 6; //HDMI_VFRMT_1920x1080p60_16_9
+
+ /* InfoFrame Type = 82 */
+ aviInfoFrame[0] = 0x82;
+ /* Version = 2 */
+ aviInfoFrame[1] = 2;
+ /* Length of AVI InfoFrame = 13 */
+ aviInfoFrame[2] = 13;
+
+ /* Data Byte 01: 0 Y1 Y0 A0 B1 B0 S1 S0 */
+ aviInfoFrame[3] = hdmi_msm_avi_iframe_lut[0][mode];
+
+ /* Setting underscan bit */
+ aviInfoFrame[3] |= 0x02;
+
+ /* Data Byte 02: C1 C0 M1 M0 R3 R2 R1 R0 */
+ aviInfoFrame[4] = hdmi_msm_avi_iframe_lut[1][mode];
+ /* Data Byte 03: ITC EC2 EC1 EC0 Q1 Q0 SC1 SC0 */
+ aviInfoFrame[5] = hdmi_msm_avi_iframe_lut[2][mode];
+ /* Data Byte 04: 0 VIC6 VIC5 VIC4 VIC3 VIC2 VIC1 VIC0 */
+ aviInfoFrame[6] = hdmi_msm_avi_iframe_lut[3][mode];
+ /* Data Byte 05: 0 0 0 0 PR3 PR2 PR1 PR0 */
+ aviInfoFrame[7] = hdmi_msm_avi_iframe_lut[4][mode];
+ /* Data Byte 06: LSB Line No of End of Top Bar */
+ aviInfoFrame[8] = hdmi_msm_avi_iframe_lut[5][mode];
+ /* Data Byte 07: MSB Line No of End of Top Bar */
+ aviInfoFrame[9] = hdmi_msm_avi_iframe_lut[6][mode];
+ /* Data Byte 08: LSB Line No of Start of Bottom Bar */
+ aviInfoFrame[10] = hdmi_msm_avi_iframe_lut[7][mode];
+ /* Data Byte 09: MSB Line No of Start of Bottom Bar */
+ aviInfoFrame[11] = hdmi_msm_avi_iframe_lut[8][mode];
+ /* Data Byte 10: LSB Pixel Number of End of Left Bar */
+ aviInfoFrame[12] = hdmi_msm_avi_iframe_lut[9][mode];
+ /* Data Byte 11: MSB Pixel Number of End of Left Bar */
+ aviInfoFrame[13] = hdmi_msm_avi_iframe_lut[10][mode];
+ /* Data Byte 12: LSB Pixel Number of Start of Right Bar */
+ aviInfoFrame[14] = hdmi_msm_avi_iframe_lut[11][mode];
+ /* Data Byte 13: MSB Pixel Number of Start of Right Bar */
+ aviInfoFrame[15] = hdmi_msm_avi_iframe_lut[12][mode];
+
+ sum = 0;
+ for (i = 0; i < 16; i++)
+ sum += aviInfoFrame[i];
+ sum &= 0xFF;
+ sum = 256 - sum;
+ checksum = (uint8_t) sum;
+
+ regVal = aviInfoFrame[5];
+ regVal = regVal << 8 | aviInfoFrame[4];
+ regVal = regVal << 8 | aviInfoFrame[3];
+ regVal = regVal << 8 | checksum;
+ writel(regVal, MSM_HDMI_BASE + 0x006C);
+
+ regVal = aviInfoFrame[9];
+ regVal = regVal << 8 | aviInfoFrame[8];
+ regVal = regVal << 8 | aviInfoFrame[7];
+ regVal = regVal << 8 | aviInfoFrame[6];
+ writel(regVal, MSM_HDMI_BASE + 0x0070);
+
+ regVal = aviInfoFrame[13];
+ regVal = regVal << 8 | aviInfoFrame[12];
+ regVal = regVal << 8 | aviInfoFrame[11];
+ regVal = regVal << 8 | aviInfoFrame[10];
+ writel(regVal, MSM_HDMI_BASE + 0x0074);
+
+ regVal = aviInfoFrame[1];
+ regVal = regVal << 16 | aviInfoFrame[15];
+ regVal = regVal << 8 | aviInfoFrame[14];
+ writel(regVal, MSM_HDMI_BASE + 0x0078);
+
+ /* INFOFRAME_CTRL0[0x002C] */
+ /* 0x3 for AVI InfFrame enable (every frame) */
+ writel(readl(0x002C) | 0x00000003L, MSM_HDMI_BASE + 0x002C);
+}
+
void hdmi_app_clk_init(int on)
{
uint32_t val = 0;
if (on) {
- // Enable clocks
- val = secure_readl(MISC_CC2_REG);
- val |= BIT(11);
- secure_writel(val, MISC_CC2_REG);
+ /* Enable hdmi apps clock */
+ val = readl(MISC_CC2_REG);
+ val = BIT(11);
+ writel(val, MISC_CC2_REG);
udelay(10);
- val = secure_readl(MMSS_AHB_EN_REG);
+
+ /* Enable hdmi master clock */
+ val = readl(MMSS_AHB_EN_REG);
val |= BIT(14);
- secure_writel(val, MMSS_AHB_EN_REG);
+ writel(val, MMSS_AHB_EN_REG);
udelay(10);
- val = secure_readl(MMSS_AHB_EN_REG);
+
+ /* Enable hdmi slave clock */
+ val = readl(MMSS_AHB_EN_REG);
val |= BIT(4);
- secure_writel(val, MMSS_AHB_EN_REG);
+ writel(val, MMSS_AHB_EN_REG);
udelay(10);
} else {
// Disable clocks
- val = secure_readl(MISC_CC2_REG);
+ val = readl(MISC_CC2_REG);
val &= ~(BIT(11));
- secure_writel(val, MISC_CC2_REG);
+ writel(val, MISC_CC2_REG);
udelay(10);
- val = secure_readl(MMSS_AHB_EN_REG);
+ val = readl(MMSS_AHB_EN_REG);
val &= ~(BIT(14));
- secure_writel(val, MMSS_AHB_EN_REG);
+ writel(val, MMSS_AHB_EN_REG);
udelay(10);
- val = secure_readl(MMSS_AHB_EN_REG);
+ val = readl(MMSS_AHB_EN_REG);
val &= ~(BIT(4));
- secure_writel(val, MMSS_AHB_EN_REG);
+ writel(val, MMSS_AHB_EN_REG);
udelay(10);
}
}
-static void hdmi_msm_reset_core()
-{
- uint32_t reg_val = 0;
- hdmi_msm_set_mode(0);
- // Disable clocks
- hdmi_app_clk_init(0);
- udelay(5);
- // Enable clocks
- hdmi_app_clk_init(1);
-
- reg_val = secure_readl(SW_RESET_CORE_REG);
- reg_val |= BIT(11);
- secure_writel(reg_val, SW_RESET_CORE_REG);
- udelay(5);
- reg_val = secure_readl(SW_RESET_AHB_REG);
- reg_val |= BIT(9);
- secure_writel(reg_val, SW_RESET_AHB_REG);
- udelay(5);
- reg_val = secure_readl(SW_RESET_AHB_REG);
- reg_val |= BIT(9);
- secure_writel(reg_val, SW_RESET_AHB_REG);
- udelay(20);
- reg_val = secure_readl(SW_RESET_CORE_REG);
- reg_val &= ~(BIT(11));
- secure_writel(reg_val, SW_RESET_CORE_REG);
- udelay(5);
- reg_val = secure_readl(SW_RESET_AHB_REG);
- reg_val &= ~(BIT(9));
- secure_writel(reg_val, SW_RESET_AHB_REG);
- udelay(5);
- reg_val = secure_readl(SW_RESET_AHB_REG);
- reg_val &= ~(BIT(9));
- secure_writel(reg_val, SW_RESET_AHB_REG);
- udelay(5);
-}
-
-void hdmi_msm_turn_on(void)
+int hdmi_msm_turn_on(void)
{
uint32_t hotplug_control;
+
+ hdmi_msm_set_mode(0);
+
hdmi_msm_reset_core(); // Reset the core
hdmi_msm_init_phy();
+
// Enable USEC REF timer
writel(0x0001001B, HDMI_USEC_REFTIMER);
- // Video setup for HDMI
- hdmi_video_setup();
+
// Write 1 to HDMI_CTRL to enable HDMI
hdmi_msm_set_mode(1);
- dprintf(SPEW, "HDMI Core is: %s\n",
- (readl(HDMI_CTRL) & 0x00000001) ? "on" : "off");
+
+ // Video setup for HDMI
+ hdmi_video_setup();
+
+ // AVI info setup
+ hdmi_msm_avi_info_frame();
+
+ return 0;
}
-struct fbcon_config *hdmi_dtv_init(struct hdmi_disp_mode_timing_type *timing)
+int hdmi_dtv_init()
{
- uint32_t dtv_width;
- uint32_t dtv_height;
- uint32_t dtv_bpp;
uint32_t hsync_period;
uint32_t hsync_ctrl;
uint32_t hsync_start_x;
@@ -219,21 +341,13 @@
unsigned char *overlay_base;
uint32_t val;
- dprintf(SPEW, "In DTV on function\n");
-
- // Turn on all the clocks
- dtv_on();
-
- dtv_width = timing->width;
- dtv_height = timing->height;
- dtv_bpp = fb_cfg.bpp;
- fb_cfg.base = FB_ADDR;
+ struct hdmi_disp_mode_timing_type *timing =
+ hdmi_common_init_panel_info();
// MDP E config
- writel((unsigned)fb_cfg.base, MDP_BASE + 0xb0008); //FB Address
-
- writel(((fb_cfg.height << 16) | fb_cfg.width), MDP_BASE + 0xb0004);
- writel((fb_cfg.width * fb_cfg.bpp / 8), MDP_BASE + 0xb000c);
+ writel((unsigned)timing->base, MDP_BASE + 0xb0008); //FB Address
+ writel(((timing->height << 16) | timing->width), MDP_BASE + 0xb0004);
+ writel((timing->width * timing->bpp / 8), MDP_BASE + 0xb000c);
writel(0, MDP_BASE + 0xb0010);
writel(DMA_PACK_PATTERN_RGB | DMA_DSTC0G_8BITS | DMA_DSTC1B_8BITS |
@@ -247,11 +361,11 @@
rgb_base += (MDP4_RGB_OFF * 1);
writel(((timing->height << 16) | timing->width), rgb_base + 0x0000);
writel(0x0, rgb_base + 0x0004);
- writel(0x0, rgb_base + 0x0008);
+ writel(((timing->height << 16) | timing->width), rgb_base + 0x0008);
writel(0x0, rgb_base + 0x000c);
- writel(fb_cfg.base, rgb_base + 0x0010); //FB address
- writel((fb_cfg.width * fb_cfg.bpp / 8), rgb_base + 0x0040);
- writel(0x24216, rgb_base + 0x0050); //format
+ writel(timing->base, rgb_base + 0x0010); //FB address
+ writel((timing->width * timing->bpp / 8), rgb_base + 0x0040);
+ writel(0x2443F, rgb_base + 0x0050); //format
writel(0x20001, rgb_base + 0x0054); //pattern
writel(0x0, rgb_base + 0x0058);
writel(0x20000000, rgb_base + 0x005c); //phaseX
@@ -271,19 +385,20 @@
// Overlay cfg
overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;
+
writel(0x0, MDP_BASE + 0x0038); //EXternal interface select
data = ((timing->height << 16) | timing->width);
writel(data, overlay_base + 0x0008);
- writel(fb_cfg.base, overlay_base + 0x000c);
- writel((fb_cfg.width * fb_cfg.bpp / 8), overlay_base + 0x0010);
+ writel(timing->base, overlay_base + 0x000c);
+ writel((timing->width * timing->bpp / 8), overlay_base + 0x0010);
writel(0x10, overlay_base + 0x104);
writel(0x10, overlay_base + 0x124);
writel(0x10, overlay_base + 0x144);
- writel(0x1, overlay_base + 0x0004); /* directout */
+ writel(0x01, overlay_base + 0x0004); /* directout */
hsync_period =
- timing->hsync_width + timing->hsync_porch_bp + dtv_width +
+ timing->hsync_width + timing->hsync_porch_bp + timing->width +
timing->hsync_porch_fp;
hsync_ctrl = (hsync_period << 16) | timing->hsync_width;
hsync_start_x = timing->hsync_width + timing->hsync_porch_bp;
@@ -291,7 +406,7 @@
display_hctl = (hsync_end_x << 16) | hsync_start_x;
vsync_period =
- (timing->vsync_width + timing->vsync_porch_bp + dtv_height +
+ (timing->vsync_width + timing->vsync_porch_bp + timing->height +
timing->vsync_porch_fp) * hsync_period;
display_v_start =
(timing->vsync_width + timing->vsync_porch_bp) * hsync_period;
@@ -299,42 +414,36 @@
vsync_period - (timing->vsync_porch_bp * hsync_period) - 1;
dtv_underflow_clr |= 0x80000000;
- hsync_polarity = 0;
- vsync_polarity = 0;
- data_en_polarity = 0;
- ctrl_polarity =
+ hsync_polarity = 0;
+ vsync_polarity = 0;
+ data_en_polarity = 0;
+ ctrl_polarity =
(data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
- writel(hsync_ctrl, MDP_BASE + DTV_BASE + 0x4);
- writel(vsync_period, MDP_BASE + DTV_BASE + 0x8);
- writel(timing->vsync_width * hsync_period, MDP_BASE + DTV_BASE + 0xc);
- writel(display_hctl, MDP_BASE + DTV_BASE + 0x18);
+ writel(hsync_ctrl, MDP_BASE + DTV_BASE + 0x4);
+ writel(vsync_period, MDP_BASE + DTV_BASE + 0x8);
+ writel(timing->vsync_width * hsync_period,
+ MDP_BASE + DTV_BASE + 0xc);
+ writel(display_hctl, MDP_BASE + DTV_BASE + 0x18);
writel(display_v_start, MDP_BASE + DTV_BASE + 0x1c);
- writel(0x25a197, MDP_BASE + DTV_BASE + 0x20);
- writel(dtv_border_clr, MDP_BASE + DTV_BASE + 0x40);
- writel(0x8fffffff, MDP_BASE + DTV_BASE + 0x44);
- writel(dtv_hsync_skew, MDP_BASE + DTV_BASE + 0x48);
- writel(ctrl_polarity, MDP_BASE + DTV_BASE + 0x50);
- writel(0, MDP_BASE + DTV_BASE + 0x2c);
- writel(active_v_start, MDP_BASE + DTV_BASE + 0x30);
- writel(active_v_end, MDP_BASE + DTV_BASE + 0x38);
+ writel(0x25a197, MDP_BASE + DTV_BASE + 0x20);
+ writel(dtv_border_clr, MDP_BASE + DTV_BASE + 0x40);
+ writel(0x8fffffff, MDP_BASE + DTV_BASE + 0x44);
+ writel(dtv_hsync_skew, MDP_BASE + DTV_BASE + 0x48);
+ writel(ctrl_polarity, MDP_BASE + DTV_BASE + 0x50);
+ writel(0x0, MDP_BASE + DTV_BASE + 0x2c);
+ writel(active_v_start, MDP_BASE + DTV_BASE + 0x30);
+ writel(active_v_end, MDP_BASE + DTV_BASE + 0x38);
- /*
- * Keep Display solid color, for future debugging
- */
-# if 0
- writel(0xffffffff, 0x05151008);
- val = readl(MDP_BASE + 0x50050);
- val |= BIT(22);
- writel(val, MDP_BASE + 0x50050);
- writel(BIT(5), MDP_BASE + 0x18000);
-#endif
/* Enable DTV block */
- writel(0x1, MDP_BASE + DTV_BASE);
+ writel(0x01, MDP_BASE + DTV_BASE);
+
+ /* Flush mixer/pipes configurations */
val = BIT(1);
val |= BIT(5);
writel(val, MDP_BASE + 0x18000);
- return &fb_cfg;
+
+ return 0;
}
void hdmi_display_shutdown()
diff --git a/platform/msm_shared/include/hdmi.h b/platform/msm_shared/include/hdmi.h
index 5edfbbe..0b4fd5b 100644
--- a/platform/msm_shared/include/hdmi.h
+++ b/platform/msm_shared/include/hdmi.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -36,8 +36,6 @@
#include <dev/fbcon.h>
#include <target/display.h>
-#define FB_ADDR 0x43E00000
-
#define MDP_GET_PACK_PATTERN(a,x,y,z,bit) (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
#define DMA_PACK_ALIGN_LSB 0
#define DMA_PACK_PATTERN_RGB \
@@ -63,7 +61,12 @@
uint8_t dir, uint8_t pull,
uint8_t drvstr, uint32_t enable);
-void dtv_on();
+int hdmi_dtv_on(void);
+void hdmi_msm_set_mode(int on);
+void hdmi_msm_init_phy(void);
+void hdmi_display_shutdown(void);
+void hdmi_msm_reset_core(void);
+void hdmi_set_fb_addr(void *addr);
struct hdmi_disp_mode_timing_type {
uint32_t height;
@@ -75,16 +78,7 @@
uint32_t vsync_width;
uint32_t vsync_porch_bp;
uint32_t refresh_rate;
+ uint32_t bpp;
+ void *base;
};
-
-static struct fbcon_config fb_cfg = {
- .height = DTV_FB_HEIGHT,
- .width = DTV_FB_WIDTH,
- .stride = DTV_FB_WIDTH,
- .format = DTV_FORMAT_RGB565,
- .bpp = DTV_BPP,
- .update_start = NULL,
- .update_done = NULL,
-};
-
#endif /* __PLATFORM_MSM_SHARED_HDMI_H */
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 6e14bd0..1519a98 100644
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -76,6 +76,15 @@
uint32_t rev;
};
+struct hdmi_panel_info {
+ uint32_t h_back_porch;
+ uint32_t h_front_porch;
+ uint32_t h_pulse_width;
+ uint32_t v_back_porch;
+ uint32_t v_front_porch;
+ uint32_t v_pulse_width;
+};
+
struct lcdc_panel_info {
uint32_t h_back_porch;
uint32_t h_front_porch;
@@ -166,6 +175,7 @@
struct lcdc_panel_info lcdc;
struct mipi_panel_info mipi;
struct lvds_panel_info lvds;
+ struct hdmi_panel_info hdmi;
int (*on) (void);
int (*off) (void);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 337e4a4..e0cbb50 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -36,7 +36,8 @@
endif
ifeq ($(PLATFORM),msm8960)
- OBJS += $(LOCAL_DIR)/mipi_dsi.o \
+ OBJS += $(LOCAL_DIR)/hdmi.o \
+ $(LOCAL_DIR)/mipi_dsi.o \
$(LOCAL_DIR)/i2c_qup.o \
$(LOCAL_DIR)/uart_dm.o \
$(LOCAL_DIR)/qgic.o \
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 837f0d2..c24eb3b 100755
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -251,6 +251,8 @@
MSM8130 = 179,
MSM8130AA = 180,
MSM8130AB = 181,
+ MSM8627AA = 182,
+ MSM8227AA = 183,
};
enum platform {
diff --git a/target/msm8960/init.c b/target/msm8960/init.c
index d0c15fc..c53db3e 100755
--- a/target/msm8960/init.c
+++ b/target/msm8960/init.c
@@ -381,7 +381,8 @@
default:
target_id = LINUX_MACHTYPE_8930_CDP;
}
- } else if ((platform == MSM8227) || (platform == MSM8627)) {
+ } else if ((platform == MSM8227) || (platform == MSM8627) ||
+ (platform == MSM8227AA) || (platform == MSM8627AA)) {
switch (platform_hw) {
case HW_PLATFORM_SURF:
target_id = LINUX_MACHTYPE_8627_CDP;
diff --git a/target/msm8960/rules.mk b/target/msm8960/rules.mk
index 0074ccc..8cf761c 100644
--- a/target/msm8960/rules.mk
+++ b/target/msm8960/rules.mk
@@ -18,6 +18,7 @@
DEFINES += DISPLAY_SPLASH_SCREEN=1
DEFINES += DISPLAY_TYPE_MIPI=1
+DEFINES += DISPLAY_TYPE_HDMI=1
MODULES += \
dev/keys \
diff --git a/target/msm8960/target_display.c b/target/msm8960/target_display.c
index 3eab940..39a3aeb 100644
--- a/target/msm8960/target_display.c
+++ b/target/msm8960/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -148,6 +148,24 @@
return 0;
}
+static int mpq8064_hdmi_panel_clock(int enable)
+{
+ if (enable)
+ mdp_clock_init();
+
+ hdmi_app_clk_init(enable);
+
+ return 0;
+}
+
+static int mpq8064_hdmi_panel_power(int enable)
+{
+ if (enable)
+ hdmi_power_init();
+
+ return 0;
+}
+
static int msm8960_liquid_mipi_panel_clock(int enable)
{
if (enable) {
@@ -298,6 +316,23 @@
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_42;
break;
+ case LINUX_MACHTYPE_8064_MPQ_CDP:
+ case LINUX_MACHTYPE_8064_MPQ_HRD:
+ case LINUX_MACHTYPE_8064_MPQ_DTV:
+ hdmi_msm_panel_init(&panel.panel_info);
+
+ panel.clk_func = mpq8064_hdmi_panel_clock;
+ panel.power_func = mpq8064_hdmi_panel_power;
+ panel.fb.base = 0x89000000;
+ panel.fb.width = panel.panel_info.xres;
+ panel.fb.height = panel.panel_info.yres;
+ panel.fb.stride = panel.panel_info.xres;
+ panel.fb.bpp = panel.panel_info.bpp;
+ panel.fb.format = FB_FORMAT_RGB565;
+ panel.mdp_rev = MDP_REV_44;
+
+ hdmi_set_fb_addr(panel.fb.base);
+ break;
default:
return;
};
@@ -307,13 +342,13 @@
return;
}
- display_image_on_screen();
display_enable = 1;
}
void display_shutdown(void)
{
- if (display_enable)
+ if (display_enable) {
msm_display_off();
+ }
}
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index e2e0222..35f00e6 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -281,3 +281,16 @@
return 0;
}
}
+
+unsigned target_pause_for_battery_charge(void)
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+
+ /* This function will always return 0 to facilitate
+ * automated testing/reboot with usb connected.
+ * uncomment if this feature is needed */
+ /* if ((pon_reason == USB_CHG) || (pon_reason == DC_CHG))
+ return 1;*/
+
+ return 0;
+}