Merge "platform/target: msm8909: Add changes to support some features."
diff --git a/platform/msm8909/gpio.c b/platform/msm8909/gpio.c
index 8d7355d..7f570a8 100644
--- a/platform/msm8909/gpio.c
+++ b/platform/msm8909/gpio.c
@@ -62,3 +62,9 @@
gpio_tlmm_config(20, 2, GPIO_OUTPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
}
+
+uint32_t gpio_status(uint32_t gpio)
+{
+ return readl(GPIO_IN_OUT_ADDR(gpio)) & GPIO_IN;
+}
+
diff --git a/platform/msm8909/include/platform/gpio.h b/platform/msm8909/include/platform/gpio.h
index d970f47..da40c1e 100644
--- a/platform/msm8909/include/platform/gpio.h
+++ b/platform/msm8909/include/platform/gpio.h
@@ -29,6 +29,8 @@
#ifndef __PLATFORM_MSM8909_GPIO_H
#define __PLATFORM_MSM8909_GPIO_H
+#include <bits.h>
+#include <gpio.h>
/* GPIO TLMM: Direction */
#define GPIO_INPUT 0
@@ -54,6 +56,9 @@
#define GPIO_ENABLE 0
#define GPIO_DISABLE 1
+/* GPIO_IN_OUT register shifts. */
+#define GPIO_IN BIT(0)
+#define GPIO_OUT BIT(1)
void gpio_config_uart_dm(uint8_t id);
#endif
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index d0c4f42..4f59eff 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -32,6 +32,16 @@
#define MSM_IOMAP_BASE 0x00000000
#define MSM_IOMAP_END 0x08000000
+#define A7_SS_BASE 0x0B000000
+#define A7_SS_END 0x0B200000
+
+#define SYSTEM_IMEM_BASE 0x08600000
+#define MSM_SHARED_IMEM_BASE 0x08600000
+
+#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+#define BS_INFO_OFFSET (0x6B0)
+#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
+
#define SDRAM_START_ADDR 0x80000000
#define MSM_SHARED_BASE 0x86300000
@@ -74,14 +84,27 @@
#define MPM2_MPM_CTRL_BASE 0x004A0000
#define MPM2_MPM_PS_HOLD 0x004AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
/* CRYPTO ENGINE */
#define MSM_CE1_BASE 0x073A000
#define MSM_CE1_BAM_BASE 0x0704000
+#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
+#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
+#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
+#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
+#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
+#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
+
+/* I2C */
+#define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010)
+#define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3018)
+#define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3014)
/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x21024)
+#define GPLL1_STATUS (CLK_CTL_BASE + 0x2001C)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
@@ -96,6 +119,14 @@
#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
+#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
@@ -195,4 +226,5 @@
#define VIDEO_MODE_CTRL 0x010
#define HS_TIMER_CTRL 0x0BC
+#define TCSR_TZ_WONCE 0x193D000
#endif
diff --git a/platform/msm8909/msm8909-clock.c b/platform/msm8909/msm8909-clock.c
index eff91e7..a2af96d 100644
--- a/platform/msm8909/msm8909-clock.c
+++ b/platform/msm8909/msm8909-clock.c
@@ -41,6 +41,8 @@
#define gpll0_source_val 1
#define cxo_mm_source_val 0
#define gpll0_mm_source_val 1
+#define gpll1_mm_source_val 3
+
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -109,6 +111,21 @@
},
};
+static struct pll_vote_clk gpll1_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(1),
+ .status_reg = (void *) GPLL1_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 614400000,
+ .dbg_name = "gpll1_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
/* SDCC Clocks */
static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
{
@@ -321,115 +338,6 @@
},
};
-/* Display clocks */
-static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
- F_MM(19200000, cxo, 1, 0, 0),
- F_END
-};
-
-static struct clk_freq_tbl ftbl_mdp_clk[] = {
- F_MM( 80000000, gpll0, 10, 0, 0),
- F_MM( 100000000, gpll0, 8, 0, 0),
- F_MM( 200000000, gpll0, 4, 0, 0),
- F_MM( 320000000, gpll0, 2.5, 0, 0),
- F_END
-};
-
-static struct rcg_clk dsi_esc0_clk_src = {
- .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR,
- .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_mdss_esc0_1_clk,
-
- .c = {
- .dbg_name = "dsi_esc0_clk_src",
- .ops = &clk_ops_rcg,
- },
-};
-
-static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
- F_MM(19200000, cxo, 1, 0, 0),
- F_END
-};
-
-static struct rcg_clk vsync_clk_src = {
- .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR,
- .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_mdss_vsync_clk,
-
- .c = {
- .dbg_name = "vsync_clk_src",
- .ops = &clk_ops_rcg,
- },
-};
-
-static struct branch_clk mdss_esc0_clk = {
- .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR,
- .parent = &dsi_esc0_clk_src.c,
- .has_sibling = 0,
-
- .c = {
- .dbg_name = "mdss_esc0_clk",
- .ops = &clk_ops_branch,
- },
-};
-
-static struct branch_clk mdss_axi_clk = {
- .cbcr_reg = (uint32_t *) MDP_AXI_CBCR,
- .has_sibling = 1,
-
- .c = {
- .dbg_name = "mdss_axi_clk",
- .ops = &clk_ops_branch,
- },
-};
-
-static struct branch_clk mdp_ahb_clk = {
- .cbcr_reg = (uint32_t *) MDP_AHB_CBCR,
- .has_sibling = 1,
-
- .c = {
- .dbg_name = "mdp_ahb_clk",
- .ops = &clk_ops_branch,
- },
-};
-
-static struct rcg_clk mdss_mdp_clk_src = {
- .cmd_reg = (uint32_t *) MDP_CMD_RCGR,
- .cfg_reg = (uint32_t *) MDP_CFG_RCGR,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_mdp_clk,
- .current_freq = &rcg_dummy_freq,
-
- .c = {
- .dbg_name = "mdss_mdp_clk_src",
- .ops = &clk_ops_rcg,
- },
-};
-
-static struct branch_clk mdss_mdp_clk = {
- .cbcr_reg = (uint32_t *) MDP_CBCR,
- .parent = &mdss_mdp_clk_src.c,
- .has_sibling = 0,
-
- .c = {
- .dbg_name = "mdss_mdp_clk",
- .ops = &clk_ops_branch,
- },
-};
-
-static struct branch_clk mdss_vsync_clk = {
- .cbcr_reg = MDSS_VSYNC_CBCR,
- .parent = &vsync_clk_src.c,
- .has_sibling = 0,
-
- .c = {
- .dbg_name = "mdss_vsync_clk",
- .ops = &clk_ops_branch,
- },
-};
-
static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
F(160000000, gpll0, 5, 0, 0),
F_END
@@ -520,13 +428,6 @@
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
- CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
- CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
- CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c),
- CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c),
- CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
- CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
-
CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
diff --git a/platform/msm8909/platform.c b/platform/msm8909/platform.c
index 3765be4..48891e9 100644
--- a/platform/msm8909/platform.c
+++ b/platform/msm8909/platform.c
@@ -35,9 +35,37 @@
#include <arch/arm/mmu.h>
#include <smem.h>
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+#define A7_SS_SIZE ((A7_SS_END - A7_SS_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ { A7_SS_BASE, A7_SS_BASE, A7_SS_SIZE, IOMAP_MEMORY},
+ { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+};
+
+static struct smem_ram_ptable ram_ptable;
+
void platform_early_init(void)
{
board_init();
+ platform_clock_init();
qgic_init();
qtimer_init();
}
@@ -51,3 +79,106 @@
{
qtimer_uninit();
}
+
+uint32_t platform_get_sclk_count(void)
+{
+ return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+addr_t get_bs_info_addr()
+{
+ return ((addr_t)BS_INFO_ADDR);
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ ram_partition ptn_entry;
+ uint32_t len = 0;
+
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Configure the MMU page entries for SDRAM and IMEM memory read
+ from the smem ram table*/
+ for(i = 0; i < len; i++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, i);
+ if(ptn_entry.type == SYS_MEMORY)
+ {
+ if((ptn_entry.category == SDRAM) ||
+ (ptn_entry.category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ptn_entry.start & (MB-1)) == 0);
+
+ sections = (ptn_entry.size) / MB;
+ while(sections--)
+ {
+ arm_mmu_map_section(ptn_entry.start +
+ sections * MB,
+ ptn_entry.start +
+ sections * MB,
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+ }
+ }
+ }
+ }
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
+
+/* DYNAMIC SMEM REGION feature enables LK to dynamically
+ * read the SMEM addr info from TCSR_TZ_WONCE register.
+ * The first word read, if indicates a MAGIC number, then
+ * Dynamic SMEM is assumed to be enabled. Read the remaining
+ * SMEM info for SMEM Size and Phy_addr from the other bytes.
+ */
+uint32_t platform_get_smem_base_addr()
+{
+ struct smem_addr_info *smem_info = NULL;
+
+ smem_info = (struct smem_addr_info *)readl(TCSR_TZ_WONCE);
+ if(smem_info && (smem_info->identifier == SMEM_TARGET_INFO_IDENTIFIER))
+ return smem_info->phy_addr;
+ else
+ return MSM_SHARED_BASE;
+}
+
diff --git a/platform/msm8909/rules.mk b/platform/msm8909/rules.mk
index da6f955..4da135e 100644
--- a/platform/msm8909/rules.mk
+++ b/platform/msm8909/rules.mk
@@ -1,7 +1,6 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
ARCH := arm
-#Compiling this as cortex-a8 until the compiler supports krait
ARM_CPU := cortex-a8
CPU := generic
@@ -11,13 +10,15 @@
DEFINES += PERIPH_BLK_BLSP=1
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
- MMC_SLOT=$(MMC_SLOT)
+ MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
OBJS += \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/msm8909-clock.o \
$(LOCAL_DIR)/gpio.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 8382017..e9d60a0 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -48,9 +48,32 @@
#include <stdlib.h>
#include <gpio.h>
+#if LONG_PRESS_POWER_ON
+#include <shutdown_detect.h>
+#endif
+
+#if PON_VIB_SUPPORT
+#include <vibrator.h>
+#endif
+
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
+#define TLMM_VOL_UP_BTN_GPIO 90
+#if PON_VIB_SUPPORT
+#define VIBRATE_TIME 250
+#endif
+
+#define FASTBOOT_MODE 0x77665500
+
+#define CE1_INSTANCE 1
+#define CE_EE 1
+#define CE_FIFO_SIZE 64
+#define CE_READ_PIPE 3
+#define CE_WRITE_PIPE 2
+#define CE_READ_PIPE_LOCK_GRP 0
+#define CE_WRITE_PIPE_LOCK_GRP 0
+#define CE_ARRAY_SIZE 20
struct mmc_device *dev;
@@ -109,8 +132,40 @@
return (void *) dev;
}
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ uint8_t status = 0;
+
+ gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE);
+
+ /* Wait for the gpio config to take effect - debounce time */
+ thread_sleep(10);
+
+ /* Get status of GPIO */
+ status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
+
+ /* Active low signal. */
+ return !status;
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ /* Volume down button tied in with PMIC RESIN. */
+ return pm8x41_resin_status();
+}
+
static void target_keystatus()
{
+ keys_init();
+
+ if(target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if(target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
+
}
static void set_sdc_power_ctrl()
@@ -155,6 +210,18 @@
ASSERT(0);
}
+#if LONG_PRESS_POWER_ON
+ shutdown_detect();
+#endif
+
+#if PON_VIB_SUPPORT
+
+ /* turn on vibrator to indicate that phone is booting up to end user */
+ vib_timed_turn_on(VIBRATE_TIME);
+#endif
+
+ if (target_use_signed_kernel())
+ target_crypto_init_params();
}
void target_serialno(unsigned char *buf)
@@ -168,6 +235,93 @@
unsigned board_machtype(void)
{
+ return LINUX_MACHTYPE_UNKNOWN;
+}
+
+unsigned check_reboot_mode(void)
+{
+ uint32_t restart_reason = 0;
+
+ /* Read reboot reason and scrub it */
+ restart_reason = readl(RESTART_REASON_ADDR);
+ writel(0x00, RESTART_REASON_ADDR);
+
+ return restart_reason;
+}
+
+static int scm_dload_mode(int mode)
+{
+ int ret = 0;
+ uint32_t dload_type;
+
+ dprintf(SPEW, "DLOAD mode: %d\n", mode);
+ if (mode == NORMAL_DLOAD)
+ dload_type = SCM_DLOAD_MODE;
+ else if(mode == EMERGENCY_DLOAD)
+ dload_type = SCM_EDLOAD_MODE;
+ else
+ dload_type = 0;
+
+ ret = scm_call_atomic2(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0);
+ if (ret)
+ dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret);
+
+ ret = scm_call_atomic2(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
+ if (ret)
+ dprintf(CRITICAL, "Failed to disable the wdog debug \n");
+
+ return ret;
+}
+
+/* Configure PMIC and Drop PS_HOLD for shutdown */
+void shutdown_device()
+{
+ dprintf(CRITICAL, "Going down for shutdown.\n");
+
+ /* Configure PMIC for shutdown */
+ pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+ uint8_t reset_type = 0;
+ uint32_t ret = 0;
+
+ /* Need to clear the SW_RESET_ENTRY register and
+ * write to the BOOT_MISC_REG for known reset cases
+ */
+ if(reboot_reason != DLOAD)
+ scm_dload_mode(NORMAL_MODE);
+
+ writel(reboot_reason, RESTART_REASON_ADDR);
+
+ /* For Reboot-bootloader and Dload cases do a warm reset
+ * For Reboot cases do a hard reset
+ */
+ if((reboot_reason == FASTBOOT_MODE) || (reboot_reason == DLOAD))
+ reset_type = PON_PSHOLD_WARM_RESET;
+ else
+ reset_type = PON_PSHOLD_HARD_RESET;
+
+ pm8x41_reset_configure(reset_type);
+
+ ret = scm_halt_pmic_arbiter();
+
+ if (ret)
+ dprintf(CRITICAL , "Failed to halt pmic arbiter: %d\n", ret);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "Rebooting failed\n");
}
/* Detect the target type */
@@ -235,3 +389,177 @@
splash_override = override;
}
+unsigned target_baseband()
+{
+ return board_baseband();
+}
+
+int emmc_recovery_init(void)
+{
+ return _emmc_recovery_init();
+}
+
+void target_usb_init(void)
+{
+ uint32_t val;
+
+ /* Select and enable external configuration with USB PHY */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
+
+ /* Enable sess_vld */
+ val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
+ writel(val, USB_GENCONFIG_2);
+
+ /* Enable external vbus configuration in the LINK */
+ val = readl(USB_USBCMD);
+ val |= SESS_VLD_CTRL;
+ writel(val, USB_USBCMD);
+}
+
+unsigned target_pause_for_battery_charge(void)
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+ uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /* In case of fastboot reboot,adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ return 1;
+ else
+ return 0;
+}
+
+void target_usb_stop(void)
+{
+ /* Disable VBUS mimicing in the controller. */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
+}
+
+
+void target_uninit(void)
+{
+#if PON_VIB_SUPPORT
+ /* wait for the vibrator timer is expried */
+ wait_vib_timeout();
+#endif
+
+ mmc_put_card_to_sleep(dev);
+ sdhci_mode_disable(&dev->host);
+
+ if (crypto_initialized())
+ crypto_eng_cleanup();
+
+ if (target_is_ssd_enabled())
+ clock_ce_disable(CE1_INSTANCE);
+}
+
+/* Do any target specific intialization needed before entering fastboot mode */
+void target_fastboot_init(void)
+{
+ /* Set the BOOT_DONE flag in PM8916 */
+ pm8x41_set_boot_done();
+
+ if (target_is_ssd_enabled()) {
+ clock_ce_enable(CE1_INSTANCE);
+ target_load_ssd_keystore();
+ }
+}
+
+int set_download_mode(enum dload_mode mode)
+{
+ int ret = 0;
+ ret = scm_dload_mode(mode);
+
+ pm8x41_clear_pmic_watchdog();
+
+ return ret;
+}
+
+void target_load_ssd_keystore(void)
+{
+ uint64_t ptn;
+ int index;
+ uint64_t size;
+ uint32_t *buffer = NULL;
+
+ if (!target_is_ssd_enabled())
+ return;
+
+ index = partition_get_index("ssd");
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0){
+ dprintf(CRITICAL, "Error: ssd partition not found\n");
+ return;
+ }
+
+ size = partition_get_size(index);
+ if (size == 0) {
+ dprintf(CRITICAL, "Error: invalid ssd partition size\n");
+ return;
+ }
+
+ buffer = memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
+ if (!buffer) {
+ dprintf(CRITICAL, "Error: allocating memory for ssd buffer\n");
+ return;
+ }
+ if (mmc_read(ptn, buffer, size)) {
+ dprintf(CRITICAL, "Error: cannot read data\n");
+ free(buffer);
+ return;
+ }
+
+ clock_ce_enable(CE1_INSTANCE);
+ scm_protect_keystore(buffer, size);
+ clock_ce_disable(CE1_INSTANCE);
+ free(buffer);
+}
+
+crypto_engine_type board_ce_type(void)
+{
+ return CRYPTO_ENGINE_TYPE_HW;
+}
+
+/* Set up params for h/w CE. */
+void target_crypto_init_params()
+{
+ struct crypto_init_params ce_params;
+
+ /* Set up base addresses and instance. */
+ ce_params.crypto_instance = CE1_INSTANCE;
+ ce_params.crypto_base = MSM_CE1_BASE;
+ ce_params.bam_base = MSM_CE1_BAM_BASE;
+
+ /* Set up BAM config. */
+ ce_params.bam_ee = CE_EE;
+ ce_params.pipes.read_pipe = CE_READ_PIPE;
+ ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
+
+ /* Assign buffer sizes. */
+ ce_params.num_ce = CE_ARRAY_SIZE;
+ ce_params.read_fifo_size = CE_FIFO_SIZE;
+ ce_params.write_fifo_size = CE_FIFO_SIZE;
+
+ /* BAM is initialized by TZ for this platform.
+ * Do not do it again as the initialization address space
+ * is locked.
+ */
+ ce_params.do_bam_init = 0;
+
+ crypto_init_params(&ce_params);
+}
+
+uint32_t target_get_hlos_subtype()
+{
+ return board_hlos_subtype();
+}