target: msm8994: Add API for ddr config value
For hs400 mode the rclk delay in the ddr config varies
based on the target, add API to return the target specific
ddr config value.
Change-Id: Ibedd30fd56d840c4e3a89f7d75466d5d65e49766
diff --git a/include/target.h b/include/target.h
index ba95cbb..16a4268 100644
--- a/include/target.h
+++ b/include/target.h
@@ -75,4 +75,5 @@
bool target_is_cdp_qvga();
uint32_t target_hw_interposer();
uint32_t target_override_pll();
+uint32_t target_ddr_cfg_val();
#endif
diff --git a/target/init.c b/target/init.c
index 78feeea..79e0466 100644
--- a/target/init.c
+++ b/target/init.c
@@ -25,6 +25,7 @@
#include <target.h>
#include <compiler.h>
#include <dload_util.h>
+#include <sdhci_msm.h>
#define EXPAND(NAME) #NAME
#define TARGET(NAME) EXPAND(NAME)
@@ -197,3 +198,9 @@
__WEAK void target_crypto_init_params()
{
}
+
+/* Default CFG delay value */
+__WEAK uint32_t target_ddr_cfg_val()
+{
+ return DDR_CONFIG_VAL;
+}
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 0780268..01b5208 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -76,6 +76,7 @@
#define FASTBOOT_MODE 0x77665500
#define PMIC_WLED_SLAVE_ID 3
+#define DDR_CFG_DLY_VAL 0x80040870
static void set_sdc_power_ctrl(uint8_t slot);
static uint32_t mmc_pwrctl_base[] =
@@ -539,3 +540,8 @@
/* We are entering fastboot mode, so read partition table */
mmc_read_partition_table(1);
}
+
+uint32_t target_ddr_cfg_val()
+{
+ return DDR_CFG_DLY_VAL;
+}