msm7627a: Add support for lcdc splash screen
This patch adds lcdc splash screen support for SKU7
device
Change-Id: Ia2560ab70280325e5e0250158798dd9121551b14
diff --git a/dev/panel/msm/lcdc_truly.h b/dev/panel/msm/lcdc_truly.h
new file mode 100644
index 0000000..acfb21d
--- /dev/null
+++ b/dev/panel/msm/lcdc_truly.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Code Aurora nor
+ * the names of its contributors may be used to endorse or promote
+ * products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#ifndef _LCDC_TRULY_H_
+#define _LCDC_TRULY_H_
+
+#define DISPLAY_RESET 90
+#define BACKLIGHT_EN 89
+#define SPI_MOSI 19
+#define SPI_SCLK 20
+#define SPI_CS 21
+#define LCD_LDO_2V8 35
+#define LCD_LDO_1V8 58
+
+#endif
diff --git a/dev/panel/msm/lcdc_truly_hvga.c b/dev/panel/msm/lcdc_truly_hvga.c
new file mode 100644
index 0000000..757194a
--- /dev/null
+++ b/dev/panel/msm/lcdc_truly_hvga.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Code Aurora nor
+ * the names of its contributors may be used to endorse or promote
+ * products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include <msm_panel.h>
+#include <platform/gpio.h>
+#include <debug.h>
+#include <err.h>
+#include "lcdc_truly.h"
+
+extern void spi_bit_bang_write(uint8_t, uint8_t, uint8_t, uint8_t);
+
+static char data1[] = { 0xff, 0x83, 0x57, };
+static char data2[] = { 0x03, };
+static char data3[] = { 0x00, 0x13, 0x1C, 0x1C, 0x83, 0x48, };
+static char data4[] = { 0x43, 0x06, 0x06, 0x06, };
+static char data5[] = { 0x53, };
+static char data6[] = { 0x02, 0x40, 0x00, 0x2a, 0x2a, 0x0d, 0x3f, };
+static char data7[] = { 0x70, 0x50, 0x01, 0x3c, 0xe8, 0x08, };
+static char data8[] = { 0x17, 0x0f, };
+static char data9[] = { 0x60};
+static char data10[] = { 0x00, 0x13, 0x1a, 0x29, 0x2d, 0x41, 0x49,
+ 0x52, 0x48, 0x41, 0x3c, 0x33, 0x30, 0x1c,
+ 0x19, 0x03, 0x00, 0x13, 0x1a, 0x29, 0x2d,
+ 0x41, 0x49, 0x52, 0x48, 0x41, 0x3c, 0x33,
+ 0x31, 0x1c, 0x19, 0x03, 0x00, 0x01,
+};
+static char data11[] = { 0x40, };
+
+static void lcdc_truly_panel_power(int on)
+{
+ uint32_t func = 0;
+ uint32_t pull = 0;
+ uint32_t drv = 0;
+ uint32_t dir = 0;
+
+ dprintf(SPEW, "lcdc_truly_panel_power on = %d\n", on);
+
+ if (on) {
+ func = 0;
+ dir = GPIO_OUTPUT;
+ pull = GPIO_NO_PULL;
+ drv = GPIO_2MA;
+
+ /* config SPI, RESET and Backlight */
+ gpio_tlmm_config(GPIO_CFG(SPI_MOSI, func, dir, pull, drv), 0);
+ gpio_tlmm_config(GPIO_CFG(SPI_SCLK, func, dir, pull, drv), 0);
+ gpio_tlmm_config(GPIO_CFG(SPI_CS, func, dir, pull, drv), 0);
+ gpio_tlmm_config(GPIO_CFG(BACKLIGHT_EN, func, dir, pull, drv), 0);
+ gpio_tlmm_config(GPIO_CFG(DISPLAY_RESET, func, dir, pull, drv), 0);
+ gpio_tlmm_config(GPIO_CFG(LCD_LDO_2V8, func, dir, pull, drv), 0);
+ gpio_tlmm_config(GPIO_CFG(LCD_LDO_1V8, func, dir, pull, drv), 0);
+
+ gpio_config(SPI_MOSI, GPIO_OUTPUT);
+ gpio_config(SPI_SCLK, GPIO_OUTPUT);
+ gpio_config(SPI_CS, GPIO_OUTPUT);
+ gpio_config(BACKLIGHT_EN, GPIO_OUTPUT);
+ gpio_config(DISPLAY_RESET, GPIO_OUTPUT);
+ gpio_config(LCD_LDO_2V8, GPIO_OUTPUT);
+ gpio_config(LCD_LDO_1V8, GPIO_OUTPUT);
+
+ /* turn on backlight */
+ gpio_set(BACKLIGHT_EN, 1);
+ /* turn on power */
+ gpio_set(LCD_LDO_1V8, 1);
+ gpio_set(LCD_LDO_2V8, 1);
+
+ /* reset */
+ gpio_set(DISPLAY_RESET, 1);
+ /*
+ * H/w requires delay between toggle
+ * reset pin
+ */
+ mdelay(20);
+ gpio_set(DISPLAY_RESET, 0);
+ mdelay(20);
+ gpio_set(DISPLAY_RESET, 1);
+ mdelay(20);
+ } else {
+ /* turn off backlight */
+ gpio_set(BACKLIGHT_EN, 0);
+
+ gpio_set(DISPLAY_RESET, 0);
+
+ /* turn off power */
+ gpio_set(LCD_LDO_1V8, 0);
+ gpio_set(LCD_LDO_2V8, 0);
+ }
+ return;
+}
+
+static int truly_spi_write(char cmd, char *data, int num)
+{
+ int i;
+
+ gpio_set(SPI_CS, 0); /* cs low */
+ /* command byte first */
+ spi_bit_bang_write(SPI_SCLK, SPI_MOSI, 0, cmd);
+ /* followed by parameter bytes */
+ for(i = 0; i < num; i++) {
+ if(data)
+ spi_bit_bang_write(SPI_SCLK, SPI_MOSI, 1, data[i]);
+ }
+ gpio_set(SPI_MOSI, 1); /* mosi high */
+ gpio_set(SPI_CS, 1); /* cs high */
+ /*
+ * H/W needs delay for gpio's to turn high
+ */
+ udelay(10);
+ return 0;
+}
+
+void lcdc_truly_disp_on(void)
+{
+ int i;
+
+ dprintf(SPEW, "lcdc_truly_disp_on\n");
+
+ gpio_set(SPI_CS, 1); /* cs high */
+ /*
+ * This function uses delays as defined by the panel
+ * vendor before writing to registers
+ */
+ truly_spi_write(0xb9, data1, sizeof(data1));
+ mdelay(20);
+ truly_spi_write(0xcc, data2, sizeof(data2));
+ truly_spi_write(0xb1, data3, sizeof(data3));
+ truly_spi_write(0xb3, data4, sizeof(data4));
+ truly_spi_write(0xb6, data5, sizeof(data5));
+ truly_spi_write(0xb4, data6, sizeof(data6));
+ truly_spi_write(0xc0, data7, sizeof(data7));
+ truly_spi_write(0xe3, data8, sizeof(data8));
+ truly_spi_write(0x3a, data9, sizeof(data9));
+ truly_spi_write(0xe0, data10, sizeof(data10));
+ truly_spi_write(0x36, data11, sizeof(data11));
+ truly_spi_write(0x11, NULL, 0);
+ mdelay(150);
+ truly_spi_write(0x29, NULL, 0);
+ mdelay(25);
+}
+
+void lcdc_truly_disp_off(void)
+{
+ dprintf(SPEW, "lcdc_truly_disp_off\n");
+ truly_spi_write(0x28, NULL, 0);
+ mdelay(5);
+ truly_spi_write(0x10, NULL, 0);
+}
+
+int lcdc_truly_panel_on(int on)
+{
+ dprintf(SPEW, "lcdc_truly_panel_on\n");
+ if (on) {
+ lcdc_truly_panel_power(1);
+ lcdc_truly_disp_on();
+ } else {
+ lcdc_truly_panel_power(0);
+ lcdc_truly_disp_off();
+ }
+ return NO_ERROR;
+}
+
+int lcdc_truly_hvga_on()
+{
+ return NO_ERROR;
+}
+
+int lcdc_truly_hvga_off()
+{
+ return NO_ERROR;
+}
+
+void lcdc_truly_hvga_init(struct msm_panel_info *pinfo)
+{
+ if (!pinfo)
+ return;
+
+ pinfo->xres = 320;
+ pinfo->yres = 480;
+
+ pinfo->type = LCDC_PANEL;
+ pinfo->wait_cycle = 0;
+ pinfo->bpp = 16;
+ pinfo->clk_rate = 10240000;
+ pinfo->lcdc.h_pulse_width = 8;
+ pinfo->lcdc.h_back_porch = 16;
+ pinfo->lcdc.h_front_porch = 4;
+ pinfo->lcdc.hsync_skew = 0;
+ pinfo->lcdc.v_pulse_width = 1;
+ pinfo->lcdc.v_back_porch = 7;
+ pinfo->lcdc.v_front_porch = 3;
+
+ pinfo->on = lcdc_truly_hvga_on;
+ pinfo->off = lcdc_truly_hvga_off;
+
+ return;
+}
diff --git a/dev/panel/msm/rules.mk b/dev/panel/msm/rules.mk
index 525bebb..87c67a4 100644
--- a/dev/panel/msm/rules.mk
+++ b/dev/panel/msm/rules.mk
@@ -17,5 +17,6 @@
$(LOCAL_DIR)/mipi_renesas_cmd_fwvga.o \
$(LOCAL_DIR)/mipi_nt35510.o \
$(LOCAL_DIR)/mipi_nt35510_video_wvga.o \
- $(LOCAL_DIR)/mipi_nt35510_cmd_wvga.o
+ $(LOCAL_DIR)/mipi_nt35510_cmd_wvga.o \
+ $(LOCAL_DIR)/lcdc_truly_hvga.o
endif
diff --git a/include/dev/lcdc.h b/include/dev/lcdc.h
index 26e8dbd..d935bcc 100644
--- a/include/dev/lcdc.h
+++ b/include/dev/lcdc.h
@@ -28,8 +28,68 @@
#ifndef __DEV_LCDC_H
#define __DEV_LCDC_H
+#include <platform/iomap.h>
+#include <msm_panel.h>
+
#define DEFAULT_LCD_TIMING 0
+#define MDP_DMA_P_CONFIG REG_MDP(0x90000)
+#define MDP_DMA_P_OUT_XY REG_MDP(0x90010)
+#define MDP_DMA_P_SIZE REG_MDP(0x90004)
+#define MDP_DMA_P_BUF_ADDR REG_MDP(0x90008)
+#define MDP_DMA_P_BUF_Y_STRIDE REG_MDP(0x9000C)
+#define MDP_DMA_P_OP_MODE REG_MDP(0x90070)
+
+#define MDP_LCDC_EN REG_MDP(LCDC_BASE + 0x00)
+#define MDP_LCDC_HSYNC_CTL REG_MDP(LCDC_BASE + 0x04)
+#define MDP_LCDC_VSYNC_PERIOD REG_MDP(LCDC_BASE + 0x08)
+#define MDP_LCDC_VSYNC_PULSE_WIDTH REG_MDP(LCDC_BASE + 0x0C)
+#define MDP_LCDC_DISPLAY_HCTL REG_MDP(LCDC_BASE + 0x10)
+#define MDP_LCDC_DISPLAY_V_START REG_MDP(LCDC_BASE + 0x14)
+#define MDP_LCDC_DISPLAY_V_END REG_MDP(LCDC_BASE + 0x18)
+#define MDP_LCDC_ACTIVE_HCTL REG_MDP(LCDC_BASE + 0x1C)
+#define MDP_LCDC_ACTIVE_V_START REG_MDP(LCDC_BASE + 0x20)
+#define MDP_LCDC_ACTIVE_V_END REG_MDP(LCDC_BASE + 0x24)
+#define MDP_LCDC_BORDER_CLR REG_MDP(LCDC_BASE + 0x28)
+#define MDP_LCDC_UNDERFLOW_CTL REG_MDP(LCDC_BASE + 0x2C)
+#define MDP_LCDC_HSYNC_SKEW REG_MDP(LCDC_BASE + 0x30)
+#define MDP_LCDC_TEST_CTL REG_MDP(LCDC_BASE + 0x34)
+#define MDP_LCDC_CTL_POLARITY REG_MDP(LCDC_BASE + 0x38)
+#define MDP_LCDC_TEST_COL_VAR1 REG_MDP(LCDC_BASE + 0x3C)
+#define MDP_LCDC_UNDERFLOW_HIDING_CTL REG_MDP(LCDC_BASE + 0x44)
+#define MDP_LCDC_LOST_PIXEL_CNT_VALUE REG_MDP(LCDC_BASE + 0x48)
+
+#define DMA_DSTC0G_8BITS (BIT(1)|BIT(0))
+#define DMA_DSTC1B_8BITS (BIT(3)|BIT(2))
+#define DMA_DSTC2R_8BITS (BIT(5)|BIT(4))
+#define DMA_DSTC0G_6BITS (BIT(1))
+#define DMA_DSTC1B_6BITS (BIT(3))
+#define DMA_DSTC2R_6BITS (BIT(5))
+#define DMA_DITHER_EN BIT(24)
+#define DMA_OUT_SEL_LCDC BIT(20)
+#define DMA_IBUF_FORMAT_RGB888 (0 << 25)
+#define DMA_IBUF_FORMAT_RGB565 (1 << 25)
+#define CLR_G 0x0
+#define CLR_B 0x1
+#define CLR_R 0x2
+#define DMA_PACK_ALIGN_LSB 0
+
+#define MDP_GET_PACK_PATTERN(a,x,y,z,bit) \
+ (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
+#define MDP_GET_PACK_PATTERN(a, x, y, z, bit) \
+ (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
+#define DMA_PACK_PATTERN_RGB \
+ (MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 2)<<8)
+#define MDP_RGB_888_FORMAT \
+ (BIT(17) | (1<<14) | (2<<9) | \
+ (0<<8) | (0<<6) | (3<<4) | \
+ (3<<2) | (3<<0))
+#define MDP_RGB_565_FORMAT \
+ (BIT(17) | (1<<14) | (1<<9) | \
+ (0<<8) | (0<<6) | (1<<4) | \
+ (1<<2) | (2<<0))
+
+
/* used for setting custom timing parameters for different panels */
struct lcdc_timing_parameters
{
diff --git a/platform/msm7x27a/include/platform/gpio.h b/platform/msm7x27a/include/platform/gpio.h
new file mode 100644
index 0000000..2733e28
--- /dev/null
+++ b/platform/msm7x27a/include/platform/gpio.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSM7X27A_GPIO_H
+#define __PLATFORM_MSM7X27A_GPIO_H
+
+/* GPIO TLMM: Direction */
+#ifndef GPIO_INPUT
+#define GPIO_INPUT 0
+#endif
+#ifndef GPIO_OUTPUT
+#define GPIO_OUTPUT 1
+#endif
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE 0
+#define GPIO_DISABLE 1
+
+#define GPIO_CFG(gpio, func, dir, pull, drvstr)\
+ ((((gpio) & 0x3ff) << 4) | \
+ ((func) & 0xf) | \
+ (((dir) & 0x1) << 14) | \
+ (((pull) & 0x3) << 15) | \
+ (((drvstr) & 0xf) << 17))
+#endif
diff --git a/platform/msm7x27a/include/platform/iomap.h b/platform/msm7x27a/include/platform/iomap.h
index b545a62..03abcef 100644
--- a/platform/msm7x27a/include/platform/iomap.h
+++ b/platform/msm7x27a/include/platform/iomap.h
@@ -117,4 +117,5 @@
#define MSM_GIC_DIST_BASE (0xC0000000)
#define MSM_GIC_CPU_BASE (0xC0002000)
+#define LCDC_BASE (0x000E0000)
#endif
diff --git a/platform/msm8960/include/platform/iomap.h b/platform/msm8960/include/platform/iomap.h
index 9a23103..2bd50b6 100644
--- a/platform/msm8960/include/platform/iomap.h
+++ b/platform/msm8960/include/platform/iomap.h
@@ -117,4 +117,5 @@
#define CE1_CRYPTO4_BASE (0x18500000)
#define MSM_CRYPTO_BASE CE1_CRYPTO4_BASE
+#define LCDC_BASE (0x000C0000)
#endif
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index 011fc15..a3d77ce 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -94,6 +94,12 @@
if (ret)
goto msm_display_config_out;
break;
+ case LCDC_PANEL:
+ dprintf(INFO, "Config LCDC PANEL.\n");
+ ret = mdp_lcdc_config(pinfo, &(panel->fb));
+ if (ret)
+ goto msm_display_config_out;
+ break;
default:
return ERR_INVALID_ARGS;
};
@@ -143,6 +149,12 @@
if (ret)
goto msm_display_on_out;
break;
+ case LCDC_PANEL:
+ dprintf(INFO, "Turn on LCDC PANEL.\n");
+ ret = mdp_lcdc_on(panel);
+ if (ret)
+ goto msm_display_on_out;
+ break;
default:
return ERR_INVALID_ARGS;
};
@@ -229,6 +241,10 @@
if (ret)
goto msm_display_off_out;
break;
+ case LCDC_PANEL:
+ dprintf(INFO, "Turn off LCDC PANEL.\n");
+ mdp_lcdc_off();
+ break;
default:
return ERR_INVALID_ARGS;
};
diff --git a/platform/msm_shared/include/mdp4.h b/platform/msm_shared/include/mdp4.h
index df7cbb0..e09cbaf 100644
--- a/platform/msm_shared/include/mdp4.h
+++ b/platform/msm_shared/include/mdp4.h
@@ -62,32 +62,6 @@
#define MDP_RGB1_SRC_FORMAT REG_MDP(0x40050)
#define MDP_RGB1_CONSTANT_COLOR REG_MDP(0x41008)
-#define MDP_DMA_P_CONFIG REG_MDP(0x90000)
-#define MDP_DMA_P_OUT_XY REG_MDP(0x90010)
-#define MDP_DMA_P_SIZE REG_MDP(0x90004)
-#define MDP_DMA_P_BUF_ADDR REG_MDP(0x90008)
-#define MDP_DMA_P_BUF_Y_STRIDE REG_MDP(0x9000C)
-#define MDP_DMA_P_OP_MODE REG_MDP(0x90070)
-
-#define MDP_LCDC_EN REG_MDP(0xC0000)
-#define MDP_LCDC_HSYNC_CTL REG_MDP(0xC0004)
-#define MDP_LCDC_VSYNC_PERIOD REG_MDP(0xC0008)
-#define MDP_LCDC_VSYNC_PULSE_WIDTH REG_MDP(0xC000C)
-#define MDP_LCDC_DISPLAY_HCTL REG_MDP(0xC0010)
-#define MDP_LCDC_DISPLAY_V_START REG_MDP(0xC0014)
-#define MDP_LCDC_DISPLAY_V_END REG_MDP(0xC0018)
-#define MDP_LCDC_ACTIVE_HCTL REG_MDP(0xC001C)
-#define MDP_LCDC_ACTIVE_V_START REG_MDP(0xC0020)
-#define MDP_LCDC_ACTIVE_V_END REG_MDP(0xC0024)
-#define MDP_LCDC_BORDER_CLR REG_MDP(0xC0028)
-#define MDP_LCDC_UNDERFLOW_CTL REG_MDP(0xC002C)
-#define MDP_LCDC_HSYNC_SKEW REG_MDP(0xC0030)
-#define MDP_LCDC_TEST_CTL REG_MDP(0xC0034)
-#define MDP_LCDC_CTL_POLARITY REG_MDP(0xC0038)
-#define MDP_LCDC_TEST_COL_VAR1 REG_MDP(0xC003C)
-#define MDP_LCDC_UNDERFLOW_HIDING_CTL REG_MDP(0xC0044)
-#define MDP_LCDC_LOST_PIXEL_CNT_VALUE REG_MDP(0xC0048)
-
#define MDP_DSI_VIDEO_EN REG_MDP(0xE0000)
#define MDP_DSI_VIDEO_HSYNC_CTL REG_MDP(0xE0004)
#define MDP_DSI_VIDEO_VSYNC_PERIOD REG_MDP(0xE0008)
@@ -104,30 +78,6 @@
#define MDP_TEST_MODE_CLK REG_MDP(0xF0000)
#define MDP_INTR_STATUS REG_MDP(0x00054)
-#define DMA_DSTC0G_8BITS (BIT(1)|BIT(0))
-#define DMA_DSTC1B_8BITS (BIT(3)|BIT(2))
-#define DMA_DSTC2R_8BITS (BIT(5)|BIT(4))
-#define CLR_G 0x0
-#define CLR_B 0x1
-#define CLR_R 0x2
-#define MDP_GET_PACK_PATTERN(a, x, y, z, bit) \
- (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
-#define DMA_PACK_ALIGN_LSB 0
-#define DMA_PACK_PATTERN_RGB \
- (MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 2)<<8)
-#define DMA_DITHER_EN BIT(24)
-#define DMA_OUT_SEL_LCDC BIT(20)
-#define DMA_IBUF_FORMAT_RGB888 (0 << 25)
-#define DMA_IBUF_FORMAT_RGB565 (1 << 25)
-#define MDP_RGB_888_FORMAT \
- (BIT(17) | (1<<14) | (2<<9) | \
- (0<<8) | (0<<6) | (3<<4) | \
- (3<<2) | (3<<0))
-#define MDP_RGB_565_FORMAT \
- (BIT(17) | (1<<14) | (1<<9) | \
- (0<<8) | (0<<6) | (1<<4) | \
- (1<<2) | (2<<0))
-
void mdp_setup_dma_p_video_config(unsigned short pack_pattern,
unsigned short img_width,
unsigned short img_height,
diff --git a/platform/msm_shared/lcdc.c b/platform/msm_shared/lcdc.c
index 2b20154..0c87b39 100644
--- a/platform/msm_shared/lcdc.c
+++ b/platform/msm_shared/lcdc.c
@@ -11,7 +11,7 @@
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
+ * the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -21,7 +21,7 @@
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
diff --git a/platform/msm_shared/mdp4.c b/platform/msm_shared/mdp4.c
index b080d49..61b6cd1 100644
--- a/platform/msm_shared/mdp4.c
+++ b/platform/msm_shared/mdp4.c
@@ -252,159 +252,6 @@
writel(0x00000001, MDP_DMA_P_START);
}
-int mdp_lcdc_config(struct msm_panel_info *pinfo,
- struct fbcon_config *fb)
-{
- unsigned mdp_rgb_size;
- unsigned mdp_rgb_size_src;
- int hsync_period, vsync_period;
- int hsync_start_x, hsync_end_x;
- int display_hctl, display_vstart, display_vend;
- unsigned mdp_rgb_format = 0;
-
- int active_x, active_y;
- int active_hstart_x, active_hend_x;
- int active_vstart, active_vend;
-
- struct lcdc_panel_info *lcdc = NULL;
-
- if (pinfo == NULL)
- return;
-
- lcdc = &(pinfo->lcdc);
- if (lcdc == NULL)
- return;
-
- mdp_rgb_size = (pinfo->yres << 16) + pinfo->xres;
- mdp_rgb_size_src = (fb->height << 16) + fb->width;
-
- dprintf(INFO, "Panel is %d x %d\n",
- pinfo->xres + lcdc->xres_pad,
- pinfo->yres + lcdc->yres_pad);
-
- /* write fb addr in MDP_DMA_P_BUF_ADDR */
- writel(fb->base, MDP_DMA_P_BUF_ADDR);
-
- /* write active region size*/
- writel(mdp_rgb_size, MDP_DMA_P_SIZE);
-
- /* set Y-stride value in bytes */
- /* Y-stride is defined as the number of bytes
- in a line.
- */
- writel((pinfo->xres * pinfo->bpp/8), MDP_DMA_P_BUF_Y_STRIDE);
-
- /* Start XY coordinates */
- writel(0, MDP_DMA_P_OUT_XY);
-
- if (fb->bpp == 16) {
- writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB |
- DMA_DITHER_EN | DMA_OUT_SEL_LCDC |
- DMA_IBUF_FORMAT_RGB565 | DMA_DSTC0G_8BITS |
- DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS,
- MDP_DMA_P_CONFIG);
- mdp_rgb_format = MDP_RGB_565_FORMAT;
- } else if (fb->bpp == 24) {
- writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB |
- DMA_DITHER_EN | DMA_OUT_SEL_LCDC |
- DMA_IBUF_FORMAT_RGB888 | DMA_DSTC0G_8BITS |
- DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS,
- MDP_DMA_P_CONFIG);
- mdp_rgb_format = MDP_RGB_888_FORMAT;
- } else {
- dprintf(CRITICAL, "Unsupported bpp detected!\n");
- return ERR_INVALID_ARGS;
- }
-
- hsync_period = lcdc->h_pulse_width +
- lcdc->h_back_porch +
- pinfo->xres + lcdc->h_front_porch;
- vsync_period = (lcdc->v_pulse_width +
- lcdc->v_back_porch +
- pinfo->yres +
- lcdc->v_front_porch) *
- hsync_period;
- hsync_start_x =
- lcdc->h_pulse_width +
- lcdc->h_back_porch;
- hsync_end_x =
- hsync_period - lcdc->h_front_porch - 1;
- display_hctl = (hsync_end_x << 16) | hsync_start_x;
- display_vstart = (lcdc->v_pulse_width +
- lcdc->v_back_porch)
- * hsync_period + lcdc->hsync_skew;
- display_vend = vsync_period -
- (lcdc->v_front_porch * hsync_period)
- +lcdc->hsync_skew - 1;
-
- active_x = (pinfo->xres - fb->width)/2;
- active_y = (pinfo->yres - fb->height)/2;
-
- active_hstart_x = lcdc->h_pulse_width + lcdc->h_back_porch
- + active_x;
- active_hend_x = active_hstart_x + fb->width - 1;
-
- active_vstart = (lcdc->v_pulse_width + lcdc->v_back_porch
- + active_y) * hsync_period
- + lcdc->hsync_skew;
- active_vend = active_vstart + (fb->height * hsync_period) - 1;
-
-
- /* LCDC specific initalizations */
- writel((hsync_period << 16) | lcdc->h_pulse_width,
- MDP_LCDC_HSYNC_CTL);
- writel(vsync_period, MDP_LCDC_VSYNC_PERIOD);
- writel(lcdc->v_pulse_width * hsync_period,
- MDP_LCDC_VSYNC_PULSE_WIDTH);
- writel(display_hctl, MDP_LCDC_DISPLAY_HCTL);
- writel(display_vstart, MDP_LCDC_DISPLAY_V_START);
- writel(display_vend, MDP_LCDC_DISPLAY_V_END);
-
- writel(BIT(31) | (active_hend_x << 16) | active_hstart_x,
- MDP_LCDC_ACTIVE_HCTL);
-
- writel(BIT(31) | active_vstart, MDP_LCDC_ACTIVE_V_START);
- writel(active_vend, MDP_LCDC_ACTIVE_V_END);
-
- writel(0xf, MDP_LCDC_BORDER_CLR);
- writel(0xff, MDP_LCDC_UNDERFLOW_CTL);
- writel(lcdc->hsync_skew,
- MDP_LCDC_HSYNC_SKEW);
- writel(0x3, MDP_LCDC_CTL_POLARITY);
- writel(0, MDP_LCDC_ACTIVE_HCTL);
- writel(0, MDP_LCDC_ACTIVE_V_START);
- writel(0, MDP_LCDC_ACTIVE_V_END);
-
- /* setting for single layer direct out mode for rgb565 source */
- writel(0x100, MDP_LAYERMIXER_IN_CFG);
- writel(mdp_rgb_size_src, MDP_RGB1_SRC_SIZE);
- writel(mdp_rgb_size, MDP_RGB1_OUT_SIZE);
- writel((int)fb->base, MDP_RGB1_SRCP0_ADDR);
- writel((fb->stride * fb->bpp / 8), MDP_RGB1_SRC_YSTRIDE1);
- writel(0x00, MDP_RGB1_CONSTANT_COLOR);
- writel(mdp_rgb_format, MDP_RGB1_SRC_FORMAT);
- writel(0x1, MDP_OVERLAYPROC0_CFG);
- if (fb->bpp == 16)
- writel(0x1, MDP_OVERLAYPROC0_OPMODE);
- else if (fb->bpp == 24)
- writel(0x0, MDP_OVERLAYPROC0_OPMODE);
-
- /* register flush and enable LCDC */
- writel(0x11, MDP_OVERLAY_REG_FLUSH);
- return NO_ERROR;
-}
-
-int mdp_lcdc_on()
-{
- writel(0x1, MDP_LCDC_EN);
- return NO_ERROR;
-}
-
-int mdp_lcdc_off()
-{
- writel(0x0, MDP_LCDC_EN);
- return NO_ERROR;
-}
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
diff --git a/platform/msm_shared/mdp_lcdc.c b/platform/msm_shared/mdp_lcdc.c
new file mode 100644
index 0000000..e33c78d
--- /dev/null
+++ b/platform/msm_shared/mdp_lcdc.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <stdlib.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <dev/fbcon.h>
+#include <target/display.h>
+#include <dev/lcdc.h>
+#include <msm_panel.h>
+#include <err.h>
+#include <mdp4.h>
+#include <bits.h>
+
+int mdp_lcdc_config(struct msm_panel_info *pinfo,
+ struct fbcon_config *fb)
+{
+ unsigned mdp_rgb_size;
+ unsigned mdp_rgb_size_src;
+ int hsync_period, vsync_period;
+ int hsync_start_x, hsync_end_x;
+ int display_hctl, display_vstart, display_vend;
+ unsigned mdp_rgb_format = 0;
+
+ int active_x, active_y;
+ int active_hstart_x, active_hend_x;
+ int active_vstart, active_vend;
+ int mdp_rev;
+
+ struct lcdc_panel_info *lcdc = NULL;
+
+ if (pinfo == NULL)
+ return;
+
+ lcdc = &(pinfo->lcdc);
+ if (lcdc == NULL)
+ return;
+
+ mdp_rev = mdp_get_revision();
+
+ mdp_rgb_size = (pinfo->yres << 16) + pinfo->xres;
+ mdp_rgb_size_src = (fb->height << 16) + fb->width;
+
+ dprintf(INFO, "Panel is %d x %d\n",
+ pinfo->xres + lcdc->xres_pad,
+ pinfo->yres + lcdc->yres_pad);
+
+ /* write fb addr in MDP_DMA_P_BUF_ADDR */
+ writel(fb->base, MDP_DMA_P_BUF_ADDR);
+
+ /* write active region size*/
+ writel(mdp_rgb_size, MDP_DMA_P_SIZE);
+
+ /* set Y-stride value in bytes */
+ /* Y-stride is defined as the number of bytes
+ in a line.
+ */
+ writel((pinfo->xres * pinfo->bpp/8), MDP_DMA_P_BUF_Y_STRIDE);
+
+ /* Start XY coordinates */
+ writel(0, MDP_DMA_P_OUT_XY);
+
+ if (fb->bpp == 16) {
+ writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB |
+ DMA_DITHER_EN | DMA_OUT_SEL_LCDC |
+ DMA_IBUF_FORMAT_RGB565 | DMA_DSTC0G_6BITS |
+ DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS,
+ MDP_DMA_P_CONFIG);
+ mdp_rgb_format = MDP_RGB_565_FORMAT;
+ } else if (fb->bpp == 24) {
+ writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB |
+ DMA_DITHER_EN | DMA_OUT_SEL_LCDC |
+ DMA_IBUF_FORMAT_RGB888 | DMA_DSTC0G_8BITS |
+ DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS,
+ MDP_DMA_P_CONFIG);
+ mdp_rgb_format = MDP_RGB_888_FORMAT;
+ } else {
+ dprintf(CRITICAL, "Unsupported bpp detected!\n");
+ return ERR_INVALID_ARGS;
+ }
+
+ hsync_period = lcdc->h_pulse_width +
+ lcdc->h_back_porch +
+ pinfo->xres + lcdc->h_front_porch;
+ vsync_period = (lcdc->v_pulse_width +
+ lcdc->v_back_porch +
+ pinfo->yres +
+ lcdc->v_front_porch) *
+ hsync_period;
+ hsync_start_x =
+ lcdc->h_pulse_width +
+ lcdc->h_back_porch;
+ hsync_end_x =
+ hsync_period - lcdc->h_front_porch - 1;
+ display_hctl = (hsync_end_x << 16) | hsync_start_x;
+ display_vstart = (lcdc->v_pulse_width +
+ lcdc->v_back_porch)
+ * hsync_period + lcdc->hsync_skew;
+ display_vend = vsync_period -
+ (lcdc->v_front_porch * hsync_period)
+ +lcdc->hsync_skew - 1;
+
+ active_x = (pinfo->xres - fb->width)/2;
+ active_y = (pinfo->yres - fb->height)/2;
+
+ active_hstart_x = lcdc->h_pulse_width + lcdc->h_back_porch
+ + active_x;
+ active_hend_x = active_hstart_x + fb->width - 1;
+
+ active_vstart = (lcdc->v_pulse_width + lcdc->v_back_porch
+ + active_y) * hsync_period
+ + lcdc->hsync_skew;
+ active_vend = active_vstart + (fb->height * hsync_period) - 1;
+
+
+ /* LCDC specific initalizations */
+ writel((hsync_period << 16) | lcdc->h_pulse_width,
+ MDP_LCDC_HSYNC_CTL);
+ writel(vsync_period, MDP_LCDC_VSYNC_PERIOD);
+ writel(lcdc->v_pulse_width * hsync_period,
+ MDP_LCDC_VSYNC_PULSE_WIDTH);
+ writel(display_hctl, MDP_LCDC_DISPLAY_HCTL);
+ writel(display_vstart, MDP_LCDC_DISPLAY_V_START);
+ writel(display_vend, MDP_LCDC_DISPLAY_V_END);
+
+ if (mdp_rev >= MDP_REV_40) {
+ writel(BIT(31) | (active_hend_x << 16) | active_hstart_x,
+ MDP_LCDC_ACTIVE_HCTL);
+
+ writel(BIT(31) | active_vstart, MDP_LCDC_ACTIVE_V_START);
+ writel(active_vend, MDP_LCDC_ACTIVE_V_END);
+
+ writel(0xf, MDP_LCDC_BORDER_CLR);
+ writel(0xff, MDP_LCDC_UNDERFLOW_CTL);
+ writel(lcdc->hsync_skew,
+ MDP_LCDC_HSYNC_SKEW);
+ writel(0x3, MDP_LCDC_CTL_POLARITY);
+ writel(0, MDP_LCDC_ACTIVE_HCTL);
+ writel(0, MDP_LCDC_ACTIVE_V_START);
+ writel(0, MDP_LCDC_ACTIVE_V_END);
+
+ /* setting for single layer direct out mode for rgb565 source */
+ writel(0x100, MDP_LAYERMIXER_IN_CFG);
+ writel(mdp_rgb_size_src, MDP_RGB1_SRC_SIZE);
+ writel(mdp_rgb_size, MDP_RGB1_OUT_SIZE);
+ writel((int)fb->base, MDP_RGB1_SRCP0_ADDR);
+ writel((fb->stride * fb->bpp / 8), MDP_RGB1_SRC_YSTRIDE1);
+ writel(0x00, MDP_RGB1_CONSTANT_COLOR);
+ writel(mdp_rgb_format, MDP_RGB1_SRC_FORMAT);
+ writel(0x1, MDP_OVERLAYPROC0_CFG);
+ if (fb->bpp == 16)
+ writel(0x1, MDP_OVERLAYPROC0_OPMODE);
+ else if (fb->bpp == 24)
+ writel(0x0, MDP_OVERLAYPROC0_OPMODE);
+ /* register flush and enable LCDC */
+ writel(0x11, MDP_OVERLAY_REG_FLUSH);
+ } else if (MDP_REV_303 == mdp_rev) {
+ writel(0x0, MDP_BASE + LCDC_BASE + 0x28);
+ writel(0xff, MDP_BASE + LCDC_BASE + 0x2c);
+ writel(lcdc->hsync_skew, MDP_BASE + LCDC_BASE + 0x30);
+ writel(0x0, MDP_BASE + LCDC_BASE + 0x38);
+ writel(0x0, MDP_BASE + LCDC_BASE + 0x1c);
+ writel(0x0, MDP_BASE + LCDC_BASE + 0x20);
+ writel(0x0, MDP_BASE + LCDC_BASE + 0x24);
+ }
+ return NO_ERROR;
+}
+
+int mdp_lcdc_on()
+{
+ writel(0x1, MDP_LCDC_EN);
+ return NO_ERROR;
+}
+
+int mdp_lcdc_off()
+{
+ writel(0x0, MDP_LCDC_EN);
+ return NO_ERROR;
+}
diff --git a/platform/msm_shared/proc_comm.c b/platform/msm_shared/proc_comm.c
index 24e5d59..a08caf4 100644
--- a/platform/msm_shared/proc_comm.c
+++ b/platform/msm_shared/proc_comm.c
@@ -257,6 +257,12 @@
clock_disable(MDP_P_CLK);
}
+void lcdc_clock_disable(void)
+{
+ clock_disable(MDP_LCDC_PAD_PCLK_CLK);
+ clock_disable(MDP_LCDC_PCLK_CLK);
+}
+
void uart3_clock_init(void)
{
clock_enable(UART3_CLK);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 64545c6..4fe1d01 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -1,7 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += \
- -I$(LOCAL_DIR)/include
+ -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/dev/panel/msm
DEFINES += $(TARGET_XRES)
DEFINES += $(TARGET_YRES)
@@ -54,7 +54,8 @@
$(LOCAL_DIR)/display.o \
$(LOCAL_DIR)/lvds.o \
$(LOCAL_DIR)/mipi_dsi_phy.o \
- $(LOCAL_DIR)/timer.o
+ $(LOCAL_DIR)/timer.o \
+ $(LOCAL_DIR)/mdp_lcdc.o
endif
ifeq ($(PLATFORM),copper)
@@ -84,7 +85,9 @@
$(LOCAL_DIR)/interrupts.o \
$(LOCAL_DIR)/timer.o \
$(LOCAL_DIR)/display.o \
- $(LOCAL_DIR)/mipi_dsi_phy.o
+ $(LOCAL_DIR)/mipi_dsi_phy.o \
+ $(LOCAL_DIR)/mdp_lcdc.o \
+ $(LOCAL_DIR)/spi.o
endif
ifeq ($(PLATFORM),msm7k)
diff --git a/platform/msm_shared/spi.c b/platform/msm_shared/spi.c
new file mode 100644
index 0000000..1051f42
--- /dev/null
+++ b/platform/msm_shared/spi.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <platform/timer.h>
+#include <dev/gpio.h>
+
+void spi_bit_bang_write(uint8_t spi_sclk, uint8_t spi_mosi, uint8_t dc, uint8_t data)
+{
+ uint8_t bit;
+ uint8_t bnum;
+
+ gpio_set(spi_sclk, 0); /* clk low */
+ /* dc: 0 for command, 1 for parameter */
+ gpio_set(spi_mosi, dc);
+ udelay(1); /* at least 20 ns */
+ gpio_set(spi_sclk, 1); /* clk high */
+ udelay(1); /* at least 20 ns */
+ bnum = 8; /* 8 data bits */
+ bit = 0x80;
+ while(bnum){
+ gpio_set(spi_sclk, 0); /* clk low */
+ if (data & bit)
+ gpio_set(spi_mosi, 1);
+ else
+ gpio_set(spi_mosi, 0);
+ udelay(1);
+ gpio_set(spi_sclk, 1); /* clk high */
+ udelay(1);
+ bit >>= 1;
+ bnum--;
+ }
+}
diff --git a/target/msm7627a/include/target/display.h b/target/msm7627a/include/target/display.h
index db35aa4..54f568c 100644
--- a/target/msm7627a/include/target/display.h
+++ b/target/msm7627a/include/target/display.h
@@ -73,6 +73,7 @@
#define NT35510_MIPI_FB_HEIGHT 800
#define MIPI_FB_ADDR 0x20000000
+#define LCDC_FB_ADDR 0x20000000
extern int mipi_dsi_phy_init(struct mipi_dsi_panel_config *);
extern void config_renesas_dsi_video_mode(void);
diff --git a/target/msm7627a/target_display.c b/target/msm7627a/target_display.c
index 92a4a93..96688f6 100644
--- a/target/msm7627a/target_display.c
+++ b/target/msm7627a/target_display.c
@@ -30,6 +30,7 @@
#include <msm_panel.h>
#include <target/display.h>
#include <target/board.h>
+#include <dev/lcdc.h>
static struct msm_fb_panel_data panel;
static uint8_t display_enabled;
@@ -38,6 +39,7 @@
extern int msm_display_off();
extern int mipi_renesas_panel_dsi_config(int);
extern int mipi_nt35510_panel_dsi_config(int);
+extern int lcdc_truly_panel_on(int);
static int msm7627a_mdp_clock_init(int enable)
{
@@ -53,6 +55,20 @@
return ret;
}
+static int msm7627a_lcdc_clock_init(int enable)
+{
+ int ret = 0;
+ unsigned rate = panel.panel_info.clk_rate;
+
+ if (enable) {
+ mdp_clock_init(rate);
+ lcdc_clock_init(rate);
+ } else {
+ mdp_clock_disable();
+ lcdc_clock_disable();
+ }
+ return ret;
+}
void display_init(void)
{
unsigned mach_type;
@@ -116,6 +132,18 @@
if (mach_type == MSM8X25_EVT)
panel.rotate = 1;
break;
+ case MSM8X25_QRD7:
+ lcdc_truly_hvga_init(&(panel.panel_info));
+ panel.clk_func = msm7627a_lcdc_clock_init;
+ panel.power_func = lcdc_truly_panel_on;
+ panel.fb.base = LCDC_FB_ADDR;
+ panel.fb.width = panel.panel_info.xres;
+ panel.fb.height = panel.panel_info.yres;
+ panel.fb.stride = panel.panel_info.xres;
+ panel.fb.bpp = panel.panel_info.bpp;
+ panel.fb.format = FB_FORMAT_RGB565;
+ panel.mdp_rev = MDP_REV_303;
+ break;
default:
return;
};