Merge "platform: msm8996: Update the load address for lk"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index da32a54..2df5af0 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -1723,10 +1723,7 @@
 		if (memcmp(info->magic, DEVICE_MAGIC, DEVICE_MAGIC_SIZE))
 		{
 			memcpy(info->magic, DEVICE_MAGIC, DEVICE_MAGIC_SIZE);
-			if (is_secure_boot_enable())
-				info->is_unlocked = 0;
-			else
-				info->is_unlocked = 1;
+			info->is_unlocked = 0;
 			info->is_verified = 0;
 			info->is_tampered = 0;
 #if USER_BUILD_VARIANT
@@ -2111,18 +2108,21 @@
 void cmd_erase(const char *arg, void *data, unsigned sz)
 {
 #if VERIFIED_BOOT
-	if(!device.is_unlocked && !device.is_verified)
+	if (target_build_variant_user())
 	{
-		fastboot_fail("device is locked. Cannot erase");
-		return;
-	}
-	if(!device.is_unlocked && device.is_verified)
-	{
-		if(!boot_verify_flash_allowed(arg))
+		if(!device.is_unlocked && !device.is_verified)
 		{
-			fastboot_fail("cannot flash this partition in verified state");
+			fastboot_fail("device is locked. Cannot erase");
 			return;
 		}
+		if(!device.is_unlocked && device.is_verified)
+		{
+			if(!boot_verify_flash_allowed(arg))
+			{
+				fastboot_fail("cannot flash this partition in verified state");
+				return;
+			}
+		}
 	}
 #endif
 
@@ -2259,10 +2259,9 @@
 void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz)
 {
 	unsigned int chunk;
-	unsigned int chunk_data_sz;
+	uint64_t chunk_data_sz;
 	uint32_t *fill_buf = NULL;
 	uint32_t fill_val;
-	uint32_t chunk_blk_cnt = 0;
 	sparse_header_t *sparse_header;
 	chunk_header_t *chunk_header;
 	uint32_t total_blocks = 0;
@@ -2350,15 +2349,13 @@
 			return;
 		}
 
-		chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
-
-		/* Make sure multiplication does not overflow uint32 size */
-		if (sparse_header->blk_sz && (chunk_header->chunk_sz != chunk_data_sz / sparse_header->blk_sz))
-		{
-			fastboot_fail("Bogus size sparse and chunk header");
+		if (!sparse_header->blk_sz ){
+			fastboot_fail("Invalid block size\n");
 			return;
 		}
 
+		chunk_data_sz = (uint64_t)sparse_header->blk_sz * chunk_header->chunk_sz;
+
 		/* Make sure that the chunk size calculated from sparse image does not
 		 * exceed partition size
 		 */
@@ -2371,7 +2368,7 @@
 		switch (chunk_header->chunk_type)
 		{
 			case CHUNK_TYPE_RAW:
-			if(chunk_header->total_sz != (sparse_header->chunk_hdr_sz +
+			if((uint64_t)chunk_header->total_sz != ((uint64_t)sparse_header->chunk_hdr_sz +
 											chunk_data_sz))
 			{
 				fastboot_fail("Bogus chunk size for chunk type Raw");
@@ -2383,8 +2380,11 @@
 				return;
 			}
 
+			/* chunk_header->total_sz is uint32,So chunk_data_sz is now less than 2^32
+			   otherwise it will return in the line above
+			 */
 			if(mmc_write(ptn + ((uint64_t)total_blocks*sparse_header->blk_sz),
-						chunk_data_sz,
+						(uint32_t)chunk_data_sz,
 						(unsigned int*)data))
 			{
 				fastboot_fail("flash write failure");
@@ -2395,7 +2395,7 @@
 				return;
 			}
 			total_blocks += chunk_header->chunk_sz;
-			data += chunk_data_sz;
+			data += (uint32_t)chunk_data_sz;
 			break;
 
 			case CHUNK_TYPE_FILL:
@@ -2419,14 +2419,13 @@
 			}
 			fill_val = *(uint32_t *)data;
 			data = (char *) data + sizeof(uint32_t);
-			chunk_blk_cnt = chunk_data_sz / sparse_header->blk_sz;
 
 			for (i = 0; i < (sparse_header->blk_sz / sizeof(fill_val)); i++)
 			{
 				fill_buf[i] = fill_val;
 			}
 
-			for (i = 0; i < chunk_blk_cnt; i++)
+			for (i = 0; i < chunk_header->chunk_sz; i++)
 			{
 				/* Make sure that the data written to partition does not exceed partition size */
 				if ((uint64_t)total_blocks * (uint64_t)sparse_header->blk_sz + sparse_header->blk_sz > size)
@@ -2461,7 +2460,7 @@
 			case CHUNK_TYPE_CRC:
 			if(chunk_header->total_sz != sparse_header->chunk_hdr_sz)
 			{
-				fastboot_fail("Bogus chunk size for chunk type Dont Care");
+				fastboot_fail("Bogus chunk size for chunk type CRC");
 				return;
 			}
 			if(total_blocks > (UINT_MAX - chunk_header->chunk_sz)) {
@@ -2473,7 +2472,7 @@
 				fastboot_fail("integer overflow occured");
 				return;
 			}
-			data += chunk_data_sz;
+			data += (uint32_t)chunk_data_sz;
 			if (data_end < (uint32_t)data) {
 				fastboot_fail("buffer overreads occured due to invalid sparse header");
 				return;
@@ -2573,18 +2572,21 @@
 #endif /* SSD_ENABLE */
 
 #if VERIFIED_BOOT
-	if(!device.is_unlocked)
+	if (target_build_variant_user())
 	{
-		fastboot_fail("device is locked. Cannot flash images");
-		return;
-	}
-	if(!device.is_unlocked && device.is_verified)
-	{
-		if(!boot_verify_flash_allowed(arg))
+		if(!device.is_unlocked)
 		{
-			fastboot_fail("cannot flash this partition in verified state");
+			fastboot_fail("device is locked. Cannot flash images");
 			return;
 		}
+		if(!device.is_unlocked && device.is_verified)
+		{
+			if(!boot_verify_flash_allowed(arg))
+			{
+				fastboot_fail("cannot flash this partition in verified state");
+				return;
+			}
+		}
 	}
 #endif
 
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_cmd.h b/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_cmd.h
new file mode 100644
index 0000000..b2bf27f
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_cmd.h
@@ -0,0 +1,273 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_NT35597_WQXGA_DUALDSI_CMD_H_
+#define _PANEL_NT35597_WQXGA_DUALDSI_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+static struct panel_config nt35597_wqxga_dualdsi_cmd_panel_data = {
+	"qcom,mdss_dsi_nt35597_wqxga_cmd", "dsi:0:", "qcom,mdss-dsi-panel",
+	10, 1, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 11, 0, 0,
+	"qcom,mdss_dsi_nt35597_wqxga_cmd"
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35597_wqxga_dualdsi_cmd_panel_res = {
+	1440, 2560, 100, 32, 16, 0, 8, 7, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35597_wqxga_dualdsi_cmd_color = {
+	24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information                                          */
+/*---------------------------------------------------------------------------*/
+static char nt35597_wqxga_dualdsi_cmd_on_cmd0[] = {
+	0xff, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd1[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd2[] = {
+	0xba, 0x03, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd3[] = {
+	0xe5, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd4[] = {
+	0x35, 0x00, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd5[] = {
+	0xbb, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd6[] = {
+	0xb0, 0x03, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd7[] = {
+	0xff, 0xe0, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd8[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd9[] = {
+	0x6b, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd10[] = {
+	0x6c, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd11[] = {
+	0x6d, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd12[] = {
+	0x6e, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd13[] = {
+	0x6f, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd14[] = {
+	0x35, 0x02, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd15[] = {
+	0x36, 0x72, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd16[] = {
+	0x37, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd17[] = {
+	0x8, 0xc0, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd18[] = {
+	0xff, 0x24, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd19[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd20[] = {
+	0xc6, 0x06, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd21[] = {
+	0xff, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd22[] = {
+	0x11, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmd_on_cmd23[] = {
+	0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_dualdsi_cmd_on_command[] = {
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd0, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd1, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd2, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd3, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd4, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd5, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd6, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd7, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd8, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd9, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd10, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd11, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd12, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd13, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd14, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd15, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd16, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd17, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd18, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd19, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd20, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd21, 0x10},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd22, 0x78},
+	{0x4, nt35597_wqxga_dualdsi_cmd_on_cmd23, 0x78},
+};
+
+#define NT35597_WQXGA_DUALDSI_CMD_ON_COMMAND 24
+
+
+static char nt35597_wqxga_dualdsi_cmdoff_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_dualdsi_cmdoff_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_dualdsi_cmd_off_command[] = {
+	{0x4, nt35597_wqxga_dualdsi_cmdoff_cmd0, 0x32},
+	{0x4, nt35597_wqxga_dualdsi_cmdoff_cmd1, 0x78}
+};
+
+#define NT35597_WQXGA_DUALDSI_CMD_OFF_COMMAND 2
+
+static struct command_state nt35597_wqxga_dualdsi_cmd_state = {
+	0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info nt35597_wqxga_dualdsi_cmd_command_panel = {
+	1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info nt35597_wqxga_dualdsi_cmd_video_panel = {
+	0, 0, 0, 0, 1, 1, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration                                                        */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration nt35597_wqxga_dualdsi_cmd_lane_config = {
+	4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing                                                              */
+/*---------------------------------------------------------------------------*/
+static const uint32_t nt35597_wqxga_dualdsi_cmd_timings[] = {
+	0xe2, 0x36, 0x24, 0x00, 0x66, 0x6a, 0x28, 0x38,  0x2a, 0x03, 0x04, 0x00
+};
+
+static const uint32_t nt35597_wqxga_dualdsi_thulium_cmd_timings[] = {
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x18, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+};
+
+static struct panel_timing nt35597_wqxga_dualdsi_cmd_timing_info = {
+	0x0, 0x04, 0x0d, 0x2d
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence                                                      */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence nt35597_wqxga_dualdsi_cmd_reset_seq = {
+	{1, 0, 1, }, {20, 20, 50, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting                                                         */
+/*---------------------------------------------------------------------------*/
+static struct backlight nt35597_wqxga_dualdsi_cmd_backlight = {
+	1, 1, 4095, 100, 1, "PMIC_8941"		/* BL_WLED */
+};
+
+static struct labibb_desc nt35597_wqxga_dualdsi_cmd_labibb = {
+	0, 1, 5500000, 5500000, 5500000, 5500000, 3, 3, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Dynamic fps supported frequencies by panel                                */
+/*---------------------------------------------------------------------------*/
+static const struct dfps_panel_info nt35597_wqxga_dualdsi_cmd_dfps = {
+	1, 8, {53, 54, 55, 56, 57, 58, 59, 60}
+};
+
+#endif
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_video.h b/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_video.h
index 4d5a1ff..b5f7cd8 100644
--- a/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_video.h
@@ -39,7 +39,7 @@
 /*---------------------------------------------------------------------------*/
 static struct panel_config nt35597_wqxga_dualdsi_video_panel_data = {
 	"qcom,mdss_dsi_nt35597_wqxga_video", "dsi:0:", "qcom,mdss-dsi-panel",
-	10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 25, 1, 0,
+	10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 11, 0, 0,
 	"qcom,mdss_dsi_nt35597_wqxga_video"
 };
 
@@ -226,15 +226,15 @@
 };
 
 static const uint32_t nt35597_wqxga_dualdsi_thulium_video_timings[] = {
-	0x23, 0x1f, 0x6, 0x8, 0x4, 0x3, 0x4, 0xa,
-	0x23, 0x1f, 0x6, 0x8, 0x4, 0x3, 0x4, 0xa,
-	0x23, 0x1f, 0x6, 0x8, 0x4, 0x3, 0x4, 0xa,
-	0x23, 0x1f, 0x6, 0x8, 0x4, 0x3, 0x4, 0xa,
-	0x23, 0x2d, 0x6, 0x8, 0x4, 0x3, 0x4, 0xa,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x18, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
 };
 
 static struct panel_timing nt35597_wqxga_dualdsi_video_timing_info = {
-	0x0, 0x04, 0x02, 0x2a
+	0x0, 0x04, 0x0d, 0x2d
 };
 
 /*---------------------------------------------------------------------------*/
diff --git a/dev/pmic/pm8x41/pm8x41_vib.c b/dev/pmic/pm8x41/pm8x41_vib.c
index 7dbba77..3246b9f 100644
--- a/dev/pmic/pm8x41/pm8x41_vib.c
+++ b/dev/pmic/pm8x41/pm8x41_vib.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -27,9 +27,7 @@
  */
 
 #include <bits.h>
-#include <debug.h>
-#include <reg.h>
-#include <pm8x41.h>
+#include <pm8x41_hw.h>
 #include <pm_vib.h>
 
 #define QPNP_VIB_EN    BIT(7)
diff --git a/dev/vib/vibrator.c b/dev/vib/vibrator.c
index e8cb8c7..b3e79c0 100644
--- a/dev/vib/vibrator.c
+++ b/dev/vib/vibrator.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -26,13 +26,11 @@
  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <debug.h>
-#include <reg.h>
 #include <stdlib.h>
 #include <kernel/timer.h>
-#include <platform/timer.h>
-#include <vibrator.h>
+#include <kernel/thread.h>
 #include <pm_vib.h>
+#include <vibrator.h>
 
 #define CHECK_VIB_TIMER_FREQUENCY    50
 
@@ -52,7 +50,7 @@
 }
 
 /* Function to turn off vibrator when the vib_timer is expired. */
-static enum handler_return vib_timer_func(struct timer *v_timer, void *arg)
+static enum handler_return vib_timer_func(struct timer *v_timer, time_t t, void *arg)
 {
 	timer_cancel(&vib_timer);
 	vib_turn_off();
diff --git a/platform/msm8952/include/platform/iomap.h b/platform/msm8952/include/platform/iomap.h
index 68b8227..ae61934 100644
--- a/platform/msm8952/include/platform/iomap.h
+++ b/platform/msm8952/include/platform/iomap.h
@@ -285,6 +285,26 @@
 #endif
 #define MDP_INTF_1_BASE                         REG_MDP(0x12700)
 
+#ifdef MDP_INTF_2_BASE
+#undef MDP_INTF_2_BASE
+#endif
+#define MDP_INTF_2_BASE                         REG_MDP(0x12F00)
+
+#ifdef MDP_REG_SPLIT_DISPLAY_EN
+#undef MDP_REG_SPLIT_DISPLAY_EN
+#endif
+#define MDP_REG_SPLIT_DISPLAY_EN                REG_MDP(0x12F4)
+
+#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
+#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
+#endif
+#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL    REG_MDP(0x12F8)
+
+#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
+#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
+#endif
+#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL    REG_MDP(0x13F0)
+
 #ifdef MMSS_MDP_SMP_ALLOC_W_BASE
 #undef MMSS_MDP_SMP_ALLOC_W_BASE
 #endif
diff --git a/platform/msm_shared/bam.c b/platform/msm_shared/bam.c
index f123b87..723ce00 100644
--- a/platform/msm_shared/bam.c
+++ b/platform/msm_shared/bam.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012,2015 The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -39,18 +39,6 @@
 
 #define HLOS_EE_INDEX          0
 
-/* Reset BAM registers and pipes */
-static void bam_reset(struct bam_instance *bam)
-{
-	/* Initiate SW reset */
-	writel(BAM_SW_RST_BIT_MASK, BAM_CTRL_REG(bam->base));
-
-	/* No delay required */
-
-	/* Disable SW reset */
-	writel(~BAM_SW_RST_BIT_MASK, BAM_CTRL_REG(bam->base));
-}
-
 /* Resets pipe registers and state machines */
 void bam_pipe_reset(struct bam_instance *bam,
 					uint8_t pipe_num)
@@ -151,10 +139,6 @@
 /* Reset and initialize the bam module */
 void bam_init(struct bam_instance *bam)
 {
-	uint32_t val = 0;
-
-//	bam_reset(bam);
-
 	/* Check for only one pipe's direction.
 	 * The other is assumed to be the opposite system
 	 * transaction.
@@ -165,13 +149,6 @@
 		/* Program the threshold count */
 		writel(bam->threshold, BAM_DESC_CNT_TRSHLD_REG(bam->base));
 	}
-
-	/* Program config register for H/W bug fixes */
-	val = 0xffffffff & ~(1 << 11);
-	writel(val, BAM_CNFG_BITS(bam->base));
-
-	/* Enable the BAM */
-	writel(BAM_ENABLE_BIT_MASK, BAM_CTRL_REG(bam->base));
 }
 
 /* Funtion to setup a simple fifo structure.
diff --git a/platform/msm_shared/include/bam.h b/platform/msm_shared/include/bam.h
index 6e4e7f4..bfeb34b 100644
--- a/platform/msm_shared/include/bam.h
+++ b/platform/msm_shared/include/bam.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012,2015 The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -71,10 +71,6 @@
 #define BAM_DATA_READ                   0
 #define BAM_DATA_WRITE                  1
 
-#define BAM_CTRL_REG(x)                 (0x0000 + (x))
-#define BAM_SW_RST_BIT_MASK             1
-#define BAM_ENABLE_BIT_MASK             (1 << 1)
-
 #define BAM_DESC_CNT_TRSHLD_REG(x)      (0x0008 + (x))
 #define COUNT_TRESHOLD_MASK             0xFF
 #define BAM_IRQ_MASK                    (1 << 31)
@@ -94,8 +90,6 @@
 #define BAM_RESET_BLK_MASK              (1 << 7)
 #define BAM_LOCK_EE_CTRL_MASK           (1 << 13)
 
-#define BAM_CNFG_BITS(x)                (0x0000007C + (x))
-
 #define P_SYS_MODE_MASK                 (1 << 5)
 /* 1: Producer mode 0: Consumer mode */
 #define P_DIRECTION_SHIFT               3
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index e48fe85..43e2c0e 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -91,6 +91,7 @@
 #define MDSS_MDP_HW_REV_108    MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
 #define MDSS_MDP_HW_REV_109    MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */
 #define MDSS_MDP_HW_REV_110    MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */
+#define MDSS_MDP_HW_REV_111    MDSS_MDP_REV(1, 11, 0) /* 8956 v1.0 */
 #define MDSS_MDP_HW_REV_112    MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */
 #define MDSS_MDP_HW_REV_200    MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
 
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 81c4612..845c495 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -71,7 +71,8 @@
 #define TIMING_DB_MODE		     0x1E8
 
 #define DSI_HW_REV_103			0x10030000	/* 8994 */
-#define DSI_HW_REV_103_1		0x10030001	/* 8936/8939 */
+#define DSI_HW_REV_103_1		0x10030001	/* 8936/8939/8952 */
+#define DSI_HW_REV_104_2		0x10040002	/* 8956 */
 #define DSI_HW_REV_104			0x10040000	/* thulium */
 
 #define DTYPE_GEN_WRITE2 0x23	/* 4th Byte is 0x80 */
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index d67b5c8..ef083ea 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -75,6 +75,7 @@
 
 	if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
 		(mdss_mdp_rev == MDSS_MDP_HW_REV_108) ||
+		(mdss_mdp_rev == MDSS_MDP_HW_REV_111) ||
 		(mdss_mdp_rev == MDSS_MDP_HW_REV_112))
 		mdss_mdp_intf_off = 0x59100;
 	else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102)
@@ -91,7 +92,8 @@
 	uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
 
 	/* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */
-	if (mdss_mdp_rev == MDSS_MDP_HW_REV_108)
+	if ((mdss_mdp_rev == MDSS_MDP_HW_REV_108) ||
+		(mdss_mdp_rev == MDSS_MDP_HW_REV_111))
 		mdss_mdp_ppb_off = 0x1420;
 	else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
 		mdss_mdp_ppb_off = 0x1334;
@@ -105,7 +107,8 @@
 {
 	uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
 
-	if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
+	if ((mdss_mdp_rev == MDSS_MDP_HW_REV_110) ||
+		(mdss_mdp_rev == MDSS_MDP_HW_REV_111))
 		return 0xB0020;
 	else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107))
 		return 0xB0000;
@@ -189,6 +192,7 @@
 	/* For targets from MDP v1.5, MDP INTF registers are double buffered */
 	if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
 		(mdss_mdp_rev == MDSS_MDP_HW_REV_108) ||
+		(mdss_mdp_rev == MDSS_MDP_HW_REV_111) ||
 		(mdss_mdp_rev == MDSS_MDP_HW_REV_112)) {
 		if (pinfo->dest == DISPLAY_2) {
 			*ctl0_reg_val |= BIT(31);
@@ -351,11 +355,12 @@
 	if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) ||
 		MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) ||
 		MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108) ||
+		MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_111) ||
 		MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_112)) {
 		switch (pinfo->pipe_type) {
 			case MDSS_MDP_PIPE_TYPE_RGB:
 				*left_sspp_client_id = 0x7; /* 7 */
-				*right_sspp_client_id = 0x11; /* 17 */
+				*right_sspp_client_id = 0x8; /* 8 */
 				break;
 			case MDSS_MDP_PIPE_TYPE_DMA:
 				*left_sspp_client_id = 0x4; /* 4 */
@@ -364,7 +369,7 @@
 			case MDSS_MDP_PIPE_TYPE_VIG:
 			default:
 				*left_sspp_client_id = 0x1; /* 1 */
-				*right_sspp_client_id = 0x4; /* 4 */
+				*right_sspp_client_id = 0x9; /* 9 */
 				break;
 		}
 	} else {
@@ -419,8 +424,9 @@
 		(mdss_mdp_rev == MDSS_MDP_HW_REV_112)) {
 		/* 8Kb per SMP on 8916/8952 */
 		smp_size = 8192;
-	} else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) {
-		/* 10Kb per SMP on 8939 */
+	} else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_108) ||
+		(mdss_mdp_rev == MDSS_MDP_HW_REV_111)) {
+		/* 10Kb per SMP on 8939/8956 */
 		smp_size = 10240;
 	} else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) &&
 		(mdss_mdp_rev < MDSS_MDP_HW_REV_200)) {
@@ -792,6 +798,8 @@
 		 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
 			MDSS_MDP_HW_REV_108) ||
 		 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+			MDSS_MDP_HW_REV_111) ||
+		 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
 			MDSS_MDP_HW_REV_112))
 		map = 0xE4;
 	else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
@@ -825,6 +833,7 @@
 
 	if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) ||
 		 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108) ||
+		 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_111) ||
 		 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_112)) {
 		vbif_qos[0] = 2;
 		vbif_qos[1] = 2;
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 9a26a9d..b7faf5d 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -32,6 +32,7 @@
 #include <mdp5.h>
 #include <platform/timer.h>
 #include <platform/iomap.h>
+#include <target/display.h>
 #include <arch/defines.h>
 
 #if (DISPLAY_TYPE_MDSS == 0)
@@ -253,56 +254,54 @@
 	}
 }
 
-static void mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd,
-	uint32_t phy_base)
+static void mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, uint32_t ctl_base,
+	uint32_t phy_base, uint32_t reg_base)
 {
 	/* DSI0 and DSI1 have a common regulator */
-	uint32_t off = 0x0280;	/* phy regulator ctrl settings */
 
 	if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) {
 		/* Regulator ctrl 0 */
-		writel(0x00, DSI0_PHY_BASE + off + (4 * 0));
+		writel(0x00, reg_base + (4 * 0));
 		/* Regulator ctrl - CAL_PWD_CFG */
-		writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6));
+		writel(pd->regulator[6], reg_base + (4 * 6));
 		/* Add h/w recommended delay */
 		udelay(1000);
 		/* Regulator ctrl - TEST */
-		writel(pd->regulator[5], DSI0_PHY_BASE + off + (4 * 5));
+		writel(pd->regulator[5], reg_base + (4 * 5));
 		/* Regulator ctrl 3 */
-		writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3));
+		writel(pd->regulator[3], reg_base + (4 * 3));
 		/* Regulator ctrl 2 */
-		writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2));
+		writel(pd->regulator[2], reg_base + (4 * 2));
 		/* Regulator ctrl 1 */
-		writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1));
+		writel(pd->regulator[1], reg_base + (4 * 1));
 		/* Regulator ctrl 4 */
-		writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4));
+		writel(pd->regulator[4], reg_base + (4 * 4));
 		/* LDO ctrl */
-		if (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1) /* 8916/8939 */
+		if ((readl(ctl_base) == DSI_HW_REV_103_1) ||
+			(readl(ctl_base) == DSI_HW_REV_104_2)) /* 8916/8939/8952/8956 */
 			writel(0x05, phy_base + 0x01dc);
-		else if (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103) /* 8994 */
-			writel(0x1d, phy_base + 0x01dc);
 		else
 			writel(0x0d, phy_base + 0x01dc);
 		dmb();
 	} else {
 		/* Regulator ctrl 0 */
-		writel(0x00, DSI0_PHY_BASE + off + (4 * 0));
+		writel(0x00, reg_base + (4 * 0));
 		/* Regulator ctrl - CAL_PWD_CFG */
-		writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6));
+		writel(pd->regulator[6], reg_base + (4 * 6));
 		/* Add h/w recommended delay */
 		udelay(1000);
 		/* Regulator ctrl 1 */
-		writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1));
+		writel(pd->regulator[1], reg_base + (4 * 1));
 		/* Regulator ctrl 2 */
-		writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2));
+		writel(pd->regulator[2], reg_base + (4 * 2));
 		/* Regulator ctrl 3 */
-		writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3));
+		writel(pd->regulator[3], reg_base + (4 * 3));
 		/* Regulator ctrl 4 */
-		writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4));
+		writel(pd->regulator[4], reg_base + (4 * 4));
 		/* LDO ctrl */
 		writel(0x00, phy_base + 0x01dc);
 		/* Regulator ctrl 0 */
-		writel(pd->regulator[0], DSI0_PHY_BASE + off + (4 * 0));
+		writel(pd->regulator[0], reg_base + (4 * 0));
 		dmb();
 	}
 }
@@ -360,20 +359,22 @@
 }
 
 static int mdss_dsi_phy_28nm_init(struct mipi_panel_info *mipi,
-				uint32_t ctl_base, uint32_t phy_base)
+				uint32_t ctl_base, uint32_t phy_base, uint32_t reg_base)
 {
 	struct mdss_dsi_phy_ctrl *pd;
-	uint32_t i, off = 0, ln, offset;
+	uint32_t i, off = 0, ln, offset, dsi0_phy_base;
 
 	if (mdp_get_revision() == MDP_REV_304)
 		return mdss_dsi_v2_phy_init(mipi, ctl_base);
 
 	pd = (mipi->mdss_dsi_phy_db);
 
+	/* PHY_CTRL_0 */
+	 writel(0x5b, phy_base + 0x0170);
 	/* Strength ctrl 0 */
 	writel(pd->strength[0], phy_base + 0x0184);
 
-	mdss_dsi_phy_regulator_init(pd, phy_base);
+	mdss_dsi_phy_regulator_init(pd, ctl_base, phy_base, reg_base);
 
 	off = 0x0140;	/* phy timing ctrl 0 - 11 */
 	for (i = 0; i < 12; i++) {
@@ -382,12 +383,6 @@
 		off += 4;
 	}
 
-	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
-	writel(0x00, phy_base + 0x0174);
-	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
-	writel(0x5f, phy_base + 0x0170);
-
-	dmb();
 	/* 4 lanes + clk lane configuration */
 	/* lane config n * (0 - 4) & DataPath setup */
 	for (ln = 0; ln < 5; ln++) {
@@ -400,16 +395,20 @@
 		}
 	}
 
-	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
-	writel(0x5f, phy_base + 0x0170);
+	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_4 */
+	writel(0x0a, phy_base + 0x0180);
+	dmb();
 
+	dsi0_phy_base = DSI0_PHY_BASE + target_display_get_base_offset(DSI0_PHY_BASE);
 	/* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */
-	if (phy_base == DSI0_PHY_BASE ||
+	if ((phy_base == dsi0_phy_base) ||
 		(readl(mipi->ctl_base) == DSI_HW_REV_103_1))
 		writel(0x01, phy_base + 0x01d4);
 	else
 		writel(0x00, phy_base + 0x01d4);
 
+	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
+	writel(0x5f, phy_base + 0x0170);
 	dmb();
 
 	off = 0x01b4;	/* phy BIST ctrl 0 - 5 */
@@ -494,11 +493,11 @@
 		break;
 	case DSI_PLL_TYPE_28NM:
 	default:
-		ret = mdss_dsi_phy_28nm_init(mipi,
-				mipi->ctl_base, mipi->phy_base);
+		ret = mdss_dsi_phy_28nm_init(mipi, mipi->ctl_base,
+					mipi->phy_base, mipi->reg_base);
 		if (mipi->dual_dsi)
 			ret = mdss_dsi_phy_28nm_init(mipi, mipi->sctl_base,
-					mipi->sphy_base);
+					mipi->sphy_base, mipi->reg_base);
 		break;
 	}
 
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index caaec78..72126bf 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -451,10 +451,11 @@
 		{
 			err_status = REG_READ16(host, SDHCI_ERR_INT_STS_REG);
 			if ((err_status & SDHCI_CMD_CRC_MASK) || (err_status & SDHCI_CMD_END_BIT_MASK)
-				|| err_status & SDHCI_CMD_TIMEOUT_MASK)
+				|| (err_status & SDHCI_CMD_TIMEOUT_MASK)
+				|| (err_status & SDHCI_CMD_IDX_MASK))
 			{
 				sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
-				return 0;
+				return 1;
 			}
 		}
 
@@ -523,7 +524,7 @@
 				if ((err_status & SDHCI_DAT_TIMEOUT_MASK) || (err_status & SDHCI_DAT_CRC_MASK))
 				{
 					sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
-					return 0;
+					return 1;
 				}
 			}
 
@@ -878,10 +879,6 @@
 	/* Write the command register */
 	REG_WRITE16(host, SDHCI_PREP_CMD(cmd->cmd_index, flags), SDHCI_CMD_REG);
 
-#if USE_TARGET_HS200_DELAY
-	udelay(1000);
-#endif
-
 	/* Command complete sequence */
 	if (sdhci_cmd_complete(host, cmd))
 	{
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index 47bdfd1..f4c5c8c 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -714,6 +714,7 @@
 	bool drv_type_changed = false;
 	int ret = 0;
 	uint32_t i;
+	uint32_t err = 0;
 	struct sdhci_msm_data *msm_host;
 
 	msm_host = host->msm_host;
@@ -756,6 +757,9 @@
 	tuned_phase_cnt = 0;
 	phase = 0;
 	struct mmc_command cmd = {0};
+	struct mmc_command sts_cmd = {0};
+	uint32_t sts_retry;
+	uint32_t sts_err;
 
 	while (phase < MAX_PHASES)
 	{
@@ -777,7 +781,30 @@
 		cmd.data.num_blocks = 0x1;
 
 		/* send command */
-		if (!sdhci_send_command(host, &cmd) && !memcmp(tuning_data, tuning_block, size))
+		err = sdhci_send_command(host, &cmd);
+		if(err)
+		{
+
+			sts_retry = 100;
+			sts_cmd.cmd_index = CMD13_SEND_STATUS;
+			sts_cmd.argument = card->rca << 16;
+			sts_cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+			sts_cmd.resp_type = SDHCI_CMD_RESP_R1;
+			while(sts_retry)
+			{
+				sts_err = sdhci_send_command(host, &sts_cmd);
+				DBG(" response is %d err is %d phase is %d\n",sts_cmd.resp[0],sts_err, phase);
+				if( sts_err || (MMC_CARD_STATUS(sts_cmd.resp[0]) != MMC_TRAN_STATE) )
+				{
+					udelay(10);
+					sts_retry--;
+					continue;
+				}
+				break;
+			}
+		}
+
+		if (!err && !memcmp(tuning_data, tuning_block, size))
 				tuned_phases[tuned_phase_cnt++] = phase;
 
 		phase++;
diff --git a/target/msm8916/include/target/display.h b/target/msm8916/include/target/display.h
index e27432f..6f2bb2e 100644
--- a/target/msm8916/include/target/display.h
+++ b/target/msm8916/include/target/display.h
@@ -126,11 +126,11 @@
 };
 
 static const char panel_lane_config[] = {
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
-  0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
+  0x01, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+  0x01, 0xc0, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
+  0x01, 0xc0, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
+  0x01, 0xc0, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff
 };
 
 static const uint32_t panel_physical_ctrl[] = {
diff --git a/target/msm8952/include/target/display.h b/target/msm8952/include/target/display.h
index 42b3527..5c02765 100644
--- a/target/msm8952/include/target/display.h
+++ b/target/msm8952/include/target/display.h
@@ -48,20 +48,28 @@
 
 extern uint32_t panel_regulator_settings[7];
 
-static const uint32_t dcdc_regulator_settings[] = {
+static const uint32_t dcdc_regulator_settings_lpm[] = {
   0x03, 0x08, 0x07, 0x00, 0x20, 0x07, 0x01
 };
 
-static const uint32_t ldo_regulator_settings[] = {
+static const uint32_t ldo_regulator_settings_lpm[] = {
+  0x00, 0x01, 0x01, 0x00, 0x20, 0x07, 0x00
+};
+
+static const uint32_t dcdc_regulator_settings_hpm[] = {
+  0x03, 0x09, 0x03, 0x00, 0x20, 0x07, 0x01
+};
+
+static const uint32_t ldo_regulator_settings_hpm[] = {
   0x00, 0x01, 0x01, 0x00, 0x20, 0x07, 0x00
 };
 
 static const char panel_lane_config[] = {
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
-  0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
+  0x01, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+  0x01, 0xc0, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
+  0x01, 0xc0, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
+  0x01, 0xc0, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+  0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff
 };
 
 static const uint32_t panel_physical_ctrl[] = {
diff --git a/target/msm8952/oem_panel.c b/target/msm8952/oem_panel.c
index f69848a..50d693f 100644
--- a/target/msm8952/oem_panel.c
+++ b/target/msm8952/oem_panel.c
@@ -317,8 +317,12 @@
 	 * Update all data structures after 'panel_init' label. Only panel
 	 * selection is supposed to happen before that.
 	 */
-	memcpy(panel_regulator_settings,
-			dcdc_regulator_settings, REGULATOR_SIZE);
+	if (platform_is_msm8956())
+		memcpy(panel_regulator_settings,
+			dcdc_regulator_settings_hpm, REGULATOR_SIZE);
+	else
+		memcpy(panel_regulator_settings,
+			dcdc_regulator_settings_lpm, REGULATOR_SIZE);
 	pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB;
 	return init_panel_data(panelstruct, pinfo, phy_db);
 }
diff --git a/target/msm8996/oem_panel.c b/target/msm8996/oem_panel.c
index 7cc95ea..785ad9d 100644
--- a/target/msm8996/oem_panel.c
+++ b/target/msm8996/oem_panel.c
@@ -46,6 +46,7 @@
 /* GCDB Panel Database                                                       */
 /*---------------------------------------------------------------------------*/
 #include "include/panel_nt35597_wqxga_dualdsi_video.h"
+#include "include/panel_nt35597_wqxga_dualdsi_cmd.h"
 #include "include/panel_sharp_wqxga_dualdsi_video.h"
 #include "include/panel_jdi_qhd_dualdsi_video.h"
 #include "include/panel_jdi_qhd_dualdsi_cmd.h"
@@ -55,6 +56,7 @@
 /*---------------------------------------------------------------------------*/
 enum {
 	NT35597_WQXGA_DUALDSI_VIDEO_PANEL,
+	NT35597_WQXGA_DUALDSI_CMD_PANEL,
 	SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
 	JDI_QHD_DUALDSI_VIDEO_PANEL,
 	JDI_QHD_DUALDSI_CMD_PANEL,
@@ -67,6 +69,7 @@
  */
 static struct panel_list supp_panels[] = {
 	{"nt35597_wqxga_dualdsi_video", NT35597_WQXGA_DUALDSI_VIDEO_PANEL},
+	{"nt35597_wqxga_dualdsi_cmd", NT35597_WQXGA_DUALDSI_CMD_PANEL},
 	{"sharp_wqxga_dualdsi_video", SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
 	{"jdi_qhd_dualdsi_video", JDI_QHD_DUALDSI_VIDEO_PANEL},
 	{"jdi_qhd_dualdsi_cmd", JDI_QHD_DUALDSI_CMD_PANEL},
@@ -139,9 +142,6 @@
 		pan_type = PANEL_TYPE_DSI;
 		pinfo->lcd_reg_en = 0;
 		panelstruct->paneldata    = &nt35597_wqxga_dualdsi_video_panel_data;
-		panelstruct->paneldata->panel_operating_mode = 11;
-		panelstruct->paneldata->panel_with_enable_gpio = 0;
-
 		panelstruct->panelres     = &nt35597_wqxga_dualdsi_video_panel_res;
 		panelstruct->color        = &nt35597_wqxga_dualdsi_video_color;
 		panelstruct->videopanel   = &nt35597_wqxga_dualdsi_video_video_panel;
@@ -169,6 +169,37 @@
 			MAX_TIMING_CONFIG * sizeof(uint32_t));
 		pinfo->mipi.tx_eot_append = true;
 		break;
+	case NT35597_WQXGA_DUALDSI_CMD_PANEL:
+		pan_type = PANEL_TYPE_DSI;
+		pinfo->lcd_reg_en = 0;
+		panelstruct->paneldata    = &nt35597_wqxga_dualdsi_cmd_panel_data;
+		panelstruct->panelres     = &nt35597_wqxga_dualdsi_cmd_panel_res;
+		panelstruct->color        = &nt35597_wqxga_dualdsi_cmd_color;
+		panelstruct->videopanel   = &nt35597_wqxga_dualdsi_cmd_video_panel;
+		panelstruct->commandpanel = &nt35597_wqxga_dualdsi_cmd_command_panel;
+		panelstruct->state        = &nt35597_wqxga_dualdsi_cmd_state;
+		panelstruct->laneconfig   = &nt35597_wqxga_dualdsi_cmd_lane_config;
+		panelstruct->paneltiminginfo
+			= &nt35597_wqxga_dualdsi_cmd_timing_info;
+		panelstruct->panelresetseq
+					 = &nt35597_wqxga_dualdsi_cmd_reset_seq;
+		panelstruct->backlightinfo = &nt35597_wqxga_dualdsi_cmd_backlight;
+
+		pinfo->labibb = &nt35597_wqxga_dualdsi_cmd_labibb;
+
+		pinfo->mipi.panel_on_cmds
+			= nt35597_wqxga_dualdsi_cmd_on_command;
+		pinfo->mipi.num_of_panel_on_cmds
+			= NT35597_WQXGA_DUALDSI_CMD_ON_COMMAND;
+		pinfo->mipi.panel_off_cmds
+			= nt35597_wqxga_dualdsi_cmd_off_command;
+		pinfo->mipi.num_of_panel_off_cmds
+			= NT35597_WQXGA_DUALDSI_CMD_OFF_COMMAND;
+		memcpy(phy_db->timing,
+			nt35597_wqxga_dualdsi_thulium_cmd_timings,
+			MAX_TIMING_CONFIG * sizeof(uint32_t));
+		pinfo->mipi.tx_eot_append = true;
+		break;
 	case JDI_QHD_DUALDSI_VIDEO_PANEL:
 		pan_type = PANEL_TYPE_DSI;
 		pinfo->lcd_reg_en = 1;