platform: msm8994: separate core and pixel clocks
Provide different APIs to program core/ahb and pixel clocks
for HDMI. Core clocks are needed for HPD and cable detection.
Once the cable detection is successful, HDMI power on is done
which needs pixel clock. As they are two different code flows,
we need to separate out the pixel clocks.
Change-Id: Id9046f59d4f74b5d5801d9036279bbbca4691dca
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index d9aa9fb..0b64ce0 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -520,7 +520,7 @@
}
}
-void hdmi_clk_enable(void)
+void hdmi_core_ahb_clk_enable(void)
{
int ret;
@@ -537,18 +537,27 @@
dprintf(CRITICAL, "failed to set hdmi_core_clk ret = %d\n", ret);
ASSERT(0);
}
+}
+
+void hdmi_pixel_clk_enable(uint32_t rate)
+{
+ int ret;
/* Configure hdmi pixel clock */
- ret = clk_get_set_enable("hdmi_extp_clk", 148500000, 1);
+ ret = clk_get_set_enable("hdmi_extp_clk", rate, 1);
if(ret) {
dprintf(CRITICAL, "failed to set hdmi_extp_clk ret = %d\n", ret);
ASSERT(0);
}
}
-void hdmi_clk_disable(void)
+void hdmi_pixel_clk_disable(void)
{
clk_disable(clk_get("hdmi_extp_clk"));
+}
+
+void hdmi_core_ahb_clk_disable(void)
+{
clk_disable(clk_get("hdmi_core_clk"));
clk_disable(clk_get("hdmi_ahb_clk"));
}
diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index f34d2ff..72d9787 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -129,7 +129,9 @@
void mmss_bus_clock_disable(void);
void mdp_clock_enable(void);
void mdp_clock_disable(void);
-void hdmi_clk_enable(void);
-void hdmi_clk_disable(void);
+void hdmi_core_ahb_clk_enable(void);
+void hdmi_pixel_clk_enable(uint32_t rate);
+void hdmi_pixel_clk_disable(void);
+void hdmi_core_ahb_clk_disable(void);
#endif
diff --git a/platform/msm_shared/hdmi_pll_20nm.c b/platform/msm_shared/hdmi_pll_20nm.c
index dc11e8d..6c2aeeb 100644
--- a/platform/msm_shared/hdmi_pll_20nm.c
+++ b/platform/msm_shared/hdmi_pll_20nm.c
@@ -851,9 +851,8 @@
return NO_ERROR;
}
-uint32_t hdmi_pll_config(void)
+uint32_t hdmi_pll_config(uint32_t tmds_clk_rate)
{
- uint32_t tmds_clk_rate = 148500000;
uint32_t clk_index;
/* Find clock target for reset sequence */
diff --git a/platform/msm_shared/include/mdss_hdmi.h b/platform/msm_shared/include/mdss_hdmi.h
index da0c5b7..6786a85 100644
--- a/platform/msm_shared/include/mdss_hdmi.h
+++ b/platform/msm_shared/include/mdss_hdmi.h
@@ -31,7 +31,7 @@
#define _PLATFORM_MSM_SHARED_MDSS_HDMI_H_
void hdmi_phy_reset(void);
-uint32_t hdmi_pll_config(void);
+uint32_t hdmi_pll_config(uint32_t tmds_clk_rate);
int hdmi_vco_enable(void);
int hdmi_vco_disable(void);
void mdss_hdmi_display_init(uint32_t rev, void *base);