commit 4e5f9f7d977efaf0716f134cc38e0565ceab315e
author Linux Build Service Account <lnxbuild@qualcomm.com> Mon Sep 13 19:11:56 2010 -0700
committer QuIC Gerrit Code Review <code-review@quicinc.com> Mon Sep 13 19:11:56 2010 -0700
tree e63ac5e1b335006d96e4470ae9fda9e82a5d9933
parent 3704083c8f47ca3e6a5d68cfbb417af434c5f94e
parent 34d711770c2c1df6f80c2b511d42076419e0c14d

Merge "[msm8660]: Enable support for 1G memory by dynamic detection."

platform/msm8x60/include/platform/iomap.h

diff --git a/platform/msm8x60/include/platform/iomap.h b/platform/msm8x60/include/platform/iomap.h
index 2c267e7..82d5eb2 100755
--- a/platform/msm8x60/include/platform/iomap.h
+++ b/platform/msm8x60/include/platform/iomap.h
@@ -50,11 +50,7 @@
 #define MSM_SDC1_BASE       0x12400000
 #define MMC_BOOT_MCI_BASE   MSM_SDC1_BASE
 
-#if defined(PLATFORM_MSM8X60)
-#define MSM_SHARED_BASE      0x00000000
-#else
-#define MSM_SHARED_BASE      0x01F00000
-#endif
+#define MSM_SHARED_BASE      0x40000000
 
 #define SURF_DEBUG_LED_ADDR      0x1D000202
 

target/msm8660_surf/atags.c

diff --git a/target/msm8660_surf/atags.c b/target/msm8660_surf/atags.c
index 66e6231..ebbf203 100755
--- a/target/msm8660_surf/atags.c
+++ b/target/msm8660_surf/atags.c
@@ -30,14 +30,16 @@
 #include <debug.h>
 #include <smem.h>
 
-#define EBI1_SIZE1   0x02D00000 // 45M
-#define EBI1_ADDR1   0x40200000
+#define SIZE_45M              0x02D00000 // 45M
+#define EBI1_ADDR_1026M       0x40200000
 
-#define EBI1_SIZE2   0x08000000 // 128M
-#define EBI1_ADDR2   0x48000000
+#define SIZE_128M             0x08000000 // 128M
+#define EBI1_ADDR_1152M       0x48000000
 
-#define EBI1_SIZE3   0x10000000 // 256M
-#define EBI1_ADDR3   0x50000000
+#define SIZE_256M             0x10000000 // 256M
+#define EBI1_ADDR_1280M       0x50000000
+
+#define SIZE_768M             0x30000000 // 256M + 512M
 
 #define EBI1_CS1_ADDR_BASE    0x00A40024
 
@@ -48,22 +50,32 @@
     /* ATAG_MEM */
     *ptr++ = 4;
     *ptr++ = 0x54410002;
-    *ptr++ = EBI1_SIZE1;
-    *ptr++ = EBI1_ADDR1;
+    *ptr++ = SIZE_45M;
+    *ptr++ = EBI1_ADDR_1026M;
 
     *ptr++ = 4;
     *ptr++ = 0x54410002;
-    *ptr++ = EBI1_SIZE2;
-    *ptr++ = EBI1_ADDR2;
+    *ptr++ = SIZE_128M;
+    *ptr++ = EBI1_ADDR_1152M;
 
-    /* For 512MB RAM*/
     value = readl(EBI1_CS1_ADDR_BASE);
-    if (((value >> 8) & 0xFF)  == 0x50)
+    value = (value >> 8) & 0xFF;
+
+    if (value == 0x50)
     {
+        /* For 512MB RAM*/
         *ptr++ = 4;
         *ptr++ = 0x54410002;
-        *ptr++ = EBI1_SIZE3;
-        *ptr++ = EBI1_ADDR3;
+        *ptr++ = SIZE_256M;
+        *ptr++ = EBI1_ADDR_1280M;
+    }
+    else if (value == 0x60)
+    {
+        /* For 1GB RAM*/
+        *ptr++ = 4;
+        *ptr++ = 0x54410002;
+        *ptr++ = SIZE_768M;
+        *ptr++ = EBI1_ADDR_1280M;
     }
 
     return ptr;