Merge "[msm8660]: Add support to read status of specific GPIO pins for PM8058"
diff --git a/platform/msm8x60/acpuclock.c b/platform/msm8x60/acpuclock.c
index ffb19f8..8cb6be7 100644
--- a/platform/msm8x60/acpuclock.c
+++ b/platform/msm8x60/acpuclock.c
@@ -43,7 +43,6 @@
writel(regval, reg);
}
-
/* Enable/disable for non-shared NT PLLs. */
int nt_pll_enable(uint8_t src, uint8_t enable)
{
@@ -57,11 +56,11 @@
};
uint32_t pll_mode;
- pll_mode = readl(pll_reg[src].mode_reg);
+ pll_mode = secure_readl(pll_reg[src].mode_reg);
if (enable) {
/* Disable PLL bypass mode. */
pll_mode |= (1<<1);
- writel( pll_mode, pll_reg[src].mode_reg);
+ secure_writel( pll_mode, pll_reg[src].mode_reg);
/* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Delay 10us just to be safe. */
@@ -69,25 +68,24 @@
/* De-assert active-low PLL reset. */
pll_mode |= (1<<2);
- writel( pll_mode, pll_reg[src].mode_reg);
+ secure_writel( pll_mode, pll_reg[src].mode_reg);
/* Enable PLL output. */
pll_mode |= (1<<0);
- writel( pll_mode, pll_reg[src].mode_reg);
+ secure_writel( pll_mode, pll_reg[src].mode_reg);
/* Wait until PLL is enabled. */
- while (!readl(pll_reg[src].status_reg));
+ while (!secure_readl(pll_reg[src].status_reg));
} else {
/* Disable the PLL output, disable test mode, enable
* the bypass mode, and assert the reset. */
pll_mode &= 0xFFFFFFF0;
- writel( pll_mode, pll_reg[src].mode_reg);
+ secure_writel( pll_mode, pll_reg[src].mode_reg);
}
return 0;
}
-
/* Write the M,N,D values and enable the MDP Core Clock */
void config_mdp_clk( uint32_t ns,
uint32_t md,
@@ -96,41 +94,41 @@
uint32_t md_addr,
uint32_t cc_addr)
{
- int val = 0;
+ unsigned int val = 0;
/* MN counter reset */
val = 1 << 31;
- writel(val, ns_addr);
+ secure_writel(val, ns_addr);
/* Write the MD and CC register values */
- writel(md, md_addr);
- writel(cc, cc_addr);
+ secure_writel(md, md_addr);
+ secure_writel(cc, cc_addr);
/* Reset the clk control, and Write ns val */
val = 1 << 31;
val |= ns;
- writel(val, ns_addr);
+ secure_writel(val, ns_addr);
/* Clear MN counter reset */
val = 1 << 31;
val = ~val;
- val = val & readl(ns_addr);
- writel(val, ns_addr);
+ val = val & secure_readl(ns_addr);
+ secure_writel(val, ns_addr);
/* Enable MND counter */
val = 1 << 8;
- val = val | readl(cc_addr);
- writel(val, cc_addr);
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
/* Enable the root of the clock tree */
val = 1 << 2;
- val = val | readl(cc_addr);
- writel(val, cc_addr);
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
/* Enable the MDP Clock */
val = 1 << 0;
- val = val | readl(cc_addr);
- writel(val, cc_addr);
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
}
/* Write the M,N,D values and enable the Pixel Core Clock */
@@ -144,42 +142,42 @@
/* Activate the reset for the M/N Counter */
val = 1 << 7;
- writel(val, ns_addr);
+ secure_writel(val, ns_addr);
/* Write the MD and CC register values */
- writel(md, md_addr);
- writel(cc, cc_addr);
+ secure_writel(md, md_addr);
+ secure_writel(cc, cc_addr);
/* Write the ns value, and active reset for M/N Counter, again */
val = 1 << 7;
val |= ns;
- writel(val, ns_addr);
+ secure_writel(val, ns_addr);
/* De-activate the reset for M/N Counter */
val = 1 << 7;
val = ~val;
- val = val & readl(ns_addr);
- writel(val, ns_addr);
+ val = val & secure_readl(ns_addr);
+ secure_writel(val, ns_addr);
/* Enable MND counter */
val = 1 << 5;
- val = val | readl(cc_addr);
- writel(val, cc_addr);
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
/* Enable the root of the clock tree */
val = 1 << 2;
- val = val | readl(cc_addr);
- writel(val, cc_addr);
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
/* Enable the MDP Clock */
val = 1 << 0;
- val = val | readl(cc_addr);
- writel(val, cc_addr);
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
/* Enable the LCDC Clock */
val = 1 << 8;
- val = val | readl(cc_addr);
- writel(val, cc_addr);
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
}
/* Set rate and enable the clock */
diff --git a/platform/msm8x60/scm-io.c b/platform/msm8x60/scm-io.c
index 222783f..3b117b0 100644
--- a/platform/msm8x60/scm-io.c
+++ b/platform/msm8x60/scm-io.c
@@ -30,6 +30,8 @@
#include <platform/clock.h>
#include <platform/scm-io.h>
+#pragma GCC optimize ("O0")
+
#define SCM_IO_READ ((((0x5 << 10) | 0x1) << 12) | (0x2 << 8) | 0x1)
#define SCM_IO_WRITE ((((0x5 << 10) | 0x2) << 12) | (0x2 << 8) | 0x2)
@@ -73,4 +75,3 @@
} else
writel(v, c);
}
-
diff --git a/target/msm8660_surf/init.c b/target/msm8660_surf/init.c
index 022afda..3b2e358 100644
--- a/target/msm8660_surf/init.c
+++ b/target/msm8660_surf/init.c
@@ -79,6 +79,7 @@
unsigned board_machtype(void)
{
struct smem_board_info_v5 board_info_v5;
+ struct smem_board_info_v6 board_info_v6;
unsigned int board_info_len = 0;
unsigned smem_status = 0;
unsigned format = 0;
@@ -92,7 +93,7 @@
&format, sizeof(format), 0);
if(!smem_status)
{
- if (format >= 5)
+ if (format == 5)
{
board_info_len = sizeof(board_info_v5);
@@ -101,12 +102,24 @@
if(!smem_status)
{
fused_chip = board_info_v5.fused_chip;
+ id = board_info_v5.board_info_v3.hw_platform;
+ }
+ }
+ else if (format == 6)
+ {
+ board_info_len = sizeof(board_info_v6);
+
+ smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v6, board_info_len);
+ if(!smem_status)
+ {
+ fused_chip = board_info_v6.fused_chip;
+ id = board_info_v6.board_info_v3.hw_platform;
}
}
}
/* Detect SURF v/s FFA v/s Fluid */
- id = board_info_v5.board_info_v3.hw_platform;
switch(id)
{
case 0x1:
@@ -185,7 +198,7 @@
unsigned check_reboot_mode(void)
{
unsigned restart_reason = 0;
- void *restart_reason_addr = 0x2A05F010;
+ void *restart_reason_addr = 0x2A05F65C;
/* Read reboot reason and scrub it */
restart_reason = readl(restart_reason_addr);