platform: msm9x35: Add support for reset clocks
Use clock framework to perform block level reset using
bcr register.
CRs-Fixed: 643324
Change-Id: I4d843926b6fb0292770cc24de5ec48ea42e00fa9
diff --git a/platform/mdm9x35/include/platform/iomap.h b/platform/mdm9x35/include/platform/iomap.h
index 7a99b8a..fc459dd 100755
--- a/platform/mdm9x35/include/platform/iomap.h
+++ b/platform/mdm9x35/include/platform/iomap.h
@@ -132,11 +132,14 @@
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
-#define GCC_USB3_PHY_BCR (CLK_CTL_BASE + 0x03FC)
-#define GCC_USB30_PHY_COM_BCR (CLK_CTL_BASE + 0x1B88)
-#define GCC_USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x1B8C)
+/* USB Phy reset */
+#define USB3_PHY_BCR (CLK_CTL_BASE + 0x03FC)
+#define USB3_PHY_COM_BCR (CLK_CTL_BASE + 0x1B88)
+#define USB3PHY_PHY_BCR (CLK_CTL_BASE + 0x1B8C)
+#define USB2B_PHY_BCR (CLK_CTL_BASE + 0x04B0)
/* USB 3.0 clocks */
+#define USB2B_PHY_SLEEP_CBCR (CLK_CTL_BASE + 0x04B4)
#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x0108)
#define GCC_USB_30_BCR (CLK_CTL_BASE + 0x03C0)
#define GCC_USB_30_MISC (CLK_CTL_BASE + 0x03C4)
diff --git a/platform/mdm9x35/mdm9x35-clock.c b/platform/mdm9x35/mdm9x35-clock.c
index 4b0605f..5ba21bb 100755
--- a/platform/mdm9x35/mdm9x35-clock.c
+++ b/platform/mdm9x35/mdm9x35-clock.c
@@ -45,11 +45,17 @@
/* Clock Operations */
+static struct clk_ops clk_ops_reset =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
static struct clk_ops clk_ops_branch =
{
.enable = clock_lib2_branch_clk_enable,
.disable = clock_lib2_branch_clk_disable,
.set_rate = clock_lib2_branch_set_rate,
+ .reset = clock_lib2_branch_clk_reset,
};
static struct clk_ops clk_ops_rcg_mnd =
@@ -292,6 +298,7 @@
};
static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) USB3PHY_PHY_BCR,
.cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
.parent = &usb30_pipe_clk_src.c,
.has_sibling = 0,
@@ -391,6 +398,35 @@
},
};
+static struct reset_clk gcc_usb30_phy_com_reset = {
+ .bcr_reg = (uint32_t *) USB3_PHY_COM_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_com_reset",
+ .ops = &clk_ops_reset,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t *) USB3_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_reset,
+ },
+};
+
+static struct branch_clk gcc_usb2b_phy_sleep_clk = {
+ .bcr_reg = (uint32_t *) USB2B_PHY_BCR,
+ .cbcr_reg = (uint32_t *) USB2B_PHY_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb2b_phy_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* Clock lookup table */
static struct clk_lookup mdm_9635_clocks[] =
{
@@ -407,6 +443,10 @@
CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c),
+ CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2b_phy_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+ CLK_LOOKUP("usb30_phy_com_reset", gcc_usb30_phy_com_reset.c),
+
CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
};