Merge "target: msm8610: Update the size and address of scratch buffer."
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index d50be73..78bfd44 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -123,6 +123,30 @@
unsigned flags;
};
+/*
+ * Partition info, required to be published
+ * for fastboot
+ */
+struct getvar_partition_info {
+ const char part_name[MAX_GPT_NAME_SIZE]; /* Partition name */
+ char getvar_size[MAX_GET_VAR_NAME_SIZE]; /* fastboot get var name for size */
+ char getvar_type[MAX_GET_VAR_NAME_SIZE]; /* fastboot get var name for type */
+ char size_response[MAX_RSP_SIZE]; /* fastboot response for size */
+ char type_response[MAX_RSP_SIZE]; /* fastboot response for type */
+};
+
+/*
+ * Right now, we are publishing the info for only
+ * three partitions
+ */
+struct getvar_partition_info part_info[] =
+{
+ { "system" , "partition-size:", "partition-type:", "", "ext4" },
+ { "userdata", "partition-size:", "partition-type:", "", "ext4" },
+ { "cache" , "partition-size:", "partition-type:", "", "ext4" },
+};
+
+char max_download_size[MAX_RSP_SIZE];
char sn_buf[13];
extern int emmc_recovery_init(void);
@@ -1200,20 +1224,8 @@
memmove((void*) hdr->tags_addr,
boot_image_start + dt_image_offset + dt_entry_ptr->offset,
dt_entry_ptr->size);
- } else {
- /*
- * If appended dev tree is found, update the atags with
- * memory address to the DTB appended location on RAM.
- * Else update with the atags address in the kernel header
- */
- void *dtb;
- dtb = dev_tree_appended((void *)hdr->kernel_addr,
- (void *)hdr->tags_addr);
- if (!dtb) {
- dprintf(CRITICAL, "ERROR: Appended Device Tree Blob not found\n");
- return -1;
- }
- }
+ } else
+ return -1;
/* Everything looks fine. Return success. */
return 0;
@@ -1226,6 +1238,8 @@
unsigned ramdisk_actual;
struct boot_img_hdr *hdr;
char *ptr = ((char*) data);
+ int ret = 0;
+ uint8_t dtb_copied = 0;
if (sz < sizeof(hdr)) {
fastboot_fail("invalid bootimage header");
@@ -1263,15 +1277,31 @@
return;
}
- memmove((void*) hdr->kernel_addr, ptr + page_size, hdr->kernel_size);
- memmove((void*) hdr->ramdisk_addr, ptr + page_size + kernel_actual, hdr->ramdisk_size);
-
#if DEVICE_TREE
/* find correct dtb and copy it to right location */
- if(copy_dtb(data))
- {
- fastboot_fail("dtb not found");
- return;
+ ret = copy_dtb(data);
+
+ dtb_copied = !ret ? 1 : 0;
+#endif
+
+ /* Load ramdisk & kernel */
+ memmove((void*) hdr->ramdisk_addr, ptr + page_size + kernel_actual, hdr->ramdisk_size);
+ memmove((void*) hdr->kernel_addr, ptr + page_size, hdr->kernel_size);
+
+#if DEVICE_TREE
+ /*
+ * If dtb is not found look for appended DTB in the kernel.
+ * If appended dev tree is found, update the atags with
+ * memory address to the DTB appended location on RAM.
+ * Else update with the atags address in the kernel header
+ */
+ if (!dtb_copied) {
+ void *dtb;
+ dtb = dev_tree_appended((void *)hdr->kernel_addr, (void *)hdr->tags_addr);
+ if (!dtb) {
+ fastboot_fail("dtb not found");
+ return;
+ }
}
#endif
@@ -1665,6 +1695,11 @@
fastboot_okay("");
}
+void cmd_preflash(const char *arg, void *data, unsigned sz)
+{
+ fastboot_okay("");
+}
+
void splash_screen ()
{
struct ptentry *ptn;
@@ -1695,6 +1730,65 @@
}
}
+/* Get the size from partiton name */
+static void get_partition_size(const char *arg, char *response)
+{
+ uint64_t ptn = 0;
+ uint64_t size;
+ int index = INVALID_PTN;
+
+ index = partition_get_index(arg);
+
+ if (index == INVALID_PTN)
+ {
+ dprintf(CRITICAL, "Invalid partition index\n");
+ return;
+ }
+
+ ptn = partition_get_offset(index);
+
+ if(!ptn)
+ {
+ dprintf(CRITICAL, "Invalid partition name %s\n", arg);
+ return;
+ }
+
+ size = partition_get_size(index);
+
+ snprintf(response, MAX_RSP_SIZE, "\t 0x%llx", size);
+ return;
+}
+
+/*
+ * Publish the partition type & size info
+ * fastboot getvar will publish the required information.
+ * fastboot getvar partition_size:<partition_name>: partition size in hex
+ * fastboot getvar partition_type:<partition_name>: partition type (ext/fat)
+ */
+static void publish_getvar_partition_info(struct getvar_partition_info *info, uint8_t num_parts)
+{
+ uint8_t i;
+
+ for (i = 0; i < num_parts; i++) {
+ get_partition_size(info[i].part_name, info[i].size_response);
+
+ if (strlcat(info[i].getvar_size, info[i].part_name, MAX_GET_VAR_NAME_SIZE) >= MAX_GET_VAR_NAME_SIZE)
+ {
+ dprintf(CRITICAL, "partition size name truncated\n");
+ return;
+ }
+ if (strlcat(info[i].getvar_type, info[i].part_name, MAX_GET_VAR_NAME_SIZE) >= MAX_GET_VAR_NAME_SIZE)
+ {
+ dprintf(CRITICAL, "partition type name truncated\n");
+ return;
+ }
+
+ /* publish partition size & type info */
+ fastboot_publish((const char *) info[i].getvar_size, (const char *) info[i].size_response);
+ fastboot_publish((const char *) info[i].getvar_type, (const char *) info[i].type_response);
+ }
+}
+
void aboot_init(const struct app_descriptor *app)
{
unsigned reboot_mode = 0;
@@ -1780,6 +1874,8 @@
fastboot:
+ sz = target_get_max_flash_size();
+
target_fastboot_init();
if(!usb_init)
@@ -1803,11 +1899,15 @@
fastboot_register("reboot-bootloader", cmd_reboot_bootloader);
fastboot_register("oem unlock", cmd_oem_unlock);
fastboot_register("oem device-info", cmd_oem_devinfo);
+ fastboot_register("preflash", cmd_preflash);
fastboot_publish("product", TARGET(BOARD));
fastboot_publish("kernel", "lk");
fastboot_publish("serialno", sn_buf);
+ publish_getvar_partition_info(part_info, ARRAY_SIZE(part_info));
+ /* Max download size supported */
+ snprintf(max_download_size, MAX_RSP_SIZE, "\t0x%x", sz);
+ fastboot_publish("max-download-size", (const char *) max_download_size);
partition_dump();
- sz = target_get_max_flash_size();
fastboot_init(target_get_scratch_address(), sz);
udc_start();
}
diff --git a/app/aboot/fastboot.c b/app/aboot/fastboot.c
index 5b9dc9a..262a08e 100644
--- a/app/aboot/fastboot.c
+++ b/app/aboot/fastboot.c
@@ -35,8 +35,8 @@
#include <kernel/thread.h>
#include <kernel/event.h>
#include <dev/udc.h>
+#include "fastboot.h"
-#define MAX_RSP_SIZE 64
#define MAX_USBFS_BULK_SIZE (32 * 1024)
void boot_linux(void *bootimg, unsigned sz);
diff --git a/app/aboot/fastboot.h b/app/aboot/fastboot.h
index d66886c..0703402 100644
--- a/app/aboot/fastboot.h
+++ b/app/aboot/fastboot.h
@@ -2,6 +2,8 @@
* Copyright (c) 2009, Google Inc.
* All rights reserved.
*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -29,6 +31,9 @@
#ifndef __APP_FASTBOOT_H
#define __APP_FASTBOOT_H
+#define MAX_RSP_SIZE 64
+#define MAX_GET_VAR_NAME_SIZE 256
+
int fastboot_init(void *xfer_buffer, unsigned max);
/* register a command handler
diff --git a/platform/mdm9x25/acpuclock.c b/platform/mdm9x25/acpuclock.c
index a602988..cf8486d 100644
--- a/platform/mdm9x25/acpuclock.c
+++ b/platform/mdm9x25/acpuclock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -82,41 +82,6 @@
}
}
-
-void qpic_nand_clock_init(void)
-{
- int ret;
- struct clk *iclk;
- struct clk *cclk;
-
- iclk = clk_get("qpic_iface_clk");
- cclk = clk_get("qpic_core_clk");
-
- ASSERT(iclk);
- ASSERT(cclk);
-
- ret = clk_enable(iclk);
- if(ret)
- {
- dprintf(CRITICAL, "failed to set qpic_iface_clk ret = %d\n", ret);
- ASSERT(0);
- }
-
- ret = clk_set_rate(cclk, 100000000);
- if(ret)
- {
- dprintf(CRITICAL, "failed to set_rate of qpic_core_clk ret = %d\n", ret);
- ASSERT(0);
- }
-
- ret = clk_enable(cclk);
- if(ret)
- {
- dprintf(CRITICAL, "failed to enable qpic_core_clk ret = %d\n", ret);
- ASSERT(0);
- }
-}
-
void clock_config_uart_dm(uint8_t id)
{
int ret;
diff --git a/platform/mdm9x25/include/platform/clock.h b/platform/mdm9x25/include/platform/clock.h
index 267ec84..d6d21cd 100644
--- a/platform/mdm9x25/include/platform/clock.h
+++ b/platform/mdm9x25/include/platform/clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -32,7 +32,6 @@
#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
void hsusb_clock_init(void);
-void qpic_nand_clock_init(void);
void clock_config_uart_dm(uint8_t id);
#endif
diff --git a/platform/mdm9x25/include/platform/iomap.h b/platform/mdm9x25/include/platform/iomap.h
index 7801e4f..5dfa761 100644
--- a/platform/mdm9x25/include/platform/iomap.h
+++ b/platform/mdm9x25/include/platform/iomap.h
@@ -126,14 +126,4 @@
#define USB_BOOT_CLOCK_CTL (CLK_CTL_BASE + 0x1A00)
-#define GCC_QPIC_BCR (CLK_CTL_BASE + 0x1A40)
-#define GCC_QPIC_CBCR (CLK_CTL_BASE + 0x1A44)
-#define GCC_QPIC_AHB_CBCR (CLK_CTL_BASE + 0x1A48)
-#define GCC_QPIC_SYSTEM_CBCR (CLK_CTL_BASE + 0x1A4C)
-#define GCC_QPIC_CMD_RCGR (CLK_CTL_BASE + 0x1A50)
-#define GCC_QPIC_CFG_RCGR (CLK_CTL_BASE + 0x1A54)
-#define GCC_QPIC_M (CLK_CTL_BASE + 0x1A58)
-#define GCC_QPIC_N (CLK_CTL_BASE + 0x1A5C)
-#define GCC_QPIC_D (CLK_CTL_BASE + 0x1A60)
-
#endif
diff --git a/platform/mdm9x25/mdm9x25-clock.c b/platform/mdm9x25/mdm9x25-clock.c
index d5f4ab3..55dc9f1 100644
--- a/platform/mdm9x25/mdm9x25-clock.c
+++ b/platform/mdm9x25/mdm9x25-clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -271,50 +271,6 @@
},
};
-static struct branch_clk gcc_qpic_ahb_clk =
-{
- .cbcr_reg = (uint32_t *) GCC_QPIC_AHB_CBCR,
- .has_sibling = 1,
-
- .c = {
- .dbg_name = "gcc_qpic_ahb_clk",
- .ops = &clk_ops_branch,
- },
-};
-
-/* NAND Clocks */
-static struct clk_freq_tbl ftbl_gcc_qpic_nand_clk[] =
-{
- F(100000000, gpll0, 6, 0, 0),
- F_END
-};
-
-static struct rcg_clk qpic_nand_clk_src =
-{
- .cmd_reg = (uint32_t *) GCC_QPIC_CMD_RCGR,
- .cfg_reg = (uint32_t *) GCC_QPIC_CFG_RCGR,
-
- .set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_qpic_nand_clk,
- .current_freq = &rcg_dummy_freq,
-
- .c = {
- .dbg_name = "qpic_nand_clk_src",
- .ops = &clk_ops_rcg_mnd,
- },
-};
-
-static struct branch_clk gcc_qpic_nand_clk =
-{
- .cbcr_reg = (uint32_t *) GCC_QPIC_CBCR,
- .parent = &qpic_nand_clk_src.c,
-
- .c = {
- .dbg_name = "gcc_qpic_nand_clk",
- .ops = &clk_ops_branch,
- },
-};
-
/* Clock lookup table */
static struct clk_lookup mdm_9625_clocks[] =
{
@@ -326,8 +282,6 @@
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
- CLK_LOOKUP("qpic_iface_clk", gcc_qpic_ahb_clk.c),
- CLK_LOOKUP("qpic_core_clk", gcc_qpic_nand_clk.c),
};
diff --git a/platform/msm8226/acpuclock.c b/platform/msm8226/acpuclock.c
index f45a4b1..96e8687 100644
--- a/platform/msm8226/acpuclock.c
+++ b/platform/msm8226/acpuclock.c
@@ -60,9 +60,6 @@
iclk = clk_get("usb_iface_clk");
cclk = clk_get("usb_core_clk");
- /* Disable USB all clock init */
- writel(0, USB_BOOT_CLOCK_CTL);
-
clk_disable(iclk);
clk_disable(cclk);
@@ -169,7 +166,118 @@
}
}
+/* Function to asynchronously reset CE.
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+ if (instance == 1)
+ {
+ /* Start the block reset for CE */
+ writel(1, GCC_CE1_BCR);
+
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CE1_BCR);
+
+ udelay(2);
+ }
+ else
+ {
+ dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
+ ASSERT(0);
+ }
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+ int ret;
+ char clk_name[64];
+
+ snprintf(clk_name, 64, "ce%u_src_clk", instance);
+ ret = clk_get_set_enable(clk_name, 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, 64, "ce%u_core_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, 64, "ce%u_axi_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Wait for 48 * #pipes cycles.
+ * This is necessary as immediately after an access control reset (boot up)
+ * or a debug re-enable, the Crypto core sequentially clears its internal
+ * pipe key storage memory. If pipe key initialization writes are attempted
+ * during this time, they may be overwritten by the internal clearing logic.
+ */
+ udelay(1);
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+ struct clk *ahb_clk;
+ struct clk *cclk;
+ struct clk *axi_clk;
+ struct clk *src_clk;
+ char clk_name[64];
+
+ snprintf(clk_name, 64, "ce%u_src_clk", instance);
+ src_clk = clk_get(clk_name);
+
+ snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
+ ahb_clk = clk_get(clk_name);
+
+ snprintf(clk_name, 64, "ce%u_axi_clk", instance);
+ axi_clk = clk_get(clk_name);
+
+ snprintf(clk_name, 64, "ce%u_core_clk", instance);
+ cclk = clk_get(clk_name);
+
+ clk_disable(ahb_clk);
+ clk_disable(axi_clk);
+ clk_disable(cclk);
+ clk_disable(src_clk);
+
+ /* Some delay for the clocks to stabalize. */
+ udelay(1);
+}
+
void clock_config_ce(uint8_t instance)
{
+ /* Need to enable the clock before disabling since the clk_disable()
+ * has a check to default to nop when the clk_enable() is not called
+ * on that particular clock.
+ */
+ clock_ce_enable(instance);
+
+ clock_ce_disable(instance);
+
+ ce_async_reset(instance);
+
+ clock_ce_enable(instance);
+
}
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index 9519882..d459984 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -72,7 +72,6 @@
#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
-#define USB_BOOT_CLOCK_CTL (CLK_CTL_BASE + 0x1A00)
#define SPMI_BASE 0xFC4C0000
#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
@@ -94,6 +93,14 @@
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
+/* CE 1 */
+#define GCC_CE1_BCR (CLK_CTL_BASE + 0x1040)
+#define GCC_CE1_CMD_RCGR (CLK_CTL_BASE + 0x1050)
+#define GCC_CE1_CFG_RCGR (CLK_CTL_BASE + 0x1054)
+#define GCC_CE1_CBCR (CLK_CTL_BASE + 0x1044)
+#define GCC_CE1_AXI_CBCR (CLK_CTL_BASE + 0x1048)
+#define GCC_CE1_AHB_CBCR (CLK_CTL_BASE + 0x104C)
+
/* SDCC */
#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
diff --git a/platform/msm8226/msm8226-clock.c b/platform/msm8226/msm8226-clock.c
index 9f5818b..ccec8fc 100644
--- a/platform/msm8226/msm8226-clock.c
+++ b/platform/msm8226/msm8226-clock.c
@@ -270,6 +270,59 @@
},
};
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_CE1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_CE1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_ce1_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "ce1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct vote_clk gcc_ce1_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(5),
+
+ .c = {
+ .dbg_name = "gcc_ce1_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(3),
+
+ .c = {
+ .dbg_name = "gcc_ce1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(4),
+
+ .c = {
+ .dbg_name = "gcc_ce1_axi_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+
/* Clock lookup table */
static struct clk_lookup msm_clocks_8226[] =
{
@@ -281,6 +334,11 @@
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+
+ CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
+ CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
+ CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+ CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
};
void platform_clock_init(void)
diff --git a/platform/msm8610/include/platform/iomap.h b/platform/msm8610/include/platform/iomap.h
index 2cbbd28..0c00cf4 100644
--- a/platform/msm8610/include/platform/iomap.h
+++ b/platform/msm8610/include/platform/iomap.h
@@ -34,7 +34,7 @@
#define SDRAM_START_ADDR 0x00000000
-#define MSM_SHARED_BASE 0x0D600000
+#define MSM_SHARED_BASE 0x0D900000
#define APPS_SS_BASE 0xF9000000
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 5996c0f..523f708 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -116,220 +116,6 @@
return NULL;
}
-/* Function to return the offset of flash node - "/qcom,mtd-partitions".
- * The function creates this node if it does not exist.
- */
-static uint32_t dev_tree_get_flash_node_offset(void *fdt)
-{
- uint32_t offset;
- int ret = DT_OP_SUCCESS;
-
- /* Find the mtd node. */
- ret = fdt_path_offset(fdt, "/qcom,mtd-partitions");
-
- if (ret & FDT_ERR_NOTFOUND)
- {
- /* Node not found.
- * Add node as sub node of root.
- */
- ret = fdt_path_offset(fdt, "/");
-
- if (ret < 0)
- {
- dprintf(CRITICAL, "Unable to calculate root offset\n");
- ret = DT_OP_FAILURE;
- goto dev_tree_get_flash_node_offset_err;
- }
-
- offset = ret;
- /* Add flash partition node. */
- ret = fdt_add_subnode(fdt, offset, "qcom,mtd-partitions");
-
- if (ret < 0)
- {
- dprintf(CRITICAL, "Unable to add partition node. \n");
- ret = DT_OP_FAILURE;
- goto dev_tree_get_flash_node_offset_err;
- }
-
- /* Save the offset of the added node. */
- offset = fdt_path_offset(fdt, "/qcom,mtd-partitions");
- }
- else if (ret != 0)
- {
- dprintf(CRITICAL, "Unable to calculate partition node offset\n");
- ret = DT_OP_FAILURE;
- goto dev_tree_get_flash_node_offset_err;
- }
-
-dev_tree_get_flash_node_offset_err:
-
- return offset;
-}
-
-/* Function to add the individual nand partition nodes to the device tree.
- * Pre-condition: The function assumes the presence of
- * "/qcom,mtd-partitions" device node.
- */
-static int dev_tree_add_ptable_nodes(void *fdt, uint32_t parent_offset)
-{
- struct ptable *ptable;
- int n;
- unsigned char array[100];
- unsigned char *ptn_name_array;
- int dt_ret = DT_OP_SUCCESS;
- int ret;
- int i;
- uint32_t node_offset;
- uint32_t blk_size;
-
- n = sizeof("partition@");
-
- /* Allocate bytes to save partition name:
- * Since address is of uint uint32_t,
- * allocate twice this size for string
- * as 1 digit occupies 1 byte is ASCII.
- */
- ptn_name_array = (unsigned char*) malloc(sizeof(uint32_t) * 2 + n + 1);
-
- if (ptn_name_array == NULL)
- {
- dprintf(CRITICAL, "Failed to allocate memory for flash partition name\n");
- return -1;
- }
-
- strcpy((char*)ptn_name_array, (const char*)"partition@");
-
- /* Add ptable nodes. */
- ptable = flash_get_ptable();
- /* Get block size. */
- blk_size = flash_block_size();
-
- dprintf(INFO, "Add %d flash partitions to dt: start\n", ptable->count);
-
- for (i = 0; i < ptable->count; i++)
- {
- /* Add the partition node. */
- if (itoa(ptable->parts[i].start * blk_size, ptn_name_array + n - 1, sizeof(uint32_t) * 2 + 1, 16) < 0)
- {
- dprintf(CRITICAL, "String len exceeded for itoa\n");
- return -1;
- }
-
- strcpy((char *)array, (const char*)"/qcom,mtd-partitions/");
- strcat((char*)array, (const char*)ptn_name_array);
-
- ret = fdt_add_subnode(fdt, parent_offset, (const char*)ptn_name_array);
-
- if (ret < 0)
- {
- dprintf(CRITICAL, "Unable to add partition node: %s.\n",
- ptn_name_array);
- dt_ret = DT_OP_FAILURE;
- goto dev_tree_add_ptable_nodes_err;
- }
-
- dt_ret = fdt_path_offset(fdt, (const char*)array);
-
- if (dt_ret < 0)
- {
- dprintf(CRITICAL, "Unable to calculate parition node offset: %s\n",
- ptn_name_array);
- dt_ret = DT_OP_FAILURE;
- goto dev_tree_add_ptable_nodes_err;
- }
-
- node_offset = dt_ret;
-
- /* Add the partition name as label. */
- ret = fdt_setprop_string(fdt, node_offset, (const char*)"label", (const char*)ptable->parts[i].name);
-
- if (ret != 0)
- {
- dprintf(CRITICAL, "Unable to add label property: %s.\n",
- ptable->parts[i].name);
- dt_ret = DT_OP_FAILURE;
- goto dev_tree_add_ptable_nodes_err;
- }
-
- /* Add the reg values. */
- ret = fdt_setprop_u32(fdt, node_offset, (const char*)"reg", ptable->parts[i].start * blk_size);
-
- if (ret != 0)
- {
- dprintf(CRITICAL, "Unable to add reg property. %s\n",
- ptable->parts[i].name);
- dt_ret = DT_OP_FAILURE;
- goto dev_tree_add_ptable_nodes_err;
- }
-
- ret = fdt_appendprop_u32(fdt, node_offset, (const char*)"reg", ptable->parts[i].length * blk_size);
-
- if (ret != 0)
- {
- dprintf(CRITICAL, "Unable to add reg property. %s\n",
- ptable->parts[i].name);
- dt_ret = DT_OP_FAILURE;
- goto dev_tree_add_ptable_nodes_err;
- }
-
- }
-
-dev_tree_add_ptable_nodes_err:
- dprintf(INFO, "Add %d flash partitions to dt: done\n", ptable->count);
- free(ptn_name_array);
- return dt_ret;
-}
-
-/* Top level function to add flash ptable info to the device tree. */
-static int dev_tree_add_flash_ptable(void *fdt)
-{
- uint32_t offset;
- int ret;
- int dt_ret = DT_OP_SUCCESS;
-
- dt_ret = dev_tree_get_flash_node_offset(fdt);
-
- if (dt_ret < 0)
- {
- dt_ret = DT_OP_FAILURE;
- goto dev_tree_add_flash_ptable_err;
- }
-
- offset = dt_ret;
-
- /* Add address and size cell properties. */
- ret = fdt_setprop_u32(fdt, offset, (const char*)"#address-cells", 1);
-
- if (ret != 0)
- {
- dprintf(CRITICAL, "Unable to add #address-cells property. \n");
- dt_ret = DT_OP_FAILURE;
- goto dev_tree_add_flash_ptable_err;
- }
-
- ret = fdt_setprop_u32(fdt, offset, (const char*)"#size-cells", 1);
-
- if (ret != 0)
- {
- dprintf(CRITICAL, "Unable to add #size-cells property. \n");
- dt_ret = DT_OP_FAILURE;
- goto dev_tree_add_flash_ptable_err;
- }
-
- ret = dev_tree_add_ptable_nodes(fdt, offset);
-
- if (ret < 0)
- {
- dprintf(CRITICAL, "Unable to add #size-cells property. \n");
- dt_ret = DT_OP_FAILURE;
- goto dev_tree_add_flash_ptable_err;
- }
-
-dev_tree_add_flash_ptable_err:
- return dt_ret;
-}
-
/* Function to add the first RAM partition info to the device tree.
* Note: The function replaces the reg property in the "/memory" node
* with the addr and size provided.
@@ -426,11 +212,6 @@
return ret;
}
- /* Skip NAND partition nodes for eMMC boot */
- if (!target_is_emmc_boot()){
- dev_tree_add_flash_ptable(fdt);
- }
-
/* Get offset of the chosen node */
ret = fdt_path_offset(fdt, "/chosen");
if (ret < 0)
diff --git a/platform/msm_shared/include/mmc.h b/platform/msm_shared/include/mmc.h
index 4feaab6..db65056 100644
--- a/platform/msm_shared/include/mmc.h
+++ b/platform/msm_shared/include/mmc.h
@@ -542,11 +542,6 @@
} \
} while(0);
-#define GET_LWORD_FROM_BYTE(x) ((unsigned)*(x) | \
- ((unsigned)*(x+1) << 8) | \
- ((unsigned)*(x+2) << 16) | \
- ((unsigned)*(x+3) << 24))
-
#define PUT_LWORD_TO_BYTE(x, y) do{*(x) = y & 0xff; \
*(x+1) = (y >> 8) & 0xff; \
*(x+2) = (y >> 16) & 0xff; \
diff --git a/platform/msm_shared/include/partition_parser.h b/platform/msm_shared/include/partition_parser.h
index 13a123d..86e2cf5 100644
--- a/platform/msm_shared/include/partition_parser.h
+++ b/platform/msm_shared/include/partition_parser.h
@@ -112,6 +112,11 @@
#define MBR_PROTECTED_TYPE 0xEE
#define MBR_SSD_TYPE 0x5D
+#define GET_LWORD_FROM_BYTE(x) ((unsigned)*(x) | \
+ ((unsigned)*(x+1) << 8) | \
+ ((unsigned)*(x+2) << 16) | \
+ ((unsigned)*(x+3) << 24))
+
#define GET_LLWORD_FROM_BYTE(x) ((unsigned long long)*(x) | \
((unsigned long long)*(x+1) << 8) | \
((unsigned long long)*(x+2) << 16) | \
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 4d6de3a..66afa82 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -133,16 +133,20 @@
/* Ignore TZ return value till it's fixed */
if (!access_secure || 1) {
+
/* Force VBIF Clocks on */
writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
- /* Configure DDR burst length */
- writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
- writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL );
- writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
- writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN);
- writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO);
- writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0);
- writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1);
+
+ if (readl(MDP_HW_REV) == MDSS_MDP_HW_REV_100) {
+ /* Configure DDR burst length */
+ writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
+ writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL );
+ writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
+ writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN);
+ writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO);
+ writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0);
+ writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1);
+ }
}
/* Allocate SMP blocks */
diff --git a/platform/msm_shared/nand.c b/platform/msm_shared/nand.c
index fae7fbb..4030c34 100644
--- a/platform/msm_shared/nand.c
+++ b/platform/msm_shared/nand.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
- * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -3329,6 +3329,10 @@
flash_data = memalign(32, 4096 + 128);
flash_spare = memalign(32, 128);
+ if (flash_ptrlist == NULL || flash_cmdlist == NULL
+ || flash_data == NULL || flash_spare == NULL)
+ ASSERT(0);
+
flash_read_id(flash_cmdlist, flash_ptrlist);
if ((FLASH_8BIT_NAND_DEVICE == flash_info.type)
|| (FLASH_16BIT_NAND_DEVICE == flash_info.type)) {
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index d52b007..6a386ce 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -1246,8 +1246,6 @@
uint32_t i;
int nand_ret;
- qpic_nand_clock_init();
-
nand_base = config->nand_base;
qpic_bam_init(config);
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index eea958e..88528e1 100755
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -285,6 +285,7 @@
MSM8110 = 161,
MSM8210 = 162,
MSM8810 = 163,
+ MSM8612 = 165,
MSM8125 = 167,
MDM9310 = 171,
APQ8064AA = 172, /* aka V2 SLOW_PRIME */
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index 326b26f..61f29b3 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -160,6 +160,7 @@
case MSM8110:
case MSM8210:
case MSM8810:
+ case MSM8612:
board->baseband = BASEBAND_MSM;
break;
default:
diff --git a/target/msm8960/init.c b/target/msm8960/init.c
index 2eb3e55..72d9463 100755
--- a/target/msm8960/init.c
+++ b/target/msm8960/init.c
@@ -289,7 +289,6 @@
case LINUX_MACHTYPE_8930_CDP:
case LINUX_MACHTYPE_8930_MTP:
case LINUX_MACHTYPE_8930_FLUID:
- case LINUX_MACHTYPE_8930_EVT:
uart_dm_init(5, 0x16400000, 0x16440000);
break;
@@ -325,8 +324,6 @@
default:
dprintf(CRITICAL, "uart gsbi not defined for target: %d\n",
target_id);
-
- ASSERT(0);
}
}
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index a3d48b7..e1ab1c2 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -449,9 +449,28 @@
*/
void target_mmc_caps(struct mmc_host *host)
{
+ uint32_t soc_ver = 0;
+
+ soc_ver = board_soc_version();
+
+ /*
+ * 8974 v1 fluid devices, have a hardware bug
+ * which limits the bus width to 4 bit.
+ */
+ switch(board_hardware_id())
+ {
+ case HW_PLATFORM_FLUID:
+ if (soc_ver >= BOARD_SOC_VERSION2)
+ host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
+ else
+ host->caps.bus_width = MMC_BOOT_BUS_WIDTH_4_BIT;
+ break;
+ default:
+ host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
+ };
+
host->caps.ddr_mode = 1;
host->caps.hs200_mode = 1;
- host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
host->caps.hs_clk_rate = MMC_CLK_96MHZ;
}