Merge "platform: msm_shared: add cache support to nand"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 55b1181..227b2fc 100755
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -1701,6 +1701,17 @@
return -1;
}
+ if(dt_entry.offset > (UINT_MAX - dt_entry.size)) {
+ dprintf(CRITICAL, "ERROR: Device tree contents are Invalid\n");
+ return -1;
+ }
+
+ /* Ensure we are not overshooting dt_size with the dt_entry selected */
+ if ((dt_entry.offset + dt_entry.size) > dt_size) {
+ dprintf(CRITICAL, "ERROR: Device tree contents are Invalid\n");
+ return -1;
+ }
+
best_match_dt_addr = (unsigned char *)table + dt_entry.offset;
dtb_size = dt_entry.size;
memmove((void *)hdr->tags_addr, (char *)best_match_dt_addr, dtb_size);
@@ -2422,6 +2433,7 @@
// Initialize boot state before trying to verify boot.img
#if VERIFIED_BOOT
boot_verifier_init();
+#endif
/* Handle overflow if the input image size is greater than
* boot image buffer can hold
*/
@@ -2430,7 +2442,6 @@
fastboot_fail("booimage: size is greater than boot image buffer can hold");
goto boot_failed;
}
-#endif
/* Verify the boot image
* device & page_size are initialized in aboot_init
diff --git a/dev/qpnp_wled/include/qpnp_wled.h b/dev/qpnp_wled/include/qpnp_wled.h
index 4ca2379..a71b96d 100644
--- a/dev/qpnp_wled/include/qpnp_wled.h
+++ b/dev/qpnp_wled/include/qpnp_wled.h
@@ -46,6 +46,7 @@
#define QPNP_WLED_ILIM_REG(b) (b + 0x4E)
#define QPNP_WLED_VLOOP_COMP_RES(b) (b + 0x55)
#define QPNP_WLED_VLOOP_COMP_GM(b) (b + 0x56)
+#define QPNP_WLED_PSM_EN(b) (b + 0x5A)
#define QPNP_WLED_PSM_CTRL(b) (b + 0x5B)
#define QPNP_WLED_TEST4(b) (b + 0xE5)
#define QPNP_WLED_CTRL_SPARE_REG(b) (b + 0xDF)
diff --git a/dev/qpnp_wled/qpnp_wled.c b/dev/qpnp_wled/qpnp_wled.c
index 4267372..6161458 100644
--- a/dev/qpnp_wled/qpnp_wled.c
+++ b/dev/qpnp_wled/qpnp_wled.c
@@ -236,6 +236,8 @@
0x81);
pm8x41_wled_reg_write(QPNP_WLED_PSM_CTRL(wled->ctrl_base),
0x83);
+ pm8x41_wled_reg_write(QPNP_WLED_PSM_EN(wled->ctrl_base),
+ 0x80);
rc = qpnp_wled_sec_access(wled, wled->ctrl_base);
if (rc)
diff --git a/include/platform.h b/include/platform.h
index 07b1c04..e29b006 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -85,7 +85,8 @@
void get_bootloader_version(unsigned char *buf);
void get_baseband_version(unsigned char *buf);
bool is_device_locked();
-bool platform_is_mdmcalifornium();
+bool platform_is_mdm9650();
bool platform_is_sdxhedgehog();
uint64_t platform_get_ddr_start();
+bool platform_is_glink_enabled();
#endif
diff --git a/platform/init.c b/platform/init.c
index 8280ffb..f429527 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -162,3 +162,14 @@
{
return SIGNATURE_SIZE;
}
+
+/* Check if glink is supported or not */
+__WEAK bool platform_is_glink_enabled()
+{
+#if GLINK_SUPPORT
+ return 1;
+#else
+ return 0;
+#endif
+}
+
diff --git a/platform/mdm9640/acpuclock.c b/platform/mdm9640/acpuclock.c
index 38b1f22..74f86c9 100644
--- a/platform/mdm9640/acpuclock.c
+++ b/platform/mdm9640/acpuclock.c
@@ -116,8 +116,8 @@
ASSERT(0);
}
- if (platform_is_mdmcalifornium())
- ret = clk_get_set_enable("usb30_pipe_clk_mdmcalifornium", 0, 1);
+ if (platform_is_mdm9650())
+ ret = clk_get_set_enable("usb30_pipe_clk_mdm9650", 0, 1);
else if (platform_is_sdxhedgehog())
ret = clk_get_set_enable("usb30_pipe_clk_sdxhedgehog", 0, 1);
else
@@ -221,7 +221,7 @@
{
int ret =0;
- if (platform_is_mdmcalifornium())
+ if (platform_is_mdm9650())
ret = clk_get_set_enable("usb30_pipe_clk", 0, true);
else
ret = clk_get_set_enable("usb30_pipe_clk", 125000000, true);
@@ -316,7 +316,7 @@
int ret;
char clk_name[64];
- if (platform_is_mdmcalifornium())
+ if (platform_is_mdm9650())
{
if (instance == 1)
rpm_send_data(&CE1_CLK[GENERIC_ENABLE][0], 24, RPM_REQUEST_TYPE);
@@ -377,7 +377,7 @@
struct clk *src_clk;
char clk_name[64];
- if (platform_is_mdmcalifornium())
+ if (platform_is_mdm9650())
{
if (instance == 1)
rpm_send_data(&CE1_CLK[GENERIC_DISABLE][0], 24, RPM_REQUEST_TYPE);
diff --git a/platform/mdm9640/include/platform/iomap.h b/platform/mdm9640/include/platform/iomap.h
index a55687c..6981256 100644
--- a/platform/mdm9640/include/platform/iomap.h
+++ b/platform/mdm9640/include/platform/iomap.h
@@ -219,4 +219,11 @@
/* Register for finding out if single ended or differential clock enablement */
#define TCSR_PHY_CLK_SCHEME_SEL 0x01956044
+/* RPM MSG RAM */
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS 0x00060000
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE 0x00006000
+/* notify RPM via IPC interrupt*/
+#define APCS_HLOS_IPC_INTERRUPT_0 APCS_ALIAS0_IPC_INTERRUPT
+
#endif
diff --git a/platform/mdm9640/include/platform/irqs.h b/platform/mdm9640/include/platform/irqs.h
index a9e8fc5..b1d958b 100644
--- a/platform/mdm9640/include/platform/irqs.h
+++ b/platform/mdm9640/include/platform/irqs.h
@@ -47,6 +47,7 @@
#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define GLINK_IPC_IRQ (GIC_SPI_START + 168)
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
diff --git a/platform/mdm9640/mdm9640-clock.c b/platform/mdm9640/mdm9640-clock.c
index b6ad898..bc47cac 100644
--- a/platform/mdm9640/mdm9640-clock.c
+++ b/platform/mdm9640/mdm9640-clock.c
@@ -412,14 +412,14 @@
};
-static struct branch_clk gcc_usb30_pipe_clk_mdmcalifornium = {
+static struct branch_clk gcc_usb30_pipe_clk_mdm9650 = {
.bcr_reg = (uint32_t *) USB3_PIPE_BCR,
.cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
.has_sibling = 1,
.halt_check = 0,
.c = {
- .dbg_name = "usb30_pipe_clk_mdmcalifornium",
+ .dbg_name = "usb30_pipe_clk_mdm9650",
.ops = &clk_ops_branch,
},
};
@@ -608,7 +608,7 @@
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
CLK_LOOKUP("usb30_master_clk_sdxhedgehog", gcc_usb30_master_clk_sdxhedgehog.c),
CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
- CLK_LOOKUP("usb30_pipe_clk_mdmcalifornium", gcc_usb30_pipe_clk_mdmcalifornium.c),
+ CLK_LOOKUP("usb30_pipe_clk_mdm9650", gcc_usb30_pipe_clk_mdm9650.c),
CLK_LOOKUP("usb30_pipe_clk_sdxhedgehog", gcc_usb30_pipe_clk_sdxhedgehog.c),
CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c),
diff --git a/platform/mdm9640/platform.c b/platform/mdm9640/platform.c
index fd866a4..37a9aa2 100644
--- a/platform/mdm9640/platform.c
+++ b/platform/mdm9640/platform.c
@@ -156,17 +156,17 @@
}
-bool platform_is_mdmcalifornium()
+bool platform_is_mdm9650()
{
uint32_t platform_id = board_platform_id();
bool ret;
switch(platform_id)
{
- case MDMCALIFORNIUM1:
- case MDMCALIFORNIUM2:
- case MDMCALIFORNIUM3:
- case MDMCALIFORNIUM4:
+ case MDM9650:
+ case MDM9655:
+ case MDM9250:
+ case MDM9255:
ret = true;
break;
default:
@@ -198,7 +198,7 @@
{
uint32_t boot_config;
- if (platform_is_mdmcalifornium() || platform_is_sdxhedgehog())
+ if (platform_is_mdm9650() || platform_is_sdxhedgehog())
boot_config = BOOT_CONFIG_REG_V2;
/* Else the platform is 9x45 */
else if (board_soc_version() >= 0x20000)
@@ -215,3 +215,10 @@
readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
}
+bool platform_is_glink_enabled()
+{
+ if (platform_is_sdxhedgehog())
+ return 1;
+ else
+ return 0;
+}
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index bca7c54..2f0ca98 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -206,6 +206,7 @@
#define MDP_DMA_P_WATERMARK_2 REG_MDP(0x9009C)
#define MDP_PANIC_ROBUST_CTRL REG_MDP(0x900A0)
#define MDP_PANIC_LUT0 REG_MDP(0x900A4)
+#define MDP_PANIC_LUT1 REG_MDP(0x900A8)
#define MDP_ROBUST_LUT REG_MDP(0x900AC)
#define MDP_DSI_VIDEO_EN REG_MDP(0xF0000)
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index 5461b49..c9d558c 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015,2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -121,7 +121,7 @@
#define RST_N_FUNC_ENABLE BIT(0)
/* RPMB Related */
-#define RPMB_PART_MIN_SIZE (128 * 2014)
+#define RPMB_PART_MIN_SIZE (128 * 1024)
#define RPMB_SIZE_MULT 168
#define REL_WR_SEC_C 222
#define PARTITION_ACCESS_MASK 0x7
diff --git a/platform/msm_shared/include/qusb2_phy.h b/platform/msm_shared/include/qusb2_phy.h
index b8e8689..d446add 100644
--- a/platform/msm_shared/include/qusb2_phy.h
+++ b/platform/msm_shared/include/qusb2_phy.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -53,6 +53,7 @@
/* QUSB2 PHY SDXHEDGEHOG */
#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x4)
+#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO_SDXHEDGEHOG (QUSB2_PHY_BASE + 0xb4)
#define QUSB2PHY_PLL_CLOCK_INVERTERS_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x18c)
#define QUSB2PHY_PLL_CMODE_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x02c)
#define QUSB2PHY_PLL_LOCK_DELAY_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x90)
@@ -63,4 +64,6 @@
#define QUSB2PHY_DEBUG_CTRL2_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x278)
#define QUSB2PHY_DEBUG_STAT5_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x298)
+#define USB30_GENERAL_CFG_PIPE 0x08af8808
+
#endif
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index 5a8a848..1014b45 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2015, 2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -35,8 +35,48 @@
#include <platform/timer.h>
#include <platform/iomap.h>
+#define BIT(bit) (1 << (bit))
static int mdp_rev;
+/**
+ * mdp3_get_panic_lut_cfg() - calculate panic and robust lut mask
+ * @panel_width: Panel width
+ *
+ * DMA buffer has 16 fill levels. Which needs to configured as safe
+ * and panic levels based on panel resolutions.
+ * No. of fill levels used = ((panel active width * 8) / 512).
+ * Roundoff the use fill levels if needed.
+ * half of the total fill levels used will be treated as panic levels.
+ * Roundoff panic levels if total used fill levels are odd.
+ *
+ * Sample calculation for 720p display:
+ * Fill levels used = (720 * 8) / 512 = 12.5 after round off 13.
+ * panic levels = 13 / 2 = 6.5 after roundoff 7.
+ * Panic mask = 0x3FFF (2 bits per level)
+ * Robust mask = 0xFF80 (1 bit per level)
+ */
+unsigned long long mdp3_get_panic_lut_cfg(int panel_width)
+{
+ unsigned int fill_levels = (((panel_width * 8) / 512) + 1);
+ unsigned int panic_mask = 0;
+ unsigned int robust_mask = 0;
+ int i = 0;
+ unsigned long long panic_config = 0;
+ int panic_levels = 0;
+
+ panic_levels = fill_levels/2;
+ if (fill_levels % 2)
+ panic_levels++;
+ for (i = 0; i < panic_levels; i++) {
+ panic_mask |= (BIT((i * 2) + 1) | BIT(i * 2));
+ robust_mask |= BIT(i);
+ }
+ panic_config = (~robust_mask);
+ panic_config = panic_config << 32;
+ panic_config |= panic_mask;
+ return panic_config;
+}
+
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
@@ -46,6 +86,7 @@
struct lcdc_panel_info *lcdc = NULL;
int ystride = 3;
int mdp_rev = mdp_get_revision();
+ unsigned long long panic_config = mdp3_get_panic_lut_cfg(pinfo->xres);
if (pinfo == NULL)
return ERR_INVALID_ARGS;
@@ -71,16 +112,14 @@
writel(0x0, MDP_DMA_P_WATERMARK_0);
writel(0x0, MDP_DMA_P_WATERMARK_1);
writel(0x0, MDP_DMA_P_WATERMARK_2);
- if (pinfo->xres >= 720) {
- writel(0xFFFF, MDP_PANIC_LUT0);
- writel(0xFF00, MDP_ROBUST_LUT);
- } else {
- writel(0x00FF, MDP_PANIC_LUT0);
- writel(0xFFF0, MDP_ROBUST_LUT);
- }
- writel(0x1, MDP_PANIC_ROBUST_CTRL);
- writel(0xFF00, MDP_ROBUST_LUT);
+ writel((panic_config & 0xFFFF), MDP_PANIC_LUT0);
+ writel(((panic_config >> 16) & 0xFFFF) , MDP_PANIC_LUT1);
+ writel(((panic_config >> 32) & 0xFFFF), MDP_ROBUST_LUT);
+ writel(0x1, MDP_PANIC_ROBUST_CTRL);
+ dprintf(INFO, "Panic Lut0 %x Lut1 %x Robest %x\n",
+ (panic_config & 0xFFFF), ((panic_config >> 16) & 0xFFFF),
+ ((panic_config >> 32) & 0xFFFF));
// ------------- programming MDP_DMA_P_CONFIG ---------------------
writel(0x1800bf, MDP_DMA_P_CONFIG); // rgb888
@@ -124,18 +163,25 @@
int ret = 0;
unsigned short pack_pattern = 0x21;
unsigned char ystride = 3;
+ unsigned long long panic_config = 0;
+
+ if (pinfo == NULL)
+ return ERR_INVALID_ARGS;
/* Program QOS remapper settings */
writel(0x1A9, MDP_DMA_P_QOS_REMAPPER);
writel(0x0, MDP_DMA_P_WATERMARK_0);
writel(0x0, MDP_DMA_P_WATERMARK_1);
writel(0x0, MDP_DMA_P_WATERMARK_2);
- if (pinfo->xres >= 720)
- writel(0xFFFF, MDP_PANIC_LUT0);
- else
- writel(0x00FF, MDP_PANIC_LUT0);
+
+ panic_config = mdp3_get_panic_lut_cfg(pinfo->xres);
+ writel((panic_config & 0xFFFF), MDP_PANIC_LUT0);
+ writel(((panic_config >> 16) & 0xFFFF) , MDP_PANIC_LUT1);
+ writel(((panic_config >> 32) & 0xFFFF), MDP_ROBUST_LUT);
writel(0x1, MDP_PANIC_ROBUST_CTRL);
- writel(0xFF00, MDP_ROBUST_LUT);
+ dprintf(INFO, "Panic Lut0 %x Lut1 %x Robest %x\n",
+ (panic_config & 0xFFFF), ((panic_config >> 16) & 0xFFFF),
+ ((panic_config >> 32) & 0xFFFF));
writel(0x03ffffff, MDP_INTR_ENABLE);
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index e13e441..14aa425 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -49,7 +49,7 @@
return 0;
}
-__WEAK int platform_is_mdmcalifornium()
+__WEAK int platform_is_mdm9650()
{
return 0;
}
@@ -89,9 +89,19 @@
dmb();
/* set CLAMP_N_EN and stay with disabled USB PHY */
- writel(0x23, QUSB2PHY_PORT_POWERDOWN);
+ if(platform_is_sdxhedgehog())
+ writel(0x23, QUSB2PHY_PWR_CTRL1_SDXHEDGEHOG);
+ else
+ writel(0x23, QUSB2PHY_PORT_POWERDOWN);
- if (platform_is_msm8996() || platform_is_mdmcalifornium() || platform_is_msm8953())
+ /* TCSR register bit 0 indicates whether single ended clock
+ * or differential clock configuration is enabled. Based on the
+ * configuration set the PLL_TEST register.
+ */
+#if TCSR_PHY_CLK_SCHEME_SEL
+ se_clock = readl(TCSR_PHY_CLK_SCHEME_SEL) & 0x1;
+#endif
+ if (platform_is_msm8996() || platform_is_mdm9650() || platform_is_msm8953())
{
if(platform_is_msm8996sg())
writel(0xD0, QUSB2PHY_PORT_TUNE1);
@@ -123,10 +133,16 @@
}
else if (platform_is_sdxhedgehog())
{
- writel(0x13, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDXHEDGEHOG);
+ /* HPG init sequence 0x13 for CML and 0x03 for CMOS */
+ if (se_clock)
+ writel(0x03, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDXHEDGEHOG);
+ else
+ writel(0x13, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDXHEDGEHOG);
+
writel(0x7C, QUSB2PHY_PLL_CLOCK_INVERTERS_SDXHEDGEHOG);
writel(0x80, QUSB2PHY_PLL_CMODE_SDXHEDGEHOG);
writel(0x0a, QUSB2PHY_PLL_LOCK_DELAY_SDXHEDGEHOG);
+ writel(0x19, QUSB2PHY_PLL_DIGITAL_TIMERS_TWO_SDXHEDGEHOG);
writel(0xa5, QUSB2PHY_TUNE1_SDXHEDGEHOG);
writel(0x09, QUSB2PHY_TUNE2_SDXHEDGEHOG);
writel(0x00, QUSB2PHY_IMP_CTRL1_SDXHEDGEHOG);
@@ -161,19 +177,15 @@
writel(0x22, QUSB2PHY_PORT_POWERDOWN);
udelay(150);
}
- /* TCSR register bit 0 indicates whether single ended clock
- * or differential clock configuration is enabled. Based on the
- * configuration set the PLL_TEST register.
- */
-#if TCSR_PHY_CLK_SCHEME_SEL
- se_clock = readl(TCSR_PHY_CLK_SCHEME_SEL) & 0x1;
-#endif
+
/* By default consider differential clock configuration and if TCSR
* register bit 0 is not set then use single ended setting
*/
if (se_clock)
{
- writel(0x80, QUSB2PHY_PLL_TEST);
+ /* PLL TEST is not valid for sdxhedgehog */
+ if(!platform_is_sdxhedgehog())
+ writel(0x80, QUSB2PHY_PLL_TEST);
}
else
{
diff --git a/platform/msm_shared/rpm-ipc.c b/platform/msm_shared/rpm-ipc.c
index 2bd3c51..a8649db 100644
--- a/platform/msm_shared/rpm-ipc.c
+++ b/platform/msm_shared/rpm-ipc.c
@@ -30,11 +30,22 @@
#include <arch/defines.h>
#include <stdint.h>
#include <sys/types.h>
+#include <platform.h>
#include <rpm-ipc.h>
#include <rpm-glink.h>
#include <rpm-smd.h>
#include <string.h>
+__WEAK glink_err_type rpm_glink_send_data(uint32_t *data, uint32_t len, msg_type type)
+{
+ return GLINK_STATUS_API_NOT_SUPPORTED;
+}
+
+__WEAK int rpm_smd_send_data(uint32_t *data, uint32_t len, msg_type type)
+{
+ return -1;
+}
+
void fill_kvp_object(kvp_data **kdata, uint32_t *data, uint32_t len)
{
*kdata = (kvp_data *) memalign(CACHE_LINE, ROUNDUP(len, CACHE_LINE));
@@ -52,11 +63,13 @@
int rpm_send_data(uint32_t *data, uint32_t len, msg_type type)
{
int ret = 0;
-#ifdef GLINK_SUPPORT
- ret = rpm_glink_send_data(data, len, type);
-#else
- ret = rpm_smd_send_data(data, len, type);
-#endif
+
+ /* Runtime select to call glink or smd */
+ if (platform_is_glink_enabled())
+ ret = rpm_glink_send_data(data, len, type);
+ else
+ ret = rpm_smd_send_data(data, len, type);
+
return ret;
}
diff --git a/platform/msm_shared/rpmb/rpmb.c b/platform/msm_shared/rpmb/rpmb.c
index 984f580..41177ed 100644
--- a/platform/msm_shared/rpmb/rpmb.c
+++ b/platform/msm_shared/rpmb/rpmb.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015,2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -66,10 +66,16 @@
((mmc_dev->card.ext_csd[MMC_EXT_CSD_EN_RPMB_REL_WR] & BIT(4)) == 0))
{
dprintf(SPEW, "EMMC Version >= 5.1 EN_RPMB_REL_WR = 0\n");
- // according to emmc version 5.1 and above if EN_RPMB_REL_WR in extended
- // csd is not set the maximum number of frames that can be reliably written
- // to emmc would be 2
- info.rel_wr_count = 2;
+ /*
+ * Some eMMC vendors violate eMMC 5.0 spec and set
+ * REL_WR_SEC_C register to 0x10 to indicate the
+ * ability of RPMB throughput improvement thus lead
+ * to failure when TZ module write data to RPMB
+ * partition. So check bit[4] of EXT_CSD[166] and
+ * if it is not set then change value of REL_WR_SEC_C
+ * to 0x1 directly ignoring value of EXT_CSD[222].
+ */
+ info.rel_wr_count = 1;
}
else
{
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 7a9e688..e18a014 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -62,7 +62,6 @@
ifeq ($(ENABLE_GLINK_SUPPORT),1)
OBJS += \
- $(LOCAL_DIR)/rpm-ipc.o \
$(LOCAL_DIR)/glink/glink_api.o \
$(LOCAL_DIR)/glink/glink_core_if.o \
$(LOCAL_DIR)/glink/glink_core_internal.o \
@@ -76,6 +75,11 @@
$(LOCAL_DIR)/rpm-glink.o
endif
+ifneq ($(ENABLE_SMD_SUPPORT),1)
+OBJS += \
+ $(LOCAL_DIR)/rpm-ipc.o
+endif
+
ifeq ($(PLATFORM),msm8x60)
OBJS += $(LOCAL_DIR)/mipi_dsi.o \
$(LOCAL_DIR)/i2c_qup.o \
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index b544201..a0c3958 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -1094,6 +1094,13 @@
// Memory passed to TZ should be algined to cache line
BUF_DMA_ALIGN(rand_buf, sizeof(uintptr_t));
+ // r_len must be less than or equal to sizeof(rand_buf) to avoid memory corruption.
+ if (r_len > sizeof(rand_buf))
+ {
+ dprintf(CRITICAL, "r_len is larger than sizeof(randbuf).");
+ return -1;
+ }
+
if (!is_scm_armv8_support())
{
data.out_buf = (uint8_t*) rand_buf;
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index b34bfd5..3f6d460 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -812,9 +812,12 @@
/* Change the driver type & rerun tuning */
while(++drv_type <= MX_DRV_SUPPORTED_HS200)
{
+ /* Marking driver type changed if we try to change it */
+ if(!drv_type_changed)
+ drv_type_changed = true;
+
if (mmc_set_drv_type(host, card, drv_type))
goto retry_tuning;
- drv_type_changed = true;
}
}
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index fc2fc8f..9a46d1d 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -432,11 +432,11 @@
FSM9916 = 276,
APQ8076 = 277,
MSM8976 = 278,
- MDMCALIFORNIUM1 = 279,
- MDMCALIFORNIUM2 = 283,
- MDMCALIFORNIUM3 = 284,
- MDMCALIFORNIUM4 = 285,
- MDMCALIFORNIUM5 = 286,
+ MDM9650 = 279,
+ MDM9655 = 283,
+ MDM9250 = 284,
+ MDM9255 = 285,
+ MDM9350 = 286,
APQ8052 = 289,
MDM9607 = 290,
MDM8207 = 296,
@@ -460,7 +460,9 @@
APQ8096AU = 311,
APQ8096SG = 312,
SDXHEDGEHOG1 = 314,
- SDXHEDGEHOG2 = 333
+ SDXHEDGEHOG2 = 333,
+ MSM8909W = 300,
+ APQ8009W = 301
};
enum platform {
diff --git a/platform/msm_shared/usb30_udc.c b/platform/msm_shared/usb30_udc.c
index a2923f1..1e378bf 100644
--- a/platform/msm_shared/usb30_udc.c
+++ b/platform/msm_shared/usb30_udc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -230,10 +230,6 @@
/* section 4.4.2: Initialization and configuration sequences */
- /* 1. UTMI Mux configuration */
- if (dev_info->t_usb_if->mux_config)
- dev_info->t_usb_if->mux_config();
-
/* 2. Put controller in reset */
dwc_reset(dwc, 1);
@@ -243,6 +239,10 @@
/* 3. Reset PHY */
phy_reset(wrapper, dev_info);
+ /* 3.1 UTMI Mux configuration */
+ if (dev_info->t_usb_if->mux_config)
+ dev_info->t_usb_if->mux_config();
+
/* 4. SS phy config */
if (!use_hsonly_mode())
usb_wrapper_ss_phy_configure(wrapper);
diff --git a/project/mdm9640.mk b/project/mdm9640.mk
index d72ee16..997f92c 100644
--- a/project/mdm9640.mk
+++ b/project/mdm9640.mk
@@ -50,6 +50,11 @@
DEFINES += SMD_SUPPORT=1
endif
+ENABLE_GLINK_SUPPORT := 1
+ifeq ($(ENABLE_GLINK_SUPPORT),1)
+DEFINES += GLINK_SUPPORT=1
+endif
+
# Reset USB clock from target code
DEFINES += USB_RESET_FROM_CLK=1
diff --git a/project/msm8952.mk b/project/msm8952.mk
index b6f5dd6..b118e8f 100644
--- a/project/msm8952.mk
+++ b/project/msm8952.mk
@@ -103,6 +103,10 @@
DEFINES += WDOG_SUPPORT=1
endif
+ifeq ($(APPEND_CMDLINE),1)
+DEFINES += _APPEND_CMDLINE=1
+endif
+
#SCM call before entering DLOAD mode
DEFINES += PLATFORM_USE_SCM_DLOAD=1
diff --git a/target/mdm9640/init.c b/target/mdm9640/init.c
index b335731..6eabed2 100644
--- a/target/mdm9640/init.c
+++ b/target/mdm9640/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -56,6 +56,7 @@
#include <boot_device.h>
#include <qmp_phy.h>
#include <crypto5_wrapper.h>
+#include <rpm-glink.h>
extern void smem_ptable_init(void);
extern void smem_add_modem_partitions(struct ptable *flash_ptable);
@@ -151,7 +152,14 @@
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
if(!platform_is_sdxhedgehog())
+ {
rpm_smd_init();
+ }
+ else
+ {
+ /* Initialize Glink */
+ rpm_glink_init();
+ }
if (platform_boot_dev_isemmc()) {
target_sdc_init();
@@ -206,7 +214,7 @@
{
uint8_t reset_type = 0;
- if (platform_is_mdmcalifornium() || platform_is_sdxhedgehog())
+ if (platform_is_mdm9650() || platform_is_sdxhedgehog())
{
/* Clear the boot partition select cookie to indicate
* its a normal reset and avoid going to download mode */
@@ -221,9 +229,9 @@
else
reset_type = PON_PSHOLD_HARD_RESET;
- if (platform_is_mdmcalifornium() || platform_is_sdxhedgehog())
+ if (platform_is_mdm9650() || platform_is_sdxhedgehog())
{
- /* PMD9655 is the PMIC used for MDMcalifornium */
+ /* PMD9655 is the PMIC used for MDM9650 */
pm8x41_reset_configure(reset_type);
} else {
/* Configure PMIC for warm reset */
@@ -421,15 +429,49 @@
crypto_eng_cleanup();
if(!platform_is_sdxhedgehog())
+ {
rpm_smd_uninit();
+ }
+ else
+ {
+ /* Tear down glink channels */
+ rpm_glink_uninit();
+ }
+}
+void target_mux_configure(void)
+{
+ uint32_t val;
+ //USB30_GENERAL_CFG_PIPE_UTMI_CLK_DIS
+ val = readl(USB30_GENERAL_CFG_PIPE);
+ val = val | 0x100;
+ writel(val, USB30_GENERAL_CFG_PIPE);
+ udelay(100);
+
+ //USB30_GENERAL_CFG_PIPE_UTMI_CLK_SEL
+ val = readl(USB30_GENERAL_CFG_PIPE);
+ val = val | 0x1;
+ writel(val, USB30_GENERAL_CFG_PIPE);
+ udelay(100);
+
+ //USB30_GENERAL_CFG_PIPE3_PHYSTATUS_SW
+ val = readl(USB30_GENERAL_CFG_PIPE);
+ val = val | 0x8;
+ writel(val, USB30_GENERAL_CFG_PIPE);
+ udelay(100);
+
+ //USB30_GENERAL_CFG_PIPE_UTMI_CLK_ENABLE
+ val = readl(USB30_GENERAL_CFG_PIPE);
+ val = val & 0xfffffeff;
+ writel(val, USB30_GENERAL_CFG_PIPE);
+ udelay(100);
}
void target_usb_phy_reset(void)
{
- /* Reset sequence for californium is different from 9x40, use the reset sequence
+ /* Reset sequence for 9650 is different from 9x40, use the reset sequence
* from clock driver
*/
- if (platform_is_mdmcalifornium() || platform_is_sdxhedgehog())
+ if (platform_is_mdm9650() || platform_is_sdxhedgehog())
clock_reset_usb_phy(); // This is the reset function for USB3
else
usb30_qmp_phy_reset();
@@ -445,8 +487,10 @@
ASSERT(t_usb_iface);
t_usb_iface->mux_config = NULL;
- if (platform_is_sdxhedgehog())
+ if (platform_is_sdxhedgehog()){
+ t_usb_iface->mux_config = target_mux_configure;
t_usb_iface->phy_init = NULL;
+ }
else
t_usb_iface->phy_init = usb30_qmp_phy_init;
t_usb_iface->phy_reset = target_usb_phy_reset;
@@ -458,7 +502,7 @@
uint32_t target_override_pll()
{
- if (platform_is_mdmcalifornium() || platform_is_sdxhedgehog())
+ if (platform_is_mdm9650() || platform_is_sdxhedgehog())
return 0;
else
return 1;
@@ -469,7 +513,7 @@
return board_hlos_subtype();
}
-/* QMP settings are different from californium when compared to v2.0/v1.0 hardware.
+/* QMP settings are different from 9650 when compared to v2.0/v1.0 hardware.
* Use the QMP settings from target code to keep the common driver clean
*/
struct qmp_reg qmp_settings[] =
@@ -565,7 +609,7 @@
struct qmp_reg *target_get_qmp_settings()
{
- if (platform_is_mdmcalifornium() || platform_is_sdxhedgehog())
+ if (platform_is_mdm9650() || platform_is_sdxhedgehog())
return qmp_settings;
else
return NULL;
@@ -573,7 +617,7 @@
int target_get_qmp_regsize()
{
- if (platform_is_mdmcalifornium() || platform_is_sdxhedgehog())
+ if (platform_is_mdm9650() || platform_is_sdxhedgehog())
return ARRAY_SIZE(qmp_settings);
else
return 0;
diff --git a/target/mdm9640/keypad.c b/target/mdm9640/keypad.c
index a79d80f..a95375d 100644
--- a/target/mdm9640/keypad.c
+++ b/target/mdm9640/keypad.c
@@ -45,7 +45,7 @@
{
int ret;
- if (platform_is_mdmcalifornium() || platform_is_sdxhedgehog())
+ if (platform_is_mdm9650() || platform_is_sdxhedgehog())
ret = pm8x41_resin_status();
else
{
diff --git a/target/msm8909/target_display.c b/target/msm8909/target_display.c
index 803c5f2..c7664dd 100755
--- a/target/msm8909/target_display.c
+++ b/target/msm8909/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -334,9 +334,33 @@
return NO_ERROR;
}
+static bool target_splash_disable(void)
+{
+ uint32_t hw_id = board_hardware_id();
+ uint32_t platform_subtype = board_hardware_subtype();
+ uint32_t platform = board_platform_id();
+
+ if ((APQ8009 == platform) &&
+ (((HW_PLATFORM_MTP == hw_id) &&
+ (HW_PLATFORM_SUBTYPE_DSDA2 == platform_subtype)) ||
+ ((HW_PLATFORM_RCM == hw_id) &&
+ ((HW_PLATFORM_SUBTYPE_SNAP == platform_subtype)||
+ (HW_PLATFORM_SUBTYPE_SNAP_NOPMI == platform_subtype))))) {
+ dprintf(INFO, "Splash disabled\n");
+ return true;
+ } else {
+ return false;
+ }
+}
+
bool target_display_panel_node(char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(pbuf, buf_size);
+ int ret = true;
+
+ if (!target_splash_disable())
+ ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+
+ return ret;
}
void target_display_init(const char *panel_name)
@@ -357,6 +381,9 @@
return;
}
+ if (target_splash_disable())
+ return;
+
do {
target_force_cont_splash_disable(false);
ret = gcdb_display_init(oem.panel, MDP_REV_305, MIPI_FB_ADDR);
diff --git a/target/msm8952/init.c b/target/msm8952/init.c
index 112a3c8..6dd3a75 100644
--- a/target/msm8952/init.c
+++ b/target/msm8952/init.c
@@ -84,6 +84,8 @@
#define RECOVERY_MODE 0x77665502
#define PON_SOFT_RB_SPARE 0x88F
+#define EXT4_CMDLINE " rootfstype=ext4 root=/dev/mmcblk0p"
+
#define CE1_INSTANCE 1
#define CE_EE 1
#define CE_FIFO_SIZE 64
@@ -765,6 +767,44 @@
return 1;
}
+#if _APPEND_CMDLINE
+int get_target_boot_params(const char *cmdline, const char *part, char **buf)
+{
+ int system_ptn_index = -1;
+ uint32_t buflen;
+ int ret = -1;
+
+ if (!cmdline || !part ) {
+ dprintf(CRITICAL, "WARN: Invalid input param\n");
+ return -1;
+ }
+
+ if (!strstr(cmdline, "root=/dev/ram")) /* This check is to handle kdev boot */
+ {
+ if (target_is_emmc_boot()) {
+ buflen = strlen(EXT4_CMDLINE) + sizeof(int) +1;
+ *buf = (char *)malloc(buflen);
+ if(!(*buf)) {
+ dprintf(CRITICAL,"Unable to allocate memory for boot params\n");
+ return -1;
+ }
+ /* Below is for emmc boot */
+ system_ptn_index = partition_get_index(part) + 1; /* Adding +1 as offsets for eMMC start at 1 and NAND at 0 */
+ if (system_ptn_index < 0) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get partition index for %s\n", part);
+ free(*buf);
+ return -1;
+ }
+ snprintf(*buf, buflen, EXT4_CMDLINE"%d", system_ptn_index);
+ ret = 0;
+ }
+ }
+ /*in success case buf will be freed in the calling function of this*/
+ return ret;
+}
+#endif
+
uint32_t target_get_pmic()
{
return PMIC_IS_PMI8950;
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index bcbf1be..ee001bc 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -51,6 +51,13 @@
#include "include/display_resource.h"
#include "gcdb_display.h"
+#define TRULY_720P_VID_PANEL "truly_720p_video"
+#define TRULY_720P_CMD_PANEL "truly_720p_cmd"
+
+#define HDMI_ADV_PANEL_STRING "1:dsi:0:qcom,mdss_dsi_adv7533_1080p:1:none:cfg:single_dsi"
+#define TRULY_VID_PANEL_STRING "1:dsi:0:qcom,mdss_dsi_truly_720p_video:1:none:cfg:single_dsi"
+#define TRULY_CMD_PANEL_STRING "1:dsi:0:qcom,mdss_dsi_truly_720p_cmd:1:none:cfg:single_dsi"
+
/*---------------------------------------------------------------------------*/
/* GPIO configuration */
/*---------------------------------------------------------------------------*/
@@ -569,7 +576,55 @@
bool target_display_panel_node(char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(pbuf, buf_size);
+ int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
+ bool ret = true;
+ struct oem_panel_data oem = mdss_dsi_get_oem_data();
+ uint32_t platform_subtype = board_hardware_subtype();
+
+ /* default to hdmi for apq iot */
+ if ((HW_PLATFORM_SUBTYPE_SNAP == platform_subtype) ||
+ (HW_PLATFORM_SUBTYPE_SNAP_NOPMI == platform_subtype)) {
+ if (!strcmp(oem.panel, "")) {
+ if (buf_size < (prefix_string_len +
+ strlen(HDMI_ADV_PANEL_STRING))) {
+ dprintf(CRITICAL, "HDMI command line argument \
+ is greater than buffer size\n");
+ return false;
+ }
+ strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+ buf_size -= prefix_string_len;
+ pbuf += prefix_string_len;
+ strlcpy(pbuf, HDMI_ADV_PANEL_STRING, buf_size);
+ } else if (!strcmp(oem.panel, TRULY_720P_VID_PANEL)) {
+ if (buf_size < (prefix_string_len +
+ strlen(TRULY_VID_PANEL_STRING))) {
+ dprintf(CRITICAL, "TRULY VIDEO command line \
+ argument is greater than \
+ buffer size\n");
+ return false;
+ }
+ strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+ buf_size -= prefix_string_len;
+ pbuf += prefix_string_len;
+ strlcpy(pbuf, TRULY_VID_PANEL_STRING, buf_size);
+ } else if (!strcmp(oem.panel, TRULY_720P_CMD_PANEL)) {
+ if (buf_size < (prefix_string_len +
+ strlen(TRULY_CMD_PANEL_STRING))) {
+ dprintf(CRITICAL, "TRULY CMD command line argument \
+ argument is greater than \
+ buffer size\n");
+ return false;
+ }
+ strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+ buf_size -= prefix_string_len;
+ pbuf += prefix_string_len;
+ strlcpy(pbuf, TRULY_CMD_PANEL_STRING, buf_size);
+ }
+ } else {
+ ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+ }
+
+ return ret;
}
void target_display_init(const char *panel_name)
@@ -577,6 +632,7 @@
struct oem_panel_data oem;
int32_t ret = 0;
uint32_t panel_loop = 0;
+ uint32_t platform_subtype = board_hardware_subtype();
set_panel_cmd_string(panel_name);
oem = mdss_dsi_get_oem_data();
@@ -590,6 +646,13 @@
return;
}
+ if ((HW_PLATFORM_SUBTYPE_SNAP == platform_subtype) ||
+ (HW_PLATFORM_SUBTYPE_SNAP_NOPMI == platform_subtype)) {
+ dprintf(INFO, "%s: Platform subtype %d\n",
+ __func__, platform_subtype);
+ return;
+ }
+
do {
target_force_cont_splash_disable(false);
ret = gcdb_display_init(oem.panel, MDP_REV_50, (void *)MIPI_FB_ADDR);