Merge "platform: msm_shared: update MDP5 driver for msm8996"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 6ee8802..ca48092 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -645,7 +645,7 @@
#if VERIFIED_BOOT
/* Write protect the device info */
- if (target_build_variant_user() && devinfo_present && mmc_write_protect("devinfo", 1))
+ if (!boot_into_recovery && target_build_variant_user() && devinfo_present && mmc_write_protect("devinfo", 1))
{
dprintf(INFO, "Failed to write protect dev info\n");
ASSERT(0);
diff --git a/lib/openssl/crypto/md32_common.h b/lib/openssl/crypto/md32_common.h
index 1cb7839..40f5055 100644
--- a/lib/openssl/crypto/md32_common.h
+++ b/lib/openssl/crypto/md32_common.h
@@ -225,15 +225,13 @@
#define HOST_c2l(c,l) (l =(((unsigned long)(*((c)++)))<<24), \
l|=(((unsigned long)(*((c)++)))<<16), \
l|=(((unsigned long)(*((c)++)))<< 8), \
- l|=(((unsigned long)(*((c)++))) ), \
- l)
+ l|=(((unsigned long)(*((c)++))) ))
#endif
#ifndef HOST_l2c
#define HOST_l2c(l,c) (*((c)++)=(unsigned char)(((l)>>24)&0xff), \
*((c)++)=(unsigned char)(((l)>>16)&0xff), \
*((c)++)=(unsigned char)(((l)>> 8)&0xff), \
- *((c)++)=(unsigned char)(((l) )&0xff), \
- l)
+ *((c)++)=(unsigned char)(((l) )&0xff))
#endif
#elif defined(DATA_ORDER_IS_LITTLE_ENDIAN)
@@ -262,15 +260,13 @@
#define HOST_c2l(c,l) (l =(((unsigned long)(*((c)++))) ), \
l|=(((unsigned long)(*((c)++)))<< 8), \
l|=(((unsigned long)(*((c)++)))<<16), \
- l|=(((unsigned long)(*((c)++)))<<24), \
- l)
+ l|=(((unsigned long)(*((c)++)))<<24))
#endif
#ifndef HOST_l2c
#define HOST_l2c(l,c) (*((c)++)=(unsigned char)(((l) )&0xff), \
*((c)++)=(unsigned char)(((l)>> 8)&0xff), \
*((c)++)=(unsigned char)(((l)>>16)&0xff), \
- *((c)++)=(unsigned char)(((l)>>24)&0xff), \
- l)
+ *((c)++)=(unsigned char)(((l)>>24)&0xff))
#endif
#endif
diff --git a/platform/msm8909/acpuclock.c b/platform/msm8909/acpuclock.c
index b8e0df4..ed2cbfc 100644
--- a/platform/msm8909/acpuclock.c
+++ b/platform/msm8909/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -37,6 +37,8 @@
#include <platform/clock.h>
#include <blsp_qup.h>
+#define MAX_LOOPS 500
+
void hsusb_clock_init(void)
{
int ret;
@@ -358,6 +360,34 @@
}
}
+static void rcg_update_config(uint32_t reg)
+{
+ int i;
+
+ for (i = 0; i < MAX_LOOPS; i++) {
+ if (!(readl(reg) & BIT(0)))
+ return;
+ udelay(1);
+ }
+
+ dprintf(CRITICAL, "failed to update rcg config for reg = 0x%x\n", reg);
+ ASSERT(0);
+}
+
+static void branch_clk_halt_check(uint32_t reg)
+{
+ int i;
+
+ for (i = 0; i < MAX_LOOPS; i++) {
+ if (!(readl(reg) & BIT(31)))
+ return;
+ udelay(1);
+ }
+
+ dprintf(CRITICAL, "failed to enable branch for reg = 0x%x\n", reg);
+ ASSERT(0);
+}
+
/* Disable all the branch clocks needed by the DSI controller */
void gcc_dsi_clocks_disable(void)
{
@@ -371,20 +401,32 @@
{
int ret;
- /* Configure Byte clock -autopll- This will not change becasue
- byte clock does not need any divider*/
+ /*
+ * Configure Byte clock -autopll- This will not change becasue
+ * byte clock does not need any divider
+ */
+ /* Set the source for DSI0 byte RCG */
writel(0x100, DSI_BYTE0_CFG_RCGR);
+ /* Set the update RCG bit */
writel(0x1, DSI_BYTE0_CMD_RCGR);
+ rcg_update_config(DSI_BYTE0_CMD_RCGR);
+ /* Enable the branch clock */
writel(0x1, DSI_BYTE0_CBCR);
+ branch_clk_halt_check(DSI_BYTE0_CBCR);
/* Configure Pixel clock */
+ /* Set the source for DSI0 pixel RCG */
writel(0x100, DSI_PIXEL0_CFG_RCGR);
- writel(0x1, DSI_PIXEL0_CMD_RCGR);
- writel(0x1, DSI_PIXEL0_CBCR);
-
+ /* Set the MND for DSI0 pixel clock */
writel(pclk0_m, DSI_PIXEL0_M);
writel(pclk0_n, DSI_PIXEL0_N);
writel(pclk0_d, DSI_PIXEL0_D);
+ /* Set the update RCG bit */
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ rcg_update_config(DSI_PIXEL0_CMD_RCGR);
+ /* Enable the branch clock */
+ writel(0x1, DSI_PIXEL0_CBCR);
+ branch_clk_halt_check(DSI_PIXEL0_CBCR);
/* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
diff --git a/platform/msm8916/acpuclock.c b/platform/msm8916/acpuclock.c
index fd365be..158ab39 100644
--- a/platform/msm8916/acpuclock.c
+++ b/platform/msm8916/acpuclock.c
@@ -38,6 +38,8 @@
#include <blsp_qup.h>
#include <platform.h>
+#define MAX_LOOPS 500
+
void hsusb_clock_init(void)
{
int ret;
@@ -262,6 +264,34 @@
}
}
+static void rcg_update_config(uint32_t reg)
+{
+ int i;
+
+ for (i = 0; i < MAX_LOOPS; i++) {
+ if (!(readl(reg) & BIT(0)))
+ return;
+ udelay(1);
+ }
+
+ dprintf(CRITICAL, "failed to update rcg config for reg = 0x%x\n", reg);
+ ASSERT(0);
+}
+
+static void branch_clk_halt_check(uint32_t reg)
+{
+ int i;
+
+ for (i = 0; i < MAX_LOOPS; i++) {
+ if (!(readl(reg) & BIT(31)))
+ return;
+ udelay(1);
+ }
+
+ dprintf(CRITICAL, "failed to enable branch for reg = 0x%x\n", reg);
+ ASSERT(0);
+}
+
/* Disable all the branch clocks needed by the DSI controller */
void gcc_dsi_clocks_disable(uint8_t dual_dsi)
{
@@ -280,20 +310,32 @@
{
int ret;
- /* Configure Byte clock -autopll- This will not change becasue
- byte clock does not need any divider*/
+ /*
+ * Configure Byte clock -autopll- This will not change becasue
+ * byte clock does not need any divider
+ */
+ /* Set the source for DSI0 byte RCG */
writel(0x100, DSI_BYTE0_CFG_RCGR);
+ /* Set the update RCG bit */
writel(0x1, DSI_BYTE0_CMD_RCGR);
+ rcg_update_config(DSI_BYTE0_CMD_RCGR);
+ /* Enable the branch clock */
writel(0x1, DSI_BYTE0_CBCR);
+ branch_clk_halt_check(DSI_BYTE0_CBCR);
/* Configure Pixel clock */
+ /* Set the source for DSI0 pixel RCG */
writel(0x100, DSI_PIXEL0_CFG_RCGR);
- writel(0x1, DSI_PIXEL0_CMD_RCGR);
- writel(0x1, DSI_PIXEL0_CBCR);
-
+ /* Set the MND for DSI0 pixel clock */
writel(pclk0_m, DSI_PIXEL0_M);
writel(pclk0_n, DSI_PIXEL0_N);
writel(pclk0_d, DSI_PIXEL0_D);
+ /* Set the update RCG bit */
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ rcg_update_config(DSI_PIXEL0_CMD_RCGR);
+ /* Enable the branch clock */
+ writel(0x1, DSI_PIXEL0_CBCR);
+ branch_clk_halt_check(DSI_PIXEL0_CBCR);
/* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
@@ -303,20 +345,27 @@
}
if (dual_dsi) {
- /* Configure Byte clock -autopll- This will not change becasue
- byte clock does not need any divider*/
+ /* Set the source for DSI1 byte RCG */
writel(0x100, DSI_BYTE1_CFG_RCGR);
+ /* Set the update RCG bit */
writel(0x1, DSI_BYTE1_CMD_RCGR);
+ rcg_update_config(DSI_BYTE1_CMD_RCGR);
+ /* Enable the branch clock */
writel(0x1, DSI_BYTE1_CBCR);
+ branch_clk_halt_check(DSI_BYTE1_CBCR);
- /* Configure Pixel clock */
+ /* Set the source for DSI1 pixel RCG */
writel(0x100, DSI_PIXEL1_CFG_RCGR);
- writel(0x1, DSI_PIXEL1_CMD_RCGR);
- writel(0x1, DSI_PIXEL1_CBCR);
-
+ /* Set the MND for DSI1 pixel clock */
writel(pclk0_m, DSI_PIXEL1_M);
writel(pclk0_n, DSI_PIXEL1_N);
writel(pclk0_d, DSI_PIXEL1_D);
+ /* Set the update RCG bit */
+ writel(0x1, DSI_PIXEL1_CMD_RCGR);
+ rcg_update_config(DSI_PIXEL1_CMD_RCGR);
+ /* Enable the branch clock */
+ writel(0x1, DSI_PIXEL1_CBCR);
+ branch_clk_halt_check(DSI_PIXEL1_CBCR);
/* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
diff --git a/platform/msm8952/acpuclock.c b/platform/msm8952/acpuclock.c
index bdd1d6d..87e31dd 100644
--- a/platform/msm8952/acpuclock.c
+++ b/platform/msm8952/acpuclock.c
@@ -36,6 +36,8 @@
#include <platform/clock.h>
#include <platform.h>
+#define MAX_LOOPS 500
+
void hsusb_clock_init(void)
{
int ret;
@@ -265,6 +267,34 @@
}
}
+static void rcg_update_config(uint32_t reg)
+{
+ int i;
+
+ for (i = 0; i < MAX_LOOPS; i++) {
+ if (!(readl(reg) & BIT(0)))
+ return;
+ udelay(1);
+ }
+
+ dprintf(CRITICAL, "failed to update rcg config for reg = 0x%x\n", reg);
+ ASSERT(0);
+}
+
+static void branch_clk_halt_check(uint32_t reg)
+{
+ int i;
+
+ for (i = 0; i < MAX_LOOPS; i++) {
+ if (!(readl(reg) & BIT(31)))
+ return;
+ udelay(1);
+ }
+
+ dprintf(CRITICAL, "failed to enable branch for reg = 0x%x\n", reg);
+ ASSERT(0);
+}
+
/* Disable all the branch clocks needed by the DSI controller */
void gcc_dsi_clocks_disable(void)
{
@@ -278,20 +308,32 @@
{
int ret;
- /* Configure Byte clock -autopll- This will not change becasue
- byte clock does not need any divider*/
+ /*
+ * Configure Byte clock -autopll- This will not change becasue
+ * byte clock does not need any divider
+ */
+ /* Set the source for DSI0 byte RCG */
writel(0x100, DSI_BYTE0_CFG_RCGR);
+ /* Set the update RCG bit */
writel(0x1, DSI_BYTE0_CMD_RCGR);
+ rcg_update_config(DSI_BYTE0_CMD_RCGR);
+ /* Enable the branch clock */
writel(0x1, DSI_BYTE0_CBCR);
+ branch_clk_halt_check(DSI_BYTE0_CBCR);
/* Configure Pixel clock */
+ /* Set the source for DSI0 pixel RCG */
writel(0x100, DSI_PIXEL0_CFG_RCGR);
- writel(0x1, DSI_PIXEL0_CMD_RCGR);
- writel(0x1, DSI_PIXEL0_CBCR);
-
+ /* Set the MND for DSI0 pixel clock */
writel(pclk0_m, DSI_PIXEL0_M);
writel(pclk0_n, DSI_PIXEL0_N);
writel(pclk0_d, DSI_PIXEL0_D);
+ /* Set the update RCG bit */
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ rcg_update_config(DSI_PIXEL0_CMD_RCGR);
+ /* Enable the branch clock */
+ writel(0x1, DSI_PIXEL0_CBCR);
+ branch_clk_halt_check(DSI_PIXEL0_CBCR);
/* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index 6f4e0f0..533cf47 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -43,6 +43,8 @@
#define CE2_CLK_ID 0x1
#define RPM_SMD_KEY_RATE 0x007A484B
+#define MAX_LOOPS 500
+
uint32_t CE2_CLK[][8]=
{
{
@@ -455,6 +457,34 @@
clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
}
+static void rcg_update_config(uint32_t reg)
+{
+ int i;
+
+ for (i = 0; i < MAX_LOOPS; i++) {
+ if (!(readl(reg) & BIT(0)))
+ return;
+ udelay(1);
+ }
+
+ dprintf(CRITICAL, "failed to update rcg config for reg = 0x%x\n", reg);
+ ASSERT(0);
+}
+
+static void branch_clk_halt_check(uint32_t reg)
+{
+ int i;
+
+ for (i = 0; i < MAX_LOOPS; i++) {
+ if (!(readl(reg) & BIT(31)))
+ return;
+ udelay(1);
+ }
+
+ dprintf(CRITICAL, "failed to enable branch for reg = 0x%x\n", reg);
+ ASSERT(0);
+}
+
void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t flags,
uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
{
@@ -462,17 +492,28 @@
if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
/* Enable DSI0 branch clocks */
+
+ /* Set the source for DSI0 byte RCG */
writel(cfg_rcgr, DSI_BYTE0_CFG_RCGR);
+ /* Set the update RCG bit */
writel(0x1, DSI_BYTE0_CMD_RCGR);
+ rcg_update_config(DSI_BYTE0_CMD_RCGR);
+ /* Enable the branch clock */
writel(0x1, DSI_BYTE0_CBCR);
+ branch_clk_halt_check(DSI_BYTE0_CBCR);
+ /* Set the source for DSI0 pixel RCG */
writel(cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
- writel(0x1, DSI_PIXEL0_CMD_RCGR);
- writel(0x1, DSI_PIXEL0_CBCR);
-
+ /* Set the MND for DSI0 pixel clock */
writel(pclk0_m, DSI_PIXEL0_M);
writel(pclk0_n, DSI_PIXEL0_N);
writel(pclk0_d, DSI_PIXEL0_D);
+ /* Set the update RCG bit */
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ rcg_update_config(DSI_PIXEL0_CMD_RCGR);
+ /* Enable the branch clock */
+ writel(0x1, DSI_PIXEL0_CBCR);
+ branch_clk_halt_check(DSI_PIXEL0_CBCR);
ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
if(ret)
@@ -484,17 +525,28 @@
if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
/* Enable DSI1 branch clocks */
+
+ /* Set the source for DSI1 byte RCG */
writel(cfg_rcgr, DSI_BYTE1_CFG_RCGR);
+ /* Set the update RCG bit */
writel(0x1, DSI_BYTE1_CMD_RCGR);
+ rcg_update_config(DSI_BYTE1_CMD_RCGR);
+ /* Enable the branch clock */
writel(0x1, DSI_BYTE1_CBCR);
+ branch_clk_halt_check(DSI_BYTE1_CBCR);
+ /* Set the source for DSI1 pixel RCG */
writel(cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
- writel(0x1, DSI_PIXEL1_CMD_RCGR);
- writel(0x1, DSI_PIXEL1_CBCR);
-
+ /* Set the MND for DSI1 pixel clock */
writel(pclk0_m, DSI_PIXEL1_M);
writel(pclk0_n, DSI_PIXEL1_N);
writel(pclk0_d, DSI_PIXEL1_D);
+ /* Set the update RCG bit */
+ writel(0x1, DSI_PIXEL1_CMD_RCGR);
+ rcg_update_config(DSI_PIXEL1_CMD_RCGR);
+ /* Enable the branch clock */
+ writel(0x1, DSI_PIXEL1_CBCR);
+ branch_clk_halt_check(DSI_PIXEL1_CBCR);
ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
if(ret)