Merge "platform: msm_shared: Add support for SBC platform type"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 9e4c905..6058aa2 100755
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -72,6 +72,8 @@
extern bool target_use_signed_kernel(void);
extern void platform_uninit(void);
extern void target_uninit(void);
+extern int get_target_boot_params(const char *cmdline, const char *part,
+ char *buf, int buflen);
void write_device_info_mmc(device_info *dev);
void write_device_info_flash(device_info *dev);
@@ -120,6 +122,7 @@
static const char *baseband_csfb = " androidboot.baseband=csfb";
static const char *baseband_svlte2a = " androidboot.baseband=svlte2a";
static const char *baseband_mdm = " androidboot.baseband=mdm";
+static const char *baseband_mdm2 = " androidboot.baseband=mdm2";
static const char *baseband_sglte = " androidboot.baseband=sglte";
static const char *baseband_dsda = " androidboot.baseband=dsda";
static const char *baseband_dsda2 = " androidboot.baseband=dsda2";
@@ -129,6 +132,7 @@
static unsigned page_mask = 0;
static char ffbm_mode_string[FFBM_MODE_BUF_SIZE];
static bool boot_into_ffbm;
+static char target_boot_params[64];
/* Assuming unauthorized kernel image by default */
static int auth_kernel_img = 0;
@@ -235,6 +239,7 @@
#endif
int pause_at_bootup = 0;
bool gpt_exists = partition_gpt_exists();
+ int have_target_boot_params = 0;
if (cmdline && cmdline[0]) {
cmdline_len = strlen(cmdline);
@@ -270,6 +275,14 @@
cmdline_len += strlen(auth_kernel);
}
+ if (get_target_boot_params(cmdline, boot_into_recovery ? "recoveryfs" :
+ "system",
+ target_boot_params,
+ sizeof(target_boot_params)) == 0) {
+ have_target_boot_params = 1;
+ cmdline_len += strlen(target_boot_params);
+ }
+
/* Determine correct androidboot.baseband to use */
switch(target_baseband())
{
@@ -293,6 +306,10 @@
cmdline_len += strlen(baseband_mdm);
break;
+ case BASEBAND_MDM2:
+ cmdline_len += strlen(baseband_mdm2);
+ break;
+
case BASEBAND_SGLTE:
cmdline_len += strlen(baseband_sglte);
break;
@@ -408,6 +425,12 @@
while ((*dst++ = *src++));
break;
+ case BASEBAND_MDM2:
+ src = baseband_mdm2;
+ if (have_cmdline) --dst;
+ while ((*dst++ = *src++));
+ break;
+
case BASEBAND_SGLTE:
src = baseband_sglte;
if (have_cmdline) --dst;
@@ -441,6 +464,12 @@
if (have_cmdline) --dst;
while ((*dst++ = *src++));
}
+
+ if (have_target_boot_params) {
+ if (have_cmdline) --dst;
+ src = target_boot_params;
+ while ((*dst++ = *src++));
+ }
}
@@ -614,6 +643,11 @@
static void verify_signed_bootimg(uint32_t bootimg_addr, uint32_t bootimg_size)
{
int ret;
+#if IMAGE_VERIF_ALGO_SHA1
+ uint32_t auth_algo = CRYPTO_AUTH_ALG_SHA1;
+#else
+ uint32_t auth_algo = CRYPTO_AUTH_ALG_SHA256;
+#endif
/* Assume device is rooted at this time. */
device.is_tampered = 1;
@@ -623,7 +657,7 @@
ret = image_verify((unsigned char *)bootimg_addr,
(unsigned char *)(bootimg_addr + bootimg_size),
bootimg_size,
- CRYPTO_AUTH_ALG_SHA256);
+ auth_algo);
dprintf(INFO, "Authenticating boot image: done return value = %d\n", ret);
@@ -1507,7 +1541,7 @@
check_aboot_addr_range_overlap(hdr->ramdisk_addr, ramdisk_actual))
{
dprintf(CRITICAL, "kernel/ramdisk addresses overlap with aboot addresses.\n");
- return -1;
+ return;
}
/* sz should have atleast raw boot image */
@@ -1525,7 +1559,7 @@
if (check_aboot_addr_range_overlap(hdr->tags_addr, MAX_TAGS_SIZE))
{
dprintf(CRITICAL, "Tags addresses overlap with aboot addresses.\n");
- return -1;
+ return;
}
#endif
@@ -1555,7 +1589,7 @@
if (check_aboot_addr_range_overlap(hdr->tags_addr, MAX_TAGS_SIZE))
{
dprintf(CRITICAL, "Tags addresses overlap with aboot addresses.\n");
- return -1;
+ return;
}
#endif
diff --git a/app/aboot/fastboot.c b/app/aboot/fastboot.c
index fd0b9eb..f8b7262 100644
--- a/app/aboot/fastboot.c
+++ b/app/aboot/fastboot.c
@@ -455,10 +455,11 @@
buffer[r] = 0;
dprintf(INFO,"fastboot: %s\n", buffer);
+ fastboot_state = STATE_COMMAND;
+
for (cmd = cmdlist; cmd; cmd = cmd->next) {
if (memcmp(buffer, cmd->prefix, cmd->prefix_len))
continue;
- fastboot_state = STATE_COMMAND;
cmd->handle((const char*) buffer + cmd->prefix_len,
(void*) download_base, download_size);
if (fastboot_state == STATE_COMMAND)
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 0f2abb1..9c36a3c 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -137,26 +137,22 @@
return ret;
}
-static int mdss_dsi_panel_post_power(uint8_t enable)
+static int mdss_dsi_panel_pre_init(void)
{
int ret = NO_ERROR;
- if (enable) {
- /* Panel Reset */
- if (panelstruct.paneldata->panel_lp11_init) {
- ret = mdss_dsi_panel_reset(enable);
- if (ret) {
- dprintf(CRITICAL, "panel reset failed\n");
- return ret;
- }
+ if (panelstruct.paneldata->panel_lp11_init) {
+ ret = mdss_dsi_panel_reset(1);
+ if (ret) {
+ dprintf(CRITICAL, "panel reset failed\n");
+ return ret;
}
-
- if(panelstruct.paneldata->panel_init_delay)
- udelay(panelstruct.paneldata->panel_init_delay);
-
- dprintf(SPEW, "Panel post power on done\n");
}
+ if(panelstruct.paneldata->panel_init_delay)
+ udelay(panelstruct.paneldata->panel_init_delay);
+
+ dprintf(SPEW, "Panel pre init done\n");
return ret;
}
@@ -261,7 +257,7 @@
panel.pll_clk_func = mdss_dsi_panel_clock;
panel.power_func = mdss_dsi_panel_power;
- panel.post_power_func = mdss_dsi_panel_post_power;
+ panel.pre_init_func = mdss_dsi_panel_pre_init;
panel.bl_func = mdss_dsi_bl_enable;
panel.fb.base = base;
panel.fb.width = panel.panel_info.xres;
diff --git a/dev/gcdb/display/include/panel_hx8389b_qhd_video.h b/dev/gcdb/display/include/panel_hx8389b_qhd_video.h
old mode 100644
new mode 100755
index b172fdb..577918d
--- a/dev/gcdb/display/include/panel_hx8389b_qhd_video.h
+++ b/dev/gcdb/display/include/panel_hx8389b_qhd_video.h
@@ -34,7 +34,6 @@
*---------------------------------------------------------------------------*/
#ifndef _PANEL_HX8389B_QHD_VIDEO_H_
-
#define _PANEL_HX8389B_QHD_VIDEO_H_
/*---------------------------------------------------------------------------*/
/* HEADER files */
@@ -44,240 +43,244 @@
/*---------------------------------------------------------------------------*/
/* Panel configuration */
/*---------------------------------------------------------------------------*/
-
static struct panel_config hx8389b_qhd_video_panel_data = {
- "qcom,mdss_dsi_hx8389b_qhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ "qcom,mdss_dsi_hx8389b_qhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
/* Panel resolution */
/*---------------------------------------------------------------------------*/
static struct panel_resolution hx8389b_qhd_video_panel_res = {
- 540, 960, 48, 96, 96, 0, 9, 13, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 540, 960, 60, 39, 39, 0, 9, 13, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
-/* Panel Color Information */
+/* Panel color information */
/*---------------------------------------------------------------------------*/
static struct color_info hx8389b_qhd_video_color = {
- 24, 0, 0xff, 0, 0, 0
+ 24, 0, 0xff, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
-/* Panel Command information */
+/* Panel on/off command information */
/*---------------------------------------------------------------------------*/
static char hx8389b_qhd_video_on_cmd0[] = {
-0x04, 0x00, 0x39, 0xC0,
-0xB9, 0xFF, 0x83, 0x89,
- };
-
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB9, 0xFF, 0x83, 0x89,
+};
static char hx8389b_qhd_video_on_cmd1[] = {
-0x08, 0x00, 0x39, 0xC0,
-0xBA, 0x41, 0x93, 0x00,
-0x16, 0xA4, 0x10, 0x18,
- };
-
+ 0xCC, 0x02, 0x15, 0x80
+};
static char hx8389b_qhd_video_on_cmd2[] = {
-0xC6, 0x08, 0x23, 0x80 };
-
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xC0, 0x43, 0x17, 0xFF,
+};
static char hx8389b_qhd_video_on_cmd3[] = {
-0x03, 0x00, 0x39, 0xC0,
-0xBC, 0x02, 0x00, 0xFF, };
-
+ 0x08, 0x00, 0x39, 0xC0,
+ 0xBA, 0x41, 0x93, 0x00,
+ 0x16, 0xA4, 0x10, 0x18,
+};
static char hx8389b_qhd_video_on_cmd4[] = {
-0xCC, 0x02, 0x23, 0x80 };
-
+ 0x14, 0x00, 0x39, 0xC0,
+ 0xB1, 0x00, 0x00, 0x06,
+ 0xEB, 0x59, 0x10, 0x11,
+ 0xEE, 0xEE, 0x3A, 0x42,
+ 0x3F, 0x3F, 0x43, 0x01,
+ 0x5A, 0xF6, 0x00, 0xE6,
+};
static char hx8389b_qhd_video_on_cmd5[] = {
-0x14, 0x00, 0x39, 0xC0,
-0xB1, 0x00, 0x00, 0x07,
-0xE8, 0x50, 0x10, 0x11,
-0x98, 0xf8, 0x21, 0x29,
-0x27, 0x27, 0x43, 0x01,
-0x58, 0xF0, 0x00, 0xE6,
- };
-
+ 0x08, 0x00, 0x39, 0xC0,
+ 0xB2, 0x00, 0x00, 0x78,
+ 0x0C, 0x07, 0x3F, 0x80,
+};
static char hx8389b_qhd_video_on_cmd6[] = {
-0x08, 0x00, 0x39, 0xC0,
-0xB2, 0x00, 0x00, 0x78,
-0x0C, 0x07, 0x3F, 0x80,
- };
-
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xb7, 0x00, 0x00, 0x50,
+};
static char hx8389b_qhd_video_on_cmd7[] = {
-0x18, 0x00, 0x39, 0xC0,
-0xb4, 0x82, 0x08, 0x00,
-0x32, 0x10, 0x04, 0x32,
-0x10, 0x00, 0x32, 0x10,
-0x00, 0x37, 0x0a, 0x40,
-0x08, 0x37, 0x0a, 0x40,
-0x14, 0x46, 0x50, 0x0a,
- };
-
+ 0x18, 0x00, 0x39, 0xC0,
+ 0xB4, 0x80, 0x08, 0x00,
+ 0x32, 0x10, 0x04, 0x32,
+ 0x10, 0x00, 0x32, 0x10,
+ 0x00, 0x37, 0x0a, 0x40,
+ 0x08, 0x37, 0x00, 0x46,
+ 0x02, 0x58, 0x58, 0x02,
+};
static char hx8389b_qhd_video_on_cmd8[] = {
-0x39, 0x00, 0x39, 0xC0,
-0xd5, 0x00, 0x00, 0x00,
-0x00, 0x01, 0x00, 0x00,
-0x00, 0x60, 0x00, 0x99,
-0x88, 0xAA, 0xBB, 0x88,
-0x23, 0x88, 0x01, 0x88,
-0x67, 0x88, 0x45, 0x01,
-0x23, 0x88, 0x88, 0x88,
-0x88, 0x88, 0x88, 0x99,
-0xBB, 0xAA, 0x88, 0x54,
-0x88, 0x76, 0x88, 0x10,
-0x88, 0x32, 0x32, 0x10,
-0x88, 0x88, 0x88, 0x88,
-0x88, 0x00, 0x04, 0x00,
-0x00, 0x00, 0x00, 0x00,
-0x00, 0xFF, 0xFF, 0xFF,
- };
-
+ 0x39, 0x00, 0x39, 0xC0,
+ 0xD5, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x60, 0x00, 0x99,
+ 0x88, 0xAA, 0xBB, 0x88,
+ 0x23, 0x88, 0x01, 0x88,
+ 0x67, 0x88, 0x45, 0x01,
+ 0x23, 0x88, 0x88, 0x88,
+ 0x88, 0x88, 0x88, 0x99,
+ 0xBB, 0xAA, 0x88, 0x54,
+ 0x88, 0x76, 0x88, 0x10,
+ 0x88, 0x32, 0x32, 0x10,
+ 0x88, 0x88, 0x88, 0x88,
+ 0x88, 0x3C, 0x04, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
static char hx8389b_qhd_video_on_cmd9[] = {
-0x03, 0x00, 0x39, 0xC0,
-0xCB, 0x07, 0x07, 0xFF,
+ 0x23, 0x00, 0x39, 0xC0,
+ 0xE0, 0x05, 0x11, 0x16,
+ 0x35, 0x3F, 0x3F, 0x21,
+ 0x43, 0x07, 0x0C, 0x0F,
+ 0x11, 0x12, 0x10, 0x10,
+ 0x1D, 0x18, 0x05, 0x11,
+ 0x16, 0x35, 0x3F, 0x3F,
+ 0x21, 0x43, 0x07, 0x0C,
+ 0x0F, 0x11, 0x12, 0x10,
+ 0x10, 0x1D, 0x18, 0xFF,
};
-
static char hx8389b_qhd_video_on_cmd10[] = {
-0x05, 0x00, 0x39, 0xC0,
-0xBB, 0x00, 0x00, 0xFF,
-0x80, 0xFF, 0xFF, 0xFF,
+ 0x80, 0x00, 0x39, 0xC0,
+ 0xC1, 0x01, 0x00, 0x07,
+ 0x13, 0x21, 0x29, 0x2F,
+ 0x34, 0x3B, 0x42, 0x48,
+ 0x50, 0x58, 0x61, 0x69,
+ 0x71, 0x79, 0x81, 0x88,
+ 0x90, 0x98, 0xA0, 0xA9,
+ 0xB1, 0xB9, 0xC1, 0xC8,
+ 0xCE, 0xD6, 0xDF, 0xE6,
+ 0xEF, 0xF7, 0xFF, 0x0E,
+ 0x5A, 0x73, 0x69, 0x36,
+ 0x8E, 0x69, 0x5F, 0xC0,
+ 0x00, 0x07, 0x13, 0x21,
+ 0x29, 0x2F, 0x34, 0x3B,
+ 0x42, 0x48, 0x50, 0x58,
+ 0x61, 0x69, 0x71, 0x79,
+ 0x81, 0x88, 0x90, 0x98,
+ 0xA0, 0xA9, 0xB1, 0xB9,
+ 0xC1, 0xC8, 0xCE, 0xD6,
+ 0xDF, 0xE6, 0xEF, 0xF7,
+ 0xFF, 0x0E, 0x5A, 0x73,
+ 0x69, 0x36, 0x8E, 0x69,
+ 0x5F, 0xC0, 0x00, 0x07,
+ 0x13, 0x21, 0x29, 0x2F,
+ 0x34, 0x3B, 0x42, 0x48,
+ 0x50, 0x58, 0x61, 0x69,
+ 0x71, 0x79, 0x81, 0x88,
+ 0x90, 0x98, 0xA0, 0xA9,
+ 0xB1, 0xB9, 0xC1, 0xC8,
+ 0xCE, 0xD6, 0xDF, 0xE6,
+ 0xEF, 0xF7, 0xFF, 0x0E,
+ 0x5A, 0x73, 0x69, 0x36,
+ 0x8E, 0x69, 0x5F, 0xC0,
};
-
static char hx8389b_qhd_video_on_cmd11[] = {
-0x04, 0x00, 0x39, 0xC0,
-0xDE, 0x05, 0x58, 0x10,
- };
-
+ 0x05, 0x00, 0x39, 0xC0,
+ 0xB6, 0x00, 0x88, 0x00,
+ 0x88, 0xFF, 0xFF, 0xFF,
+};
static char hx8389b_qhd_video_on_cmd12[] = {
-0x05, 0x00, 0x39, 0xC0,
-0xB6, 0x00, 0x8A, 0x00,
-0x8A, 0xFF, 0xFF, 0xFF,
+ 0x11, 0x00, 0x05, 0x80
};
-
static char hx8389b_qhd_video_on_cmd13[] = {
-0x23, 0x00, 0x39, 0xC0,
-0xE0, 0x01, 0x08, 0x0C,
-0x1F, 0x25, 0x36, 0x12,
-0x35, 0x05, 0x09, 0x0D,
-0x10, 0x11, 0x0F, 0x0F,
-0x1C, 0x1D, 0x01, 0x08,
-0x0C, 0x1F, 0x25, 0x36,
-0x12, 0x35, 0x05, 0x09,
-0x0D, 0x10, 0x11, 0x0F,
-0x0F, 0x1C, 0x1D, 0xFF, };
-
-
-static char hx8389b_qhd_video_on_cmd14[] = {
-0x11, 0x00, 0x05, 0x80 };
-
-
-static char hx8389b_qhd_video_on_cmd15[] = {
-0x29, 0x00, 0x05, 0x80 };
-
-
-
+ 0x29, 0x00, 0x05, 0x80
+};
static struct mipi_dsi_cmd hx8389b_qhd_video_on_command[] = {
-{ 0x8 , hx8389b_qhd_video_on_cmd0},
-{ 0xc , hx8389b_qhd_video_on_cmd1},
-{ 0x4 , hx8389b_qhd_video_on_cmd2},
-{ 0x8 , hx8389b_qhd_video_on_cmd3},
-{ 0x4 , hx8389b_qhd_video_on_cmd4},
-{ 0x18 , hx8389b_qhd_video_on_cmd5},
-{ 0xc , hx8389b_qhd_video_on_cmd6},
-{ 0x1c , hx8389b_qhd_video_on_cmd7},
-{ 0x3c , hx8389b_qhd_video_on_cmd8},
-{ 0x8 , hx8389b_qhd_video_on_cmd9},
-{ 0xc , hx8389b_qhd_video_on_cmd10},
-{ 0x8 , hx8389b_qhd_video_on_cmd11},
-{ 0xc , hx8389b_qhd_video_on_cmd12},
-{ 0x28 , hx8389b_qhd_video_on_cmd13},
-{ 0x4 , hx8389b_qhd_video_on_cmd14},
-{ 0x4 , hx8389b_qhd_video_on_cmd15}
+ {0x8, hx8389b_qhd_video_on_cmd0, 0x0A},
+ {0x4, hx8389b_qhd_video_on_cmd1, 0x01},
+ {0x8, hx8389b_qhd_video_on_cmd2, 0x01},
+ {0xc, hx8389b_qhd_video_on_cmd3, 0x01},
+ {0x18, hx8389b_qhd_video_on_cmd4, 0x01},
+ {0xc, hx8389b_qhd_video_on_cmd5, 0x01},
+ {0x8, hx8389b_qhd_video_on_cmd6, 0x01},
+ {0x1c, hx8389b_qhd_video_on_cmd7, 0x01},
+ {0x40, hx8389b_qhd_video_on_cmd8, 0x01},
+ {0x28, hx8389b_qhd_video_on_cmd9, 0x01},
+ {0x84, hx8389b_qhd_video_on_cmd10, 0x05},
+ {0xc, hx8389b_qhd_video_on_cmd11, 0x01},
+ {0x4, hx8389b_qhd_video_on_cmd12, 0x78},
+ {0x4, hx8389b_qhd_video_on_cmd13, 0x32}
};
-#define HX8389B_QHD_VIDEO_ON_COMMAND 16
+
+#define HX8389B_QHD_VIDEO_ON_COMMAND 14
static char hx8389b_qhd_videooff_cmd0[] = {
-0x28, 0x00, 0x05, 0x80 };
-
+ 0x28, 0x00, 0x05, 0x80
+};
static char hx8389b_qhd_videooff_cmd1[] = {
-0x10, 0x00, 0x05, 0x80 };
-
-
-
+ 0x10, 0x00, 0x05, 0x80
+};
static struct mipi_dsi_cmd hx8389b_qhd_video_off_command[] = {
-{ 0x4 , hx8389b_qhd_videooff_cmd0},
-{ 0x4 , hx8389b_qhd_videooff_cmd1}
+ {0x4, hx8389b_qhd_videooff_cmd0, 0x32},
+ {0x4, hx8389b_qhd_videooff_cmd1, 0x78}
};
+
#define HX8389B_QHD_VIDEO_OFF_COMMAND 2
static struct command_state hx8389b_qhd_video_state = {
- 0, 0
+ 0, 0
};
/*---------------------------------------------------------------------------*/
/* Command mode panel information */
/*---------------------------------------------------------------------------*/
-
static struct commandpanel_info hx8389b_qhd_video_command_panel = {
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
/* Video mode panel information */
/*---------------------------------------------------------------------------*/
-
static struct videopanel_info hx8389b_qhd_video_video_panel = {
- 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
};
/*---------------------------------------------------------------------------*/
-/* Lane Configuration */
+/* Lane configuration */
/*---------------------------------------------------------------------------*/
-
static struct lane_configuration hx8389b_qhd_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0
};
-
/*---------------------------------------------------------------------------*/
-/* Panel Timing */
+/* Panel timing */
/*---------------------------------------------------------------------------*/
static const uint32_t hx8389b_qhd_video_timings[] = {
- 0x97,0x23,0x17,0x00,0x4B,0x53,0x1C,0x27,0x27,0x03,0x04,0x00
+ 0x87, 0x1E, 0x14, 0x00, 0x44, 0x4B, 0x19, 0x21, 0x22, 0x03, 0x04, 0x00
};
static struct panel_timing hx8389b_qhd_video_timing_info = {
- 0, 4, 0x04, 0x1b
+ 0, 4, 0x04, 0x1b
};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
static struct panel_reset_sequence hx8389b_qhd_video_reset_seq = {
{ 2, 0, 2, }, { 20, 2, 20, }, 2
};
/*---------------------------------------------------------------------------*/
-/* Backlight Settings */
+/* Backlight setting */
/*---------------------------------------------------------------------------*/
-
static struct backlight hx8389b_qhd_video_backlight = {
0, 1, 255, 0, 1, 0
};
-
#endif /*_PANEL_HX8389B_QHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
index 8afaa4b..841579b 100755
--- a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
+++ b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
@@ -45,7 +45,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config ssd2080m_720p_video_panel_data = {
"qcom,mdss_dsi_ssd2080m_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 50000
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index 40fe319..8503760 100644
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -74,9 +74,6 @@
if (pstruct->paneldata->panel_operating_mode & SPLIT_DISPLAY_FLAG)
pinfo->lcdc.split_display = 1;
- pinfo->mipi.lp11_init = pstruct->paneldata->panel_lp11_init;
- pinfo->mipi.init_delay = pstruct->paneldata->panel_init_delay;
-
/* Color setting*/
pinfo->lcdc.border_clr = pstruct->color->border_color;
pinfo->lcdc.underflow_clr = pstruct->color->underflow_color;
diff --git a/dev/pmic/pm8x41/include/pm8x41_wled.h b/dev/pmic/pm8x41/include/pm8x41_wled.h
index 389d470..92632ca 100644
--- a/dev/pmic/pm8x41/include/pm8x41_wled.h
+++ b/dev/pmic/pm8x41/include/pm8x41_wled.h
@@ -53,6 +53,7 @@
#define PM_WLED_LED2_SINK_MASK BIT(6)
#define PM_WLED_LED3_SINK_MASK BIT(7)
+#define PM_WLED_LED_MODULATOR_EN BIT(7)
#define PM_WLED_LED1_ILED_SYNC_MASK BIT(0)
#define PM_WLED_LED2_ILED_SYNC_MASK BIT(1)
#define PM_WLED_LED3_ILED_SYNC_MASK BIT(2)
@@ -73,5 +74,6 @@
void pm8x41_wled_config(struct pm8x41_wled_data *wled_ctrl);
void pm8x41_wled_iled_sync_control(uint8_t enable);
void pm8x41_wled_sink_control(uint8_t enable);
+void pm8x41_wled_led_mod_enable(uint8_t enable);
void pm8x41_wled_enable(uint8_t enable);
void pm8x41_wled_config_slave_id(uint8_t slave_id);
diff --git a/dev/pmic/pm8x41/pm8x41_wled.c b/dev/pmic/pm8x41/pm8x41_wled.c
index e879f1f..42283e1 100644
--- a/dev/pmic/pm8x41/pm8x41_wled.c
+++ b/dev/pmic/pm8x41/pm8x41_wled.c
@@ -109,6 +109,21 @@
}
+void pm8x41_wled_led_mod_enable(uint8_t enable) {
+
+ uint8_t value = 0x0;
+
+ if (enable)
+ value = PM_WLED_LED_MODULATOR_EN;
+
+ wled_reg_write(PM_WLED_LED_CTNL_REG(1), value);
+ wled_reg_write(PM_WLED_LED_CTNL_REG(2), value);
+ wled_reg_write(PM_WLED_LED_CTNL_REG(3), value);
+
+ dprintf(SPEW, "WLED LED Module Enable Success\n");
+
+}
+
void pm8x41_wled_enable(uint8_t enable) {
uint8_t value = 0x0;
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index 873eeda..0cd1d8d 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -217,14 +217,110 @@
*/
static void ce_async_reset(uint8_t instance)
{
+ if (instance == 1)
+ {
+ /* Start the block reset for CE */
+ writel(1, GCC_CE1_BCR);
+
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CE1_BCR);
+
+ udelay(2);
+ }
+ else if (instance == 2)
+ {
+ /* Start the block reset for CE */
+ writel(1, GCC_CE2_BCR);
+
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CE2_BCR);
+
+ udelay(2);
+ }
+ else
+ {
+ dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
+ ASSERT(0);
+ }
}
void clock_ce_enable(uint8_t instance)
{
+ int ret;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ ret = clk_get_set_enable(clk_name, 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
+ ASSERT(0);
+ }
+
+ /* Wait for 48 * #pipes cycles.
+ * This is necessary as immediately after an access control reset (boot up)
+ * or a debug re-enable, the Crypto core sequentially clears its internal
+ * pipe key storage memory. If pipe key initialization writes are attempted
+ * during this time, they may be overwritten by the internal clearing logic.
+ */
+ udelay(1);
}
void clock_ce_disable(uint8_t instance)
{
+ struct clk *ahb_clk;
+ struct clk *cclk;
+ struct clk *axi_clk;
+ struct clk *src_clk;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ src_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ahb_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ axi_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ cclk = clk_get(clk_name);
+
+ clk_disable(ahb_clk);
+ clk_disable(axi_clk);
+ clk_disable(cclk);
+ clk_disable(src_clk);
+
+ /* Some delay for the clocks to stabalize. */
+ udelay(1);
}
void clock_config_ce(uint8_t instance)
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index cedafec..1b5504c 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -396,6 +396,111 @@
},
};
+/* CE Clocks */
+static struct clk_freq_tbl ftbl_gcc_ce2_clk[] = {
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct rcg_clk ce2_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_CE2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_CE2_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_ce2_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "ce2_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct vote_clk gcc_ce2_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE2_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(2),
+
+ .c = {
+ .dbg_name = "gcc_ce2_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE2_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(0),
+
+ .c = {
+ .dbg_name = "gcc_ce2_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce2_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE2_AXI_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(1),
+
+ .c = {
+ .dbg_name = "gcc_ce2_axi_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_CE1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_CE1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_ce1_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "ce1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct vote_clk gcc_ce1_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(5),
+
+ .c = {
+ .dbg_name = "gcc_ce1_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(3),
+
+ .c = {
+ .dbg_name = "gcc_ce1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(4),
+
+ .c = {
+ .dbg_name = "gcc_ce1_axi_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
/* Display clocks */
static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
F_MM(19200000, cxo, 1, 0, 0),
@@ -621,6 +726,16 @@
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+ CLK_LOOKUP("ce2_ahb_clk", gcc_ce2_ahb_clk.c),
+ CLK_LOOKUP("ce2_axi_clk", gcc_ce2_axi_clk.c),
+ CLK_LOOKUP("ce2_core_clk", gcc_ce2_clk.c),
+ CLK_LOOKUP("ce2_src_clk", ce2_clk_src.c),
+
+ CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
+ CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
+ CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+ CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
+
/* USB 3.0 */
CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index b09e214..b5218e4 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -74,6 +74,22 @@
#define CLK_CTL_BASE 0xFC400000
+/* CE 1 */
+#define GCC_CE1_BCR (CLK_CTL_BASE + 0x1040)
+#define GCC_CE1_CMD_RCGR (CLK_CTL_BASE + 0x1050)
+#define GCC_CE1_CFG_RCGR (CLK_CTL_BASE + 0x1054)
+#define GCC_CE1_CBCR (CLK_CTL_BASE + 0x1044)
+#define GCC_CE1_AXI_CBCR (CLK_CTL_BASE + 0x1048)
+#define GCC_CE1_AHB_CBCR (CLK_CTL_BASE + 0x104C)
+
+/* CE 2 */
+#define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080)
+#define GCC_CE2_CMD_RCGR (CLK_CTL_BASE + 0x1090)
+#define GCC_CE2_CFG_RCGR (CLK_CTL_BASE + 0x1094)
+#define GCC_CE2_CBCR (CLK_CTL_BASE + 0x1084)
+#define GCC_CE2_AXI_CBCR (CLK_CTL_BASE + 0x1088)
+#define GCC_CE2_AHB_CBCR (CLK_CTL_BASE + 0x108C)
+
/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x001C)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
diff --git a/platform/apq8084/rules.mk b/platform/apq8084/rules.mk
index 260dc2d..bd022b3 100644
--- a/platform/apq8084/rules.mk
+++ b/platform/apq8084/rules.mk
@@ -10,7 +10,7 @@
DEFINES += PERIPH_BLK_BLSP=1
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
- MMC_SLOT=$(MMC_SLOT)
+ MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
#DEFINES += TZ_SAVE_KERNEL_HASH
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
diff --git a/platform/init.c b/platform/init.c
index 5001373..7efea46 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -105,3 +105,9 @@
__WEAK void clock_config_cdc(uint8_t slot)
{
}
+
+__WEAK int get_target_boot_params(const char *cmdline, const char *part,
+ char *buf, int buflen)
+{
+ return -1;
+}
diff --git a/platform/mpq8092/acpuclock.c b/platform/mpq8092/acpuclock.c
index 2adfacb..1e2ee63 100644
--- a/platform/mpq8092/acpuclock.c
+++ b/platform/mpq8092/acpuclock.c
@@ -38,30 +38,137 @@
void hsusb_clock_init(void)
{
+ int ret;
+ struct clk *iclk, *cclk;
+ ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Wait for the clocks to be stable since we are disabling soon after. */
+ mdelay(1);
+
+ iclk = clk_get("usb_iface_clk");
+ cclk = clk_get("usb_core_clk");
+
+ clk_disable(iclk);
+ clk_disable(cclk);
+
+ /* Wait for the clock disable to complete. */
+ mdelay(1);
+
+ /* Start the block reset for usb */
+ writel(1, USB_HS_BCR);
+
+ /* Wait for reset to complete. */
+ mdelay(1);
+
+ /* Take usb block out of reset */
+ writel(0, USB_HS_BCR);
+
+ /* Wait for the block to be brought out of reset. */
+ mdelay(1);
+
+ ret = clk_enable(iclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_enable(cclk);
}
void clock_init_mmc(uint32_t interface)
{
+ char clk_name[64];
+ int ret;
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
uint32_t reg;
+ int ret;
+ char clk_name[64];
- reg = 0;
- reg |= MMC_BOOT_MCI_CLK_ENABLE;
- reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
- reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
- writel(reg, MMC_BOOT_MCI_CLK);
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+ mmc_boot_mci_clk_disable();
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else if(freq == MMC_CLK_96MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 100000000, 1);
+ }
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
+ /* Enable MCI clk */
+ mmc_boot_mci_clk_enable();
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
}
/* Function to asynchronously reset CE.
diff --git a/platform/mpq8092/gpio.c b/platform/mpq8092/gpio.c
index 6f0c834..d34f6a0 100644
--- a/platform/mpq8092/gpio.c
+++ b/platform/mpq8092/gpio.c
@@ -54,10 +54,10 @@
void gpio_config_uart_dm(uint8_t id)
{
/* configure rx gpio */
- gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+ gpio_tlmm_config(29, 2, GPIO_INPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
/* configure tx gpio */
- gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ gpio_tlmm_config(28, 2, GPIO_OUTPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
}
diff --git a/platform/mpq8092/include/platform/gpio.h b/platform/mpq8092/include/platform/gpio.h
index 4c6e24e..36d81cd 100644
--- a/platform/mpq8092/include/platform/gpio.h
+++ b/platform/mpq8092/include/platform/gpio.h
@@ -29,6 +29,8 @@
#ifndef __PLATFORM_MPQ8092_GPIO_H
#define __PLATFORM_MPQ8092_GPIO_H
+#include <gpio.h>
+
/* GPIO TLMM: Direction */
#define GPIO_INPUT 0
#define GPIO_OUTPUT 1
diff --git a/platform/mpq8092/include/platform/iomap.h b/platform/mpq8092/include/platform/iomap.h
index ba10f13..4957aa0 100644
--- a/platform/mpq8092/include/platform/iomap.h
+++ b/platform/mpq8092/include/platform/iomap.h
@@ -37,6 +37,10 @@
#define MSM_SHARED_BASE 0x0FA00000
#define APPS_SS_BASE 0xF9000000
+#define SYSTEM_IMEM_BASE 0xFE800000
+#define MSM_SHARED_IMEM_BASE 0xFE805000
+
+#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
#define MSM_GIC_DIST_BASE APPS_SS_BASE
#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
@@ -65,10 +69,36 @@
#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000)
#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
+#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000)
+
#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
+#define USB2_PHY_SEL 0xFD4AB000
#define CLK_CTL_BASE 0xFC400000
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
+#define BLSP1_UART5_APPS_CBCR (CLK_CTL_BASE + 0x884)
+#define BLSP1_UART5_APPS_CMD_RCGR (CLK_CTL_BASE + 0x88C)
+#define BLSP1_UART5_APPS_CFG_RCGR (CLK_CTL_BASE + 0x890)
+#define BLSP1_UART5_APPS_M (CLK_CTL_BASE + 0x894)
+#define BLSP1_UART5_APPS_N (CLK_CTL_BASE + 0x898)
+#define BLSP1_UART5_APPS_D (CLK_CTL_BASE + 0x89C)
+
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xA44)
+#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C)
+#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50)
+#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xA54)
+#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xA58)
+#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xA5C)
+
+#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
+#define BLSP2_UART1_APPS_CBCR (CLK_CTL_BASE + 0x9C4)
+#define BLSP2_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x9CC)
+#define BLSP2_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x9D0)
+#define BLSP2_UART1_APPS_M (CLK_CTL_BASE + 0x9D4)
+#define BLSP2_UART1_APPS_N (CLK_CTL_BASE + 0x9D8)
+#define BLSP2_UART1_APPS_D (CLK_CTL_BASE + 0x9DC)
+
#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
@@ -112,8 +142,9 @@
#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
+
/* UART */
-#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
diff --git a/platform/mpq8092/mpq8092-clock.c b/platform/mpq8092/mpq8092-clock.c
new file mode 100644
index 0000000..2da2809
--- /dev/null
+++ b/platform/mpq8092/mpq8092-clock.c
@@ -0,0 +1,303 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val 0
+#define gpll0_source_val 1
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+ .enable = clock_lib2_branch_clk_enable,
+ .disable = clock_lib2_branch_clk_disable,
+ .set_rate = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+ .enable = cxo_clk_enable,
+ .disable = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 600000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 96, 15625),
+ F( 7372800, gpll0, 1, 192, 15625),
+ F(14745600, gpll0, 1, 384, 15625),
+ F(16000000, gpll0, 5, 2, 15),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 5, 1, 5),
+ F(32000000, gpll0, 1, 4, 75),
+ F(40000000, gpll0, 15, 0, 0),
+ F(46400000, gpll0, 1, 29, 375),
+ F(48000000, gpll0, 12.5, 0, 0),
+ F(51200000, gpll0, 1, 32, 375),
+ F(56000000, gpll0, 1, 7, 75),
+ F(58982400, gpll0, 1, 1536, 15625),
+ F(60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk blsp1_uart5_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART5_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART5_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART5_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART5_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART5_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart5_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart5_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART5_APPS_CBCR,
+ .parent = &blsp1_uart5_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart5_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(17),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_blsp2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(15),
+
+ .c = {
+ .dbg_name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+ F(75000000, gpll0, 8, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+ .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb_hs_system_clk",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
+ .parent = &usb_hs_system_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_system_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F(200000000, gpll0, 3, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_8092[] =
+{
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+
+ CLK_LOOKUP("uart4_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart4_core_clk", gcc_blsp1_uart5_apps_clk.c),
+
+ CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
+ CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+
+};
+
+void platform_clock_init(void)
+{
+ clk_init(msm_clocks_8092, ARRAY_SIZE(msm_clocks_8092));
+}
diff --git a/platform/mpq8092/platform.c b/platform/mpq8092/platform.c
index 5509d78..9ebf5d6 100644
--- a/platform/mpq8092/platform.c
+++ b/platform/mpq8092/platform.c
@@ -31,9 +31,48 @@
#include <platform/iomap.h>
#include <qgic.h>
#include <qtimer.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* Kernel region - cacheable, write through */
+#define KERNEL_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* Scratch region - cacheable, write through */
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+ /* Physical addr, Virtual addr, Size (in MB), Flags */
+ {MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ {MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ {BASE_ADDR, BASE_ADDR, 44, KERNEL_MEMORY},
+ {SCRATCH_ADDR, SCRATCH_ADDR, 512, SCRATCH_MEMORY},
+ /* IMEM needs a seperate entry in the table as it's length is only 0x8000. */
+ {SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+};
void platform_early_init(void)
{
+ board_init();
+ platform_clock_init();
qgic_init();
qtimer_init();
}
@@ -47,3 +86,76 @@
{
qtimer_uninit();
}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ ram_partition ptn_entry;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ uint32_t len = 0;
+
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Configure the MMU page entries for SDRAM and IMEM memory read
+ from the smem ram table*/
+ for(i = 0; i < len; i++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, i);
+ if(ptn_entry.type == SYS_MEMORY)
+ {
+ if((ptn_entry.category == SDRAM) ||
+ (ptn_entry.category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ptn_entry.start & (MB-1)) == 0);
+
+ sections = (ptn_entry.size) / MB;
+ while(sections--)
+ {
+ arm_mmu_map_section(ptn_entry.start +
+ sections * MB,
+ ptn_entry.start + sections * MB,
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+ }
+ }
+ }
+ }
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
diff --git a/platform/mpq8092/rules.mk b/platform/mpq8092/rules.mk
index 11faf01..b42764d 100644
--- a/platform/mpq8092/rules.mk
+++ b/platform/mpq8092/rules.mk
@@ -18,7 +18,8 @@
OBJS += \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/acpuclock.o \
- $(LOCAL_DIR)/gpio.o
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/mpq8092-clock.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/platform/msm8610/include/platform/pm_pwm.h b/platform/msm8610/include/platform/pm_pwm.h
new file mode 100644
index 0000000..238004d
--- /dev/null
+++ b/platform/msm8610/include/platform/pm_pwm.h
@@ -0,0 +1,63 @@
+/*
+ * * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PMIC_PWM_H
+#define __PMIC_PWM_H
+
+#define PM_PWM_SIZE_SEL_MASK 0x04
+#define PM_PWM_SIZE_SEL_SHIFT 2
+
+#define PM_PWM_CLK_SEL_MASK 0x03
+
+#define PM_PWM_PREDIVIDE_MASK 0x60
+#define PM_PWM_PREDIVIDE_SHIFT 5
+
+#define PM_PWM_M_MASK 0x07
+
+#define PM_PWM_SYNC_MASK 0x01
+
+#define PM_PWM_ENABLE_CTL_MASK 0x80
+#define PM_PWM_ENABLE_CTL_SHIFT 7
+
+#define PM_PWM_EN_GLITCH_REMOVAL_MASK 0x20
+#define PM_PWM_EN_GLITCH_REMOVAL_SHIFT 5
+
+#define PM_PWM_VALUE_BIT7_0 0xFF
+#define PM_PWM_VALUE_BIT8 0x01
+#define PM_PWM_VALUE_BIT5_0 0x3F
+
+#define PM_PWM_BASE(x) (0x1BC00 + (x))
+#define PM_PWM_CTL_REG_OFFSET 0x41
+#define PM_PWM_SYNC_REG_OFFSET 0x47
+#define PM_PWM_ENABLE_CTL_REG_OFFSET 0x46
+
+int pm_pwm_config(unsigned int duty_us, unsigned int period_us);
+void pm_pwm_enable(bool enable);
+
+#endif
diff --git a/platform/msm8610/pm_pwm.c b/platform/msm8610/pm_pwm.c
new file mode 100644
index 0000000..19ccbb0
--- /dev/null
+++ b/platform/msm8610/pm_pwm.c
@@ -0,0 +1,256 @@
+/*
+ * * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/pm_pwm.h>
+#include <pm8x41_hw.h>
+
+#define NSEC_PER_USEC 1000L
+#define USEC_PER_SEC 1000000L
+#define NSEC_PER_SEC 1000000000L
+
+#define NUM_REF_CLOCKS 3
+#define NSEC_1024HZ (NSEC_PER_SEC / 1024)
+#define NSEC_32768HZ (NSEC_PER_SEC / 32768)
+#define NSEC_19P2MHZ (NSEC_PER_SEC / 19200000)
+
+#define NUM_PRE_DIVIDE 4
+#define PRE_DIVIDE_1 1
+#define PRE_DIVIDE_3 3
+#define PRE_DIVIDE_5 5
+#define PRE_DIVIDE_6 6
+static unsigned int pt_t[NUM_PRE_DIVIDE][NUM_REF_CLOCKS] = {
+ { PRE_DIVIDE_1 * NSEC_1024HZ,
+ PRE_DIVIDE_1 * NSEC_32768HZ,
+ PRE_DIVIDE_1 * NSEC_19P2MHZ,
+ },
+ { PRE_DIVIDE_3 * NSEC_1024HZ,
+ PRE_DIVIDE_3 * NSEC_32768HZ,
+ PRE_DIVIDE_3 * NSEC_19P2MHZ,
+ },
+ { PRE_DIVIDE_5 * NSEC_1024HZ,
+ PRE_DIVIDE_5 * NSEC_32768HZ,
+ PRE_DIVIDE_5 * NSEC_19P2MHZ,
+ },
+ { PRE_DIVIDE_6 * NSEC_1024HZ,
+ PRE_DIVIDE_6 * NSEC_32768HZ,
+ PRE_DIVIDE_6 * NSEC_19P2MHZ,
+ },
+};
+
+enum pwm_ctl_reg {
+ SIZE_CLK,
+ FREQ_PREDIV_CLK,
+ TYPE_CONFIG,
+ VALUE_LSB,
+ VALUE_MSB,
+};
+
+#define NUM_PWM_CTL_REGS 5
+struct pm_pwm_config {
+ int pwm_size; /* round up to 6 or 9 for 6/9-bit PWM SIZE */
+ int clk;
+ int pre_div;
+ int pre_div_exp;
+ int pwm_value;
+ uint8_t pwm_ctl[NUM_PWM_CTL_REGS];
+};
+
+static void pm_pwm_reg_write(uint8_t off, uint8_t val)
+{
+ REG_WRITE(PM_PWM_BASE(off), val);
+}
+
+/*
+ * PWM Frequency = Clock Frequency / (N * T)
+ * or
+ * PWM Period = Clock Period * (N * T)
+ * where
+ * N = 2^9 or 2^6 for 9-bit or 6-bit PWM size
+ * T = Pre-divide * 2^m, where m = 0..7 (exponent)
+ *
+ * This is the formula to figure out m for the best pre-divide and clock:
+ * (PWM Period / N) = (Pre-divide * Clock Period) * 2^m
+ */
+
+#define PRE_DIVIDE_MAX 6
+#define CLK_PERIOD_MAX NSEC_1024HZ
+#define PM_PWM_M_MAX 7
+#define MAX_MPT ((PRE_DIVIDE_MAX * CLK_PERIOD_MAX) << PM_PWM_M_MAX)
+static void pm_pwm_calc_period(unsigned int period_us,
+ struct pm_pwm_config *pwm_config)
+{
+ int n, m, clk, div;
+ int best_m, best_div, best_clk;
+ unsigned int last_err, cur_err, min_err;
+ unsigned int tmp_p, period_n;
+
+ n = 6;
+
+ if (period_us < ((unsigned)(-1) / NSEC_PER_USEC))
+ period_n = (period_us * NSEC_PER_USEC) >> n;
+ else
+ period_n = (period_us >> n) * NSEC_PER_USEC;
+
+ if (period_n >= MAX_MPT) {
+ n = 9;
+ period_n >>= 3;
+ }
+
+ min_err = last_err = (unsigned)(-1);
+ best_m = 0;
+ best_clk = 0;
+ best_div = 0;
+ for (clk = 0; clk < NUM_REF_CLOCKS; clk++) {
+ for (div = 0; div < NUM_PRE_DIVIDE; div++) {
+ /* period_n = (PWM Period / N) */
+ /* tmp_p = (Pre-divide * Clock Period) * 2^m */
+ tmp_p = pt_t[div][clk];
+ for (m = 0; m <= PM_PWM_M_MAX; m++) {
+ if (period_n > tmp_p)
+ cur_err = period_n - tmp_p;
+ else
+ cur_err = tmp_p - period_n;
+
+ if (cur_err < min_err) {
+ min_err = cur_err;
+ best_m = m;
+ best_clk = clk;
+ best_div = div;
+ }
+
+ if (m && cur_err > last_err)
+ /* Break for bigger cur_err */
+ break;
+
+ last_err = cur_err;
+ tmp_p <<= 1;
+ }
+ }
+ }
+
+ pwm_config->pwm_size = n;
+ pwm_config->clk = best_clk;
+ pwm_config->pre_div = best_div;
+ pwm_config->pre_div_exp = best_m;
+}
+
+static void pm_pwm_calc_pwm_value(struct pm_pwm_config *pwm_config,
+ unsigned int period_us,
+ unsigned int duty_us)
+{
+ unsigned int max_pwm_value, tmp;
+
+ /* Figure out pwm_value with overflow handling */
+ tmp = 1 << (sizeof(tmp) * 8 - pwm_config->pwm_size);
+ if (duty_us < tmp) {
+ tmp = duty_us << pwm_config->pwm_size;
+ pwm_config->pwm_value = tmp / period_us;
+ } else {
+ tmp = period_us >> pwm_config->pwm_size;
+ pwm_config->pwm_value = duty_us / tmp;
+ }
+ max_pwm_value = (1 << pwm_config->pwm_size) - 1;
+ if (pwm_config->pwm_value > max_pwm_value)
+ pwm_config->pwm_value = max_pwm_value;
+}
+
+#define PM_PWM_SIZE_9_BIT 1
+#define PM_PWM_SIZE_6_BIT 0
+static void pm_pwm_config_regs(struct pm_pwm_config *pwm_config)
+{
+ int i;
+ uint8_t reg;
+
+ reg = ((pwm_config->pwm_size > 6 ? PM_PWM_SIZE_9_BIT : PM_PWM_SIZE_6_BIT)
+ << PM_PWM_SIZE_SEL_SHIFT)
+ & PM_PWM_SIZE_SEL_MASK;
+ reg |= (pwm_config->clk + 1) & PM_PWM_CLK_SEL_MASK;
+ pwm_config->pwm_ctl[SIZE_CLK] = reg;
+
+ reg = (pwm_config->pre_div << PM_PWM_PREDIVIDE_SHIFT)
+ & PM_PWM_PREDIVIDE_MASK;
+ reg |= pwm_config->pre_div_exp & PM_PWM_M_MASK;
+ pwm_config->pwm_ctl[FREQ_PREDIV_CLK] = reg;
+
+ /* Enable glitch removal by default */
+ reg = 1 << PM_PWM_EN_GLITCH_REMOVAL_SHIFT
+ & PM_PWM_EN_GLITCH_REMOVAL_MASK;
+ pwm_config->pwm_ctl[TYPE_CONFIG] = reg;
+
+ if (pwm_config->pwm_size > 6) {
+ pwm_config->pwm_ctl[VALUE_LSB] = pwm_config->pwm_value
+ & PM_PWM_VALUE_BIT7_0;
+ pwm_config->pwm_ctl[VALUE_MSB] = (pwm_config->pwm_value >> 8)
+ & PM_PWM_VALUE_BIT8;
+ } else
+ pwm_config->pwm_ctl[VALUE_LSB] = pwm_config->pwm_value
+ & PM_PWM_VALUE_BIT5_0;
+
+ for (i = 0; i < NUM_PWM_CTL_REGS; i++)
+ pm_pwm_reg_write(PM_PWM_CTL_REG_OFFSET + i, pwm_config->pwm_ctl[i]);
+
+ reg = 1 & PM_PWM_SYNC_MASK;
+ pm_pwm_reg_write(PM_PWM_SYNC_REG_OFFSET, reg);
+}
+
+/* usec: 19.2M, n=6, m=0, pre=2 */
+#define PM_PWM_PERIOD_MIN 7
+/* 1K, n=9, m=7, pre=6 */
+#define PM_PWM_PERIOD_MAX (384 * USEC_PER_SEC)
+int pm_pwm_config(unsigned int duty_us, unsigned int period_us)
+{
+ struct pm_pwm_config pwm_config;
+
+ if ((duty_us > period_us) || (period_us > PM_PWM_PERIOD_MAX) ||
+ (period_us < PM_PWM_PERIOD_MIN)) {
+ dprintf(CRITICAL, "Error in duty cycle and period\n");
+ return -1;
+ }
+
+ pm_pwm_calc_period(period_us, &pwm_config);
+ pm_pwm_calc_pwm_value(&pwm_config, period_us, duty_us);
+
+ dprintf(SPEW, "duty/period=%u/%u usec: pwm_value=%d (of %d)\n",
+ duty_us, period_us, pwm_config.pwm_value, 1 << pwm_config.pwm_size);
+
+ pm_pwm_config_regs(&pwm_config);
+
+ return 0;
+}
+
+void pm_pwm_enable(bool enable)
+{
+ uint8_t reg;
+
+ reg = enable << PM_PWM_ENABLE_CTL_SHIFT
+ & PM_PWM_ENABLE_CTL_MASK;
+
+ pm_pwm_reg_write(PM_PWM_ENABLE_CTL_REG_OFFSET, reg);
+}
diff --git a/platform/msm8610/rules.mk b/platform/msm8610/rules.mk
index 234432f..fa41936 100644
--- a/platform/msm8610/rules.mk
+++ b/platform/msm8610/rules.mk
@@ -22,7 +22,8 @@
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/acpuclock.o \
$(LOCAL_DIR)/msm8610-clock.o \
- $(LOCAL_DIR)/gpio.o
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/pm_pwm.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/platform/msm_shared/crypto5_eng.c b/platform/msm_shared/crypto5_eng.c
index 3fecd61..ce9cf32 100644
--- a/platform/msm_shared/crypto5_eng.c
+++ b/platform/msm_shared/crypto5_eng.c
@@ -321,12 +321,22 @@
static uint32_t crypto5_get_sha_cfg(void *ctx_ptr, crypto_auth_alg_type auth_alg)
{
- crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
- uint32_t seg_cfg_val;
+ crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
+ crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx *) ctx_ptr;
+ uint32_t seg_cfg_val;
- seg_cfg_val = SEG_CFG_AUTH_ALG_SHA;
+ seg_cfg_val = SEG_CFG_AUTH_ALG_SHA;
- if (auth_alg == CRYPTO_AUTH_ALG_SHA256)
+ if (auth_alg == CRYPTO_AUTH_ALG_SHA1)
+ {
+ seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA1;
+
+ if (sha1_ctx->flags & CRYPTO_LAST_CHUNK)
+ {
+ seg_cfg_val |= SEG_CFG_LAST;
+ }
+ }
+ else if (auth_alg == CRYPTO_AUTH_ALG_SHA256)
{
seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA256;
@@ -348,35 +358,45 @@
void *ctx_ptr,
crypto_auth_alg_type auth_alg)
{
- crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
- uint32_t i = 0;
- uint32_t iv_len = SHA256_INIT_VECTOR_SIZE;
- uint32_t *auth_iv = sha256_ctx->auth_iv;
- uint32_t seg_cfg_val;
- uint32_t total_bytes_to_write = sha256_ctx->bytes_to_write;
- uint32_t bytes_to_write = total_bytes_to_write;
- uint32_t burst_mask;
+ crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
+ crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx *) ctx_ptr;
+ uint32_t i = 0;
+ uint32_t iv_len = 0;
+ uint32_t *auth_iv = sha1_ctx->auth_iv;
+ uint32_t seg_cfg_val;
+ uint32_t total_bytes_to_write = sha256_ctx->bytes_to_write;
+ uint32_t bytes_to_write = total_bytes_to_write;
+ uint32_t burst_mask;
- seg_cfg_val = crypto5_get_sha_cfg(ctx_ptr, auth_alg);
+ if(auth_alg == CRYPTO_AUTH_ALG_SHA1)
+ {
+ iv_len = SHA1_INIT_VECTOR_SIZE;
+ }
+ else if(auth_alg == CRYPTO_AUTH_ALG_SHA256)
+ {
+ iv_len = SHA256_INIT_VECTOR_SIZE;
+ }
- if (!seg_cfg_val)
- {
+ seg_cfg_val = crypto5_get_sha_cfg(ctx_ptr, auth_alg);
+
+ if (!seg_cfg_val)
+ {
dprintf(CRITICAL, "Authentication alg config failed.\n");
return;
- }
+ }
/* Initialize CE pointers. */
REG_WRITE_QUEUE_INIT(dev);
- REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_CFG(dev->base), seg_cfg_val);
+ REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_CFG(dev->base), seg_cfg_val);
- for (i = 0; i < iv_len; i++)
- {
+ for (i = 0; i < iv_len; i++)
+ {
if (sha256_ctx->flags & CRYPTO_FIRST_CHUNK)
REG_WRITE_QUEUE(dev, CRYPTO_AUTH_IVn(dev->base, i), BE32(*(auth_iv + i)));
else
REG_WRITE_QUEUE(dev, CRYPTO_AUTH_IVn(dev->base, i), (*(auth_iv + i)));
- }
+ }
/* Check if the transfer length is a 8 beat burst multiple. */
burst_mask = CRYPTO_BURST_LEN - 1;
@@ -391,15 +411,15 @@
/* Typecast with crypto_SHA1_ctx because offset of auth_bytecnt
* in both crypto_SHA1_ctx and crypto_SHA256_ctx are same.
*/
- REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 0), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0]);
- REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 1), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1]);
+ REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 0), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0]);
+ REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 1), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1]);
/* Assume no header, always. */
REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_START(dev->base), 0);
- REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_SIZE(dev->base), bytes_to_write);
- REG_WRITE_QUEUE(dev, CRYPTO_SEG_SIZE(dev->base), total_bytes_to_write);
- REG_WRITE_QUEUE(dev, CRYPTO_GOPROC(dev->base), GOPROC_GO);
+ REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_SIZE(dev->base), bytes_to_write);
+ REG_WRITE_QUEUE(dev, CRYPTO_SEG_SIZE(dev->base), total_bytes_to_write);
+ REG_WRITE_QUEUE(dev, CRYPTO_GOPROC(dev->base), GOPROC_GO);
REG_WRITE_QUEUE_DONE(dev, BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG);
diff --git a/platform/msm_shared/crypto_hash.c b/platform/msm_shared/crypto_hash.c
index 1568243..0d3cce8 100644
--- a/platform/msm_shared/crypto_hash.c
+++ b/platform/msm_shared/crypto_hash.c
@@ -33,14 +33,10 @@
static crypto_SHA256_ctx g_sha256_ctx;
static crypto_SHA1_ctx g_sha1_ctx;
-static unsigned char crypto_init_done = FALSE;
+static bool crypto_init_done;
extern void ce_clock_init(void);
-__WEAK void crypto_eng_cleanup()
-{
-}
-
/*
* Top level function which calculates SHAx digest with given data and size.
* Digest varies based on the authentication algorithm.
@@ -54,7 +50,7 @@
crypto_result_type ret_val = CRYPTO_SHA_ERR_NONE;
crypto_engine_type platform_ce_type = board_ce_type();
- if (auth_alg == 1) {
+ if (auth_alg == CRYPTO_AUTH_ALG_SHA1) {
if(platform_ce_type == CRYPTO_ENGINE_TYPE_SW)
/* Hardware CE is not present , use software hashing */
digest = SHA1(addr, size, digest);
@@ -62,7 +58,7 @@
ret_val = crypto_sha1(addr, size, digest);
else
ret_val = CRYPTO_SHA_ERR_FAIL;
- } else if (auth_alg == 2) {
+ } else if (auth_alg == CRYPTO_AUTH_ALG_SHA256) {
if(platform_ce_type == CRYPTO_ENGINE_TYPE_SW)
/* Hardware CE is not present , use software hashing */
digest = SHA256(addr, size, digest);
@@ -71,13 +67,12 @@
else
ret_val = CRYPTO_SHA_ERR_FAIL;
}
+ else
+ ret_val = CRYPTO_SHA_ERR_FAIL;
if (ret_val != CRYPTO_SHA_ERR_NONE) {
dprintf(CRITICAL, "crypto_sha256 returns error %d\n", ret_val);
}
-
- crypto_eng_cleanup();
-
}
/*
@@ -96,6 +91,15 @@
}
/*
+ * Function to return if crypto is initialized
+ */
+
+bool crypto_initialized()
+{
+ return crypto_init_done;
+}
+
+/*
* Function to initialize SHA256 context
*/
diff --git a/platform/msm_shared/include/baseband.h b/platform/msm_shared/include/baseband.h
index 5b02d48..64dde97 100644
--- a/platform/msm_shared/include/baseband.h
+++ b/platform/msm_shared/include/baseband.h
@@ -40,6 +40,7 @@
BASEBAND_DSDA = 7,
BASEBAND_DSDA2 = 8,
BASEBAND_SGLTE2 = 9,
+ BASEBAND_MDM2 = 10,
BASEBAND_32BITS = 0x7FFFFFFF
};
diff --git a/platform/msm_shared/include/crypto_hash.h b/platform/msm_shared/include/crypto_hash.h
index 03dccbc..bdcf7e0 100644
--- a/platform/msm_shared/include/crypto_hash.h
+++ b/platform/msm_shared/include/crypto_hash.h
@@ -71,17 +71,18 @@
unsigned int auth_bytecnt[2];
unsigned char saved_buff[64];
unsigned char saved_buff_indx;
- unsigned int auth_iv[5];
+ uint32_t bytes_to_write;
uint32_t flags;
+ unsigned int auth_iv[5];
} crypto_SHA1_ctx;
typedef struct {
unsigned int auth_bytecnt[2];
unsigned char saved_buff[64];
unsigned char saved_buff_indx;
- unsigned int auth_iv[8];
uint32_t bytes_to_write;
uint32_t flags;
+ unsigned int auth_iv[8];
} crypto_SHA256_ctx;
extern void crypto_eng_reset(void);
@@ -129,4 +130,6 @@
static crypto_result_type crypto_sha1(unsigned char *buff_ptr,
unsigned int buff_size,
unsigned char *digest_ptr);
+
+bool crypto_initialized(void);
#endif
diff --git a/platform/msm_shared/include/mmc.h b/platform/msm_shared/include/mmc.h
index 597992a..15375e4 100644
--- a/platform/msm_shared/include/mmc.h
+++ b/platform/msm_shared/include/mmc.h
@@ -399,6 +399,7 @@
/* EXT_CSD */
#define MMC_BOOT_ACCESS_WRITE 0x3
+#define MMC_BOOT_SET_BIT 0x1
#define MMC_BOOT_EXT_USER_WP 171
#define MMC_BOOT_EXT_ERASE_GROUP_DEF 175
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index e12722d..abd552e 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -163,9 +163,6 @@
uint8_t mode_gpio_state;
uint32_t signature;
uint32_t use_enable_gpio;
-
- uint8_t lp11_init;
- uint32_t init_delay;
};
struct edp_panel_info {
@@ -223,6 +220,7 @@
int (*bl_func) (int enable);
int (*pll_clk_func) (int enable, struct msm_panel_info *);
int (*post_power_func)(int enable);
+ int (*pre_init_func)(void);
};
#endif
diff --git a/platform/msm_shared/include/partition_parser.h b/platform/msm_shared/include/partition_parser.h
index 25a73ca..bbd8422 100644
--- a/platform/msm_shared/include/partition_parser.h
+++ b/platform/msm_shared/include/partition_parser.h
@@ -72,7 +72,7 @@
#define MAX_GPT_NAME_SIZE 72
#define PARTITION_TYPE_GUID_SIZE 16
#define UNIQUE_PARTITION_GUID_SIZE 16
-#define NUM_PARTITIONS 32
+#define NUM_PARTITIONS 128
/* Some useful define used to access the MBR/EBR table */
#define BLOCK_SIZE 0x200
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 5e662e3..3b18833 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -114,6 +114,38 @@
return NULL;
}
+static uint32_t response_value = 0;
+
+uint32_t mdss_dsi_read_panel_signature(uint32_t panel_signature)
+{
+ uint32_t rec_buf[1];
+ uint32_t *lp = rec_buf, data;
+ int ret = response_value;
+
+#if (DISPLAY_TYPE_MDSS == 1)
+ if (ret && ret != panel_signature)
+ goto exit_read_signature;
+
+ ret = mipi_dsi_cmds_tx(&read_ddb_start_cmd, 1);
+ if (ret)
+ goto exit_read_signature;
+ if (!mdss_dsi_cmds_rx(&lp, 1, 1))
+ goto exit_read_signature;
+
+ data = ntohl(*lp);
+ data = data >> 8;
+ response_value = data;
+ if (response_value != panel_signature)
+ ret = response_value;
+
+exit_read_signature:
+ /* Keep the non detectable panel at the end and set panel signature 0xFFFF */
+ if (panel_signature == 0xFFFF)
+ ret = 0;
+#endif
+ return ret;
+}
+
int mdss_dual_dsi_cmd_dma_trigger_for_panel()
{
uint32_t ReadValue;
@@ -383,7 +415,7 @@
return data;
}
-int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t
+int mdss_dsi_host_init(struct mipi_dsi_panel_config *pinfo, uint32_t
broadcast)
{
uint8_t DMA_STREAM1 = 0; // for mdp display processor path
@@ -393,7 +425,6 @@
uint8_t VC1 = 0;
uint8_t DT1 = 0; // non embedded mode
uint8_t WC1 = 0; // for non embedded mode only
- int status = 0;
uint8_t DLNx_EN;
uint8_t lane_swap = 0;
uint32_t timing_ctl = 0;
@@ -452,7 +483,17 @@
writel(lane_swap, MIPI_DSI0_BASE + LANE_SWAP_CTL);
writel(timing_ctl, MIPI_DSI0_BASE + TIMING_CTL);
+#endif
+ return 0;
+}
+
+int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t
+ broadcast)
+{
+ int status = 0;
+
+#if (DISPLAY_TYPE_MDSS == 1)
if (pinfo->panel_cmds) {
if (broadcast) {
@@ -464,7 +505,7 @@
pinfo->num_of_panel_cmds);
if (!status && target_panel_auto_detect_enabled())
status =
- target_read_panel_signature(pinfo->signature);
+ mdss_dsi_read_panel_signature(pinfo->signature);
}
}
#endif
@@ -988,12 +1029,31 @@
if (pinfo->mipi.dual_dsi)
mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE);
- ret += mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast);
+ ret = mdss_dsi_host_init(&mipi_pinfo, pinfo->mipi.broadcast);
+ if (ret) {
+ dprintf(CRITICAL, "dsi host init error\n");
+ goto error;
+ }
+
+ if (panel->pre_init_func) {
+ ret = panel->pre_init_func();
+ if (ret) {
+ dprintf(CRITICAL, "pre_init_func error\n");
+ goto error;
+ }
+ }
+
+ ret = mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast);
+ if (ret) {
+ dprintf(CRITICAL, "dsi panel init error\n");
+ goto error;
+ }
if (pinfo->rotate && panel->rotate)
pinfo->rotate();
#endif
+error:
return ret;
}
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index 75f937f..2c9636a 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -2559,7 +2559,7 @@
sizeof(struct mmc_boot_command));
/* Disabling PERM_WP for USER AREA (CMD6) */
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_SET_BIT,
MMC_BOOT_EXT_USER_WP,
MMC_BOOT_US_PERM_WP_DIS);
@@ -2606,8 +2606,7 @@
}
/* Setting POWER_ON_WP for USER AREA (CMD6) */
-
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_SET_BIT,
MMC_BOOT_EXT_USER_WP,
MMC_BOOT_US_PWR_WP_EN);
@@ -2690,13 +2689,29 @@
unsigned int rc = MMC_BOOT_E_SUCCESS;
/* Checking whether group write protection feature is available */
- if (mmc_card.csd.wp_grp_enable) {
+ if (mmc_card.csd.wp_grp_enable)
+ {
rc = mmc_boot_get_wp_status(&mmc_card, sector);
+ if (rc != MMC_BOOT_E_SUCCESS)
+ {
+ dprintf(CRITICAL, "Failure in getting wp_status (%u):%s:%u\n", rc, __FILE__, __LINE__);
+ return rc;
+ }
rc = mmc_boot_set_clr_power_on_wp_user(&mmc_card, sector, size,
set_clear_wp);
+ if (rc != MMC_BOOT_E_SUCCESS)
+ {
+ dprintf(CRITICAL, "Failure in setting power on wp user (%u):%s:%u\n", rc, __FILE__, __LINE__);
+ return rc;
+ }
rc = mmc_boot_get_wp_status(&mmc_card, sector);
- return rc;
- } else
+ if (rc != MMC_BOOT_E_SUCCESS)
+ {
+ dprintf(CRITICAL, "Failure in getting wp_status (%u)%s:%u\n", rc, __FILE__, __LINE__);
+ return rc;
+ }
+ }
+ else
return MMC_BOOT_E_FAILURE;
}
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index e2d548e..6facb93 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -58,7 +58,7 @@
unsigned int ext3_count = 0;
unsigned int vfat_count = 0;
-struct partition_entry partition_entries[NUM_PARTITIONS];
+struct partition_entry *partition_entries;
static unsigned gpt_partitions_exist = 0;
unsigned partition_count = 0;
@@ -69,6 +69,10 @@
block_size = mmc_get_device_blocksize();
+ /* Allocate partition entries array */
+ partition_entries = (struct partition_entry *) calloc(NUM_PARTITIONS, sizeof(struct partition_entry));
+ ASSERT(partition_entries);
+
/* Read MBR of the card */
ret = mmc_boot_read_mbr(block_size);
if (ret) {
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index c70d1cd..1105cdd 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -149,6 +149,7 @@
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/dev_tree.o
endif
@@ -172,7 +173,12 @@
$(LOCAL_DIR)/qpic_nand.o \
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/scm.o \
- $(LOCAL_DIR)/gpio.o
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/certificate.o \
+ $(LOCAL_DIR)/image_verify.o \
+ $(LOCAL_DIR)/crypto_hash.o \
+ $(LOCAL_DIR)/crypto5_eng.o \
+ $(LOCAL_DIR)/crypto5_wrapper.o
endif
ifeq ($(PLATFORM),apq8084)
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index 26e203e..8adc0d2 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -293,7 +293,7 @@
parse_req.md_len *= MULTIPLICATION_FACTOR;
- arch_clean_invalidate_cache_range((addr_t) *(img_ptr + prev_len),
+ arch_clean_invalidate_cache_range((addr_t) (*img_ptr + prev_len),
(parse_req.md_len - prev_len) );
continue;
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index daa9b0f..7c36cd7 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -317,6 +317,11 @@
MSM8674 = 186,
MDMKRYPTON = 187,
FSM9900 = 188,
+ FSM9905 = 189,
+ FSM9955 = 190,
+ FSM9950 = 191,
+ FSM9915 = 192,
+ FSM9910 = 193,
MSM8974AC = 194,
MSM8962 = 195,
MSM8262 = 196,
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index 4f95988..698e62f 100644
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -60,6 +60,8 @@
#define BOOT_DEVICE_MASK(val) ((val & 0x3E) >>1)
+#define SSD_CE_INSTANCE 1
+
enum cdp_subtype
{
CDP_SUBTYPE_SMB349 = 0,
@@ -88,6 +90,12 @@
RCM_SUBTYPE_SMB350
};
+enum liquid_subtype
+{
+ LIQUID_SUBTYPE_STANDALONE = 0,
+ LIQUID_SUBTYPE_9x25,
+};
+
static void set_sdc_power_ctrl(void);
static uint32_t mmc_pwrctl_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE };
@@ -309,6 +317,58 @@
#endif
}
+void target_load_ssd_keystore(void)
+{
+ uint64_t ptn;
+ int index;
+ uint64_t size;
+ uint32_t *buffer = NULL;
+
+ if (!target_is_ssd_enabled())
+ return;
+
+ index = partition_get_index("ssd");
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0){
+ dprintf(CRITICAL, "Error: ssd partition not found\n");
+ return;
+ }
+
+ size = partition_get_size(index);
+ if (size == 0) {
+ dprintf(CRITICAL, "Error: invalid ssd partition size\n");
+ return;
+ }
+
+ buffer = memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
+ if (!buffer) {
+ dprintf(CRITICAL, "Error: allocating memory for ssd buffer\n");
+ return;
+ }
+
+ if (mmc_read(ptn, buffer, size)) {
+ dprintf(CRITICAL, "Error: cannot read data\n");
+ free(buffer);
+ return;
+ }
+
+ clock_ce_enable(SSD_CE_INSTANCE);
+ scm_protect_keystore(buffer, size);
+ clock_ce_disable(SSD_CE_INSTANCE);
+ free(buffer);
+}
+
+/* Do any target specific intialization needed before entering fastboot mode */
+void target_fastboot_init(void)
+{
+ if (target_is_ssd_enabled()) {
+ clock_ce_enable(SSD_CE_INSTANCE);
+ target_load_ssd_keystore();
+ }
+
+}
+
unsigned board_machtype(void)
{
return LINUX_MACHTYPE_UNKNOWN;
@@ -329,9 +389,11 @@
switch(platform_subtype) {
case CDP_SUBTYPE_9x25_SMB349:
case CDP_SUBTYPE_9x25_SMB1357:
- case CDP_SUBTYPE_9x35:
board->baseband = BASEBAND_MDM;
break;
+ case CDP_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM2;
+ break;
case CDP_SUBTYPE_SMB349:
case CDP_SUBTYPE_SMB1357:
case CDP_SUBTYPE_SMB350:
@@ -354,9 +416,11 @@
switch(platform_subtype) {
case MTP_SUBTYPE_9x25_SMB349:
case MTP_SUBTYPE_9x25_SMB1357:
- case MTP_SUBTYPE_9x35:
board->baseband = BASEBAND_MDM;
break;
+ case MTP_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM2;
+ break;
case MTP_SUBTYPE_SMB349:
board->baseband = BASEBAND_APQ;
break;
@@ -375,9 +439,11 @@
switch(platform_subtype) {
case RCM_SUBTYPE_9x25_SMB349:
case RCM_SUBTYPE_9x25_SMB1357:
- case RCM_SUBTYPE_9x35:
board->baseband = BASEBAND_MDM;
break;
+ case RCM_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM2;
+ break;
case RCM_SUBTYPE_SMB349:
case RCM_SUBTYPE_SMB1357:
case RCM_SUBTYPE_SMB350:
@@ -390,6 +456,26 @@
};
}
+void set_liquid_baseband(struct board_data *board)
+{
+ uint32_t platform_subtype;
+
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype)
+ {
+ case LIQUID_SUBTYPE_STANDALONE:
+ board->baseband = BASEBAND_APQ;
+ break;
+ case LIQUID_SUBTYPE_9x25:
+ board->baseband = BASEBAND_MDM;
+ break;
+ default:
+ dprintf(CRITICAL, "Liquid platform subtype :%u is not supported\n",platform_subtype);
+ ASSERT(0);
+ }
+}
+
/* Returns 1 if target supports continuous splash screen. */
int target_cont_splash_screen()
{
@@ -429,7 +515,7 @@
set_rcm_baseband(board);
break;
case HW_PLATFORM_LIQUID:
- board->baseband = BASEBAND_APQ;
+ set_liquid_baseband(board);
break;
default:
dprintf(CRITICAL, "Platform :%u is not supported\n",
diff --git a/target/fsm9900/init.c b/target/fsm9900/init.c
index eed402c..ae2f91b 100644
--- a/target/fsm9900/init.c
+++ b/target/fsm9900/init.c
@@ -339,6 +339,11 @@
switch (platform) {
case FSM9900:
+ case FSM9905:
+ case FSM9910:
+ case FSM9915:
+ case FSM9950:
+ case FSM9955:
board->baseband = BASEBAND_MSM;
break;
default:
diff --git a/target/init.c b/target/init.c
index 345819c..bd5b325 100644
--- a/target/init.c
+++ b/target/init.c
@@ -120,11 +120,6 @@
{
}
-__WEAK uint32_t target_read_panel_signature(uint32_t panel_signature)
-{
- return 0;
-}
-
/* Default target does not support continuous splash screen feature. */
__WEAK int target_cont_splash_screen()
{
diff --git a/target/mdmkrypton/init.c b/target/mdmkrypton/init.c
index d362633..89e17ad 100644
--- a/target/mdmkrypton/init.c
+++ b/target/mdmkrypton/init.c
@@ -223,3 +223,41 @@
return restart_reason;
}
+int get_target_boot_params(const char *cmdline, const char *part, char *buf,
+ int buflen)
+{
+ struct ptable *ptable;
+ int system_ptn_index = -1;
+
+ if (!cmdline || !part || !buf || buflen < 0) {
+ dprintf(CRITICAL, "WARN: Invalid input param\n");
+ return -1;
+ }
+
+ ptable = flash_get_ptable();
+ if (!ptable) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get flash partition table\n");
+ return -1;
+ }
+
+ system_ptn_index = ptable_get_index(ptable, part);
+ if (system_ptn_index < 0) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get partition index for %s\n", part);
+ return -1;
+ }
+
+ /*
+ * check if cmdline contains "root=" at the beginning of buffer or
+ * " root=" in the middle of buffer.
+ */
+ if (((!strncmp(cmdline, "root=", strlen("root="))) ||
+ (strstr(cmdline, " root="))))
+ dprintf(DEBUG, "DEBUG: cmdline has root=\n");
+ else
+ snprintf(buf, buflen, " root=/dev/mtdblock%d",
+ system_ptn_index);
+
+ return 0;
+}
diff --git a/target/mpq8092/init.c b/target/mpq8092/init.c
index 86b7bc9..12b0d97 100644
--- a/target/mpq8092/init.c
+++ b/target/mpq8092/init.c
@@ -35,19 +35,29 @@
#include <mmc.h>
#include <spmi.h>
#include <board.h>
+#include <hsusb.h>
+#include <smem.h>
+#include <baseband.h>
+#include <dev/keys.h>
+#include <pm8x41.h>
+#include <platform/gpio.h>
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
+#define FASTBOOT_MODE 0x77665500
static uint32_t mmc_sdc_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE };
+static void set_sdc_power_ctrl();
+
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(1, 0, BLSP1_UART1_BASE);
+ uart_dm_init(4, 0, BLSP1_UART4_BASE); /* DEBUG_UART BLSP1_UART5 */
#endif
}
+
void target_mmc_caps(struct mmc_host *host)
{
host->caps.ddr_mode = 0;
@@ -55,8 +65,69 @@
host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
host->caps.hs_clk_rate = MMC_CLK_50MHZ;
}
+
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ uint8_t status = 0;
+ struct pm8x41_gpio gpio;
+
+ /* Configure the GPIO */
+ gpio.direction = PM_GPIO_DIR_IN;
+ gpio.function = 0;
+ gpio.pull = PM_GPIO_PULL_UP_30;
+ gpio.vin_sel = 2;
+
+ pm8x41_gpio_config(2, &gpio);
+
+ /* Wait for the pmic gpio configuration to take effect */
+ thread_sleep(1);
+
+ /* Get status of P_GPIO_2 */
+ pm8x41_gpio_get(2, &status);
+
+ return !status; /* active low */
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ return pm8x41_resin_status();
+}
+
static void target_keystatus()
{
+ keys_init();
+
+ if(target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if(target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
+}
+
+static void set_sdc_power_ctrl()
+{
+ /* Drive strength configs for sdc pins */
+ struct tlmm_cfgs sdc1_hdrv_cfg[] =
+ {
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ };
+
+ /* Pull configs for sdc pins */
+ struct tlmm_cfgs sdc1_pull_cfg[] =
+ {
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK },
+ };
+
+ /* Set the drive strength & pull control values */
+ tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+ tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
}
void target_init(void)
@@ -70,6 +141,8 @@
target_keystatus();
+ set_sdc_power_ctrl();
+
/* Trying Slot 1*/
slot = 1;
base_addr = mmc_sdc_base[slot - 1];
@@ -97,4 +170,95 @@
unsigned board_machtype(void)
{
+ return LINUX_MACHTYPE_UNKNOWN;
+}
+
+/* Do target specific usb initialization */
+void target_usb_init(void)
+{
+ uint32_t val;
+
+ /* Route ChipIDea to use secondary USB HS port2 */
+ writel(1, USB2_PHY_SEL);
+
+ /* Enable access to secondary PHY by clamping the low
+ * voltage interface between DVDD of the PHY and Vddcx
+ * (set bit16 (USB2_PHY_HS2_DIG_CLAMP_N_2) = 1) */
+ writel(readl(USB_OTG_HS_PHY_SEC_CTRL)
+ | 0x00010000, USB_OTG_HS_PHY_SEC_CTRL);
+
+ /* Perform power-on-reset of the PHY.
+ * Delay values are arbitrary */
+ writel(readl(USB_OTG_HS_PHY_SEC_CTRL)|1,
+ USB_OTG_HS_PHY_SEC_CTRL);
+ thread_sleep(10);
+ writel(readl(USB_OTG_HS_PHY_SEC_CTRL) & 0xFFFFFFFE,
+ USB_OTG_HS_PHY_SEC_CTRL);
+ thread_sleep(10);
+
+ /* Select and enable external configuration with USB PHY */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
+
+ /* Enable sess_vld */
+ val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
+ writel(val, USB_GENCONFIG_2);
+
+ /* Enable external vbus configuration in the LINK */
+ val = readl(USB_USBCMD);
+ val |= SESS_VLD_CTRL;
+ writel(val, USB_USBCMD);
+}
+
+void target_usb_stop(void)
+{
+ /* Disable VBUS mimicing in the controller. */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+ uint8_t reset_type = 0;
+
+ /* Write the reboot reason */
+ writel(reboot_reason, RESTART_REASON_ADDR);
+
+ if(reboot_reason == FASTBOOT_MODE)
+ reset_type = PON_PSHOLD_WARM_RESET;
+ else
+ reset_type = PON_PSHOLD_HARD_RESET;
+
+ pm8x41_reset_configure(reset_type);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+ mdelay(5000);
+
+ dprintf(CRITICAL, "Rebooting failed\n");
+}
+
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+ board->target = LINUX_MACHTYPE_UNKNOWN;
+}
+
+void target_baseband_detect(struct board_data *board)
+{
+ uint32_t platform;
+
+ platform = board->platform;
+ switch(platform)
+ {
+ case MPQ8092:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "Platform type: %u is not supported\n", platform);
+ ASSERT(0);
+ };
+}
+
+unsigned target_baseband()
+{
+ return board_baseband();
}
diff --git a/target/mpq8092/rules.mk b/target/mpq8092/rules.mk
index 2bf8320..d319fec 100644
--- a/target/mpq8092/rules.mk
+++ b/target/mpq8092/rules.mk
@@ -4,7 +4,7 @@
PLATFORM := mpq8092
-MEMBASE := 0x0FF00000 # SDRAM
+MEMBASE := 0x10000000 # SDRAM
MEMSIZE := 0x00100000 # 1MB
BASE_ADDR := 0x00000
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index db95264..62782a9 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -391,6 +391,9 @@
if (target_is_ssd_enabled())
clock_ce_disable(SSD_CE_INSTANCE);
+
+ if (crypto_initialized())
+ crypto_eng_cleanup();
}
void target_usb_init(void)
@@ -410,21 +413,45 @@
writel(val, USB_USBCMD);
}
+uint8_t target_panel_auto_detect_enabled()
+{
+ switch(board_hardware_id())
+ {
+ case HW_PLATFORM_QRD:
+ return 1;
+ case HW_PLATFORM_SURF:
+ case HW_PLATFORM_MTP:
+ default:
+ return 0;
+ }
+ return 0;
+}
+
+static uint8_t splash_override;
/* Returns 1 if target supports continuous splash screen. */
int target_cont_splash_screen()
{
- switch(board_hardware_id())
- {
- case HW_PLATFORM_MTP:
- case HW_PLATFORM_QRD:
- case HW_PLATFORM_SURF:
- dprintf(SPEW, "Target_cont_splash=1\n");
- return 1;
- break;
- default:
- dprintf(SPEW, "Target_cont_splash=0\n");
- return 0;
- }
+ uint8_t splash_screen = 0;
+ if(!splash_override) {
+ switch(board_hardware_id())
+ {
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_QRD:
+ case HW_PLATFORM_SURF:
+ dprintf(SPEW, "Target_cont_splash=1\n");
+ splash_screen = 1;
+ break;
+ default:
+ dprintf(SPEW, "Target_cont_splash=0\n");
+ splash_screen = 0;
+ }
+ }
+ return splash_screen;
+}
+
+void target_force_cont_splash_disable(uint8_t override)
+{
+ splash_override = override;
}
unsigned target_pause_for_battery_charge(void)
diff --git a/target/msm8226/oem_panel.c b/target/msm8226/oem_panel.c
index 5dcfdbf..14fd179 100755
--- a/target/msm8226/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -49,6 +49,10 @@
#include "include/panel_ssd2080m_720p_video.h"
#include "include/panel_jdi_1080p_video.h"
+#define DISPLAY_MAX_PANEL_DETECTION 2
+
+#define SSD2080M_720P_VIDEO_PANEL_ON_DELAY 200
+
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
/*---------------------------------------------------------------------------*/
@@ -60,7 +64,8 @@
HX8394A_720P_VIDEO_PANEL,
NT35521_720P_VIDEO_PANEL,
SSD2080M_720P_VIDEO_PANEL,
-JDI_1080P_VIDEO_PANEL
+JDI_1080P_VIDEO_PANEL,
+UNKNOWN_PANEL
};
enum target_subtype {
@@ -95,11 +100,14 @@
return ret;
}
-
int oem_panel_on()
{
/* OEM can keep there panel spefic on instructions in this
function */
+ if (panel_id == SSD2080M_720P_VIDEO_PANEL) {
+ /* SSD2080M needs extra delay to avoid unexpected artifacts */
+ mdelay(SSD2080M_720P_VIDEO_PANEL_ON_DELAY);
+ }
return NO_ERROR;
}
@@ -214,6 +222,7 @@
= HX8394A_720P_VIDEO_ON_COMMAND;
memcpy(phy_db->timing,
hx8394a_720p_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = HX8394A_720P_VIDEO_SIGNATURE;
break;
case NT35590_720P_CMD_PANEL:
@@ -255,6 +264,7 @@
= NT35596_1080P_VIDEO_ON_COMMAND;
memcpy(phy_db->timing,
nt35596_1080p_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = NT35596_1080P_VIDEO_SIGNATURE;
break;
case JDI_1080P_VIDEO_PANEL:
panelstruct->paneldata = &jdi_1080p_video_panel_data;
@@ -277,9 +287,24 @@
memcpy(phy_db->timing,
jdi_1080p_video_timings, TIMING_SIZE);
break;
+ case UNKNOWN_PANEL:
+ memset(panelstruct, 0, sizeof(struct panel_struct));
+ memset(pinfo->mipi.panel_cmds, 0, sizeof(struct mipi_dsi_cmd));
+ pinfo->mipi.num_of_panel_cmds = 0;
+ memset(phy_db->timing, 0, TIMING_SIZE);
+ pinfo->mipi.signature = 0;
+ break;
}
}
+uint32_t oem_panel_max_auto_detect_panels()
+{
+ return target_panel_auto_detect_enabled() ?
+ DISPLAY_MAX_PANEL_DETECTION : 0;
+}
+
+static uint32_t auto_pan_loop = 0;
+
bool oem_panel_select(struct panel_struct *panelstruct,
struct msm_panel_info *pinfo,
struct mdss_dsi_phy_ctrl *phy_db)
@@ -288,6 +313,7 @@
uint32_t target_id = board_target_id();
uint32_t nt35590_panel_id = NT35590_720P_VIDEO_PANEL;
uint32_t hw_subtype = board_hardware_subtype();
+ bool ret = true;
#if DISPLAY_TYPE_CMD_MODE
nt35590_panel_id = NT35590_720P_CMD_PANEL;
@@ -302,8 +328,23 @@
} else {
if (((target_id >> 16) & 0xFF) == 0x1 || ((target_id >> 16) & 0xFF) == 0x3) //EVT || PVT
panel_id = nt35590_panel_id;
- else if (((target_id >> 16) & 0xFF) == 0x2) //DVT
+ else if (((target_id >> 16) & 0xFF) == 0x2) { //DVT
panel_id = HX8394A_720P_VIDEO_PANEL;
+ switch (auto_pan_loop) {
+ case 0:
+ panel_id = HX8394A_720P_VIDEO_PANEL;
+ break;
+ case 1:
+ panel_id = NT35596_1080P_VIDEO_PANEL;
+ break;
+ default:
+ panel_id = UNKNOWN_PANEL;
+ ret = false;
+ dprintf(CRITICAL, "Unknown panel\n");
+ return ret;
+ }
+ auto_pan_loop++;
+ }
else {
dprintf(CRITICAL, "Not supported device, target_id=%x\n"
, target_id);
@@ -331,5 +372,5 @@
init_panel_data(panelstruct, pinfo, phy_db);
- return true;
+ return ret;
}
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index d63352a..8ddfa89 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -202,10 +202,14 @@
{
dprintf(SPEW, "target_backlight_ctrl\n");
- pm8x41_wled_config(&wled_ctrl);
- pm8x41_wled_sink_control(1);
- pm8x41_wled_iled_sync_control(1);
- pm8x41_wled_enable(1);
+ if (enable) {
+ pm8x41_wled_config(&wled_ctrl);
+ pm8x41_wled_sink_control(enable);
+ pm8x41_wled_iled_sync_control(enable);
+ pm8x41_wled_led_mod_enable(enable);
+ }
+
+ pm8x41_wled_enable(enable);
return 0;
}
@@ -328,7 +332,20 @@
void display_init(void)
{
- gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR);
+ uint32_t panel_loop = 0;
+ uint32_t ret = 0;
+
+ do {
+ ret = gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR);
+ if (!ret || ret == ERR_NOT_SUPPORTED) {
+ break;
+ } else {
+ target_force_cont_splash_disable(true);
+ msm_display_off();
+ target_force_cont_splash_disable(false);
+ }
+ } while (++panel_loop <= oem_panel_max_auto_detect_panels());
+
}
void display_shutdown(void)
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index a3806f0..070413c 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -49,10 +49,20 @@
#include <partition_parser.h>
#include <platform/clock.h>
#include <platform/timer.h>
+#include <crypto5_wrapper.h>
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
+#define CRYPTO_ENGINE_INSTANCE 1
+#define CRYPTO_ENGINE_EE 1
+#define CRYPTO_ENGINE_FIFO_SIZE 64
+#define CRYPTO_ENGINE_READ_PIPE 3
+#define CRYPTO_ENGINE_WRITE_PIPE 2
+#define CRYPTO_READ_PIPE_LOCK_GRP 0
+#define CRYPTO_WRITE_PIPE_LOCK_GRP 0
+#define CRYPTO_ENGINE_CMD_ARRAY_SIZE 20
+
#define TLMM_VOL_UP_BTN_GPIO 72
enum target_subtype {
@@ -168,11 +178,17 @@
dprintf(SPEW, "Display Init: Start\n");
display_init();
dprintf(SPEW, "Display Init: Done\n");
+
+ if (target_use_signed_kernel())
+ target_crypto_init_params();
}
void target_uninit(void)
{
- mmc_put_card_to_sleep(dev);
+ mmc_put_card_to_sleep(dev);
+
+ if (crypto_initialized())
+ crypto_eng_cleanup();
}
#define SSD_CE_INSTANCE 1
@@ -432,3 +448,35 @@
{
return (void *) dev;
}
+
+/* Set up params for h/w CRYPTO_ENGINE. */
+void target_crypto_init_params()
+{
+ struct crypto_init_params ce_params;
+
+ /* Set up base addresses and instance. */
+ ce_params.crypto_instance = CRYPTO_ENGINE_INSTANCE;
+ ce_params.crypto_base = MSM_CE1_BASE;
+ ce_params.bam_base = MSM_CE1_BAM_BASE;
+
+ /* Set up BAM config. */
+ ce_params.bam_ee = CRYPTO_ENGINE_EE;
+ ce_params.pipes.read_pipe = CRYPTO_ENGINE_READ_PIPE;
+ ce_params.pipes.write_pipe = CRYPTO_ENGINE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CRYPTO_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CRYPTO_WRITE_PIPE_LOCK_GRP;
+
+ /* Assign buffer sizes. */
+ ce_params.num_ce = CRYPTO_ENGINE_CMD_ARRAY_SIZE;
+ ce_params.read_fifo_size = CRYPTO_ENGINE_FIFO_SIZE;
+ ce_params.write_fifo_size = CRYPTO_ENGINE_FIFO_SIZE;
+
+ ce_params.do_bam_init = 0;
+
+ crypto_init_params(&ce_params);
+}
+
+crypto_engine_type board_ce_type(void)
+{
+ return CRYPTO_ENGINE_TYPE_HW;
+}
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index 36f25a6..e352c46 100644
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -37,6 +37,7 @@
#include <board.h>
#include <platform/gpio.h>
#include <platform/iomap.h>
+#include <platform/pm_pwm.h>
#include <target/display.h>
#include "include/panel.h"
@@ -49,16 +50,29 @@
#define GPIO_STATE_HIGH 2
#define RESET_GPIO_SEQ_LEN 3
+#define PWM_DUTY_US 13
+#define PWM_PERIOD_US 27
+
int target_backlight_ctrl(uint8_t enable)
{
struct pm8x41_mpp mpp;
+ int rc;
+
mpp.base = PM8x41_MMP3_BASE;
- mpp.mode = MPP_HIGH;
mpp.vin = MPP_VIN3;
if (enable) {
+ pm_pwm_enable(false);
+ rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
+ if (rc < 0)
+ mpp.mode = MPP_HIGH;
+ else {
+ mpp.mode = MPP_DTEST1;
+ pm_pwm_enable(true);
+ }
pm8x41_config_output_mpp(&mpp);
pm8x41_enable_mpp(&mpp, MPP_ENABLE);
} else {
+ pm_pwm_enable(false);
pm8x41_enable_mpp(&mpp, MPP_DISABLE);
}
/* Need delay before power on regulators */
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index aef7cb2..d97140c 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -679,6 +679,8 @@
#ifdef SSD_ENABLE
clock_ce_disable(SSD_CE_INSTANCE_1);
#endif
+ if (crypto_initialized())
+ crypto_eng_cleanup();
}
void shutdown_device()
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index e877f27..ddee155 100644
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -36,7 +36,6 @@
#include <pm8x41_wled.h>
#include <board.h>
#include <mdp5.h>
-#include <endian.h>
#include <platform/gpio.h>
#include <platform/clock.h>
#include <platform/iomap.h>
@@ -111,6 +110,7 @@
pm8x41_wled_config(&wled_ctrl);
pm8x41_wled_sink_control(enable);
pm8x41_wled_iled_sync_control(enable);
+ pm8x41_wled_led_mod_enable(enable);
}
pm8x41_wled_enable(enable);
@@ -218,33 +218,6 @@
return NO_ERROR;
}
-static uint32_t response_value = 0;
-
-uint32_t target_read_panel_signature(uint32_t panel_signature)
-{
- uint32_t rec_buf[1];
- uint32_t *lp = rec_buf, data;
- int ret = response_value;
-
- if (ret && ret != panel_signature)
- goto exit_read_signature;
-
- ret = mipi_dsi_cmds_tx(&read_ddb_start_cmd, 1);
- if (ret)
- goto exit_read_signature;
- if (!mdss_dsi_cmds_rx(&lp, 1, 1))
- goto exit_read_signature;
-
- data = ntohl(*lp);
- data = data >> 8;
- response_value = data;
- if (response_value != panel_signature)
- ret = response_value;
-
-exit_read_signature:
- return ret;
-}
-
static int msm8974_mdss_edp_panel_clock(int enable)
{
if (enable) {