[msm7630]: Support local clock control for MDDI display
Change-Id: Ic8ed24a016efb8de8a83bbe8e34f8491dc6b4e1e
CRs-Fixed: 271867
diff --git a/platform/msm7x30/include/platform/iomap.h b/platform/msm7x30/include/platform/iomap.h
index 853c4b3..2e7e1c2 100644
--- a/platform/msm7x30/include/platform/iomap.h
+++ b/platform/msm7x30/include/platform/iomap.h
@@ -52,20 +52,33 @@
#define MSM_CLK_CTL_BASE 0xAB800000
#define MSM_CLK_CTL_SH2_BASE 0xABA01000
+
+#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off))
+#define REG_SH2_BASE(off) (MSM_CLK_CTL_SH2_BASE + (off))
+
#define SCSS_CLK_CTL 0xC0101004
#define SCSS_CLK_SEL 0xC0101008
#define MSM_USB_BASE 0xA3600000
-#define SH2_USBH_MD_REG 0xABA012BC
-#define SH2_USBH_NS_REG 0xABA012C0
+#define SH2_USBH_MD_REG REG_SH2_BASE(0x2BC)
+#define SH2_USBH_NS_REG REG_SH2_BASE(0x2C0)
-#define SH2_MDP_NS_REG 0xABA0114C
-#define SH2_MDP_LCDC_MD_REG 0xABA0138C
-#define SH2_MDP_LCDC_NS_REG 0xABA01390
-#define SH2_MDP_VSYNC_REG 0xABA01460
+#define SH2_MDP_NS_REG REG_SH2_BASE(0x14C)
+#define SH2_MDP_LCDC_MD_REG REG_SH2_BASE(0x38C)
+#define SH2_MDP_LCDC_NS_REG REG_SH2_BASE(0x390)
+#define SH2_MDP_VSYNC_REG REG_SH2_BASE(0x460)
+#define SH2_PMDH_NS_REG REG_SH2_BASE(0x8C)
-#define SH2_GLBL_CLK_ENA_SC 0xABA013BC
-#define SH2_GLBL_CLK_ENA_2_SC 0xABA013C0
+#define SH2_GLBL_CLK_ENA_SC REG_SH2_BASE(0x3BC)
+#define SH2_GLBL_CLK_ENA_2_SC REG_SH2_BASE(0x3C0)
+
+#define SH2_OWN_ROW1_BASE_REG REG_BASE(0x041C)
+#define SH2_OWN_ROW2_BASE_REG REG_BASE(0x0424)
+#define SH2_OWN_APPS2_BASE_REG REG_BASE(0x0414)
#define MSM_SAW_BASE 0xC0102000
+
+#define PLL_ENA_REG REG_SH2_BASE(0x0264)
+#define PLL2_STATUS_BASE_REG REG_BASE(0x0350)
+#define PLL2_L_VAL_ADDR REG_BASE(0x033C)
#endif