Merge "pm8x41: Adding support for output pmic gpios"
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 94436b1..7f849dc 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -43,6 +43,22 @@
#define PM_GPIO_PULL_RESV_1 4
#define PM_GPIO_PULL_RESV_2 5
+
+#define PM_GPIO_OUT_CMOS 0x00
+#define PM_GPIO_OUT_DRAIN_NMOS 0x01
+#define PM_GPIO_OUT_DRAIN_PMOS 0x02
+
+#define PM_GPIO_OUT_DRIVE_LOW 0x01
+#define PM_GPIO_OUT_DRIVE_MED 0x02
+#define PM_GPIO_OUT_DRIVE_HIGH 0x03
+
+
+#define PM_GPIO_FUNC_LOW 0x00
+#define PM_GPIO_FUNC_HIGH 0x01
+
+#define PM_GPIO_MODE_MASK 0x70
+#define PM_GPIO_OUTPUT_MASK 0x0F
+
#define PON_PSHOLD_WARM_RESET 0x1
struct pm8x41_gpio {
@@ -58,6 +74,7 @@
};
int pm8x41_gpio_get(uint8_t gpio, uint8_t *status);
+int pm8x41_gpio_set(uint8_t gpio, uint8_t value);
int pm8x41_gpio_config(uint8_t gpio, struct pm8x41_gpio *config);
void pm8x41_set_boot_done();
int pm8x41_vol_down_key_status();
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index c547a75..39d4000 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -95,9 +95,6 @@
uint8_t val;
uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
- /* Only input configuration is implemented at this time. */
- ASSERT(config->direction == PM_GPIO_DIR_IN);
-
/* Disable the GPIO */
val = REG_READ(gpio_base + GPIO_EN_CTL);
val &= ~BIT(PERPH_EN_BIT);
@@ -115,12 +112,18 @@
val = config->vin_sel;
REG_WRITE(gpio_base + GPIO_DIG_VIN_CTL, val);
+ if (config->direction == PM_GPIO_DIR_OUT) {
+ /* Set the right dig out control */
+ val = config->out_strength | (config->output_buffer << 4);
+ REG_WRITE(gpio_base + GPIO_DIG_OUT_CTL, val);
+ }
+
/* Enable the GPIO */
val = REG_READ(gpio_base + GPIO_EN_CTL);
val |= BIT(PERPH_EN_BIT);
REG_WRITE(gpio_base + GPIO_EN_CTL, val);
- return 1;
+ return 0;
}
/* Reads the status of requested gpio */
@@ -135,7 +138,21 @@
dprintf(SPEW, "GPIO %d status is %d\n", gpio, *status);
- return 1;
+ return 0;
+}
+
+/* Write the output value of the requested gpio */
+int pm8x41_gpio_set(uint8_t gpio, uint8_t value)
+{
+ uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
+ uint8_t val;
+
+ /* Set the output value of the gpio */
+ val = REG_READ(gpio_base + GPIO_MODE_CTL);
+ val = (val & ~PM_GPIO_OUTPUT_MASK) | value;
+ REG_WRITE(gpio_base + GPIO_MODE_CTL, val);
+
+ return 0;
}
/* Prepare PON RESIN S2 reset */