Merge "fbcon: Read the splash image from splash partition"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
old mode 100644
new mode 100755
index 79061f5..74c81b1
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -93,9 +93,14 @@
#define RECOVERY_MODE 0x77665502
#define FASTBOOT_MODE 0x77665500
+/* make 4096 as default size to ensure EFS,EXT4's erasing */
+#define DEFAULT_ERASE_SIZE 4096
+#define MAX_PANEL_BUF_SIZE 64
+
static const char *emmc_cmdline = " androidboot.emmc=true";
static const char *usb_sn_cmdline = " androidboot.serialno=";
static const char *androidboot_mode = " androidboot.mode=";
+static const char *display_cmdline = " mdss_mdp.panel=";
static const char *loglevel = " quiet";
static const char *battchg_pause = " androidboot.mode=charger";
static const char *auth_kernel = " androidboot.authorized_kernel=true";
@@ -155,6 +160,7 @@
char max_download_size[MAX_RSP_SIZE];
char charger_screen_enabled[MAX_RSP_SIZE];
char sn_buf[13];
+char display_panel_buf[MAX_PANEL_BUF_SIZE];
extern int emmc_recovery_init(void);
@@ -262,6 +268,13 @@
break;
}
+ if (target_display_panel_node(display_panel_buf, MAX_PANEL_BUF_SIZE) &&
+ strlen(display_panel_buf))
+ {
+ cmdline_len += strlen(display_cmdline);
+ cmdline_len += strlen(display_panel_buf);
+ }
+
if (cmdline_len > 0) {
const char *src;
unsigned char *dst = (unsigned char*) malloc((cmdline_len + 4) & (~3));
@@ -373,7 +386,18 @@
while ((*dst++ = *src++));
break;
}
+
+ if (strlen(display_panel_buf)) {
+ src = display_cmdline;
+ if (have_cmdline) --dst;
+ while ((*dst++ = *src++));
+ src = display_panel_buf;
+ if (have_cmdline) --dst;
+ while ((*dst++ = *src++));
+ }
}
+
+
dprintf(INFO, "cmdline: %s\n", cmdline_final);
return cmdline_final;
}
@@ -1494,8 +1518,9 @@
void cmd_erase_mmc(const char *arg, void *data, unsigned sz)
{
- BUF_DMA_ALIGN(out, 512);
+ BUF_DMA_ALIGN(out, DEFAULT_ERASE_SIZE);
unsigned long long ptn = 0;
+ unsigned long long size;
int index = INVALID_PTN;
index = partition_get_index(arg);
@@ -1505,9 +1530,14 @@
fastboot_fail("Partition table doesn't exist\n");
return;
}
+
+ size = partition_get_size(index);
+ if (size > DEFAULT_ERASE_SIZE)
+ size = DEFAULT_ERASE_SIZE;
+
/* Simple inefficient version of erase. Just writing
- 0 in first block */
- if (mmc_write(ptn , 512, (unsigned int *)out)) {
+ 0 in first several blocks */
+ if (mmc_write(ptn , size, (unsigned int *)out)) {
fastboot_fail("failed to erase partition");
return;
}
@@ -2133,6 +2163,8 @@
target_serialno((unsigned char *) sn_buf);
dprintf(SPEW,"serial number: %s\n",sn_buf);
+ memset(display_panel_buf, '\0', MAX_PANEL_BUF_SIZE);
+
/* Check if we should do something other than booting up */
if (keys_get_state(KEY_VOLUMEUP) && keys_get_state(KEY_VOLUMEDOWN))
{
diff --git a/app/aboot/fastboot.c b/app/aboot/fastboot.c
index 66d0437..67bd760 100644
--- a/app/aboot/fastboot.c
+++ b/app/aboot/fastboot.c
@@ -159,6 +159,100 @@
event_signal(&txn_done, 0);
}
+#ifdef USB30_SUPPORT
+static int usb_read(void *buf, unsigned len)
+{
+ int r;
+ struct udc_request req;
+
+ ASSERT(buf);
+ ASSERT(len);
+
+ if (fastboot_state == STATE_ERROR)
+ goto oops;
+
+ dprintf(SPEW, "usb_read(): len = %d\n", len);
+
+ req.buf = (void*) PA((addr_t)buf);
+ req.length = len;
+ req.complete = req_complete;
+
+ r = udc_request_queue(out, &req);
+ if (r < 0)
+ {
+ dprintf(CRITICAL, "usb_read() queue failed. r = %d\n", r);
+ goto oops;
+ }
+ event_wait(&txn_done);
+
+ if (txn_status < 0)
+ {
+ dprintf(CRITICAL, "usb_read() transaction failed. txn_status = %d\n",
+ txn_status);
+ goto oops;
+ }
+
+ /* note: req->length is update by callback to reflect the amount of data
+ * actually read.
+ */
+ dprintf(SPEW, "usb_read(): DONE. req.length = %d\n", req.length);
+
+ /* invalidate any cached buf data (controller updates main memory) */
+ arch_invalidate_cache_range((addr_t) buf, len);
+
+ return req.length;
+
+oops:
+ fastboot_state = STATE_ERROR;
+ dprintf(CRITICAL, "usb_read(): DONE: ERROR: len = %d\n", len);
+ return -1;
+}
+
+static int usb_write(void *buf, unsigned len)
+{
+ int r;
+ struct udc_request req;
+
+ ASSERT(buf);
+ ASSERT(len);
+
+ if (fastboot_state == STATE_ERROR)
+ goto oops;
+
+ dprintf(SPEW, "usb_write(): len = %d str = %s\n", len, (char *) buf);
+
+ /* flush buffer to main memory before giving to udc */
+ arch_clean_invalidate_cache_range((addr_t) buf, len);
+
+ req.buf = (void*) PA((addr_t)buf);
+ req.length = len;
+ req.complete = req_complete;
+
+ r = udc_request_queue(in, &req);
+ if (r < 0) {
+ dprintf(CRITICAL, "usb_write() queue failed. r = %d\n", r);
+ goto oops;
+ }
+ event_wait(&txn_done);
+
+ dprintf(SPEW, "usb_write(): DONE: len = %d req->length = %d str = %s\n",
+ len, req.length, (char *) buf);
+
+ if (txn_status < 0) {
+ dprintf(CRITICAL, "usb_write() transaction failed. txn_status = %d\n",
+ txn_status);
+ goto oops;
+ }
+
+ return req.length;
+
+oops:
+ fastboot_state = STATE_ERROR;
+ dprintf(CRITICAL, "usb_write(): DONE: ERROR: len = %d\n", len);
+ return -1;
+}
+
+#else
static int usb_read(void *_buf, unsigned len)
{
int r;
@@ -231,6 +325,7 @@
fastboot_state = STATE_ERROR;
return -1;
}
+#endif
void fastboot_ack(const char *code, const char *reason)
{
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 169fb1c..1d50e89 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -31,6 +31,8 @@
#include <err.h>
#include <smem.h>
#include <msm_panel.h>
+#include <string.h>
+#include <stdlib.h>
#include <board.h>
#include <mdp5.h>
#include <platform/gpio.h>
@@ -51,7 +53,6 @@
static uint8_t display_enable;
static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db;
-
/*---------------------------------------------------------------------------*/
/* Extern */
/*---------------------------------------------------------------------------*/
@@ -76,7 +77,7 @@
uint32_t ret = NO_ERROR;
ret = target_panel_reset(enable, &reset_gpio,
- &enable_gpio, &reset_sequence);
+ &enable_gpio, panelstruct.panelresetseq);
return ret;
}
@@ -149,6 +150,36 @@
return ret;
}
+bool target_display_panel_node(char *pbuf, uint16_t buf_size)
+{
+ char *dsi_id = panelstruct.paneldata->panel_controller;
+ char *panel_node = panelstruct.paneldata->panel_node_id;
+ bool ret = true;
+
+ if (buf_size < (strlen(panel_node) + MAX_DSI_STREAM_LEN +
+ MAX_PANEL_FORMAT_STRING + 1) ||
+ !strlen(panel_node) ||
+ !strlen(dsi_id))
+ {
+ ret = false;
+ }
+ else
+ {
+ pbuf[0] = '1'; // 1 indicates that LK is overriding the panel
+ pbuf[1] = ':'; // seperator
+ pbuf += MAX_PANEL_FORMAT_STRING;
+ buf_size -= MAX_PANEL_FORMAT_STRING;
+
+ strlcpy(pbuf, dsi_id, buf_size);
+ pbuf += MAX_DSI_STREAM_LEN;
+ buf_size -= MAX_DSI_STREAM_LEN;
+
+ strlcpy(pbuf, panel_node, buf_size);
+ }
+ return ret;
+}
+
+
static void init_platform_data()
{
memcpy(dsi_video_mode_phy_db.regulator, panel_regulator_settings,
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index dd6a6a8..6d647b2 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -43,6 +43,10 @@
#define BIST_SIZE 6
#define LANE_SIZE 45
+#define MAX_DSI_STREAM_LEN 6
+
+#define MAX_PANEL_FORMAT_STRING 2
+
/*---------------------------------------------------------------------------*/
/* API */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/display_resource.h b/dev/gcdb/display/include/display_resource.h
index 24a375d..c469ec8 100755
--- a/dev/gcdb/display/include/display_resource.h
+++ b/dev/gcdb/display/include/display_resource.h
@@ -37,8 +37,6 @@
#include <smem.h>
#include <board.h>
-#define TOTAL_RESET_GPIO_CTRL 5
-
#define TOTAL_LDO_CTRL 5
/*---------------------------------------------------------------------------*/
@@ -56,13 +54,6 @@
uint32_t pin_state;
};
-typedef struct panel_reset_sequence {
-
- uint8_t pin_state[TOTAL_RESET_GPIO_CTRL];
- uint32_t sleep[TOTAL_RESET_GPIO_CTRL];
- uint8_t pin_direction;
-};
-
/*LDO entry structure for different LDO entries. */
typedef struct ldo_entry{
char *ldo_name;
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index 3056fbf..8a762bd 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -36,6 +36,8 @@
#include <debug.h>
#include <smem.h>
+#define TOTAL_RESET_GPIO_CTRL 5
+
/*---------------------------------------------------------------------------*/
/* Structure definition */
/*---------------------------------------------------------------------------*/
@@ -43,7 +45,7 @@
/*Panel Configuration */
typedef struct panel_config{
- char *panel_name;
+ char *panel_node_id;
char *panel_controller;
char *panel_compatible;
uint16_t panel_interface;
@@ -150,6 +152,12 @@
BL_LPG,
};
+typedef struct panel_reset_sequence {
+ uint8_t pin_state[TOTAL_RESET_GPIO_CTRL];
+ uint32_t sleep[TOTAL_RESET_GPIO_CTRL];
+ uint8_t pin_direction;
+};
+
typedef struct backlight {
uint16_t bl_interface_type;
uint16_t bl_min_level;
diff --git a/dev/gcdb/display/include/panel_hx8394a_720p_video.h b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
index fd62f1e..36a88bc 100644
--- a/dev/gcdb/display/include/panel_hx8394a_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
@@ -46,7 +46,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config hx8394a_720p_video_panel_data = {
- "hx8394a 720p video mode dsi panel", "mdss_dsi0", "qcom,mdss-dsi-panel",
+ "qcom,mdss_dsi_hx8394a_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
10, 0, "DISPLAY_1", 0, 424000000, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
@@ -265,6 +265,10 @@
0, 4, 0x1f, 0x2d
};
+static struct panel_reset_sequence hx8394a_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35521_720p_video.h b/dev/gcdb/display/include/panel_nt35521_720p_video.h
index e25360c..c5f9069 100644
--- a/dev/gcdb/display/include/panel_nt35521_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35521_720p_video.h
@@ -46,7 +46,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config nt35521_720p_video_panel_data = {
- "nt35521 720p video mode dsi panel", "mdss_dsi0", "qcom,mdss-dsi-panel",
+ "qcom,mdss_dsi_nt35521_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
10, 0, "DISPLAY_1", 0, 424000000, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
@@ -1466,6 +1466,10 @@
0, 4, 0x20, 0x2D
};
+static struct panel_reset_sequence nt35521_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
index 59fe531..47ec49f 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
@@ -46,7 +46,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config nt35590_720p_cmd_panel_data = {
- "nt25590 720p command mode dsi panel", "mdss_dsi0", "qcom,mdss-dsi-panel",
+ "qcom,mdss_dsi_nt35590_720p_cmd", "dsi:0:", "qcom,mdss-dsi-panel",
10, 1, "DISPLAY_1", 0, 424000000, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
@@ -2923,6 +2923,10 @@
0, 4, 0x20, 0x2c
};
+static struct panel_reset_sequence nt35590_720p_cmd_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_video.h b/dev/gcdb/display/include/panel_nt35590_720p_video.h
index c144f14..ce740a7 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_video.h
@@ -46,7 +46,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config nt35590_720p_video_panel_data = {
- "nt25590 720p video mode dsi panel", "mdss_dsi0", "qcom,mdss-dsi-panel",
+ "qcom,mdss_dsi_nt35590_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
10, 0, "DISPLAY_1", 0, 424000000, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
@@ -2923,6 +2923,10 @@
0, 4, 0x20, 0x2c
};
+static struct panel_reset_sequence nt35590_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35596_1080p_video.h b/dev/gcdb/display/include/panel_nt35596_1080p_video.h
index d90dff9..3d35b61 100644
--- a/dev/gcdb/display/include/panel_nt35596_1080p_video.h
+++ b/dev/gcdb/display/include/panel_nt35596_1080p_video.h
@@ -46,7 +46,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config nt35596_1080p_video_panel_data = {
- "nt35596 1080p video mode dsi panel", "mdss_dsi0", "qcom,mdss-dsi-panel",
+ "qcom,mdss_dsi_nt35596_1080p_video", "dsi:0:", "qcom,mdss-dsi-panel",
10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
@@ -3251,6 +3251,10 @@
0, 4, 0x1e, 0x38
};
+static struct panel_reset_sequence nt35596_1080p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_toshiba_720p_video.h b/dev/gcdb/display/include/panel_toshiba_720p_video.h
index 8f3cd68..312aade 100755
--- a/dev/gcdb/display/include/panel_toshiba_720p_video.h
+++ b/dev/gcdb/display/include/panel_toshiba_720p_video.h
@@ -46,7 +46,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config toshiba_720p_video_panel_data = {
- "toshiba 720p video mode dsi panel", "mdss_dsi0", "qcom,mdss-dsi-panel",
+ "qcom,mdss_dsi_toshiba_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
10, 0, "DISPLAY_1", 0, 424000000, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
};
@@ -332,6 +332,10 @@
0x0, 0x04, 0x04, 0x1b
};
+static struct panel_reset_sequence toshiba_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 200, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/oem_panel.c b/dev/gcdb/display/oem_panel.c
index b1e19e9..228dc6b 100755
--- a/dev/gcdb/display/oem_panel.c
+++ b/dev/gcdb/display/oem_panel.c
@@ -112,6 +112,8 @@
panelstruct->laneconfig = &toshiba_720p_video_lane_config;
panelstruct->paneltiminginfo
= &toshiba_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &toshiba_720p_video_panel_reset_seq;
panelstruct->backlightinfo = &toshiba_720p_video_backlight;
pinfo->mipi.panel_cmds
= toshiba_720p_video_on_command;
@@ -130,6 +132,8 @@
panelstruct->laneconfig = &nt35590_720p_video_lane_config;
panelstruct->paneltiminginfo
= &nt35590_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35590_720p_video_panel_reset_seq;
panelstruct->backlightinfo = &nt35590_720p_video_backlight;
pinfo->mipi.panel_cmds
= nt35590_720p_video_on_command;
@@ -148,6 +152,8 @@
panelstruct->laneconfig = &nt35521_720p_video_lane_config;
panelstruct->paneltiminginfo
= &nt35521_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35521_720p_video_panel_reset_seq;
panelstruct->backlightinfo = &nt35521_720p_video_backlight;
pinfo->mipi.panel_cmds
= nt35521_720p_video_on_command;
@@ -166,6 +172,8 @@
panelstruct->laneconfig = &hx8394a_720p_video_lane_config;
panelstruct->paneltiminginfo
= &hx8394a_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8394a_720p_video_panel_reset_seq;
panelstruct->backlightinfo = &hx8394a_720p_video_backlight;
pinfo->mipi.panel_cmds
= hx8394a_720p_video_on_command;
@@ -184,6 +192,8 @@
panelstruct->state = &nt35590_720p_cmd_state;
panelstruct->laneconfig = &nt35590_720p_cmd_lane_config;
panelstruct->paneltiminginfo = &nt35590_720p_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &nt35590_720p_cmd_panel_reset_seq;
panelstruct->backlightinfo = &nt35590_720p_cmd_backlight;
pinfo->mipi.panel_cmds
= nt35590_720p_cmd_on_command;
@@ -202,6 +212,8 @@
panelstruct->laneconfig = &nt35596_1080p_video_lane_config;
panelstruct->paneltiminginfo
= &nt35596_1080p_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35596_1080p_video_panel_reset_seq;
panelstruct->backlightinfo
= &nt35596_1080p_video_backlight;
pinfo->mipi.panel_cmds
@@ -221,6 +233,11 @@
uint32_t hw_id = board_hardware_id();
uint32_t platformid = board_platform_id();
uint32_t target_id = board_target_id();
+ uint32_t nt35590_panel_id = NT35590_720P_VIDEO_PANEL;
+
+#if DISPLAY_TYPE_CMD_MODE
+ nt35590_panel_id = NT35590_720P_CMD_PANEL;
+#endif
switch (platformid) {
case MSM8974:
@@ -249,7 +266,7 @@
panel_id = NT35521_720P_VIDEO_PANEL;
} else {
if (((target_id >> 16) & 0xFF) == 0x1) //EVT
- panel_id = NT35590_720P_VIDEO_PANEL;
+ panel_id = nt35590_panel_id;
else if (((target_id >> 16) & 0xFF) == 0x2) //DVT
panel_id = HX8394A_720P_VIDEO_PANEL;
else {
@@ -261,7 +278,7 @@
break;
case HW_PLATFORM_MTP:
case HW_PLATFORM_SURF:
- panel_id = NT35590_720P_VIDEO_PANEL;
+ panel_id = nt35590_panel_id;
break;
default:
dprintf(CRITICAL, "Display not enabled for %d HW type\n"
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index 195a82c..e141a0c 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -43,15 +43,16 @@
/* struct definition */
/*---------------------------------------------------------------------------*/
typedef struct panel_struct{
- struct panel_config *paneldata;
- struct panel_resolution *panelres;
- struct color_info *color;
- struct videopanel_info *videopanel;
- struct commandpanel_info *commandpanel;
- struct command_state *state;
- struct lane_configuration *laneconfig;
- struct panel_timing *paneltiminginfo;
- struct backlight *backlightinfo;
+ struct panel_config *paneldata;
+ struct panel_resolution *panelres;
+ struct color_info *color;
+ struct videopanel_info *videopanel;
+ struct commandpanel_info *commandpanel;
+ struct command_state *state;
+ struct lane_configuration *laneconfig;
+ struct panel_timing *paneltiminginfo;
+ struct panel_reset_sequence *panelresetseq;
+ struct backlight *backlightinfo;
};
diff --git a/dev/panel/msm/mipi_hx8379a_video_wvga.c b/dev/panel/msm/mipi_hx8379a_video_wvga.c
index de04f2f..ce698f5 100644
--- a/dev/panel/msm/mipi_hx8379a_video_wvga.c
+++ b/dev/panel/msm/mipi_hx8379a_video_wvga.c
@@ -48,25 +48,22 @@
#define HX8379A_PANEL_BPP 24
#define HX8379A_PANEL_CLK_RATE 499000000
-#define MIPI_HSYNC_PULSE_WIDTH 17
-#define MIPI_HSYNC_BACK_PORCH_DCLK 90
-#define MIPI_HSYNC_FRONT_PORCH_DCLK 90
-#define MIPI_VSYNC_PULSE_WIDTH 6
-#define MIPI_VSYNC_BACK_PORCH_LINES 10
-#define MIPI_VSYNC_FRONT_PORCH_LINES 15
+#define MIPI_HSYNC_PULSE_WIDTH 40
+#define MIPI_HSYNC_BACK_PORCH_DCLK 100
+#define MIPI_HSYNC_FRONT_PORCH_DCLK 70
+#define MIPI_VSYNC_PULSE_WIDTH 4
+#define MIPI_VSYNC_BACK_PORCH_LINES 6
+#define MIPI_VSYNC_FRONT_PORCH_LINES 6
static char disp_on0[8] = {
0x04, 0x00, 0x39, 0xC0,
0xB9, 0xFF, 0x83, 0x79
};
-static char disp_on1[4] = {
- 0xBA, 0x51, 0x23, 0x80,
+static char disp_on1[8] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xBA, 0x51, 0x93, 0xFF
};
-static char disp_on2[8] = {
- 0x04, 0x00, 0x39, 0xC0,
- 0xDE, 0x05, 0x50, 0x04
-};
-static char disp_on3[24] = {
+static char disp_on2[24] = {
0x14, 0x00, 0x39, 0xC0,
0xB1, 0x00, 0x50, 0x44,
0xEA, 0x8D, 0x08, 0x11,
@@ -74,25 +71,25 @@
0x9A, 0x1A, 0x42, 0x0B,
0x6E, 0xF1, 0x00, 0xE6
};
-static char disp_on4[20] = {
+static char disp_on3[20] = {
0x0E, 0x00, 0x39, 0xC0,
0xB2, 0x00, 0x00, 0x3C,
0x08, 0x04, 0x19, 0x22,
0x00, 0xFF, 0x08, 0x04,
0x19, 0x20, 0xFF, 0xFF
};
-static char disp_on5[36] = {
+static char disp_on4[36] = {
0x20, 0x00, 0x39, 0xC0,
0xB4, 0x82, 0x08, 0x00,
0x32, 0x10, 0x03, 0x32,
0x13, 0x70, 0x32, 0x10,
0x08, 0x37, 0x01, 0x28,
- 0x07, 0x37, 0x08, 0x3A,
- 0x08, 0x42, 0x42, 0x08,
+ 0x07, 0x37, 0x08, 0x3C,
+ 0x08, 0x44, 0x44, 0x08,
0x00, 0x40, 0x08, 0x28,
0x08, 0x30, 0x30, 0x04
};
-static char disp_on6[52] = {
+static char disp_on5[52] = {
0x30, 0x00, 0x39, 0xC0,
0xD5, 0x00, 0x00, 0x0A,
0x00, 0x01, 0x05, 0x00,
@@ -107,30 +104,30 @@
0x88, 0x88, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
};
-static char disp_on7[40] = {
+static char disp_on6[40] = {
0x24, 0x00, 0x39, 0xC0,
0xE0, 0x79, 0x05, 0x0F,
0x14, 0x26, 0x29, 0x3F,
- 0x2B, 0x46, 0x04, 0x0E,
+ 0x2B, 0x44, 0x04, 0x0E,
0x12, 0x15, 0x18, 0x16,
- 0x16, 0x11, 0x17, 0x05,
+ 0x16, 0x12, 0x15, 0x05,
0x0F, 0x14, 0x26, 0x29,
- 0x3F, 0x2B, 0x46, 0x04,
+ 0x3F, 0x2B, 0x44, 0x04,
0x0E, 0x12, 0x15, 0x18,
- 0x16, 0x16, 0x11, 0x17
+ 0x16, 0x16, 0x12, 0x15
};
-static char disp_on8[4] = {
+static char disp_on7[4] = {
0xCC, 0x02, 0x23, 0x80,
};
-static char disp_on9[12] = {
+static char disp_on8[12] = {
0x05, 0x00, 0x39, 0xC0,
0xB6, 0x00, 0x9C, 0x00,
0x9C, 0xFF, 0xFF, 0xFF
};
-static char disp_on10[4] = {
+static char disp_on9[4] = {
0x11, 0x00, 0x05, 0x80
};
-static char disp_on11[4] = {
+static char disp_on10[4] = {
0x29, 0x00, 0x05, 0x80
};
@@ -146,7 +143,6 @@
{sizeof(disp_on8), (char *)disp_on8},
{sizeof(disp_on9), (char *)disp_on9},
{sizeof(disp_on10), (char *)disp_on10},
- {sizeof(disp_on11), (char *)disp_on11},
};
int mipi_hx8379a_video_wvga_config(void *pdata)
@@ -175,9 +171,9 @@
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
- (lcdc->h_back_porch),
+ (lcdc->h_back_porch + lcdc->h_pulse_width),
(lcdc->v_front_porch),
- (lcdc->v_back_porch),
+ (lcdc->v_back_porch + lcdc->v_pulse_width),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
@@ -206,8 +202,8 @@
/* regulator */
{0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
/* timing */
- {0x5d, 0x12, 0x0c, 0x00, 0x33, 0x39,
- 0x10, 0x16, 0x15, 0x03, 0x04, 0x00},
+ {0x75, 0x1A, 0x11, 0x00, 0x3D, 0x45,
+ 0x15, 0x1D, 0x1C, 0x03, 0x04, 0x00},
/* phy ctrl */
{0x7f, 0x00, 0x00, 0x00},
/* strength */
diff --git a/dev/panel/msm/mipi_nt35590_video_720p.c b/dev/panel/msm/mipi_nt35590_video_720p.c
index af74b43..9e53a8d 100644
--- a/dev/panel/msm/mipi_nt35590_video_720p.c
+++ b/dev/panel/msm/mipi_nt35590_video_720p.c
@@ -2425,22 +2425,22 @@
static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* 720x1280, RGB888, 4 Lane 60 fps video mode */
/* regulator */
- {0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01},
+ {0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
/* timing */
- {0x7d, 0x25, 0x1d, 0x00, 0x37, 0x33, 0x22, 0x27,
- 0x1e, 0x03, 0x04, 0x00},
+ {0x86, 0x1E, 0x14, 0x00, 0x43, 0x4D,
+ 0x19, 0x21, 0x30, 0x03, 0x04, 0x00},
/* phy ctrl */
- {0x5f, 0x00, 0x00, 0x10},
+ {0x7f, 0x00, 0x00, 0x00},
/* strength */
{0xff, 0x06},
/* bist control */
- {0x00, 0x00, 0xb1, 0xff, 0x00, 0x00},
+ {0x03, 0x03, 0x00, 0x00, 0x0f, 0x00},
/* lanes config */
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb},
+ {0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00},
};
void mipi_nt35590_video_720p_init(struct msm_panel_info *pinfo)
diff --git a/dev/panel/msm/mipi_otm8018b_video_fwvga.c b/dev/panel/msm/mipi_otm8018b_video_fwvga.c
index 4a7a179..9f0a7ee 100644
--- a/dev/panel/msm/mipi_otm8018b_video_fwvga.c
+++ b/dev/panel/msm/mipi_otm8018b_video_fwvga.c
@@ -540,9 +540,9 @@
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
- (lcdc->h_back_porch),
+ (lcdc->h_back_porch + lcdc->h_pulse_width),
(lcdc->v_front_porch),
- (lcdc->v_back_porch),
+ (lcdc->v_back_porch + lcdc->v_pulse_width),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
diff --git a/dev/panel/msm/mipi_truly_video_wvga.c b/dev/panel/msm/mipi_truly_video_wvga.c
index fa757fe..44465ce 100644
--- a/dev/panel/msm/mipi_truly_video_wvga.c
+++ b/dev/panel/msm/mipi_truly_video_wvga.c
@@ -225,9 +225,9 @@
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
- (lcdc->h_back_porch),
+ (lcdc->h_back_porch + lcdc->h_pulse_width),
(lcdc->v_front_porch),
- (lcdc->v_back_porch),
+ (lcdc->v_back_porch + lcdc->v_pulse_width),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
diff --git a/dev/panel/msm/rules.mk b/dev/panel/msm/rules.mk
index ddeb6dd..cfce68d 100644
--- a/dev/panel/msm/rules.mk
+++ b/dev/panel/msm/rules.mk
@@ -38,5 +38,6 @@
$(LOCAL_DIR)/mipi_truly_video_wvga.o \
$(LOCAL_DIR)/mipi_truly_cmd_wvga.o \
$(LOCAL_DIR)/mipi_hx8379a_video_wvga.o \
- $(LOCAL_DIR)/mipi_otm8018b_video_fwvga.o
+ $(LOCAL_DIR)/mipi_otm8018b_video_fwvga.o \
+ $(LOCAL_DIR)/mipi_nt35590_video_720p.o
endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_wled.h b/dev/pmic/pm8x41/include/pm8x41_wled.h
index 0ef9091..300c0b9 100644
--- a/dev/pmic/pm8x41/include/pm8x41_wled.h
+++ b/dev/pmic/pm8x41/include/pm8x41_wled.h
@@ -42,6 +42,7 @@
#define PM_WLED_LED3_BRIGHTNESS_MSB PM_WLED_CTNL_REG(0x45)
#define PM_WLED_ENABLE PM_WLED_CTNL_REG(0x46)
#define PM_WLED_ILED_SYNC_BIT PM_WLED_CTNL_REG(0x47)
+#define PM_WLED_FDBCK_CONTROL PM_WLED_CTNL_REG(0x48)
#define PM_WLED_MODULATION_SCHEME PM_WLED_CTNL_REG(0x4A)
#define PM_WLED_MAX_DUTY_CYCLE PM_WLED_CTNL_REG(0x4B)
#define PM_WLED_OVP PM_WLED_CTNL_REG(0x4D)
@@ -65,7 +66,8 @@
uint16_t led3_brightness;
uint8_t max_duty_cycle;
uint8_t ovp;
- uint8_t full_current_scale;;
+ uint8_t full_current_scale;
+ uint8_t fdbck;
};
void pm8x41_wled_config(struct pm8x41_wled_data *wled_ctrl);
diff --git a/dev/pmic/pm8x41/pm8x41_adc.c b/dev/pmic/pm8x41/pm8x41_adc.c
index 6e4aa29..a4b3a82 100644
--- a/dev/pmic/pm8x41/pm8x41_adc.c
+++ b/dev/pmic/pm8x41/pm8x41_adc.c
@@ -242,7 +242,7 @@
calib_result = vadc_calibrate(result, adc->calib_type);
- dprintf(SPEW, "Result: Raw %u\tCalibrated:%llu\n", result, calib_result);
+ dprintf(SPEW, "Result: Raw %u\tCalibrated:%u\n", result, calib_result);
return calib_result;
}
diff --git a/dev/pmic/pm8x41/pm8x41_wled.c b/dev/pmic/pm8x41/pm8x41_wled.c
index 8c37e12..e879f1f 100644
--- a/dev/pmic/pm8x41/pm8x41_wled.c
+++ b/dev/pmic/pm8x41/pm8x41_wled.c
@@ -72,6 +72,7 @@
wled_reg_write(LEDn_FULL_SCALE_CURRENT(2), wled_ctrl->full_current_scale);
wled_reg_write(LEDn_FULL_SCALE_CURRENT(3), wled_ctrl->full_current_scale);
+ wled_reg_write(PM_WLED_FDBCK_CONTROL, wled_ctrl->fdbck);
dprintf(SPEW, "WLED Configuration Success.\n");
}
@@ -98,8 +99,8 @@
if (enable) {
value = PM_WLED_LED1_ILED_SYNC_MASK |
- PM_WLED_LED1_ILED_SYNC_MASK |
- PM_WLED_LED1_ILED_SYNC_MASK;
+ PM_WLED_LED2_ILED_SYNC_MASK |
+ PM_WLED_LED3_ILED_SYNC_MASK;
}
wled_reg_write(PM_WLED_ILED_SYNC_BIT, value);
diff --git a/include/target.h b/include/target.h
index dc86864..45f1605 100644
--- a/include/target.h
+++ b/include/target.h
@@ -50,5 +50,6 @@
bool target_is_ssd_enabled(void);
struct mmc_device *target_mmc_device();
+bool target_display_panel_node(char *pbuf, uint16_t buf_size);
#endif
diff --git a/platform/apq8084/rules.mk b/platform/apq8084/rules.mk
index 4738c69..260dc2d 100644
--- a/platform/apq8084/rules.mk
+++ b/platform/apq8084/rules.mk
@@ -11,7 +11,7 @@
DEFINES += PERIPH_BLK_BLSP=1
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
MMC_SLOT=$(MMC_SLOT)
-DEFINES += TZ_SAVE_KERNEL_HASH
+#DEFINES += TZ_SAVE_KERNEL_HASH
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
diff --git a/platform/msm8610/acpuclock.c b/platform/msm8610/acpuclock.c
index 4376e68..ecb4854 100644
--- a/platform/msm8610/acpuclock.c
+++ b/platform/msm8610/acpuclock.c
@@ -166,16 +166,12 @@
}
}
-void clock_config_ce(uint8_t instance)
-{
-}
-
/* Configure MDP clock */
void mdp_clock_enable(void)
{
int ret;
- ret = clk_get_set_enable("axi_clk_src", 100000000, 1);
+ ret = clk_get_set_enable("axi_clk_src", 200000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set axi_clk_src ret = %d\n", ret);
@@ -445,3 +441,119 @@
vco_enable(0);
clk_disable(clk_get("dsi_ahb_clk"));
}
+
+
+void clock_ce_enable(uint8_t instance)
+{
+ int ret;
+ char clk_name[64];
+
+ snprintf(clk_name, 64, "ce%u_src_clk", instance);
+ ret = clk_get_set_enable(clk_name, 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, 64, "ce%u_core_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, 64, "ce%u_axi_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Wait for 48 * #pipes cycles.
+ * This is necessary as immediately after an access control reset (boot up)
+ * or a debug re-enable, the Crypto core sequentially clears its internal
+ * pipe key storage memory. If pipe key initialization writes are attempted
+ * during this time, they may be overwritten by the internal clearing logic.
+ */
+ udelay(1);
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+ struct clk *ahb_clk;
+ struct clk *cclk;
+ struct clk *axi_clk;
+ struct clk *src_clk;
+ char clk_name[64];
+
+ snprintf(clk_name, 64, "ce%u_src_clk", instance);
+ src_clk = clk_get(clk_name);
+
+ snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
+ ahb_clk = clk_get(clk_name);
+
+ snprintf(clk_name, 64, "ce%u_axi_clk", instance);
+ axi_clk = clk_get(clk_name);
+
+ snprintf(clk_name, 64, "ce%u_core_clk", instance);
+ cclk = clk_get(clk_name);
+
+ clk_disable(ahb_clk);
+ clk_disable(axi_clk);
+ clk_disable(cclk);
+ clk_disable(src_clk);
+
+ /* Some delay for the clocks to stabalize. */
+ udelay(1);
+}
+
+/* Function to asynchronously reset CE.
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+ if (instance == 1)
+ {
+ /* Start the block reset for CE */
+ writel(1, GCC_CE1_BCR);
+
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CE1_BCR);
+
+ udelay(2);
+ }
+ else
+ {
+ dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
+ ASSERT(0);
+ }
+}
+
+void clock_config_ce(uint8_t instance)
+{
+ /* Need to enable the clock before disabling since the clk_disable()
+ * has a check to default to nop when the clk_enable() is not called
+ * on that particular clock.
+ */
+ clock_ce_enable(instance);
+
+ clock_ce_disable(instance);
+
+ ce_async_reset(instance);
+
+ clock_ce_enable(instance);
+
+}
diff --git a/platform/msm8610/include/platform/clock.h b/platform/msm8610/include/platform/clock.h
index de50978..df08046 100644
--- a/platform/msm8610/include/platform/clock.h
+++ b/platform/msm8610/include/platform/clock.h
@@ -79,5 +79,7 @@
void mdp_clock_disable(void);
void dsi_clock_enable(uint32_t dsiclk_rate, uint32_t byteclk_rate);
void dsi_clock_disable(void);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
#endif
diff --git a/platform/msm8610/include/platform/iomap.h b/platform/msm8610/include/platform/iomap.h
index f9f1c27..7999453 100644
--- a/platform/msm8610/include/platform/iomap.h
+++ b/platform/msm8610/include/platform/iomap.h
@@ -246,4 +246,13 @@
#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+
+/* CE 1 */
+#define GCC_CE1_BCR (CLK_CTL_BASE + 0x1040)
+#define GCC_CE1_CMD_RCGR (CLK_CTL_BASE + 0x1050)
+#define GCC_CE1_CFG_RCGR (CLK_CTL_BASE + 0x1054)
+#define GCC_CE1_CBCR (CLK_CTL_BASE + 0x1044)
+#define GCC_CE1_AXI_CBCR (CLK_CTL_BASE + 0x1048)
+#define GCC_CE1_AHB_CBCR (CLK_CTL_BASE + 0x104C)
+
#endif
diff --git a/platform/msm8610/msm8610-clock.c b/platform/msm8610/msm8610-clock.c
index 95cb4d3..1ed04f7 100644
--- a/platform/msm8610/msm8610-clock.c
+++ b/platform/msm8610/msm8610-clock.c
@@ -316,6 +316,7 @@
static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
F_MM(19200000, cxo, 1, 0, 0),
F_MM(100000000, gpll0, 6, 0, 0),
+ F_MM(200000000, gpll0, 3, 0, 0),
F_END
};
@@ -449,6 +450,58 @@
},
};
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_CE1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_CE1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_ce1_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "ce1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct vote_clk gcc_ce1_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(5),
+
+ .c = {
+ .dbg_name = "gcc_ce1_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(3),
+
+ .c = {
+ .dbg_name = "gcc_ce1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(4),
+
+ .c = {
+ .dbg_name = "gcc_ce1_axi_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
/* Clock lookup table */
static struct clk_lookup msm_clocks_8610[] =
{
@@ -478,6 +531,11 @@
CLK_LOOKUP("dsi_byte_clk", dsi_byte_clk.c),
CLK_LOOKUP("dsi_esc_clk", dsi_esc_clk.c),
CLK_LOOKUP("dsi_pclk_clk", dsi_pclk_clk.c),
+
+ CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
+ CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
+ CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+ CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
};
void platform_clock_init(void)
diff --git a/platform/msm8610/rules.mk b/platform/msm8610/rules.mk
index b050c3d..234432f 100644
--- a/platform/msm8610/rules.mk
+++ b/platform/msm8610/rules.mk
@@ -11,7 +11,7 @@
DEFINES += PERIPH_BLK_BLSP=1
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
- MMC_SLOT=$(MMC_SLOT)
+ MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
diff --git a/platform/msm_shared/include/clock_lib2.h b/platform/msm_shared/include/clock_lib2.h
index 008d5fa..7998a89 100644
--- a/platform/msm_shared/include/clock_lib2.h
+++ b/platform/msm_shared/include/clock_lib2.h
@@ -29,10 +29,10 @@
#ifndef __CLOCK_LIB2_H
#define __CLOCK_LIB2_H
+#include <bits.h>
/*
* Bit manipulation macros
*/
-#define BIT(n) (1 << (n))
#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index 169dce5..d83fa9e 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -45,6 +45,7 @@
unsigned long vsync_period_intmd;
struct lcdc_panel_info *lcdc = NULL;
int ystride = 3;
+ int mdp_rev = mdp_get_revision();
if (pinfo == NULL)
return ERR_INVALID_ARGS;
@@ -59,6 +60,10 @@
lcdc->h_back_porch + 1;
vsync_period_intmd = pinfo->yres + lcdc->v_front_porch + \
lcdc->v_back_porch + 1;
+ if (mdp_rev == MDP_REV_304) {
+ hsync_period += lcdc->h_pulse_width - 1;
+ vsync_period_intmd += lcdc->v_pulse_width - 1;
+ }
vsync_period = vsync_period_intmd * hsync_period;
// ------------- programming MDP_DMA_P_CONFIG ---------------------
@@ -73,12 +78,23 @@
writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
writel(lcdc->v_pulse_width * hsync_period, \
MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
- writel((pinfo->xres + lcdc->h_back_porch - 1) << 16 | \
- lcdc->h_back_porch, MDP_DSI_VIDEO_DISPLAY_HCTL);
- writel(lcdc->v_back_porch * hsync_period, \
- MDP_DSI_VIDEO_DISPLAY_V_START);
- writel((pinfo->yres + lcdc->v_back_porch) * hsync_period,
+ if (mdp_rev == MDP_REV_304) {
+ writel((pinfo->xres + lcdc->h_back_porch + \
+ lcdc->h_pulse_width - 1) << 16 | \
+ lcdc->h_back_porch + lcdc->h_pulse_width, \
+ MDP_DSI_VIDEO_DISPLAY_HCTL);
+ writel((lcdc->v_back_porch + lcdc->v_pulse_width) \
+ * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
+ writel(vsync_period - lcdc->v_front_porch * hsync_period - 1,
MDP_DSI_VIDEO_DISPLAY_V_END);
+ } else {
+ writel((pinfo->xres + lcdc->h_back_porch - 1) << 16 | \
+ lcdc->h_back_porch, MDP_DSI_VIDEO_DISPLAY_HCTL);
+ writel(lcdc->v_back_porch * hsync_period, \
+ MDP_DSI_VIDEO_DISPLAY_V_START);
+ writel((pinfo->yres + lcdc->v_back_porch) * hsync_period,
+ MDP_DSI_VIDEO_DISPLAY_V_END);
+ }
writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 92d575e..1a92f3e 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -855,7 +855,8 @@
writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
ctl_base + VIDEO_MODE_ACTIVE_V);
- if (mdp_get_revision() >= MDP_REV_41) {
+ if (mdp_get_revision() >= MDP_REV_41 ||
+ mdp_get_revision() == MDP_REV_304) {
writel(((disp_height + vsync_porch0_fp
+ vsync_porch0_bp - 1) << 16)
| (disp_width + hsync_porch0_fp
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 9b7ff98..ccf164c 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -10,7 +10,6 @@
$(LOCAL_DIR)/debug.o \
$(LOCAL_DIR)/smem.o \
$(LOCAL_DIR)/smem_ptable.o \
- $(LOCAL_DIR)/hsusb.o \
$(LOCAL_DIR)/jtag_hook.o \
$(LOCAL_DIR)/jtag.o \
$(LOCAL_DIR)/partition_parser.o \
@@ -170,6 +169,7 @@
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
$(LOCAL_DIR)/dev_tree.o \
+ $(LOCAL_DIR)/scm.o \
$(LOCAL_DIR)/gpio.o
endif
@@ -187,7 +187,8 @@
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
$(LOCAL_DIR)/dev_tree.o \
- $(LOCAL_DIR)/gpio.o
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/scm.o
endif
ifeq ($(PLATFORM),msm7x27a)
@@ -279,3 +280,14 @@
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/dload_util.o
endif
+
+ifeq ($(ENABLE_USB30_SUPPORT),1)
+ OBJS += \
+ $(LOCAL_DIR)/usb30_dwc.o \
+ $(LOCAL_DIR)/usb30_dwc_hw.o \
+ $(LOCAL_DIR)/usb30_udc.o \
+ $(LOCAL_DIR)/usb30_wrapper.o
+else
+ OBJS += \
+ $(LOCAL_DIR)/hsusb.o
+endif
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index ba77c86..4838b6f 100755
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -292,6 +292,7 @@
MSM8125 = 167,
MDM9310 = 171,
APQ8064AA = 172, /* aka V2 SLOW_PRIME */
+ APQ8084 = 178,
MSM8130 = 179,
MSM8130AA = 180,
MSM8130AB = 181,
@@ -302,6 +303,9 @@
MSM8674 = 186,
FSM9900 = 188,
MSM8974AC = 194,
+ MSMSAMARIUM9 = 195,
+ MSMSAMARIUM2 = 196,
+ MSMSAMARIUM0 = 197,
MSM8126 = 198,
APQ8026 = 199,
MSM8926 = 200,
@@ -317,6 +321,12 @@
MSM8674AC = 216,
MSM8974AA = 217,
MSM8974AB = 218,
+ APQ8028 = 219,
+ MSM8128 = 220,
+ MSM8228 = 221,
+ MSM8528 = 222,
+ MSM8628 = 223,
+ MSM8928 = 224,
};
enum platform {
@@ -343,7 +353,6 @@
enum platform_subtype {
HW_PLATFORM_SUBTYPE_UNKNOWN = 0,
HW_PLATFORM_SUBTYPE_MDM = 1,
- HW_PLATFORM_SUBTYPE_8974PRO_PM8084 = 1,
HW_PLATFORM_SUBTYPE_CSFB = 1,
HW_PLATFORM_SUBTYPE_SVLTE1 = 2,
HW_PLATFORM_SUBTYPE_SVLTE2A = 3,
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
new file mode 100644
index 0000000..1347bd8
--- /dev/null
+++ b/platform/msm_shared/usb30_dwc.c
@@ -0,0 +1,1822 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* This code implements the DesignWare Cores USB 3.0 driver. This file only
+ * implements the state machine and higher level logic as described in the
+ * SNPS DesignWare Cores SS USB3.0 Controller databook.
+ * Another file (dwc_hw.c) file implements the functions to interact with
+ * the dwc hardware registers directly.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <bits.h>
+#include <string.h>
+#include <malloc.h>
+#include <stdlib.h>
+#include <arch/defines.h>
+#include <platform/timer.h>
+#include <platform/interrupts.h>
+#include <platform/irqs.h>
+#include <kernel/event.h>
+#include <usb30_dwc.h>
+#include <usb30_dwc_hw.h>
+#include <usb30_dwc_hwio.h>
+
+//#define DEBUG_USB
+
+#ifdef DEBUG_USB
+#define DBG(...) dprintf(ALWAYS, __VA_ARGS__)
+#else
+#define DBG(...)
+#endif
+
+#define ERR(...) dprintf(ALWAYS, __VA_ARGS__)
+
+/* debug only: enum string lookup for debug purpose */
+char* ss_link_state_lookup[20];
+char* hs_link_state_lookup[20];
+char* event_lookup_device[20];
+char* event_lookup_ep[20];
+char* dev_ctrl_state_lookup[20];
+char* ep_state_lookup[20];
+char* speed_lookup[20];
+char* cmd_lookup[20];
+
+/* debug only: initialize the enum lookup */
+void dwc_debug_lookup_init(void)
+{
+ /* EP event */
+ event_lookup_ep[DWC_EVENT_EP_CMD_COMPLETE] = "DWC_EVENT_EP_CMD_COMPLETE ";
+ event_lookup_ep[DWC_EVENT_EP_XFER_NOT_READY] = "DWC_EVENT_EP_XFER_NOT_READY ";
+ event_lookup_ep[DWC_EVENT_EP_XFER_IN_PROGRESS] = "DWC_EVENT_EP_XFER_IN_PROGRESS";
+ event_lookup_ep[DWC_EVENT_EP_XFER_COMPLETE] = "DWC_EVENT_EP_XFER_COMPLETE ";
+
+ /* Device event */
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_VENDOR_DEVICE_TEST_LMP] = "DWC_EVENT_DEVICE_EVENT_ID_VENDOR_DEVICE_TEST_LMP";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_BUFFER_OVERFLOW] = "DWC_EVENT_DEVICE_EVENT_ID_BUFFER_OVERFLOW ";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_GENERIC_CMD_COMPLETE] = "DWC_EVENT_DEVICE_EVENT_ID_GENERIC_CMD_COMPLETE ";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_ERRATIC_ERROR] = "DWC_EVENT_DEVICE_EVENT_ID_ERRATIC_ERROR ";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_SOF] = "DWC_EVENT_DEVICE_EVENT_ID_SOF ";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_SUSPEND_ENTRY] = "DWC_EVENT_DEVICE_EVENT_ID_SUSPEND_ENTRY ";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_HIBER] = "DWC_EVENT_DEVICE_EVENT_ID_HIBER ";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_WAKEUP] = "DWC_EVENT_DEVICE_EVENT_ID_WAKEUP ";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_USB_LINK_STATUS_CHANGE] = "DWC_EVENT_DEVICE_EVENT_ID_USB_LINK_STATUS_CHANGE";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_CONNECT_DONE] = "DWC_EVENT_DEVICE_EVENT_ID_CONNECT_DONE ";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_USB_RESET] = "DWC_EVENT_DEVICE_EVENT_ID_USB_RESET ";
+ event_lookup_device[DWC_EVENT_DEVICE_EVENT_ID_DISCONNECT] = "DWC_EVENT_DEVICE_EVENT_ID_DISCONNECT ";
+
+ /* Control state */
+ dev_ctrl_state_lookup[EP_FSM_INIT] = "EP_FSM_INIT ";
+ dev_ctrl_state_lookup[EP_FSM_SETUP] = "EP_FSM_SETUP ";
+ dev_ctrl_state_lookup[EP_FSM_CTRL_DATA] = "EP_FSM_CTRL_DATA ";
+ dev_ctrl_state_lookup[EP_FSM_WAIT_FOR_HOST_2] = "EP_FSM_WAIT_FOR_HOST_2";
+ dev_ctrl_state_lookup[EP_FSM_WAIT_FOR_HOST_3] = "EP_FSM_WAIT_FOR_HOST_3";
+ dev_ctrl_state_lookup[EP_FSM_STATUS_2] = "EP_FSM_STATUS_2 ";
+ dev_ctrl_state_lookup[EP_FSM_STATUS_3] = "EP_FSM_STATUS_3 ";
+ dev_ctrl_state_lookup[EP_FSM_STALL] = "EP_FSM_STALL ";
+
+ /* EP state */
+ ep_state_lookup[EP_STATE_INIT] = "EP_STATE_INIT";
+ ep_state_lookup[EP_STATE_INACTIVE] = "EP_STATE_INACTIVE";
+ ep_state_lookup[EP_STATE_START_TRANSFER] = "EP_STATE_START_TRANSFER";
+ ep_state_lookup[EP_STATE_XFER_IN_PROG] = "EP_STATE_XFER_IN_PROG";
+
+ /* HS link status */
+ hs_link_state_lookup[ON] = "ON ";
+ hs_link_state_lookup[L1] = "L1 ";
+ hs_link_state_lookup[L2] = "L2 ";
+ hs_link_state_lookup[DISCONNECTED] = "DISCONNECTED ";
+ hs_link_state_lookup[EARLY_SUSPEND] = "EARLY_SUSPEND";
+ hs_link_state_lookup[RESET] = "RESET ";
+ hs_link_state_lookup[RESUME] = "RESUME ";
+
+ /* SS link status */
+ ss_link_state_lookup[U0] = "U0 ";
+ ss_link_state_lookup[U1] = "U1 ";
+ ss_link_state_lookup[U2] = "U2 ";
+ ss_link_state_lookup[U3] = "U3 ";
+ ss_link_state_lookup[SS_DIS] = "SS_DIS ";
+ ss_link_state_lookup[RX_DET] = "RX_DET ";
+ ss_link_state_lookup[SS_INACT] = "SS_INACT ";
+ ss_link_state_lookup[POLL] = "POLL ";
+ ss_link_state_lookup[RECOV] = "RECOV ";
+ ss_link_state_lookup[HRESET] = "HRESET ";
+ ss_link_state_lookup[CMPLY] = "CMPLY ";
+ ss_link_state_lookup[LPBK] = "LPBK ";
+ ss_link_state_lookup[RESUME_RESET] = "RESUME_RESET";
+
+ /* connection speed */
+ speed_lookup[DSTS_CONNECTSPD_HS] = "DSTS_CONNECTSPD_HS ";
+ speed_lookup[DSTS_CONNECTSPD_FS1] = "DSTS_CONNECTSPD_FS1";
+ speed_lookup[DSTS_CONNECTSPD_LS] = "DSTS_CONNECTSPD_LS ";
+ speed_lookup[DSTS_CONNECTSPD_FS2] = "DSTS_CONNECTSPD_FS1";
+ speed_lookup[DSTS_CONNECTSPD_SS] = "DSTS_CONNECTSPD_SS ";
+
+ /* dwc command */
+ cmd_lookup[DEPCMD_CMD_SET_EP_CONF] = "DEPCMD_CMD_SET_EP_CONF ";
+ cmd_lookup[DEPCMD_CMD_SET_TR_CONF] = "DEPCMD_CMD_SET_TR_CONF ";
+ cmd_lookup[DEPCMD_CMD_GET_EP_STATE] = "DEPCMD_CMD_GET_EP_STATE ";
+ cmd_lookup[DEPCMD_CMD_SET_STALL] = "DEPCMD_CMD_SET_STALL ";
+ cmd_lookup[DEPCMD_CMD_CLEAR_STALL] = "DEPCMD_CMD_CLEAR_STALL ";
+ cmd_lookup[DEPCMD_CMD_START_TRANSFER] = "DEPCMD_CMD_START_TRANSFER ";
+ cmd_lookup[DEPCMD_CMD_UPDATE_TRANSFER] = "DEPCMD_CMD_UPDATE_TRANSFER";
+ cmd_lookup[DEPCMD_CMD_END_TRANSFER] = "DEPCMD_CMD_END_TRANSFER ";
+ cmd_lookup[DEPCMD_CMD_START_NEW_CONF] = "DEPCMD_CMD_START_NEW_CONF ";
+}
+
+
+/******************************** DWC global **********************************/
+/* Initialize DWC driver. */
+dwc_dev_t* dwc_init(dwc_config_t *config)
+{
+ dwc_dev_t *dev = (dwc_dev_t*) malloc(sizeof(dwc_dev_t));
+ ASSERT(dev);
+
+ memset(dev, 0, sizeof(dev));
+
+ /* save config info */
+ dev->base = config->base;
+ dev->event_buf.buf = config->event_buf;
+ dev->event_buf.buf_size = config->event_buf_size;
+ dev->event_buf.index = 0;
+ dev->event_buf.max_index = (config->event_buf_size)/4 - 1; /* (max num of 4 byte events) - 1 */
+
+ dev->notify_context = config->notify_context;
+ dev->notify = config->notify;
+
+ /* allocate buffer for receiving setup packet */
+ dev->setup_pkt = memalign(CACHE_LINE, ROUNDUP(DWC_SETUP_PKT_LEN, CACHE_LINE));
+ ASSERT(dev->setup_pkt);
+
+ /* callback function to handler setup packet */
+ dev->setup_context = config->setup_context;
+ dev->setup_handler = config->setup_handler;
+
+ /* read core version from h/w */
+ dev->core_id = dwc_coreid(dev);
+
+ /* register for interrupt */
+ register_int_handler(USB30_EE1_IRQ, dwc_irq_handler_ee1, dev);
+
+#ifdef DEBUG_USB
+ /* note: only for debug */
+ dwc_debug_lookup_init();
+#endif
+
+ return dev;
+}
+
+/* interrupt handler */
+static enum handler_return dwc_irq_handler_ee1(void* context)
+{
+ dwc_dev_t *dev;
+ uint16_t event_size; /* number of bytes used by the event */
+ uint32_t event[3] = {0x0, 0x0, 0x0};
+
+ /* get the device on which this interrupt occurred */
+ dev = (dwc_dev_t *) context;
+
+ /* while there are events to be processed */
+ while((event_size = dwc_event_get_next(dev, event)))
+ {
+ /* device event? */
+ if(DWC_EVENT_IS_DEVICE_EVENT(*event))
+ {
+ /* handle device events */
+ dwc_event_handler_device(dev, event);
+ }
+ else
+ {
+ /* endpoint event */
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+
+ if ((ep_phy_num == 0) ||
+ (ep_phy_num == 1))
+ {
+ /* handle control ep event */
+ dwc_event_handler_ep_ctrl(dev, event);
+ }
+ else
+ {
+ /* handle non-control ep event. only bulk ep is supported.*/
+ dwc_event_handler_ep_bulk(dev, event);
+ }
+ }
+
+ /* update number of bytes processed */
+ dwc_event_processed(dev, event_size);
+ }
+
+ return INT_NO_RESCHEDULE;
+}
+
+/*====================== DWC Event configuration/handling functions========== */
+
+/* handles all device specific events */
+void dwc_event_handler_device(dwc_dev_t *dev, uint32_t *event)
+{
+ dwc_event_device_event_id_t event_id = DWC_EVENT_DEVICE_EVENT_ID(*event);
+
+ DBG("\nDEVICE_EVENT: %s in %s \n", event_lookup_device[event_id],
+ dev_ctrl_state_lookup[dev->ctrl_state]);
+
+ switch (event_id)
+ {
+ case DWC_EVENT_DEVICE_EVENT_ID_VENDOR_DEVICE_TEST_LMP:
+ case DWC_EVENT_DEVICE_EVENT_ID_BUFFER_OVERFLOW:
+ case DWC_EVENT_DEVICE_EVENT_ID_GENERIC_CMD_COMPLETE:
+ case DWC_EVENT_DEVICE_EVENT_ID_ERRATIC_ERROR:
+ case DWC_EVENT_DEVICE_EVENT_ID_SOF:
+ case DWC_EVENT_DEVICE_EVENT_ID_SUSPEND_ENTRY:
+ case DWC_EVENT_DEVICE_EVENT_ID_HIBER:
+ case DWC_EVENT_DEVICE_EVENT_ID_WAKEUP:
+ break;
+ case DWC_EVENT_DEVICE_EVENT_ID_USB_LINK_STATUS_CHANGE:
+ {
+ dwc_event_device_link_status_change(dev, event);
+ }
+ break;
+ case DWC_EVENT_DEVICE_EVENT_ID_CONNECT_DONE:
+ {
+ dwc_event_device_connect_done(dev);
+ }
+ break;
+ case DWC_EVENT_DEVICE_EVENT_ID_USB_RESET:
+ {
+ dwc_event_device_reset(dev);
+ }
+ break;
+ case DWC_EVENT_DEVICE_EVENT_ID_DISCONNECT:
+ {
+ dwc_event_device_disconnect(dev);
+ }
+ break;
+
+ default:
+ ASSERT(0);
+ }
+}
+
+/* handle link status change event: does nothing for now.
+ * only for debug purpose.
+ */
+static void dwc_event_device_link_status_change(dwc_dev_t *dev, uint32_t *event)
+{
+#ifdef DEBUG_USB
+ uint8_t event_info = DWC_EVENT_DEVICE_EVENT_INFO(*event);
+ uint8_t ss_event = DWC_EVENT_DEVICE_EVENT_INFO_SS_EVENT(*event);
+ uint8_t link_state = DWC_EVENT_DEVICE_EVENT_INFO_LINK_STATE(event_info);
+
+ if(ss_event)
+ {
+ DBG("\n SS link state = %s (%d)\n", ss_link_state_lookup[link_state], link_state);
+ }
+ else
+ {
+ DBG("\n HS link state = %s (%d)\n", hs_link_state_lookup[link_state], link_state);
+ }
+#endif
+}
+
+/* handle disconnect event */
+static void dwc_event_device_disconnect(dwc_dev_t *dev)
+{
+ /* inform client that device is disconnected */
+ if (dev->notify)
+ dev->notify(dev->notify_context, DWC_NOTIFY_EVENT_DISCONNECTED);
+}
+
+/* handle connect event: snps 8.1.3 */
+static void dwc_event_device_connect_done(dwc_dev_t *dev)
+{
+ uint8_t speed;
+ uint16_t max_pkt_size = 0;
+ dwc_notify_event_t dwc_event = DWC_NOTIFY_EVENT_DISCONNECTED;
+
+ /* get connection speed */
+ speed = dwc_connectspeed(dev);
+
+ switch (speed)
+ {
+ case DSTS_CONNECTSPD_SS:
+ {
+ max_pkt_size = 512;
+ dwc_event = DWC_NOTIFY_EVENT_CONNECTED_SS;
+ }
+ break;
+ case DSTS_CONNECTSPD_HS:
+ {
+ max_pkt_size = 64;
+ dwc_event = DWC_NOTIFY_EVENT_CONNECTED_HS;
+ }
+ break;
+ case DSTS_CONNECTSPD_FS1:
+ case DSTS_CONNECTSPD_FS2:
+ {
+ max_pkt_size = 64;
+ dwc_event = DWC_NOTIFY_EVENT_CONNECTED_FS;
+ }
+ break;
+ case DSTS_CONNECTSPD_LS:
+ {
+ max_pkt_size = 8;
+ dwc_event = DWC_NOTIFY_EVENT_CONNECTED_LS;
+ }
+ break;
+ default:
+ ASSERT(0);
+ }
+
+ DBG("\nspeed = %d : %s max_pkt_size %d \n", speed,
+ speed_lookup[speed],
+ max_pkt_size);
+
+
+ /* save max pkt size for control endpoints */
+ dev->ep[0].max_pkt_size = max_pkt_size;
+ dev->ep[1].max_pkt_size = max_pkt_size;
+
+ /* Issue a DEPCFG command (with Config Action set to "Modify") for
+ * physical endpoints 0 & 1 using the same endpoint characteristics from
+ * Power-On Reset, but set
+ * MaxPacketSize to 512 (SuperSpeed), 64 (High-Speed),
+ * 8/16/32/64 (Full-Speed), or 8 (Low-Speed).
+ */
+ dwc_ep_cmd_set_config(dev, 0, SET_CONFIG_ACTION_MODIFY);
+ dwc_ep_cmd_set_config(dev, 1, SET_CONFIG_ACTION_MODIFY);
+
+ /* TODO: future optimization:
+ * GUSB2CFG/GUSB3PIPECTL
+ * Depending on the connected speed, write to the other PHY's control
+ * register to suspend it.
+ * GTXFIFOSIZn (optional) Based on the new MaxPacketSize of IN endpoint 0,
+ * software may choose to re-allocate
+ * the TX FIFO sizes by writing to these registers.
+ */
+
+ /* inform client that device is connected */
+ if (dev->notify)
+ dev->notify(dev->notify_context, dwc_event);
+}
+
+/* handle usb reset event:
+ * snps 8.1.2:
+ * Set DevAddr to 0
+ * end transfer for any active transfers (except for the default control EP)
+ */
+void dwc_event_device_reset(dwc_dev_t *dev)
+{
+ /* set dev address to 0 */
+ dwc_device_set_addr(dev, 0x0);
+
+ /* Send "stop transfer" on any non-control ep
+ * which has a transfer in progress: snps 8.2.5
+ */
+ for (uint8_t ep_index = 2; ep_index < DWC_MAX_NUM_OF_EP; ep_index++)
+ {
+ dwc_ep_t *ep = &dev->ep[ep_index];
+
+ DBG("\n RESET on EP = %d while state = %s", ep_index,
+ ep_state_lookup[ep->state]);
+
+ if ((ep->state == EP_STATE_START_TRANSFER) ||
+ (ep->state == EP_STATE_XFER_IN_PROG))
+ {
+ DBG("\n NEED to do end transfer");
+
+ dwc_ep_cmd_end_transfer(dev, ep->phy_num);
+ }
+ }
+
+ /* inform client that device is offline */
+ if (dev->notify)
+ {
+ DBG("\n calling Notify for OFFLINE event.\n");
+ dev->notify(dev->notify_context, DWC_NOTIFY_EVENT_OFFLINE);
+ }
+}
+
+/* handle control endpoint specific events:
+ * implements the control transfer programming model as described
+ * in snps chapter 8.4, figure 8-2.
+ */
+void dwc_event_handler_ep_ctrl(dwc_dev_t *dev, uint32_t *event)
+{
+#ifdef DEBUG_USB
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+ uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+ uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+#endif
+
+ DBG("\n\n\n++EP_EVENT: %s in ctrl_state: %s ep_state[%d]: %s",
+ event_lookup_ep[event_id],
+ dev_ctrl_state_lookup[dev->ctrl_state],
+ ep_phy_num,
+ ep_state_lookup[ep->state]);
+
+ DBG("\n ep_phy_num = %d param = 0x%x status = 0x%x", ep_phy_num,
+ event_param,
+ event_status);
+
+
+ /* call the handler for the current control state */
+ switch (dev->ctrl_state)
+ {
+ case EP_FSM_SETUP:
+ {
+ dwc_event_handler_ep_ctrl_state_setup(dev, event);
+ }
+ break;
+ case EP_FSM_CTRL_DATA:
+ {
+ dwc_event_handler_ep_ctrl_state_data(dev, event);
+ }
+ break;
+ case EP_FSM_WAIT_FOR_HOST_2:
+ {
+ dwc_event_handler_ep_ctrl_state_wait_for_host_2(dev, event);
+ }
+ break;
+ case EP_FSM_WAIT_FOR_HOST_3:
+ {
+ dwc_event_handler_ep_ctrl_state_wait_for_host_3(dev, event);
+ }
+ break;
+ case EP_FSM_STATUS_2:
+ {
+ dwc_event_handler_ep_ctrl_state_status_2(dev, event);
+ }
+ break;
+ case EP_FSM_STATUS_3:
+ {
+ dwc_event_handler_ep_ctrl_state_status_3(dev, event);
+ }
+ break;
+ case EP_FSM_STALL:
+ {
+ dwc_event_handler_ep_ctrl_state_stall(dev, event);
+ }
+ break;
+
+ default:
+ ASSERT(0);
+ }
+
+ DBG("\n--EP_EVENT: %s in ctrl_state: %s ep_state[%d]: %s",
+ event_lookup_ep[event_id],
+ dev_ctrl_state_lookup[dev->ctrl_state],
+ ep_phy_num,
+ ep_state_lookup[ep->state]);
+}
+
+/* check status of transfer:
+ * returns TRB status: non-zero value indicates failure to complete transfer.
+ * Also updates the "bytes_in_buf". This field indicates the number of bytes
+ * still remaining to be transferred. This field will be zero when all the
+ * requested data is transferred.
+ */
+uint8_t dwc_event_check_trb_status(dwc_dev_t *dev,
+ uint32_t *event,
+ uint8_t index,
+ uint32_t *bytes_in_buf)
+{
+ uint8_t status = 0;
+ uint8_t trb_updated = 0;
+ uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+ dwc_ep_t *ep = &dev->ep[index];
+ dwc_trb_t *trb = ep->trb;
+ uint32_t num_of_trb = ep->trb_queued;
+ uint32_t bytes_remaining = 0;
+
+ /* sanity ck. */
+ ASSERT(num_of_trb);
+
+ /* invalidate trb data before reading */
+ arch_invalidate_cache_range((addr_t) trb, sizeof(dwc_trb_t)*num_of_trb);
+
+ while (num_of_trb)
+ {
+ bytes_remaining += REG_READ_FIELD_LOCAL(&trb->f3, TRB_F3, BUFSIZ);
+
+ /* point to next trb */
+ trb++;
+
+ /* decrement trb count */
+ num_of_trb--;
+
+ /* The first non-zero status indicates the transfer status. Update
+ * "status" only once but still go through all the TRBs to find out
+ * the bytes still remaining to be transferred.
+ */
+ if (!status)
+ {
+ status = REG_READ_FIELD_LOCAL(&trb->f3, TRB_F3, TRBSTS);
+ }
+
+ if ((event_status & DWC_XFER_COMPLETE_EVT_STATUS_SHORT_PKT) &&
+ (REG_READ_FIELD_LOCAL(&trb->f4, TRB_F4, HWO)))
+ {
+ /* This TRB needs to be reclaimed since transfer completed due to
+ * reception of a short pkt.
+ * "fast-forward" condition as described in snps 8.2.3.2.
+ */
+ DBG("\n TRB needs to be reclaimed by sw. trb = 0x%x\n", (uint32_t) trb);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, HWO, 0x0);
+ trb_updated = 1;
+ }
+ }
+
+ /* flush out any updates to trb before continuing */
+ if (trb_updated)
+ {
+ arch_clean_invalidate_cache_range((addr_t) ep->trb,
+ sizeof(dwc_trb_t)*ep->trb_queued);
+ }
+
+ /* reset the EP's queued trb count */
+ ep->trb_queued = 0;
+
+ *bytes_in_buf = bytes_remaining;
+
+ DBG("\n trb_status: %d total buf size = 0x%x \n", status, *bytes_in_buf);
+
+ return status;
+}
+
+/* handle all events occurring in Control-Setup state */
+static void dwc_event_handler_ep_ctrl_state_setup(dwc_dev_t *dev,
+ uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+ uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+
+ if (cmd == DEPCMD_CMD_START_TRANSFER)
+ {
+ ASSERT(ep->state == EP_STATE_START_TRANSFER);
+
+ ASSERT(event_status == 0);
+
+ /* save the resource id assigned to this ep. */
+ ep->state = EP_STATE_XFER_IN_PROG;
+ ep->resource_idx = DWC_EVENT_EP_EVENT_XFER_RES_IDX(*event);
+ }
+ else
+ {
+ DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ }
+ }
+ break;
+
+ case DWC_EVENT_EP_XFER_NOT_READY:
+ {
+ /* attempting to start data/status before setup. snps 8.4.2 #2 */
+ DBG("\nattempting to start data/status before setup. stalling..\n");
+
+ dwc_ep_cmd_stall(dev, ep_phy_num);
+
+ /* new state is stall */
+ dev->ctrl_state = EP_FSM_STALL;
+ }
+ break;
+
+ case DWC_EVENT_EP_XFER_COMPLETE:
+ {
+ uint32_t bytes_remaining = 0;
+ uint8_t status = 0;
+
+ /* cannot happen on any other ep */
+ ASSERT(ep_phy_num == 0);
+
+ /* Assert if ep state is not xfer_in_prog. fatal error. */
+ ASSERT(ep->state == EP_STATE_XFER_IN_PROG);
+
+ /* update ep state to inactive. */
+ ep->state = EP_STATE_INACTIVE;
+
+ /* check transfer status. */
+ status = dwc_event_check_trb_status(dev,
+ event,
+ DWC_EP_PHY_TO_INDEX(ep_phy_num),
+ &bytes_remaining);
+
+ if (status || bytes_remaining)
+ {
+ /* transfer failed. queue another transfer. */
+ dwc_ep_ctrl_state_setup_enter(dev);
+ }
+ else
+ {
+ int ret;
+ uint8_t *data = dev->setup_pkt; /* setup pkt data */
+
+ /* invalidate any cached setup data before reading */
+ arch_invalidate_cache_range((addr_t) data, DWC_SETUP_PKT_LEN);
+
+ /* call setup handler */
+ ret = dev->setup_handler(dev->setup_context, data);
+
+ if (ret == DWC_SETUP_2_STAGE)
+ {
+ /* this is a 2 stage setup. */
+ dev->ctrl_state = EP_FSM_WAIT_FOR_HOST_2;
+ }
+ else if (ret == DWC_SETUP_3_STAGE)
+ {
+ /* this is a 3 stage setup. */
+ dev->ctrl_state = EP_FSM_CTRL_DATA;
+ }
+ else
+ {
+ /* bad setup bytes. stall */
+ dwc_ep_cmd_stall(dev, ep_phy_num);
+
+ /* new state is stall */
+ dev->ctrl_state = EP_FSM_STALL;
+ }
+ }
+ }
+ break;
+ case DWC_EVENT_EP_XFER_IN_PROGRESS:
+ default:
+ /* event is not expected in this state */
+ ERR("\n unhandled event_id = %d \n", event_id);
+ ASSERT(0);
+ }
+}
+
+/* handle all events occurring in Control-Data state */
+static void dwc_event_handler_ep_ctrl_state_data(dwc_dev_t *dev,
+ uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+ uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
+ uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+
+ if (cmd == DEPCMD_CMD_START_TRANSFER)
+ {
+ ASSERT(ep->state == EP_STATE_START_TRANSFER);
+
+ ASSERT(event_status == 0);
+
+ /* save the resource id assigned to this ep. */
+ ep->state = EP_STATE_XFER_IN_PROG;
+ ep->resource_idx = DWC_EVENT_EP_EVENT_XFER_RES_IDX(*event);
+ }
+ else
+ {
+ DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ }
+ }
+ break;
+
+ case DWC_EVENT_EP_XFER_NOT_READY:
+ {
+ /* confirm that this is control data request.
+ * control_status_request is invalid event in this state.
+ * assert if it ever occurs.
+ * something must be wrong in fsm implementation.
+ */
+ ASSERT(event_ctrl_stage == CONTROL_DATA_REQUEST);
+
+ /* In this state, the ep must be in transfer state.
+ * otherwise this came on an ep that we are not expecting any data.
+ */
+ if((ep->state == EP_STATE_START_TRANSFER) ||
+ (ep->state == EP_STATE_XFER_IN_PROG))
+ {
+ DBG("\n Host requested data on ep_phy_num = %d."
+ "Transfer already started. No action....", ep_phy_num);
+ }
+ else
+ {
+ /* host attempting to move data in wrong direction.
+ * end transfer for the direction that we started and stall.
+ */
+ uint8_t end_ep_phy_num;
+
+ /* end the other ep */
+ end_ep_phy_num = (ep_phy_num == 0) ? 1 : 0;
+
+ DBG("\nAttempting to move data in wrong direction. stalling. ");
+
+ dwc_ep_cmd_end_transfer(dev, end_ep_phy_num);
+
+ /* stall */
+ dwc_ep_cmd_stall(dev, end_ep_phy_num);
+
+ /* move to stall state. */
+ dev->ctrl_state = EP_FSM_STALL;
+ }
+ }
+ break;
+ case DWC_EVENT_EP_XFER_COMPLETE:
+ {
+ uint32_t bytes_remaining;
+ uint8_t status;
+
+ /* should never happen in any other state.
+ * something wrong in fsm implementation.
+ */
+ ASSERT(ep->state == EP_STATE_XFER_IN_PROG);
+
+ /* transfer is complete */
+ ep->state = EP_STATE_INACTIVE;
+
+ /* check transfer status */
+ status = dwc_event_check_trb_status(dev,
+ event,
+ DWC_EP_PHY_TO_INDEX(ep_phy_num),
+ &bytes_remaining);
+
+ if (status || bytes_remaining)
+ {
+ DBG("\n\n ********DATA TRANSFER FAILED ************* "
+ "status = %d bytes_remaining = %d\n\n",
+ status, bytes_remaining);
+ }
+
+ /* wait for host to request status */
+ dev->ctrl_state = EP_FSM_WAIT_FOR_HOST_3;
+ }
+ break;
+ case DWC_EVENT_EP_XFER_IN_PROGRESS:
+ default:
+ /* event is not expected in this state */
+ ASSERT(0);
+ }
+}
+
+/* handle all events occurring in Wait-for-Host-2 state */
+static void dwc_event_handler_ep_ctrl_state_wait_for_host_2(dwc_dev_t *dev,
+ uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+ uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_XFER_NOT_READY:
+ {
+ if (event_ctrl_stage == CONTROL_DATA_REQUEST)
+ {
+ DBG("\n\n attempting to start data when setup did not indicate"
+ "data stage. stall...\n\n");
+
+ dwc_ep_cmd_stall(dev, ep_phy_num);
+
+ /* move to stall state. */
+ dev->ctrl_state = EP_FSM_STALL;
+ }
+ else if (event_ctrl_stage == CONTROL_STATUS_REQUEST)
+ {
+ /* status cannot happen on phy = 0 */
+ ASSERT(ep_phy_num == 1);
+
+ dwc_request_t req;
+
+ req.callback = 0x0;
+ req.context = 0x0;
+ req.data = 0x0;
+ req.len = 0x0;
+ req.trbctl = TRBCTL_CONTROL_STATUS_2;
+
+ dwc_request_queue(dev, ep_phy_num, &req);
+
+ dev->ctrl_state = EP_FSM_STATUS_2;
+ }
+ else
+ {
+ ASSERT(0);
+ }
+ }
+ break;
+ case DWC_EVENT_EP_XFER_IN_PROGRESS:
+ case DWC_EVENT_EP_XFER_COMPLETE:
+ default:
+ /* event not expected in this state. */
+ ASSERT(0);
+ }
+}
+
+/* handle all events occurring in Wait-for-Host-3 state */
+static void dwc_event_handler_ep_ctrl_state_wait_for_host_3(dwc_dev_t *dev,
+ uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+ uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_XFER_NOT_READY:
+ {
+ if (event_ctrl_stage == CONTROL_DATA_REQUEST)/* data request */
+ {
+ /* TODO:
+ * special case handling when data stage transfer length
+ * was exact multiple of max_pkt_size.
+ * Need to setup a TRB to complete data stage with a zero
+ * length pkt transfer.
+ * Not implemented currently since all data during enumeration
+ * is less then max_pkt_size.
+ */
+ ASSERT(0);
+ }
+ else if (event_ctrl_stage == CONTROL_STATUS_REQUEST)/* stat req */
+ {
+ dwc_request_t req;
+
+ req.callback = 0x0;
+ req.context = 0x0;
+ req.data = 0x0;
+ req.len = 0x0;
+ req.trbctl = TRBCTL_CONTROL_STATUS_3;
+
+ dwc_request_queue(dev, ep_phy_num, &req);
+
+ dev->ctrl_state = EP_FSM_STATUS_3;
+ }
+ else
+ {
+ ASSERT(0);
+ }
+ }
+ break;
+ case DWC_EVENT_EP_XFER_IN_PROGRESS:
+ case DWC_EVENT_EP_XFER_COMPLETE:
+ default:
+ /* event is not expected in this state */
+ ASSERT(0);
+ }
+}
+
+
+/* handle all events occurring in Status-2 state */
+static void dwc_event_handler_ep_ctrl_state_status_2(dwc_dev_t *dev,
+ uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+ uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+
+ if (cmd == DEPCMD_CMD_START_TRANSFER)
+ {
+ ASSERT(ep->state == EP_STATE_START_TRANSFER);
+
+ ASSERT(event_status == 0);
+
+ /* save the resource id assigned to this ep. */
+ ep->state = EP_STATE_XFER_IN_PROG;
+ ep->resource_idx = DWC_EVENT_EP_EVENT_XFER_RES_IDX(*event);
+ }
+ else
+ {
+ DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ }
+ }
+ break;
+ case DWC_EVENT_EP_XFER_COMPLETE:
+ {
+ uint32_t bytes_remaining;
+ uint8_t status;
+
+ /* cannot happen on ep 0 */
+ ASSERT(ep_phy_num == 1);
+
+ /* should never happen in any other state.
+ * something wrong in fsm implementation.
+ */
+ ASSERT(ep->state == EP_STATE_XFER_IN_PROG);
+
+ ep->state = EP_STATE_INACTIVE;
+
+ /* check transfer status */
+ status = dwc_event_check_trb_status(dev,
+ event,
+ DWC_EP_PHY_TO_INDEX(ep_phy_num),
+ &bytes_remaining);
+
+ if (status || bytes_remaining)
+ {
+ DBG("\n\n ******** TRANSFER FAILED ************* status ="
+ " %d bytes_remaining = %d\n\n", status, bytes_remaining);
+ }
+
+ dwc_ep_ctrl_state_setup_enter(dev);
+ }
+ break;
+ case DWC_EVENT_EP_XFER_NOT_READY:
+ case DWC_EVENT_EP_XFER_IN_PROGRESS:
+ default:
+ /* event is not expected in this state */
+ ASSERT(0);
+ }
+}
+
+/* handle all events occurring in Status-3 state */
+static void dwc_event_handler_ep_ctrl_state_status_3(dwc_dev_t *dev,
+ uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+ uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+
+ if (cmd == DEPCMD_CMD_START_TRANSFER)
+ {
+ /* something wrong with fsm. cannot happen in any other ep state.*/
+ ASSERT(ep->state == EP_STATE_START_TRANSFER);
+
+ ASSERT(event_status == 0);
+
+ /* save the resource id assigned to this ep. */
+ ep->state = EP_STATE_XFER_IN_PROG;
+ ep->resource_idx = DWC_EVENT_EP_EVENT_XFER_RES_IDX(*event);
+ }
+ else
+ {
+ DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ }
+ }
+ break;
+ case DWC_EVENT_EP_XFER_COMPLETE:
+ {
+ uint32_t bytes_remaining;
+ uint8_t status;
+
+ /* should never happen in any other state.
+ * something wrong in fsm implementation.
+ */
+ ASSERT(ep->state == EP_STATE_XFER_IN_PROG);
+
+ ep->state = EP_STATE_INACTIVE;
+
+ /* check transfer status */
+ status = dwc_event_check_trb_status(dev,
+ event,
+ DWC_EP_PHY_TO_INDEX(ep_phy_num),
+ &bytes_remaining);
+
+ if (status || bytes_remaining)
+ {
+ DBG("\n\n ******** TRANSFER FAILED ************* status ="
+ " %d bytes_remaining = %d\n\n", status, bytes_remaining);
+
+ /* data stage failed. */
+ dwc_ep_cmd_stall(dev, ep_phy_num);
+
+ /* move to stall state. */
+ dev->ctrl_state = EP_FSM_STALL;
+ }
+ else
+ {
+ dwc_ep_ctrl_state_setup_enter(dev);
+ }
+ }
+ break;
+ case DWC_EVENT_EP_XFER_NOT_READY:
+ case DWC_EVENT_EP_XFER_IN_PROGRESS:
+ default:
+ /* event is not expected in this state */
+ ASSERT(0);
+ }
+}
+
+/* handle all events occurring in stall state */
+static void dwc_event_handler_ep_ctrl_state_stall(dwc_dev_t *dev,
+ uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+
+ if (cmd == DEPCMD_CMD_SET_STALL)
+ {
+ /* stall complete. go back to setup state. */
+ dwc_ep_ctrl_state_setup_enter(dev);
+ }
+ else if (cmd == DEPCMD_CMD_END_TRANSFER)
+ {
+ /* reset state and resource index */
+ ep->state = EP_STATE_INACTIVE;
+ ep->resource_idx = 0;
+ }
+ else
+ {
+ DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ }
+ }
+ break;
+ default:
+ DBG("\n\n ********No Action defined for this event. ignored. \n\n");
+ break;
+ }
+}
+
+/* event handler for INACTIVE state of bulk endpoint */
+static void dwc_event_handler_ep_bulk_state_inactive(dwc_dev_t *dev,
+ uint32_t *event)
+{
+#ifdef DEBUG_USB
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+#endif
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ }
+ break;
+ case DWC_EVENT_EP_XFER_NOT_READY:
+ {
+ /* This is a valid scenario where host is requesting data and
+ * our client has not queued the request yet.
+ */
+ DBG("\n Host requested data on ep_phy_num = %d. "
+ "No action. ignored.", ep_phy_num);
+ }
+ break;
+ case DWC_EVENT_EP_XFER_IN_PROGRESS:
+ case DWC_EVENT_EP_XFER_COMPLETE:
+ default:
+ /* event is not expected in this state */
+ ASSERT(0);
+ }
+}
+
+/* event handler for START_TRANSFER state of bulk endpoint */
+static void dwc_event_handler_ep_bulk_state_start_transfer(dwc_dev_t *dev,
+ uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+ uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+
+ if (cmd == DEPCMD_CMD_START_TRANSFER)
+ {
+ if (event_status == 0)
+ {
+ /* save the resource id assigned to this ep. */
+ ep->state = EP_STATE_XFER_IN_PROG;
+ ep->resource_idx = DWC_EVENT_EP_EVENT_XFER_RES_IDX(*event);
+ }
+ else
+ {
+ /* start transfer failed. inform client */
+ if (ep->req.callback)
+ {
+ ep->req.callback(ep->req.context, 0, -1);
+ }
+
+ /* back to inactive state */
+ dwc_ep_bulk_state_inactive_enter(dev, ep_phy_num);
+ }
+ }
+ else
+ {
+ DBG("\n cmd = %s has no action. ignored.\n", cmd_lookup[cmd]);
+ }
+ }
+ break;
+ default:
+ ASSERT(0);
+ }
+}
+
+/* event handler for TRANSFER_IN_PROGRESS state of bulk endpoint */
+static void dwc_event_handler_ep_bulk_state_xfer_in_prog(dwc_dev_t *dev,
+ uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ switch (event_id)
+ {
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+
+ if (cmd == DEPCMD_CMD_END_TRANSFER)
+ {
+ /* transfer was cancelled for some reason. */
+ DBG("\n transfer was cancelled on ep_phy_num = %d\n", ep_phy_num);
+
+ /* inform client that transfer failed. */
+ if (ep->req.callback)
+ {
+ ep->req.callback(ep->req.context, 0, -1);
+ }
+
+ /* back to inactive state */
+ dwc_ep_bulk_state_inactive_enter(dev, ep_phy_num);
+ }
+ else
+ {
+ DBG("\n cmd = %s has no action. ignored.\n", cmd_lookup[cmd]);
+ }
+ }
+ break;
+ case DWC_EVENT_EP_XFER_NOT_READY:
+ {
+ /* This is a valid scenario where host is requesting data and
+ * we have not yet moved to start transfer state.
+ */
+ DBG("\n Host requested data on ep_phy_num = %d."
+ "No action. ignored.", ep_phy_num);
+ }
+ break;
+ case DWC_EVENT_EP_XFER_COMPLETE:
+ {
+ uint32_t bytes_remaining;
+ uint8_t status;
+
+ /* Check how many TRBs were processed and how much data got
+ * transferred. If there are bytes_remaining, it does not
+ * necessarily mean failed xfer. We could have queued a 512 byte
+ * read and receive say 13 bytes of data which is a valid scenario.
+ */
+ status = dwc_event_check_trb_status(dev,
+ event,
+ DWC_EP_PHY_TO_INDEX(ep_phy_num),
+ &bytes_remaining);
+
+ DBG("\n\n ******DATA TRANSFER COMPLETED (ep_phy_num = %d) ********"
+ "bytes_remaining = %d\n\n", ep_phy_num, bytes_remaining);
+
+ if (ep->req.callback)
+ {
+ ep->req.callback(ep->req.context,
+ ep->bytes_queued - bytes_remaining,
+ status ? -1 : 0);
+ }
+
+ dwc_ep_bulk_state_inactive_enter(dev, ep_phy_num);
+ }
+ break;
+ default:
+ ASSERT(0);
+ }
+}
+
+/* bulk endpoint event handler */
+void dwc_event_handler_ep_bulk(dwc_dev_t *dev, uint32_t *event)
+{
+ uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
+#ifdef DEBUG_USB
+ dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
+ uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+ uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
+#endif
+
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ DBG("\n\n\n++EP_EVENT: %s in ctrl_state: %s ep_state[%d]: %s",
+ event_lookup_ep[event_id],
+ dev_ctrl_state_lookup[dev->ctrl_state],
+ ep_phy_num,
+ ep_state_lookup[ep->state]);
+
+ DBG("\n ep_phy_num = %d param = 0x%x status = 0x%x",
+ ep_phy_num, event_param, event_status);
+
+ switch (ep->state)
+ {
+ case EP_STATE_INACTIVE:
+ {
+ dwc_event_handler_ep_bulk_state_inactive(dev, event);
+ }
+ break;
+ case EP_STATE_START_TRANSFER:
+ {
+ dwc_event_handler_ep_bulk_state_start_transfer(dev, event);
+ }
+ break;
+ case EP_STATE_XFER_IN_PROG:
+ {
+ dwc_event_handler_ep_bulk_state_xfer_in_prog(dev, event);
+ }
+ break;
+ default:
+ DBG("\n EP state is invalid. Asserting...\n");
+ ASSERT(0);
+ }
+
+ DBG("\n--EP_EVENT: %s in ctrl_state: %s ep_state[%d]: %s",
+ event_lookup_ep[event_id],
+ dev_ctrl_state_lookup[dev->ctrl_state],
+ ep_phy_num,
+ ep_state_lookup[ep->state]);
+}
+
+
+
+
+/******************** Endpoint related APIs **********************************/
+
+/* Initialize and enable EP:
+ * - set the initial configuration for an endpoint
+ * - set transfer resources
+ * - enable the endpoint
+ */
+static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index)
+{
+ uint8_t ep_phy_num = dev->ep[index].phy_num;
+
+ dwc_ep_cmd_set_config(dev, index, SET_CONFIG_ACTION_INIT);
+
+ dev->ep[index].state = EP_STATE_INACTIVE;
+
+ /* Set transfer resource configs for the end points */
+ dwc_ep_cmd_set_transfer_resource(dev, ep_phy_num);
+
+ /* enable endpoint */
+ dwc_ep_enable(dev, ep_phy_num);
+}
+
+/* Initialize control EPs:
+ * Do the one time initialization of control EPs
+ */
+static void dwc_ep_ctrl_init(dwc_dev_t *dev)
+{
+ uint8_t index;
+
+ /* Control OUT */
+ index = DWC_EP_INDEX(0, DWC_EP_DIRECTION_OUT);
+
+ dev->ep[index].number = 0;
+ dev->ep[index].dir = DWC_EP_DIRECTION_OUT;
+ dev->ep[index].phy_num = 0;
+ dev->ep[index].type = EP_TYPE_CONTROL;
+ dev->ep[index].state = EP_STATE_INIT;
+ dev->ep[index].max_pkt_size = 512;
+ dev->ep[index].burst_size = 0;
+ dev->ep[index].tx_fifo_num = 0;
+ dev->ep[index].zlp = 0;
+ dev->ep[index].trb_count = 1;
+ /* TRB must be aligned to 16 */
+ dev->ep[index].trb = memalign(lcm(CACHE_LINE, 16),
+ ROUNDUP(dev->ep[index].trb_count*sizeof(dwc_trb_t), CACHE_LINE));
+ ASSERT(dev->ep[index].trb);
+ dev->ep[index].trb_queued = 0;
+ dev->ep[index].bytes_queued = 0;
+
+ /* Control IN */
+ index = DWC_EP_INDEX(0, DWC_EP_DIRECTION_OUT);
+
+ dev->ep[index].number = 0;
+ dev->ep[index].dir = DWC_EP_DIRECTION_IN;
+ dev->ep[index].phy_num = 1;
+ dev->ep[index].type = EP_TYPE_CONTROL;
+ dev->ep[index].state = EP_STATE_INIT;
+ dev->ep[index].max_pkt_size = 512;
+ dev->ep[index].burst_size = 0;
+ dev->ep[index].tx_fifo_num = 0;
+ dev->ep[index].zlp = 0;
+ dev->ep[index].trb_count = 1;
+ /* TRB must be aligned to 16 */
+ dev->ep[index].trb = memalign(lcm(CACHE_LINE, 16),
+ ROUNDUP(dev->ep[index].trb_count*sizeof(dwc_trb_t), CACHE_LINE));
+ ASSERT(dev->ep[index].trb);
+ dev->ep[index].trb_queued = 0;
+ dev->ep[index].bytes_queued = 0;
+
+ /* configure and enable the endpoints */
+ dwc_ep_config_init_enable(dev, 0);
+ dwc_ep_config_init_enable(dev, 1);
+}
+
+
+/* entry function into setup state for control fsm */
+static void dwc_ep_ctrl_state_setup_enter(dwc_dev_t *dev)
+{
+ dwc_request_t req;
+
+ /* queue request to receive the first setup pkt from host */
+ memset(dev->setup_pkt, 0, DWC_SETUP_PKT_LEN);
+
+ /* flush data */
+ arch_clean_invalidate_cache_range((addr_t) dev->setup_pkt, DWC_SETUP_PKT_LEN);
+
+ req.data = dev->setup_pkt;
+ req.len = DWC_SETUP_PKT_LEN;
+ req.trbctl = TRBCTL_CONTROL_SETUP;
+ req.callback = NULL;
+ req.context = NULL;
+
+ dwc_request_queue(dev, 0, &req);
+
+ /* reset control ep state to "setup" state */
+ dev->ctrl_state = EP_FSM_SETUP;
+}
+
+/* entry function into inactive state for data transfer fsm */
+static void dwc_ep_bulk_state_inactive_enter(dwc_dev_t *dev, uint8_t ep_phy_num)
+{
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ /* queue request to receive the first setup pkt from host */
+ ep->req.data = NULL;
+ ep->req.len = 0;
+ ep->req.trbctl = 0;
+ ep->req.callback = NULL;
+ ep->req.context = NULL;
+
+ /* inactive state */
+ ep->state = EP_STATE_INACTIVE;
+
+ /* reset the resource index, trb and bytes queued */
+ ep->resource_idx = 0;
+ ep->trb_queued = 0;
+ ep->bytes_queued = 0;
+}
+
+/*************************** External APIs ************************************/
+
+/* Initialize controller for device mode operation.
+ * Implements sequence as described in HPG.
+ * Numbers indicate the step # in HPG.
+ */
+void dwc_device_init(dwc_dev_t *dev)
+{
+ /* 15. reset device ctrl. */
+ dwc_device_reset(dev);
+
+ /* 16. initialize global control reg for device mode operation */
+ dwc_gctl_init(dev);
+
+ /* 17. AXI master config */
+ dwc_axi_master_config(dev);
+
+ /* 18. */
+ /* a. tx fifo config */
+ /* reset value is good. */
+ /* b. rx fifo config */
+ /* reset value is good. */
+
+ /* 18.c */
+ dwc_event_init(dev);
+
+ /* 18.d */
+ /* enable device event generation */
+ dwc_event_device_enable(dev, BIT(DWC_EVENT_DEVICE_EVENT_ID_DISCONNECT) |
+ BIT(DWC_EVENT_DEVICE_EVENT_ID_USB_RESET) |
+ BIT(DWC_EVENT_DEVICE_EVENT_ID_CONNECT_DONE));
+
+ /* 18.e initialize control end point
+ * start new config on end point 0. only needed for ep0.
+ * resource index must be set to 0.
+ */
+ dwc_ep_cmd_start_new_config(dev, 0, 0);
+
+ /* steps described in snps 8.1 */
+ dwc_ep_ctrl_init(dev);
+
+ /* Unmask interrupts */
+ unmask_interrupt(USB30_EE1_IRQ);
+
+ /* start the control ep fsm */
+ dwc_ep_ctrl_state_setup_enter(dev);
+}
+
+/* add a new non-control endpoint belonging to the selected USB configuration.
+ * This is called when "set config" setup is received from host.
+ * udc layer first adds the endpoints which are part of the selected
+ * configuration by calling this api.
+ * Then it calls dwc_device_set_configuration() to enable that configuration.
+ * TODO: need better api to manage this. possibly a single api to do both.
+ * also, currently this only works as long as same configuration is selected
+ * every time. The cleanup during usb reset is not cleanly removing the
+ * endpoints added during a set config. This works fine for our usecase.
+ */
+void dwc_device_add_ep(dwc_dev_t *dev, dwc_ep_t new_ep)
+{
+ uint8_t index = DWC_EP_INDEX(new_ep.number, new_ep.dir);
+
+ dwc_ep_t *ep = &dev->ep[index];
+
+ memset(ep, 0, sizeof(ep));
+
+ /* copy client specified params */
+
+ ep->number = new_ep.number;
+ ep->dir = new_ep.dir;
+ ep->type = new_ep.type;
+ ep->max_pkt_size = new_ep.max_pkt_size;
+ ep->burst_size = new_ep.burst_size;
+ ep->zlp = new_ep.zlp;
+ ep->trb_count = new_ep.trb_count;
+ ep->trb = new_ep.trb;
+
+ ASSERT(ep->trb);
+
+ /* clear out trb memory space. */
+ memset(ep->trb, 0, (ep->trb_count)*sizeof(ep->trb));
+ arch_clean_invalidate_cache_range((addr_t) ep->trb,
+ (ep->trb_count)*sizeof(ep->trb));
+
+ /* initialize dwc specified params */
+
+ /* map this usb ep to the next available phy ep.
+ * we assume non-flexible endpoint mapping.
+ * so the physical ep number is same as the index into our EP array.
+ */
+ ep->phy_num = index;
+
+ if (ep->dir == DWC_EP_DIRECTION_IN)
+ {
+ /* TODO: this works only as long as we just one IN EP (non-control).
+ * Need to increment this for every new IN ep added.
+ */
+ ep->tx_fifo_num = 1;
+ }
+ else
+ {
+ ep->tx_fifo_num = 0; /* tx fifo num must be 0 for OUT ep */
+ }
+
+ ep->trb_queued = 0;
+ ep->bytes_queued = 0;
+ ep->resource_idx = 0;
+ ep->state = EP_STATE_INIT;
+}
+
+/* Configure and enable non-control endpoints:
+ * This is called when "set config" setup is received from host.
+ * Implements sequence as described in snps databook 8.1.5.
+ */
+void dwc_device_set_configuration(dwc_dev_t *dev)
+{
+ /* disable every ep other than control EPs */
+ dwc_ep_disable_non_control(dev);
+
+ /* re-initialize TX FIFO by sending set config cmd to ep-1 */
+ dwc_ep_cmd_set_config(dev, 1, SET_CONFIG_ACTION_MODIFY);
+
+ /* re-initialize transfer resource allocation:
+ * only needed for ep0.
+ * resource index must be set to 2 when doing set config
+ */
+ dwc_ep_cmd_start_new_config(dev, 0, 2);
+
+ /* Initialize config for each non-control EP in the new configuration */
+ for (uint8_t ep_index = 2; ep_index < DWC_MAX_NUM_OF_EP; ep_index++)
+ {
+ /* non-zero phy ep num indicates that this ep data is initialized
+ * and ready for use.
+ */
+ if (dev->ep[ep_index].phy_num)
+ {
+ dwc_ep_config_init_enable(dev, ep_index);
+ }
+ }
+
+ /* optional: re-initialize tx FIFO : GTXFIFOSIZn*/
+}
+
+/* Enqueue new data transfer request on an endpoint. */
+static int dwc_request_queue(dwc_dev_t *dev,
+ uint8_t ep_phy_num,
+ dwc_request_t *req)
+{
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ dwc_trb_t *trb = ep->trb;
+ uint8_t *data_ptr = req->data;
+ uint32_t transfer_len = req->len;
+ dwc_trb_trbctl_t trbctl = req->trbctl;
+
+ uint32_t pad_len;
+
+ if(ep->state != EP_STATE_INACTIVE)
+ {
+ DBG("\n EP must be in INACTIVE state to start queue transfer. ep_phy_num = %d current state = %s",
+ ep_phy_num, ep_state_lookup[ep->state]);
+ return -1;
+ }
+
+ /* trb queued must be 0 at this time. */
+ ASSERT(ep->trb_queued == 0);
+
+ /* save the original request for this ep */
+ ep->req = *req;
+
+ ep->bytes_queued = 0;
+
+ if (ep->type == EP_TYPE_CONTROL)
+ {
+ memset(trb, 0, sizeof(dwc_trb_t));
+
+ REG_WRITE_FIELD_LOCAL(&trb->f1, TRB_F1, PTR_LOW, (uint32_t) data_ptr);
+ REG_WRITE_FIELD_LOCAL(&trb->f2, TRB_F2, PTR_HIGH, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f3, TRB_F3, BUFSIZ, transfer_len);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, LST, 0x1);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, CHN, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, CSP, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, TRBCTL, trbctl);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, IOC, 0x1);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, HWO, 0x1);
+
+ /* increment the queued trb count */
+ ep->trb_queued++;
+ ep->bytes_queued += transfer_len;
+ data_ptr += transfer_len;
+ }
+ else if (ep->type == EP_TYPE_BULK)
+ {
+ /* reserve 1 trb for pad/zero-length pkt */
+ uint32_t trb_available = ep->trb_count - 1;
+ uint32_t max_bytes_per_trb;
+ uint32_t offset;
+ uint32_t trb_len = 0;
+
+ /* snps 7.2 table 7-1. applies only to older versions of the controller:
+ * - data_ptr in first TRB can be aligned to byte
+ * - but the following TRBs should point to data that is aligned
+ * to master bus data width.
+ */
+
+ /* align default MAX_BYTES_PER_TRB to DWC_MASTER_BUS_WIDTH */
+ max_bytes_per_trb = ROUNDDOWN(DWC_MAX_BYTES_PER_TRB, DWC_MASTER_BUS_WIDTH);
+
+ while (trb_available && transfer_len)
+ {
+ /* clear out trb fields */
+ memset(trb, 0, sizeof(dwc_trb_t));
+
+ if (ep->trb_queued == 0)
+ {
+ /* first trb: limit the transfer length in this TRB such that
+ * the next trb data_ptr will be aligned to master bus width.
+ */
+ offset = ((uint32_t) data_ptr) & (DWC_MASTER_BUS_WIDTH - 1);
+ trb_len = (transfer_len <= max_bytes_per_trb) ?
+ transfer_len : (max_bytes_per_trb - offset);
+ }
+ else
+ {
+ trb_len = (transfer_len <= max_bytes_per_trb) ?
+ transfer_len : max_bytes_per_trb;
+ }
+
+ REG_WRITE_FIELD_LOCAL(&trb->f1, TRB_F1, PTR_LOW, (uint32_t) data_ptr);
+ REG_WRITE_FIELD_LOCAL(&trb->f2, TRB_F2, PTR_HIGH, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f3, TRB_F3, BUFSIZ, trb_len);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, LST, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, CHN, 0x1);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, CSP, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, TRBCTL, trbctl);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, IOC, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, HWO, 0x1);
+
+ /* increment the queued trb count */
+ ep->trb_queued++;
+ ep->bytes_queued += trb_len;
+ data_ptr += trb_len;
+
+ /* remaining transfer len */
+ transfer_len -= trb_len;
+
+ /* remaining trb */
+ trb_available--;
+
+ /* point to the next trb */
+ trb++;
+ }
+
+ if (transfer_len)
+ {
+ /* TRBs not available to queue the entire request.
+ * If more data is expected in each request, increase the number
+ * of TRBs allocated for this EP.
+ */
+ ERR("\n ERROR: Enough TRBs are not available to setup transfer\n");
+ ERR("\n ERROR: Increase TRB chain for the ep.\n");
+ ERR("\n ERROR: phy_ep_num = %d xfer len = %d\n", ep_phy_num, req->len);
+ ASSERT(0);
+ }
+
+ /* snps 8.2.3.3:
+ * For an OUT ep:
+ * (a) The "buffer descriptor" must be exact multiple of max_pkt_size
+ * "buffer descriptor" consists of one or more TRBs upto the TRB
+ * with CHN (chain) flag is not set.
+ * Add a TRB to pad the len if it is not exact multiple.
+ *
+ * (b) If the expected amount of data is exact multiple of max_pkt_size:
+ * add a max_pkt_size trb to sink in zero-length pkt, only if
+ * the EP expects it.
+ */
+ uint32_t roundup = req->len % ep->max_pkt_size;
+
+ if ( (ep->dir == DWC_EP_DIRECTION_OUT) &&
+ (roundup || ep->zlp))
+ {
+ if(roundup)
+ {
+ /* add a TRB to make it exact multiple of max_pkt_size */
+ pad_len = ep->max_pkt_size - roundup;
+ }
+ else
+ {
+ /* "buffer descriptor" is exact multiple of max_pkt_size and
+ * ep expects a zero-length pkt.
+ * Add a TRB to sink in the zero-length pkt.
+ */
+ pad_len = ep->max_pkt_size;
+ }
+
+ memset(trb, 0, sizeof(dwc_trb_t));
+ memset(ep->zlp_buf, 0, DWC_ZLP_BUF_SIZE);
+
+ REG_WRITE_FIELD_LOCAL(&trb->f1, TRB_F1, PTR_LOW, (uint32_t) ep->zlp_buf);
+ REG_WRITE_FIELD_LOCAL(&trb->f2, TRB_F2, PTR_HIGH, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f3, TRB_F3, BUFSIZ, pad_len);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, LST, 0x1);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, CHN, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, CSP, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, TRBCTL, trbctl);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, IOC, 0x1);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, HWO, 0x1);
+
+ /* increment the queued trb count */
+ ep->trb_queued++;
+ ep->bytes_queued += pad_len;
+ }
+ else /* pad trb not needed. */
+ {
+ /* point trb to the last programmed trb */
+ trb--;
+
+ /* setup params for last TRB */
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, CHN, 0x0);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, LST, 0x1);
+ REG_WRITE_FIELD_LOCAL(&trb->f4, TRB_F4, IOC, 0x1);
+ }
+ }
+ else
+ {
+ /* invalid EP type */
+ ASSERT(0);
+ }
+
+ /* flush the trb data to main memory */
+ arch_clean_invalidate_cache_range((addr_t) ep->trb,
+ sizeof(dwc_trb_t)*ep->trb_queued);
+
+ DBG("\n Starting new xfer on ep_phy_num = %d TRB_QUEUED = %d \n",
+ ep_phy_num, ep->trb_queued);
+
+ /* dwc_request_queue could be triggered from app and thus
+ * outside of interrupt context. Use critical section to make sure all
+ * states are updated properly before we handle other interrupts.
+ */
+ enter_critical_section();
+
+ if(ep->state == EP_STATE_INACTIVE)
+ {
+ dwc_ep_cmd_start_transfer(dev, ep_phy_num);
+
+ if(dwc_device_run_status(dev))
+ {
+ ep->state = EP_STATE_START_TRANSFER;
+ }
+ else
+ {
+ /* no interrupt expected on completion of start transfer.
+ * directly move to xfer in prog state.
+ */
+ ep->state = EP_STATE_XFER_IN_PROG;
+ }
+ }
+ else
+ {
+ DBG("\n Attempting START_TRANSFER in invalid state: %s. .......\n",
+ ep_state_lookup[ep->state]);
+ ASSERT(0);
+ }
+
+ exit_critical_section();
+
+ return 0;
+}
+
+/* data transfer request:
+ * NOTE: Assumes that the data to be transferred is already in main memory.
+ * Any cache management must be done by caller .
+ * For received data, cache mgmt must be done in callback function.
+ */
+int dwc_transfer_request(dwc_dev_t *dwc,
+ uint8_t usb_ep,
+ dwc_ep_direction_t dir,
+ void *buf,
+ uint32_t len,
+ dwc_transfer_callback_t callback,
+ void *callback_context)
+{
+ uint8_t ep_phy_num;
+ dwc_request_t req;
+
+ /* map usb ep to physical ep */
+ ep_phy_num = DWC_EP_PHY_NUM(usb_ep, dir);
+
+ req.data = buf;
+ req.len = len;
+ req.callback = callback;
+ req.context = callback_context;
+
+ if (usb_ep == 0)
+ {
+ /* control EP always has CONTROL_DATA trb */
+ req.trbctl = TRBCTL_CONTROL_DATA;
+ }
+ else
+ {
+ req.trbctl = TRBCTL_NORMAL;
+ }
+
+ return dwc_request_queue(dwc, ep_phy_num, &req);
+}
diff --git a/platform/msm_shared/usb30_dwc.h b/platform/msm_shared/usb30_dwc.h
new file mode 100644
index 0000000..7a222ff
--- /dev/null
+++ b/platform/msm_shared/usb30_dwc.h
@@ -0,0 +1,498 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _USB30_DWC_H
+#define _USB30_DWC_H
+
+#include <bits.h>
+
+
+/********************* START: h/w defined values ******************************/
+/* device command ids */
+typedef enum
+{
+ DWC_DEV_CMD_TX_SET_LINK_FN_LMP_VAL = 0x01,
+ DWC_DEV_CMD_SET_PERIODIC_PARAMS_VAL = 0x02,
+ DWC_DEV_CMD_TX_FN_WAKE_DEV_NOTIFY_VAL = 0x03,
+ DWC_DEV_CMD_SET_SCRATCHPAD_BUF_LO_VAL = 0x04,
+ DWC_DEV_CMD_SET_SCRATCHPAD_BUF_HI_VAL = 0x05,
+ DWC_DEV_CMD_TX_FN_HOST_REQ_NOTIFY_VAL = 0x06,
+ DWC_DEV_CMD_TX_DEVICE_NOTIFY_VAL = 0x07,
+ DWC_DEV_CMD_SELECTED_FIFO_FLUSH_VAL = 0x09,
+ DWC_DEV_CMD_ALL_FIFO_FLUSH_VAL = 0x0A,
+ DWC_DEV_CMD_SET_EP_NRDY_VAL = 0x0C,
+ DWC_DEV_CMD_RUN_SOC_LOOPBACK_TEST_VAL = 0x10,
+} dwc_dev_cmd_t;
+
+/* ep command ids */
+typedef enum
+{
+ DEPCMD_CMD_SET_EP_CONF = 0x1,
+ DEPCMD_CMD_SET_TR_CONF = 0x2,
+ DEPCMD_CMD_GET_EP_STATE = 0x3,
+ DEPCMD_CMD_SET_STALL = 0x4,
+ DEPCMD_CMD_CLEAR_STALL = 0x5,
+ DEPCMD_CMD_START_TRANSFER = 0x6,
+ DEPCMD_CMD_UPDATE_TRANSFER = 0x7,
+ DEPCMD_CMD_END_TRANSFER = 0x8,
+ DEPCMD_CMD_START_NEW_CONF = 0x9,
+} dwc_dep_cmd_id_t;
+
+/* ep type */
+typedef enum {
+ EP_TYPE_CONTROL = 0x0,
+ EP_TYPE_ISOCHRONOUS = 0x1,
+ EP_TYPE_BULK = 0x2,
+ EP_TYPE_INTERRUPT = 0x3,
+} dwc_ep_type_t;
+
+/* ep direction */
+typedef enum
+{
+ DWC_EP_DIRECTION_OUT = 0x0,
+ DWC_EP_DIRECTION_IN = 0x1
+} dwc_ep_direction_t;
+
+
+/* macros to parse event information */
+#define DWC_EVENT_IS_DEVICE_EVENT(_event) BIT_SHIFT(_event, 0)
+
+/* parse device events */
+#define DWC_EVENT_DEVICE_EVENT_ID(_event) BITS_SHIFT(_event, 11, 8)
+#define DWC_EVENT_DEVICE_EVENT_INFO(_event) BITS_SHIFT(_event, 24, 16)
+
+#define DWC_EVENT_DEVICE_EVENT_INFO_SS_EVENT(_event_info) BIT_SHIFT(_event_info, 4)
+#define DWC_EVENT_DEVICE_EVENT_INFO_LINK_STATE(_event_info) BITS_SHIFT(_event_info, 3, 0)
+
+/* parse ep events */
+#define DWC_EVENT_EP_EVENT_PARAM(_event) BITS_SHIFT(_event, 31, 16)
+#define DWC_EVENT_EP_EVENT_CMD_TYPE(_event) BITS_SHIFT(_event, 27, 24)
+#define DWC_EVENT_EP_EVENT_XFER_RES_IDX(_event) BITS_SHIFT(_event, 22, 16)
+#define DWC_EVENT_EP_EVENT_STATUS(_event) BITS_SHIFT(_event, 15, 12)
+#define DWC_EVENT_EP_EVENT_CTRL_STAGE(_event) BITS_SHIFT(_event, 13, 12)
+#define DWC_EVENT_EP_EVENT_ID(_event) BITS_SHIFT(_event, 9, 6)
+#define DWC_EVENT_EP_EVENT_EP_NUM(_event) BITS_SHIFT(_event, 5, 1)
+
+/* device event ids */
+typedef enum
+{
+ DWC_EVENT_DEVICE_EVENT_ID_VENDOR_DEVICE_TEST_LMP = 12,
+ DWC_EVENT_DEVICE_EVENT_ID_BUFFER_OVERFLOW = 11,
+ DWC_EVENT_DEVICE_EVENT_ID_GENERIC_CMD_COMPLETE = 10,
+ DWC_EVENT_DEVICE_EVENT_ID_ERRATIC_ERROR = 9,
+ DWC_EVENT_DEVICE_EVENT_ID_SOF = 7,
+ DWC_EVENT_DEVICE_EVENT_ID_SUSPEND_ENTRY = 6,
+ DWC_EVENT_DEVICE_EVENT_ID_HIBER = 5,
+ DWC_EVENT_DEVICE_EVENT_ID_WAKEUP = 4,
+ DWC_EVENT_DEVICE_EVENT_ID_USB_LINK_STATUS_CHANGE = 3,
+ DWC_EVENT_DEVICE_EVENT_ID_CONNECT_DONE = 2,
+ DWC_EVENT_DEVICE_EVENT_ID_USB_RESET = 1,
+ DWC_EVENT_DEVICE_EVENT_ID_DISCONNECT = 0,
+ DWC_EVENT_DEVICE_EVENTS_ALL = BITS(0xFFFFFFFF, 12, 0)
+} dwc_event_device_event_id_t;
+
+/* ep event ids */
+typedef enum
+{
+ DWC_EVENT_EP_CMD_COMPLETE = 7,
+ DWC_EVENT_EP_XFER_NOT_READY = 3,
+ DWC_EVENT_EP_XFER_IN_PROGRESS = 2,
+ DWC_EVENT_EP_XFER_COMPLETE = 1,
+} dwc_event_ep_event_id_t;
+
+/* values for control stage in ep events */
+#define CONTROL_DATA_REQUEST 1
+#define CONTROL_STATUS_REQUEST 2
+
+/* values for event status field for transfer complete event */
+#define DWC_XFER_COMPLETE_EVT_STATUS_SHORT_PKT 0x2
+#define DWC_XFER_COMPLETE_EVT_STATUS_IOC 0x4
+#define DWC_XFER_COMPLETE_EVT_STATUS_LST 0x8
+
+/* master bus data width (DWC_USB3_MDWIDTH in snps data book) */
+#define DWC_MASTER_BUS_WIDTH 8
+
+/* super speed link states */
+typedef enum
+{
+ U0 = 0x0,
+ U1,
+ U2,
+ U3,
+ SS_DIS,
+ RX_DET,
+ SS_INACT,
+ POLL,
+ RECOV,
+ HRESET,
+ CMPLY,
+ LPBK,
+ RESUME_RESET = 0xF,
+} dwc_event_device_ss_link_state_t;
+
+/* high speed link states */
+typedef enum
+{
+ ON = 0x0,
+ L1 = 0x2,
+ L2 = 0x3,
+ DISCONNECTED = 0x4,
+ EARLY_SUSPEND = 0x5,
+ RESET = 0xE,
+ RESUME = 0xF,
+} dwc_event_device_hs_link_state_t;
+
+/* action for set config*/
+enum
+{
+ SET_CONFIG_ACTION_INIT = 0x0,
+ SET_CONFIG_ACTION_RESTORE = 0x1,
+ SET_CONFIG_ACTION_MODIFY = 0x2,
+};
+
+/* EP Cmd Param bits */
+#define DEPCMDPAR1_USB_EP_NUM_BIT 26
+#define DEPCMDPAR1_USB_EP_DIR_BIT 25
+
+#define DEPCMDPAR0_ACTION_BIT 30
+#define DEPCMDPAR0_BURST_SIZE_BIT 22
+#define DEPCMDPAR0_FIFO_NUM_BIT 17
+#define DEPCMDPAR0_MAX_PKT_SIZE_BIT 3
+#define DEPCMDPAR0_EP_TYPE_BIT 1
+
+#define DEPCMDPAR2_XFER_N_RDY_BIT 10
+#define DEPCMDPAR2_XFER_IN_PROG_BIT 9
+#define DEPCMDPAR2_XFER_COMPLETE_BIT 8
+
+enum
+{
+ DSTS_CONNECTSPD_HS = 0,
+ DSTS_CONNECTSPD_FS1 = 1, /* phy clk @ 30 or 60 MHz */
+ DSTS_CONNECTSPD_LS = 2,
+ DSTS_CONNECTSPD_FS2 = 3, /* phy clk @ 48 MHz */
+ DSTS_CONNECTSPD_SS = 4,
+};
+
+/**************************** TRB (Transfer Request Block)*********************/
+#define DWC_TRB_F1_PTR_LOW_BMSK 0xFFFFFFFF
+#define DWC_TRB_F1_PTR_LOW_SHFT 0
+
+#define DWC_TRB_F2_PTR_HIGH_BMSK 0xFFFFFFFF
+#define DWC_TRB_F2_PTR_HIGH_SHFT 0
+
+#define DWC_TRB_F3_BUFSIZ_BMSK 0x00FFFFFF
+#define DWC_TRB_F3_BUFSIZ_SHFT 0
+#define DWC_TRB_F3_PCM1_BMSK 0x03000000
+#define DWC_TRB_F3_PCM1_SHFT 24
+#define DWC_TRB_F3_TRBSTS_BMSK 0xF0000000
+#define DWC_TRB_F3_TRBSTS_SHFT 28
+
+#define DWC_TRB_F4_IOC_BMSK 0x800
+#define DWC_TRB_F4_IOC_SHFT 11
+
+#define DWC_TRB_F4_ISP_BMSK 0x400
+#define DWC_TRB_F4_ISP_SHFT 10
+
+#define DWC_TRB_F4_TRBCTL_BMSK 0x3F0
+#define DWC_TRB_F4_TRBCTL_SHFT 4
+
+#define DWC_TRB_F4_CSP_BMSK 0x8
+#define DWC_TRB_F4_CSP_SHFT 3
+
+#define DWC_TRB_F4_CHN_BMSK 0x4
+#define DWC_TRB_F4_CHN_SHFT 2
+
+#define DWC_TRB_F4_LST_BMSK 0x2
+#define DWC_TRB_F4_LST_SHFT 1
+
+#define DWC_TRB_F4_HWO_BMSK 0x1
+#define DWC_TRB_F4_HWO_SHFT 0
+/**************************** END - TRB ***************************************/
+
+#define DWC_MAX_BYTES_PER_TRB 0x00FFFFFF
+
+/********************* END: h/w defined values ********************************/
+
+
+
+/******************** START: local data not needed by external APIs ***********/
+
+/* event buffer: used to manage various controller events */
+typedef struct {
+ uint32_t *buf; /* ptr to event buffer. */
+ uint16_t buf_size; /* size of buf. */
+ uint16_t max_index; /* max index value. initialized once. used to track rollover. */
+ uint16_t index; /* index into the buf for reading next event */
+} dwc_event_buf_t;
+
+/* device command */
+typedef struct {
+ uint32_t cmd;
+ uint32_t param;
+} dwc_device_cmd_t;
+
+/* ep command */
+typedef struct {
+ uint32_t cmd;
+ uint8_t xfer_resource_index;
+ uint32_t param2;
+ uint32_t param1;
+ uint32_t param0;
+} dwc_ep_cmd_t;
+
+/* state of data transfer on an ep */
+typedef enum
+{
+ EP_STATE_INIT = 0x0, /* initial state. cannot start transfer. */
+ EP_STATE_INACTIVE = 0x1, /* start xfer has not been issued. transfer is NOT in progress. start transfer can be issued ONLY in this state. */
+ EP_STATE_START_TRANSFER = 0x2, /* start xfer is issued but cmd is not completed yet. */
+ EP_STATE_XFER_IN_PROG = 0x3, /* start xfer is issued and xfer is in progress. */
+} dwc_ep_state_t;
+
+/* control fsm states: states to manage control transfers */
+typedef enum
+{
+ EP_FSM_INIT = 0,
+ EP_FSM_SETUP = 1,
+ EP_FSM_CTRL_DATA = 2,
+ EP_FSM_WAIT_FOR_HOST_2 = 3, /* 2-stage transfer wait-for-host stage */
+ EP_FSM_WAIT_FOR_HOST_3 = 4, /* 3-stage transfer wait-for-host stage */
+ EP_FSM_STATUS_2 = 5,
+ EP_FSM_STATUS_3 = 6,
+ EP_FSM_STALL = 7,
+} dwc_ctrl_fsm_t;
+
+/* TRB type */
+typedef enum
+{
+ TRBCTL_NORMAL = 1,
+ TRBCTL_CONTROL_SETUP = 2,
+ TRBCTL_CONTROL_STATUS_2 = 3,
+ TRBCTL_CONTROL_STATUS_3 = 4,
+ TRBCTL_CONTROL_DATA = 5,
+ TRBCTL_LINK_TRB = 8,
+} dwc_trb_trbctl_t;
+
+/* data transfer request */
+typedef struct
+{
+ uint8_t *data;
+ uint32_t len;
+ dwc_trb_trbctl_t trbctl;
+ void *context;
+ void (*callback)(void *context, uint32_t actual, int status);
+} dwc_request_t;
+
+/******************** END: local data not needed by external APIs *************/
+
+
+/******************** START: data needed by external APIs *********************/
+
+/* TRB fields */
+typedef struct
+{
+ uint32_t f1;
+ uint32_t f2;
+ uint32_t f3;
+ uint32_t f4;
+} dwc_trb_t;
+
+/* index into the ep array of the dwc device */
+#define DWC_EP_INDEX(_usb_ep, _direction) (((_usb_ep) << 1) | (_direction))
+
+/* phyical ep number: same as ep index. */
+#define DWC_EP_PHY_NUM(_usb_ep, _direction) (((_usb_ep) << 1) | (_direction))
+
+/* since we assume non-flexible mapping, phy_num is same as index. */
+#define DWC_EP_PHY_TO_INDEX(_ep_phy_num) (_ep_phy_num)
+
+typedef void (*dwc_transfer_callback_t)(void *context, uint32_t actual, int status);
+
+/* length of zero-length-packet */
+/* TODO: shouldn't this be same a max pkt size for the EP
+ * which is specified by udc? fastboot doesn't need this.
+ * So this is not verified.
+ */
+#define DWC_ZLP_BUF_SIZE 512
+
+/* Structure to keep all information about an endpoint */
+typedef struct
+{
+ uint8_t number; /* usb ep number */
+ dwc_ep_direction_t dir; /* usb ep direction */
+ dwc_ep_type_t type; /* ctrl/blk etc. */
+ uint16_t max_pkt_size; /* max packet size */
+ uint8_t zlp; /* uses zero length pkt to terminate xfer */
+ uint32_t burst_size; /* max packets to transfer before waiting for ack */
+
+ uint8_t phy_num; /* physical EP to which this usb ep is mapped */
+ uint8_t tx_fifo_num; /* which TX FIFO to use. only applies to IN endpoints */
+
+ uint8_t zlp_buf[DWC_ZLP_BUF_SIZE]; /* buffer needed to pad when OUT requests are not exact multiple of max_pkt_size and for zlp */
+
+ uint8_t resource_idx; /* assigned by h/w on each start xfer cmd. Needed to stop/update xfers. */
+
+ dwc_trb_t *trb; /* ptr to the first TRB in the chain. */
+ uint32_t trb_count; /* size of TRB chain. */
+ uint32_t trb_queued; /* number of TRBs queued in the current request. */
+ uint32_t bytes_queued; /* number of bytes queued in the current request. */
+ dwc_request_t req; /* transfer request that is currently queued on this ep. */
+
+ dwc_ep_state_t state; /* data transfer state of the ep. */
+
+} dwc_ep_t;
+
+
+/* dwc device events */
+typedef enum
+{
+ DWC_NOTIFY_EVENT_OFFLINE,
+ DWC_NOTIFY_EVENT_CONNECTED_LS,
+ DWC_NOTIFY_EVENT_CONNECTED_FS,
+ DWC_NOTIFY_EVENT_CONNECTED_HS,
+ DWC_NOTIFY_EVENT_CONNECTED_SS,
+ DWC_NOTIFY_EVENT_DISCONNECTED,
+} dwc_notify_event_t;
+
+/* maximum number of endpoints supported. */
+#define DWC_MAX_NUM_OF_EP 4
+
+/* length of setup packet */
+#define DWC_SETUP_PKT_LEN 8
+
+enum
+{
+ DWC_SETUP_ERROR = -1,
+ DWC_SETUP_2_STAGE = 2,
+ DWC_SETUP_3_STAGE = 3,
+};
+
+/* Structure to keep all DWC device information. */
+typedef struct
+{
+ void *base; /* base address for snps core registers */
+ uint32_t core_id; /* snps core version. read from h/w during init */
+
+ dwc_ep_t ep[DWC_MAX_NUM_OF_EP]; /* array of endpoint data */
+ dwc_event_buf_t event_buf; /* event buffer management */
+ dwc_ctrl_fsm_t ctrl_state; /* states to manage control transfers : setup/data/wait/status */
+
+ uint8_t *setup_pkt; /* Buffer for the received setup packet */
+
+ /* callback into client to notify device events: online/offline/connect speed */
+ void *notify_context;
+ void (*notify)(void *context, dwc_notify_event_t event);
+
+ /* callback into client to process the setup msgs. */
+ void *setup_context;
+ int (*setup_handler)(void* context, uint8_t* data);
+
+} dwc_dev_t;
+
+
+/* config data to initialize dwc layer */
+typedef struct
+{
+ void *base; /* dwc base address */
+ uint32_t *event_buf; /* buffer to be used for h/w events */
+ uint16_t event_buf_size; /* buffer size */
+
+ /* callback for dwc events */
+ void *notify_context;
+ void (*notify)(void *context, dwc_notify_event_t event);
+
+ /* callback for handling setup packets */
+ void *setup_context;
+ int (*setup_handler)(void *context, uint8_t *data);
+
+} dwc_config_t;
+
+/********************************* dwc global apis ****************************/
+
+/* generic apis */
+dwc_dev_t* dwc_init(dwc_config_t *config);
+void dwc_reset(dwc_dev_t *dev, uint8_t reset);
+
+/* phy specific apis */
+void dwc_phy_digital_reset(dwc_dev_t *dev);
+void dwc_usb2_phy_soft_reset(dwc_dev_t *dev);
+void dwc_ss_phy_workaround_12(dwc_dev_t *dev);
+
+/* device specific apis */
+void dwc_device_init(dwc_dev_t *dev);
+void dwc_device_reset(dwc_dev_t *dev);
+void dwc_device_run(dwc_dev_t *dev, uint8_t run);
+void dwc_device_set_addr(dwc_dev_t *dev, uint16_t addr);
+void dwc_device_set_configuration(dwc_dev_t *dev);
+void dwc_device_set_periodic_param(dwc_dev_t *dev, uint32_t val);
+void dwc_device_add_ep(dwc_dev_t *dev, dwc_ep_t new_ep);
+
+/* data transfer apis */
+int dwc_transfer_request(dwc_dev_t *dwc,
+ uint8_t usb_ep,
+ dwc_ep_direction_t dir,
+ void *buf,
+ uint32_t len,
+ dwc_transfer_callback_t callback,
+ void *callback_context);
+
+/******************** END: data needed by external APIs *********************/
+/* static apis */
+
+/* command complete event handler */
+static void dwc_event_handle_cmd_complete(dwc_dev_t *dev, uint32_t *event);
+
+/* device event handler */
+static void dwc_event_handler_device(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_device_link_status_change(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_device_reset(dwc_dev_t *dev);
+static void dwc_event_device_connect_done(dwc_dev_t *dev);
+static void dwc_event_device_disconnect(dwc_dev_t *dev);
+
+/* bulk ep event handling functions */
+static void dwc_event_handler_ep_bulk(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_handler_ep_bulk_state_inactive(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_handler_ep_bulk_state_xfer_in_prog(dwc_dev_t *dev, uint32_t *event);
+static void dwc_ep_bulk_state_inactive_enter(dwc_dev_t *dev, uint8_t ep_phy_num);
+
+/* control ep event handling functions */
+static void dwc_event_handler_ep_ctrl(dwc_dev_t *dev, uint32_t *event);
+
+static void dwc_ep_ctrl_state_setup_enter(dwc_dev_t *dev);
+static void dwc_event_handler_ep_ctrl_state_setup(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_handler_ep_ctrl_state_data(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_handler_ep_ctrl_state_wait_for_host_2(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_handler_ep_ctrl_state_wait_for_host_3(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_handler_ep_ctrl_state_status_2(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_handler_ep_ctrl_state_status_3(dwc_dev_t *dev, uint32_t *event);
+static void dwc_event_handler_ep_ctrl_state_stall(dwc_dev_t *dev, uint32_t *event);
+
+static enum handler_return dwc_irq_handler_ee1(void* arg);
+static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index);
+
+static int dwc_request_queue(dwc_dev_t *dev, uint8_t ep_phy_num, dwc_request_t *req);
+#endif
diff --git a/platform/msm_shared/usb30_dwc_hw.c b/platform/msm_shared/usb30_dwc_hw.c
new file mode 100644
index 0000000..fd18f1a
--- /dev/null
+++ b/platform/msm_shared/usb30_dwc_hw.c
@@ -0,0 +1,639 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <debug.h>
+#include <reg.h>
+#include <bits.h>
+#include <string.h>
+#include <malloc.h>
+#include <stdlib.h>
+#include <arch/defines.h>
+#include <platform/timer.h>
+#include <platform/interrupts.h>
+#include <platform/irqs.h>
+#include <kernel/event.h>
+#include <usb30_dwc_hwio.h>
+#include <usb30_dwc.h>
+#include <usb30_dwc_hw.h>
+
+extern char* ss_link_state_lookup[20];
+extern char* hs_link_state_lookup[20];
+extern char* event_lookup_device[20];
+extern char* event_lookup_ep[20];
+extern char* dev_ctrl_state_lookup[20];
+extern char* ep_state_lookup[20];
+extern char* dev_state_lookup[20];
+extern char* speed_lookup[20];
+
+//#define DEBUG_USB
+
+#ifdef DEBUG_USB
+#define DBG(...) dprintf(ALWAYS, __VA_ARGS__)
+#else
+#define DBG(...)
+#endif
+
+#define ERR(...) dprintf(ALWAYS, __VA_ARGS__)
+
+/* This file provides interface to interact with DWC hardware. This code
+ * does not maintain any soft states. It programs the h/w as requested by the
+ * APIs.
+ */
+
+/* generic api to send endpoint command */
+static void dwc_ep_cmd(dwc_dev_t *dev, uint8_t ep_phy_num, dwc_ep_cmd_t *ep_cmd)
+{
+ if(REG_READ_FIELDI(dev, GUSB2PHYCFG, 0, SUSPENDUSB20))
+ {
+ /* this must be 0. see snps 6.3.2.5.8 */
+ ASSERT(0);
+ }
+
+ /* wait until previous command is in-active */
+ while( REG_READ_FIELDI(dev, DEPCMD, ep_phy_num, CMDACT) == 1);
+
+ /* clear cmd reg */
+ REG_WRITEI(dev, DEPCMD, ep_phy_num, 0);
+
+ /* write the command parameters */
+ REG_WRITEI(dev, DEPCMDPAR2, ep_phy_num, ep_cmd->param2);
+ REG_WRITEI(dev, DEPCMDPAR1, ep_phy_num, ep_cmd->param1);
+ REG_WRITEI(dev, DEPCMDPAR0, ep_phy_num, ep_cmd->param0);
+
+ /* command */
+ REG_WRITE_FIELDI(dev, DEPCMD, ep_phy_num, CMDTYP, ep_cmd->cmd);
+
+ if ((ep_cmd->cmd == DEPCMD_CMD_UPDATE_TRANSFER) ||
+ (ep_cmd->cmd == DEPCMD_CMD_END_TRANSFER) ||
+ (ep_cmd->cmd == DEPCMD_CMD_START_NEW_CONF))
+ {
+ /* set the transfer resource index */
+ REG_WRITE_FIELDI(dev,
+ DEPCMD,
+ ep_phy_num,
+ COMMANDPARAM,
+ ep_cmd->xfer_resource_index);
+ }
+
+ /* command interrupt can be set only if device is in running state. */
+ if(dwc_device_run_status(dev))
+ {
+ REG_WRITE_FIELDI(dev, DEPCMD, ep_phy_num, CMDIOC, 1);
+ }
+
+ DBG("\nEP CMD: ep = %d : 0x%05x "
+ "pram0 = 0x%08x param1 = 0x%08x param2 = 0x%08x",
+ ep_phy_num,
+ REG_READI(dev, DEPCMD, ep_phy_num) | (1 << 10),
+ ep_cmd->param0,
+ ep_cmd->param1,
+ ep_cmd->param2);
+
+ /* set active */
+ REG_WRITE_FIELDI(dev, DEPCMD, ep_phy_num, CMDACT, 1);
+
+ /* Wait until active bit is cleared.
+ * This does not necessarily mean that command is executed.
+ * It only means a new command can be issued.
+ * We get an interrupt when command execution is complete.
+ */
+ while( REG_READ_FIELDI(dev, DEPCMD, ep_phy_num, CMDACT) == 1);
+}
+
+/* send start transfer command to the specified ep.
+ * assumes the trb are already populated.
+ */
+void dwc_ep_cmd_start_transfer(dwc_dev_t *dev, uint8_t ep_phy_num)
+{
+ dwc_ep_cmd_t ep_cmd;
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ uint32_t td_addr_low = (uint32_t) ep->trb;
+ uint32_t td_addr_high = (uint32_t) 0x0;
+
+ /* transfer descriptor (aka TRB list) address must be on 16 byte boundary.*/
+ ASSERT((td_addr_low & 0xF) == 0);
+ ASSERT((td_addr_high & 0xF) == 0);
+
+ /* set command */
+ ep_cmd.cmd = DEPCMD_CMD_START_TRANSFER;
+
+ /* set params */
+ ep_cmd.param2 = 0;
+ ep_cmd.param1 = td_addr_low;
+ ep_cmd.param0 = td_addr_high;
+
+ dwc_ep_cmd(dev, ep_phy_num, &ep_cmd);
+
+ /* Note: On execution of this cmd, a ep command complete event occurs.
+ * this DEPEVT ep event returns a XferRscIdx - transfer resource
+ * index. That must be used to Update or End this transfer.
+ */
+ DBG("\n START_TRANSFER: new EP phy_num = %d state is = %s",
+ ep_phy_num, ep_state_lookup[ep->state]);
+}
+
+/* end transfer on a particular endpoint */
+void dwc_ep_cmd_end_transfer(dwc_dev_t *dev, uint8_t ep_phy_num)
+{
+ dwc_ep_cmd_t ep_cmd;
+
+ dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+
+ ep_cmd.cmd = 0;
+
+ /* set cmd and the resource index */
+ ep_cmd.cmd = DEPCMD_CMD_END_TRANSFER;
+ ep_cmd.xfer_resource_index = ep->resource_idx;
+
+ /* params */
+ ep_cmd.param2 = 0;
+ ep_cmd.param1 = 0;
+ ep_cmd.param0 = 0;
+
+ /* note: TRB status is not updated by the h/w when end transfer is issued.
+ * snps: 6.3.2.5.7
+ */
+ dwc_ep_cmd(dev, ep_phy_num, &ep_cmd);
+}
+
+/* set number of transfer resources to be used for the ep. */
+void dwc_ep_cmd_set_transfer_resource(dwc_dev_t *dev, uint8_t ep_phy_num)
+{
+ dwc_ep_cmd_t ep_cmd;
+
+ /* set command */
+ ep_cmd.cmd = DEPCMD_CMD_SET_TR_CONF;
+
+ ep_cmd.param2 = 0;
+ ep_cmd.param1 = 0;
+ ep_cmd.param0 = 1; /* number of transfer resources: always set to 1 */
+
+ dwc_ep_cmd(dev, ep_phy_num, &ep_cmd);
+}
+
+/* Configure end point in the core before starting to use it. The following
+ parameters need to be configured:
+ - usb ep number
+ - ep direction
+ - ep type
+ - mak pkt size
+ - burst size
+ - transfer events to be generated for this ep
+ - for IN ep, tx fifo to be used
+*/
+void dwc_ep_cmd_set_config(dwc_dev_t *dev, uint8_t index, uint8_t action)
+{
+ uint8_t ep_phy_num;
+ uint8_t ep_usb_num;
+ uint8_t ep_direction;
+ uint16_t max_pkt_size;
+ uint32_t burst_size;
+ uint8_t tx_fifo_num;
+
+ dwc_ep_t ep;
+ dwc_ep_cmd_t ep_cmd;
+ dwc_ep_type_t ep_type;
+
+ ep = dev->ep[index];
+
+ /* get the corresponding physical ep number */
+ ep_phy_num = ep.phy_num;
+ ep_usb_num = ep.number;
+ ep_direction = ep.dir;
+ ep_type = ep.type;
+ max_pkt_size = ep.max_pkt_size;
+ burst_size = ep.burst_size;
+ tx_fifo_num = ep.tx_fifo_num;
+
+ /* set command */
+ ep_cmd.cmd = DEPCMD_CMD_SET_EP_CONF;
+ ep_cmd.param2 = 0x0;
+ ep_cmd.param1 = 0x0;
+ ep_cmd.param0 = 0x0;
+
+ /* TODO: set bInterval according to ep value.
+ * ignored since it is not used for bulk.
+ */
+
+ /* map this usb ep to the ep_phy_num */
+ ep_cmd.param1 |= ep_usb_num << DEPCMDPAR1_USB_EP_NUM_BIT;
+ ep_cmd.param1 |= ep_direction << DEPCMDPAR1_USB_EP_DIR_BIT;
+
+ /* enable event generation */
+ ep_cmd.param1 |= BIT(DEPCMDPAR2_XFER_N_RDY_BIT);
+ ep_cmd.param1 |= BIT(DEPCMDPAR2_XFER_COMPLETE_BIT);
+
+ /* interrupt number: which event buffer to be used. */
+ ep_cmd.param1 |= 0;
+
+ /* action: 0 = initialize */
+ ep_cmd.param0 |= (action << DEPCMDPAR0_ACTION_BIT);
+ /* burst size */
+ ep_cmd.param0 |= (burst_size << DEPCMDPAR0_BURST_SIZE_BIT);
+
+ ep_cmd.param0 |= tx_fifo_num << DEPCMDPAR0_FIFO_NUM_BIT;
+ ep_cmd.param0 |= ep_type << DEPCMDPAR0_EP_TYPE_BIT;
+ ep_cmd.param0 |= max_pkt_size << DEPCMDPAR0_MAX_PKT_SIZE_BIT;
+
+ dwc_ep_cmd(dev, ep_phy_num, &ep_cmd);
+}
+
+/* send stall command to ep */
+void dwc_ep_cmd_stall(dwc_dev_t *dev, uint8_t ep_phy_num)
+{
+ dwc_ep_cmd_t ep_cmd;
+
+ /* set command */
+ ep_cmd.cmd = DEPCMD_CMD_SET_STALL;
+
+ ep_cmd.param2 = 0;
+ ep_cmd.param1 = 0;
+ ep_cmd.param0 = 0;
+
+ DBG("\nSTALLING.... ep_phy_num = %d\n", ep_phy_num);
+
+ dwc_ep_cmd(dev, ep_phy_num, &ep_cmd);
+}
+
+/* clear stall */
+void dwc_ep_cmd_clear_stall(dwc_dev_t *dev, uint8_t ep_phy_num)
+{
+ dwc_ep_cmd_t ep_cmd;
+
+ /* set command */
+ ep_cmd.cmd = DEPCMD_CMD_CLEAR_STALL;
+
+ ep_cmd.param2 = 0;
+ ep_cmd.param1 = 0;
+ ep_cmd.param0 = 0;
+
+ dwc_ep_cmd(dev, ep_phy_num, &ep_cmd);
+}
+
+/* send a start new config command */
+void dwc_ep_cmd_start_new_config(dwc_dev_t *dev,
+ uint8_t ep_phy_num,
+ uint8_t resource_idx)
+{
+ dwc_ep_cmd_t ep_cmd;
+
+ /* set command */
+ ep_cmd.cmd = DEPCMD_CMD_START_NEW_CONF;
+ ep_cmd.xfer_resource_index = resource_idx;
+
+ ep_cmd.param2 = 0;
+ ep_cmd.param1 = 0;
+ ep_cmd.param0 = 0;
+
+ dwc_ep_cmd(dev, ep_phy_num, &ep_cmd);
+}
+
+/******************** DWC Device related APIs *********************************/
+
+/* generic api to send device command */
+static void dwc_device_cmd(dwc_dev_t *dev, dwc_device_cmd_t *cmd)
+{
+ uint8_t active = REG_READ_FIELD(dev, DGCMD, CMDACT);
+
+ ASSERT(active);
+
+ REG_WRITE(dev, DGCMDPAR, cmd->param);
+ REG_WRITE_FIELD(dev, DGCMD, CMDTYP, cmd->cmd);
+
+ /* wait until active field is cleared. */
+ while(!REG_READ_FIELD(dev, DGCMD, CMDACT));
+
+ if(REG_READ_FIELD(dev, DGCMD, CMDSTATUS))
+ {
+ ERR("\n\n device command failed. \n\n");
+ ASSERT(0);
+ }
+}
+
+/* set periodic param */
+void dwc_device_set_periodic_param(dwc_dev_t *dev, uint32_t val)
+{
+ dwc_device_cmd_t cmd;
+
+ cmd.cmd = DWC_DEV_CMD_SET_PERIODIC_PARAMS_VAL;
+ cmd.param = val;
+
+ /* send device command to set period param value */
+ dwc_device_cmd(dev, &cmd);
+}
+
+/* set device address */
+void dwc_device_set_addr(dwc_dev_t *dev, uint16_t addr)
+{
+ REG_WRITE_FIELD(dev, DCFG, DEVADDR, addr);
+}
+
+/* reset device */
+void dwc_device_reset(dwc_dev_t *dev)
+{
+ /* start reset */
+ REG_WRITE_FIELD(dev, DCTL, CSFTRST, 1);
+
+ /* wait until done */
+ while(REG_READ_FIELD(dev, DCTL, CSFTRST));
+}
+
+/* Run/Stop device: 1 == run. 0 == stop */
+void dwc_device_run(dwc_dev_t *dev, uint8_t run)
+{
+ REG_WRITE_FIELD(dev, DCTL, RUN_STOP, run);
+}
+
+/* is device running? */
+uint8_t dwc_device_run_status(dwc_dev_t *dev)
+{
+ return REG_READ_FIELD(dev, DCTL, RUN_STOP);
+}
+
+/******************** Managing various events *********************************/
+/* event init:
+ program event buffer address, size and reset event count to 0.
+ */
+void dwc_event_init(dwc_dev_t *dev)
+{
+ /* snps 8.2.2 */
+
+ /* event buffer address */
+ REG_WRITEI(dev, GEVNTADRLO, 0, (uint32_t) dev->event_buf.buf);
+ REG_WRITEI(dev, GEVNTADRHI, 0, 0x0);
+
+ /* set buffer size. assuming interrupt is always needed on new event,
+ * bit 31 is not set.
+ */
+ REG_WRITEI(dev, GEVNTSIZ, 0, dev->event_buf.buf_size);
+
+ /* reset count */
+ REG_WRITEI(dev, GEVNTCOUNT, 0, 0x0);
+}
+
+/* event update index */
+static void dwc_event_update_index(uint16_t *index, uint16_t max_count)
+{
+ if(*index == max_count)
+ {
+ /* we have read the last entry. Need to roll over for next reading.*/
+ *index = 0;
+ }
+ else
+ {
+ *index += 1;
+ }
+}
+
+/* Returns next event from event queue and the size of event
+ * Event buffer is a circular buffer that the hardware populates when any of
+ * the enabled event occurs. An interrupt is generated if interrupt is enabled
+ * for that event.
+ * This api returns the next valid event from the event buffer and updates event
+ * buffer index.
+ * Most events are 4 byte long
+ * Note: caller must provide at least 12 bytes buffer in case the
+ * next event is the special 12 byte event.
+ */
+uint16_t dwc_event_get_next(dwc_dev_t *dev, uint32_t *event)
+{
+ uint16_t count;
+ uint16_t event_size = 0;
+ uint32_t *buf;
+
+ /* read the number of valid event data in event buffer. */
+ count = REG_READI(dev, GEVNTCOUNT, 0);
+
+ if(count == 0)
+ {
+ /* no events in buffer. */
+ return event_size;
+ }
+
+ /* each event is at least 4 bytes long.
+ * make sure there is at least one event to read.
+ */
+ ASSERT(count >= 4);
+
+ /* get event buffer for this device */
+ buf = dev->event_buf.buf;
+
+ /* invalidate cached event buf data */
+ arch_invalidate_cache_range((addr_t) (buf + dev->event_buf.index), 4);
+
+ /* read next event */
+ *event = buf[dev->event_buf.index];
+ event_size += 4;
+ dwc_event_update_index(&dev->event_buf.index, dev->event_buf.max_index);
+
+
+ /* is this buffer overflow event? */
+ if((DWC_EVENT_DEVICE_EVENT_ID(*event) == DWC_EVENT_DEVICE_EVENT_ID_BUFFER_OVERFLOW))
+ {
+ /* ouch... */
+ ERR("\n Event buffer is full. Need to increase size.\n");
+ ASSERT(0);
+ }
+
+ /* check for that special 12 byte event */
+ if( DWC_EVENT_IS_DEVICE_EVENT(*event) &
+ (DWC_EVENT_DEVICE_EVENT_ID(*event) == DWC_EVENT_DEVICE_EVENT_ID_VENDOR_DEVICE_TEST_LMP))
+ {
+ /* invalidate cached event buf data */
+ arch_invalidate_cache_range((addr_t) (buf + dev->event_buf.index), 4);
+
+ *(event + 1) = buf[dev->event_buf.index];
+ event_size += 4;
+ dwc_event_update_index(&dev->event_buf.index, dev->event_buf.buf_size);
+
+ /* invalidate cached event buf data */
+ arch_invalidate_cache_range((addr_t) (buf + dev->event_buf.index), 4);
+
+ *(event + 1) = buf[dev->event_buf.index];
+ event_size += 4;
+ dwc_event_update_index(&dev->event_buf.index, dev->event_buf.buf_size);
+ }
+
+ return event_size;
+}
+
+/* Lets h/w know that we have processed "count" bytes of data from event buffer
+ * and it can use that space for new events.
+ * This must be done only after the event is processed.
+ */
+void dwc_event_processed(dwc_dev_t *dev, uint16_t count)
+{
+ REG_WRITEI(dev, GEVNTCOUNT, 0, count);
+}
+
+/* enable device event generation:
+ * events - bit map of events defined in dwc_event_device_event_id_t
+ */
+void dwc_event_device_enable(dwc_dev_t *dev, uint32_t events)
+{
+ REG_WRITE(dev, DEVTEN, events);
+}
+
+/*************** Generic APIs affecting overall controller ********************/
+
+/* reset HS and SS PHY's digital interface: UTMI + PIPE3 */
+void dwc_phy_digital_reset(dwc_dev_t *dev)
+{
+ REG_WRITE_FIELDI(dev, GUSB2PHYCFG, 0, PHYSOFTRST, 1);
+ REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 1);
+
+ /* per HPG */
+ udelay(100);
+
+ REG_WRITE_FIELDI(dev, GUSB2PHYCFG, 0, PHYSOFTRST, 0);
+ REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 0);
+
+ /* per HPG */
+ udelay(100);
+}
+
+void dwc_usb2_phy_soft_reset(dwc_dev_t *dev)
+{
+ REG_WRITE_FIELDI(dev, GUSB2PHYCFG, 0, PHYSOFTRST, 1);
+
+ udelay(100);
+
+ REG_WRITE_FIELDI(dev, GUSB2PHYCFG, 0, PHYSOFTRST, 0);
+
+ udelay(100);
+}
+
+/* workaround_12 as described in HPG */
+void dwc_ss_phy_workaround_12(dwc_dev_t *dev)
+{
+ /* 12. */
+ REG_WRITEI(dev, GUSB3PIPECTL, 0, 0x30C0003);
+}
+
+/* AXI master config */
+void dwc_axi_master_config(dwc_dev_t *dev)
+{
+ uint32_t reg = 0;
+
+ reg = (DWC_GSBUSCFG0_INCR4BRSTENA_BMSK |
+ DWC_GSBUSCFG0_INCR8BRSTENA_BMSK |
+ DWC_GSBUSCFG0_INCR16BRSTENA_BMSK);
+
+ REG_WRITE(dev, GSBUSCFG0, reg);
+}
+
+/* read the controller id and version information */
+uint32_t dwc_coreid(dwc_dev_t *dev)
+{
+ return REG_READ(dev, GSNPSID);
+}
+
+/* read the current connection speed. */
+uint8_t dwc_connectspeed(dwc_dev_t *dev)
+{
+ return REG_READ_FIELD(dev, DSTS, CONNECTSPD);
+}
+
+/* disable all non-control EPs */
+void dwc_ep_disable_non_control(dwc_dev_t *dev)
+{
+ uint32_t reg = REG_READ(dev, DALEPENA);
+
+ /* clear all except the control IN and OUT ep */
+ reg &= 0x3;
+
+ REG_WRITE(dev, DALEPENA, reg);
+}
+
+/* disable a specific ep */
+void dwc_ep_disable(dwc_dev_t *dev, uint8_t ep_phy_num)
+{
+ uint32_t reg = REG_READ(dev, DALEPENA);
+
+ reg &= ~BIT(ep_phy_num);
+
+ REG_WRITE(dev, DALEPENA, reg);
+}
+
+/* enable a specific ep */
+void dwc_ep_enable(dwc_dev_t *dev, uint8_t ep_phy_num)
+{
+ uint32_t reg = REG_READ(dev, DALEPENA);
+
+ reg |= BIT(ep_phy_num);
+
+ REG_WRITE(dev, DALEPENA, reg);
+}
+
+/* global reset of controller.
+ * 1 == put in reset. 0 == out of reset
+ */
+void dwc_reset(dwc_dev_t *dev, uint8_t reset)
+{
+ /* snps databook table 6-11 indicates this field to be used only for debug
+ * purpose. use dctl.softreset instead for devide mode.
+ * but hpg 4.4.2. 8.a says use this.
+ */
+ REG_WRITE_FIELD(dev, GCTL, CORESOFTRESET, reset);
+
+ /* per HPG */
+ udelay(100);
+}
+
+/* initialize global control reg for device mode operation.
+ * sequence numbers are as described in HPG.
+ */
+void dwc_gctl_init(dwc_dev_t *dev)
+{
+ /* 16. */
+ /* a. default value is good for RAM clock */
+ /* b. default value is good for Disable Debug Attach */
+ REG_WRITE_FIELD(dev, GCTL, DEBUGATTACH, 0);
+
+ /* c & d: disable loopback/local loopback
+ * TODO: possibly for older version. no such fields in GCTL
+ */
+
+ /* e. no soft reset. */
+ REG_WRITE_FIELD(dev, GCTL, CORESOFTRESET, 0);
+
+ /* f. set port capability direction: device */
+ REG_WRITE_FIELD(dev, GCTL, PRTCAPDIR, 0x2);
+
+ /* g. set scale down value */
+ REG_WRITE_FIELD(dev, GCTL, FRMSCLDWN, 0x0);
+
+ /* h. enable multiple attempts for SS connection */
+ REG_WRITE_FIELD(dev, GCTL, U2RSTECN, 1);
+
+ /* i. set power down scale of snps phy */
+ REG_WRITE_FIELD(dev, GCTL, PWRDNSCALE, 0x2);
+
+ /* j. clear SOFITPSYNC bit */
+ REG_WRITE_FIELD(dev, GCTL, SOFITPSYNC, 0);
+}
diff --git a/platform/msm_shared/usb30_dwc_hw.h b/platform/msm_shared/usb30_dwc_hw.h
new file mode 100644
index 0000000..56b32ba
--- /dev/null
+++ b/platform/msm_shared/usb30_dwc_hw.h
@@ -0,0 +1,54 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _USB30_DWC_HW_
+#define _USB30_DWC_HW_
+
+void dwc_ep_cmd_start_transfer(dwc_dev_t *dev, uint8_t ep_phy_num);
+void dwc_ep_cmd_end_transfer(dwc_dev_t *dev, uint8_t ep_phy_num);
+void dwc_ep_cmd_set_config(dwc_dev_t *dev, uint8_t index, uint8_t action);
+void dwc_ep_cmd_set_transfer_resource(dwc_dev_t *dev, uint8_t index);
+void dwc_ep_cmd_stall(dwc_dev_t *dev, uint8_t ep_phy_num);
+void dwc_ep_cmd_start_new_config(dwc_dev_t *dev,
+ uint8_t ep_phy_num,
+ uint8_t resource_idx);
+
+void dwc_ep_enable(dwc_dev_t *dev, uint8_t ep_phy_num);
+void dwc_ep_disable(dwc_dev_t *dev, uint8_t ep_phy_num);
+void dwc_ep_disable_non_control(dwc_dev_t *dev);
+
+void dwc_event_init(dwc_dev_t *dev);
+uint16_t dwc_event_get_next(dwc_dev_t *dev, uint32_t *event);
+void dwc_event_processed(dwc_dev_t *dev, uint16_t count);
+void dwc_event_device_enable(dwc_dev_t *dev, uint32_t events);
+
+uint32_t dwc_coreid(dwc_dev_t *dev);
+uint8_t dwc_connectspeed(dwc_dev_t *dev);
+uint8_t dwc_device_run_status(dwc_dev_t *dev);
+void dwc_gctl_init(dwc_dev_t *dev);
+void dwc_axi_master_config(dwc_dev_t *dev);
+#endif
diff --git a/platform/msm_shared/usb30_dwc_hwio.h b/platform/msm_shared/usb30_dwc_hwio.h
new file mode 100644
index 0000000..ce77d26
--- /dev/null
+++ b/platform/msm_shared/usb30_dwc_hwio.h
@@ -0,0 +1,1529 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _USB30_DWC_HWIO_H_
+#define _USB30_DWC_HWIO_H_
+
+/* Macros to simplify dwc reg read */
+#define REG_READ(_dev, _reg) readl(DWC_##_reg##_ADDR(_dev->base))
+#define REG_READI(_dev, _reg, _index) readl(DWC_##_reg##_ADDR(_dev->base, _index))
+
+/* Macros to simplify dwc reg write */
+#define REG_WRITE(_dev, _reg, _value) writel(_value, DWC_##_reg##_ADDR(_dev->base))
+#define REG_WRITEI(_dev, _reg, _index, _value) writel(_value, DWC_##_reg##_ADDR(_dev->base, _index))
+
+#define REG_BMSK(_reg, _field) DWC_##_reg##_##_field##_BMSK
+#define REG_SHFT(_reg, _field) DWC_##_reg##_##_field##_SHFT
+
+/* read specified field in the register */
+#define REG_READ_FIELD(_dev, _reg, _field) ((REG_READ(_dev,_reg) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field))
+#define REG_READ_FIELDI(_dev, _reg, _index, _field) ((REG_READI(_dev,_reg, _index) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field))
+#define REG_READ_FIELD_LOCAL(_addr, _reg, _field) (((*_addr) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field))
+
+
+/* write specified field in the register: implements a read/modify/write */
+#define REG_WRITE_FIELD(_dev, _reg, _field, _value) \
+ REG_WRITE(_dev, _reg, ((REG_READ(_dev, _reg) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field))))
+
+#define REG_WRITE_FIELDI(_dev, _reg, _index, _field, _value) \
+ REG_WRITEI(_dev, _reg, _index, ((REG_READI(_dev, _reg, _index) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field))))
+
+#define REG_WRITE_FIELD_LOCAL(_addr, _reg, _field, _value) \
+ (*(_addr) = ((*(_addr) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field))))
+
+
+
+/* The following defines are auto generated. */
+
+/**
+ @file usb30_dwc_hwio.h
+ @brief Auto-generated HWIO interface include file.
+
+ This file contains HWIO register definitions for the following modules:
+ DWC_USB3
+
+ 'Include' filters applied:
+ 'Exclude' filters applied: RESERVED DUMMY
+*/
+/*----------------------------------------------------------------------------
+ * MODULE: DWC_USB3
+ *--------------------------------------------------------------------------*/
+#define DWC_USB3_REG_BASE_OFFS 0x00000000
+#define DWC_GUSB2PHYCFG_ADDR(base,p) ((base) + 0x0000c200 + 0x4 * (p))
+#define DWC_GUSB2PHYCFG_OFFS(p) (0x0000c200 + 0x4 * (p))
+#define DWC_GUSB2PHYCFG_RMSK 0xffffffff
+#define DWC_GUSB2PHYCFG_MAXp 0
+#define DWC_GUSB2PHYCFG_POR 0x00002500
+#define DWC_GUSB2PHYCFG_PHYSOFTRST_BMSK 0x80000000
+#define DWC_GUSB2PHYCFG_PHYSOFTRST_SHFT 0x1f
+#define DWC_GUSB2PHYCFG_RSVD_BMSK 0x7ff80000
+#define DWC_GUSB2PHYCFG_RSVD_SHFT 0x13
+#define DWC_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_BMSK 0x40000
+#define DWC_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_SHFT 0x12
+#define DWC_GUSB2PHYCFG_ULPIEXTVBUSDRV_BMSK 0x20000
+#define DWC_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHFT 0x11
+#define DWC_GUSB2PHYCFG_ULPICLKSUSM_BMSK 0x10000
+#define DWC_GUSB2PHYCFG_ULPICLKSUSM_SHFT 0x10
+#define DWC_GUSB2PHYCFG_ULPIAUTORES_BMSK 0x8000
+#define DWC_GUSB2PHYCFG_ULPIAUTORES_SHFT 0xf
+#define DWC_GUSB2PHYCFG_RSVD9_BMSK 0x4000
+#define DWC_GUSB2PHYCFG_RSVD9_SHFT 0xe
+#define DWC_GUSB2PHYCFG_USBTRDTIM_BMSK 0x3c00
+#define DWC_GUSB2PHYCFG_USBTRDTIM_SHFT 0xa
+#define DWC_GUSB2PHYCFG_RSVD0_BMSK 0x200
+#define DWC_GUSB2PHYCFG_RSVD0_SHFT 0x9
+#define DWC_GUSB2PHYCFG_ENBLSLPM_BMSK 0x100
+#define DWC_GUSB2PHYCFG_ENBLSLPM_SHFT 0x8
+#define DWC_GUSB2PHYCFG_PHYSEL_BMSK 0x80
+#define DWC_GUSB2PHYCFG_PHYSEL_SHFT 0x7
+#define DWC_GUSB2PHYCFG_SUSPENDUSB20_BMSK 0x40
+#define DWC_GUSB2PHYCFG_SUSPENDUSB20_SHFT 0x6
+#define DWC_GUSB2PHYCFG_FSINTF_BMSK 0x20
+#define DWC_GUSB2PHYCFG_FSINTF_SHFT 0x5
+#define DWC_GUSB2PHYCFG_ULPI_UTMI_SEL_BMSK 0x10
+#define DWC_GUSB2PHYCFG_ULPI_UTMI_SEL_SHFT 0x4
+#define DWC_GUSB2PHYCFG_PHYIF_BMSK 0x8
+#define DWC_GUSB2PHYCFG_PHYIF_SHFT 0x3
+#define DWC_GUSB2PHYCFG_B1L_BMSK 0x7
+#define DWC_GUSB2PHYCFG_B1L_SHFT 0x0
+
+#define DWC_GUSB2I2CCTL_ADDR(base,p) ((base) + 0x0000c240 + 0x4 * (p))
+#define DWC_GUSB2I2CCTL_OFFS(p) (0x0000c240 + 0x4 * (p))
+#define DWC_GUSB2I2CCTL_RMSK 0xffffffff
+#define DWC_GUSB2I2CCTL_MAXp 0
+#define DWC_GUSB2I2CCTL_POR 0x00000000
+#define DWC_GUSB2I2CCTL_RSVD_BMSK 0x80000000
+#define DWC_GUSB2I2CCTL_RSVD_SHFT 0x1f
+#define DWC_GUSB2I2CCTL_BSYDNE_BMSK 0x40000000
+#define DWC_GUSB2I2CCTL_BSYDNE_SHFT 0x1e
+#define DWC_GUSB2I2CCTL_ACK_BMSK 0x20000000
+#define DWC_GUSB2I2CCTL_ACK_SHFT 0x1d
+#define DWC_GUSB2I2CCTL_RW_BMSK 0x10000000
+#define DWC_GUSB2I2CCTL_RW_SHFT 0x1c
+#define DWC_GUSB2I2CCTL_I2CDATSE0_BMSK 0x8000000
+#define DWC_GUSB2I2CCTL_I2CDATSE0_SHFT 0x1b
+#define DWC_GUSB2I2CCTL_I2CDEVADR_BMSK 0x6000000
+#define DWC_GUSB2I2CCTL_I2CDEVADR_SHFT 0x19
+#define DWC_GUSB2I2CCTL_I2CSUSPCTL_BMSK 0x1000000
+#define DWC_GUSB2I2CCTL_I2CSUSPCTL_SHFT 0x18
+#define DWC_GUSB2I2CCTL_I2CEN_BMSK 0x800000
+#define DWC_GUSB2I2CCTL_I2CEN_SHFT 0x17
+#define DWC_GUSB2I2CCTL_ADDR_BMSK 0x7f0000
+#define DWC_GUSB2I2CCTL_ADDR_SHFT 0x10
+#define DWC_GUSB2I2CCTL_REGADDR_BMSK 0xff00
+#define DWC_GUSB2I2CCTL_REGADDR_SHFT 0x8
+#define DWC_GUSB2I2CCTL_RWDATA_BMSK 0xff
+#define DWC_GUSB2I2CCTL_RWDATA_SHFT 0x0
+
+#define DWC_GUSB2PHYACC_ULPI_ADDR(base,p) ((base) + 0x0000c280 + 0x4 * (p))
+#define DWC_GUSB2PHYACC_ULPI_OFFS(p) (0x0000c280 + 0x4 * (p))
+#define DWC_GUSB2PHYACC_ULPI_RMSK 0xffff1fff
+#define DWC_GUSB2PHYACC_ULPI_MAXp 0
+#define DWC_GUSB2PHYACC_ULPI_POR 0x00000000
+#define DWC_GUSB2PHYACC_ULPI_RSVD42_BMSK 0xf8000000
+#define DWC_GUSB2PHYACC_ULPI_RSVD42_SHFT 0x1b
+#define DWC_GUSB2PHYACC_ULPI_DISUIPIDRVR_BMSK 0x4000000
+#define DWC_GUSB2PHYACC_ULPI_DISUIPIDRVR_SHFT 0x1a
+#define DWC_GUSB2PHYACC_ULPI_NEWREGREQ_BMSK 0x2000000
+#define DWC_GUSB2PHYACC_ULPI_NEWREGREQ_SHFT 0x19
+#define DWC_GUSB2PHYACC_ULPI_VSTSDONE_BMSK 0x1000000
+#define DWC_GUSB2PHYACC_ULPI_VSTSDONE_SHFT 0x18
+#define DWC_GUSB2PHYACC_ULPI_VSTSBSY_BMSK 0x800000
+#define DWC_GUSB2PHYACC_ULPI_VSTSBSY_SHFT 0x17
+#define DWC_GUSB2PHYACC_ULPI_REGWR_BMSK 0x400000
+#define DWC_GUSB2PHYACC_ULPI_REGWR_SHFT 0x16
+#define DWC_GUSB2PHYACC_ULPI_REGADDR_BMSK 0x3f0000
+#define DWC_GUSB2PHYACC_ULPI_REGADDR_SHFT 0x10
+#define DWC_GUSB2PHYACC_ULPI_EXTREGADDR_BMSK 0x1f00
+#define DWC_GUSB2PHYACC_ULPI_EXTREGADDR_SHFT 0x8
+#define DWC_GUSB2PHYACC_ULPI_REGDATA_BMSK 0xff
+#define DWC_GUSB2PHYACC_ULPI_REGDATA_SHFT 0x0
+
+#define DWC_GUSB3PIPECTL_ADDR(base,p) ((base) + 0x0000c2c0 + 0x4 * (p))
+#define DWC_GUSB3PIPECTL_OFFS(p) (0x0000c2c0 + 0x4 * (p))
+#define DWC_GUSB3PIPECTL_RMSK 0xffffffff
+#define DWC_GUSB3PIPECTL_MAXp 0
+#define DWC_GUSB3PIPECTL_POR 0x034c0003
+#define DWC_GUSB3PIPECTL_PHYSOFTRST_BMSK 0x80000000
+#define DWC_GUSB3PIPECTL_PHYSOFTRST_SHFT 0x1f
+#define DWC_GUSB3PIPECTL_RSVD8_BMSK 0x40000000
+#define DWC_GUSB3PIPECTL_RSVD8_SHFT 0x1e
+#define DWC_GUSB3PIPECTL_U2SSINACTP3OK_BMSK 0x20000000
+#define DWC_GUSB3PIPECTL_U2SSINACTP3OK_SHFT 0x1d
+#define DWC_GUSB3PIPECTL_DISRXDETP3_BMSK 0x10000000
+#define DWC_GUSB3PIPECTL_DISRXDETP3_SHFT 0x1c
+#define DWC_GUSB3PIPECTL_UX_EXIT_IN_PX_BMSK 0x8000000
+#define DWC_GUSB3PIPECTL_UX_EXIT_IN_PX_SHFT 0x1b
+#define DWC_GUSB3PIPECTL_PING_ENHANCEMENT_EN_BMSK 0x4000000
+#define DWC_GUSB3PIPECTL_PING_ENHANCEMENT_EN_SHFT 0x1a
+#define DWC_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_BMSK 0x2000000
+#define DWC_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_SHFT 0x19
+#define DWC_GUSB3PIPECTL_REQUEST_P1P2P3_BMSK 0x1000000
+#define DWC_GUSB3PIPECTL_REQUEST_P1P2P3_SHFT 0x18
+#define DWC_GUSB3PIPECTL_STARTRXDETU3RXDET_BMSK 0x800000
+#define DWC_GUSB3PIPECTL_STARTRXDETU3RXDET_SHFT 0x17
+#define DWC_GUSB3PIPECTL_DISRXDETU3RXDET_BMSK 0x400000
+#define DWC_GUSB3PIPECTL_DISRXDETU3RXDET_SHFT 0x16
+#define DWC_GUSB3PIPECTL_GUSBPIPECTL_BUS_BMSK 0x200000
+#define DWC_GUSB3PIPECTL_GUSBPIPECTL_BUS_SHFT 0x15
+#define DWC_GUSB3PIPECTL_DELAYP1P2P3_BMSK 0x180000
+#define DWC_GUSB3PIPECTL_DELAYP1P2P3_SHFT 0x13
+#define DWC_GUSB3PIPECTL_DELAYP1TRANS_BMSK 0x40000
+#define DWC_GUSB3PIPECTL_DELAYP1TRANS_SHFT 0x12
+#define DWC_GUSB3PIPECTL_SUSPENDENABLE_BMSK 0x20000
+#define DWC_GUSB3PIPECTL_SUSPENDENABLE_SHFT 0x11
+#define DWC_GUSB3PIPECTL_DATWIDTH_BMSK 0x18000
+#define DWC_GUSB3PIPECTL_DATWIDTH_SHFT 0xf
+#define DWC_GUSB3PIPECTL_ABORTRXDETINU2_BMSK 0x4000
+#define DWC_GUSB3PIPECTL_ABORTRXDETINU2_SHFT 0xe
+#define DWC_GUSB3PIPECTL_SKIPRXDET_BMSK 0x2000
+#define DWC_GUSB3PIPECTL_SKIPRXDET_SHFT 0xd
+#define DWC_GUSB3PIPECTL_LFPSP0ALGN_BMSK 0x1000
+#define DWC_GUSB3PIPECTL_LFPSP0ALGN_SHFT 0xc
+#define DWC_GUSB3PIPECTL_P3P2TRANOK_BMSK 0x800
+#define DWC_GUSB3PIPECTL_P3P2TRANOK_SHFT 0xb
+#define DWC_GUSB3PIPECTL_P3EXSIGP2_BMSK 0x400
+#define DWC_GUSB3PIPECTL_P3EXSIGP2_SHFT 0xa
+#define DWC_GUSB3PIPECTL_LFPSFILTER_BMSK 0x200
+#define DWC_GUSB3PIPECTL_LFPSFILTER_SHFT 0x9
+#define DWC_GUSB3PIPECTL_PRTOPDIR_BMSK 0x180
+#define DWC_GUSB3PIPECTL_PRTOPDIR_SHFT 0x7
+#define DWC_GUSB3PIPECTL_TX_SWING_BMSK 0x40
+#define DWC_GUSB3PIPECTL_TX_SWING_SHFT 0x6
+#define DWC_GUSB3PIPECTL_TX_MARGIN_BMSK 0x38
+#define DWC_GUSB3PIPECTL_TX_MARGIN_SHFT 0x3
+#define DWC_GUSB3PIPECTL_TX_DE_EPPHASIS_BMSK 0x6
+#define DWC_GUSB3PIPECTL_TX_DE_EPPHASIS_SHFT 0x1
+#define DWC_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_BMSK 0x1
+#define DWC_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_SHFT 0x0
+
+#define DWC_GTXFIFOSIZ_ADDR(base,p) ((base) + 0x0000c300 + 0x4 * (p))
+#define DWC_GTXFIFOSIZ_OFFS(p) (0x0000c300 + 0x4 * (p))
+#define DWC_GTXFIFOSIZ_RMSK 0xffffffff
+#define DWC_GTXFIFOSIZ_MAXp 15
+#define DWC_GTXFIFOSIZ_POR 0x00000000
+#define DWC_GTXFIFOSIZ_TXFSTADDR_N_BMSK 0xffff0000
+#define DWC_GTXFIFOSIZ_TXFSTADDR_N_SHFT 0x10
+#define DWC_GTXFIFOSIZ_TXFDEP_N_BMSK 0xffff
+#define DWC_GTXFIFOSIZ_TXFDEP_N_SHFT 0x0
+
+#define DWC_GRXFIFOSIZ_ADDR(base,p) ((base) + 0x0000c380 + 0x4 * (p))
+#define DWC_GRXFIFOSIZ_OFFS(p) (0x0000c380 + 0x4 * (p))
+#define DWC_GRXFIFOSIZ_RMSK 0xffffffff
+#define DWC_GRXFIFOSIZ_MAXp 2
+#define DWC_GRXFIFOSIZ_POR 0x00000000
+#define DWC_GRXFIFOSIZ_RXFSTADDR_N_BMSK 0xffff0000
+#define DWC_GRXFIFOSIZ_RXFSTADDR_N_SHFT 0x10
+#define DWC_GRXFIFOSIZ_RXFDEP_N_BMSK 0xffff
+#define DWC_GRXFIFOSIZ_RXFDEP_N_SHFT 0x0
+
+#define DWC_GEVNTADRLO_ADDR(base,p) ((base) + 0x0000c400 + 0x10 * (p))
+#define DWC_GEVNTADRLO_OFFS(p) (0x0000c400 + 0x10 * (p))
+#define DWC_GEVNTADRLO_RMSK 0xffffffff
+#define DWC_GEVNTADRLO_MAXp 1
+#define DWC_GEVNTADRLO_POR 0x00000000
+#define DWC_GEVNTADRLO_EVNTADRLO_BMSK 0xffffffff
+#define DWC_GEVNTADRLO_EVNTADRLO_SHFT 0x0
+
+#define DWC_GEVNTADRHI_ADDR(base,p) ((base) + 0x0000c404 + 0x10 * (p))
+#define DWC_GEVNTADRHI_OFFS(p) (0x0000c404 + 0x10 * (p))
+#define DWC_GEVNTADRHI_RMSK 0xffffffff
+#define DWC_GEVNTADRHI_MAXp 1
+#define DWC_GEVNTADRHI_POR 0x00000000
+#define DWC_GEVNTADRHI_EVNTADRHI_BMSK 0xffffffff
+#define DWC_GEVNTADRHI_EVNTADRHI_SHFT 0x0
+
+#define DWC_GEVNTSIZ_ADDR(base,p) ((base) + 0x0000c408 + 0x10 * (p))
+#define DWC_GEVNTSIZ_OFFS(p) (0x0000c408 + 0x10 * (p))
+#define DWC_GEVNTSIZ_RMSK 0xffffffff
+#define DWC_GEVNTSIZ_MAXp 1
+#define DWC_GEVNTSIZ_POR 0x00000000
+#define DWC_GEVNTSIZ_EVNTINTRPTMASK_BMSK 0x80000000
+#define DWC_GEVNTSIZ_EVNTINTRPTMASK_SHFT 0x1f
+#define DWC_GEVNTSIZ_RSVD74_BMSK 0x7fff0000
+#define DWC_GEVNTSIZ_RSVD74_SHFT 0x10
+#define DWC_GEVNTSIZ_EVENTSIZ_BMSK 0xffff
+#define DWC_GEVNTSIZ_EVENTSIZ_SHFT 0x0
+
+#define DWC_GEVNTCOUNT_ADDR(base,p) ((base) + 0x0000c40c + 0x10 * (p))
+#define DWC_GEVNTCOUNT_OFFS(p) (0x0000c40c + 0x10 * (p))
+#define DWC_GEVNTCOUNT_RMSK 0xffffffff
+#define DWC_GEVNTCOUNT_MAXp 1
+#define DWC_GEVNTCOUNT_POR 0x00000000
+#define DWC_GEVNTCOUNT_RSVD75_BMSK 0xffff0000
+#define DWC_GEVNTCOUNT_RSVD75_SHFT 0x10
+#define DWC_GEVNTCOUNT_EVNTCOUNT_BMSK 0xffff
+#define DWC_GEVNTCOUNT_EVNTCOUNT_SHFT 0x0
+
+#define DWC_GSBUSCFG0_ADDR(x) ((x) + 0x0000c100)
+#define DWC_GSBUSCFG0_OFFS (0x0000c100)
+#define DWC_GSBUSCFG0_RMSK 0xffffffff
+#define DWC_GSBUSCFG0_POR 0x0000000e
+#define DWC_GSBUSCFG0_RSVD10_BMSK 0xffffff00
+#define DWC_GSBUSCFG0_RSVD10_SHFT 0x8
+#define DWC_GSBUSCFG0_INCR256BRSTENA_BMSK 0x80
+#define DWC_GSBUSCFG0_INCR256BRSTENA_SHFT 0x7
+#define DWC_GSBUSCFG0_INCR128BRSTENA_BMSK 0x40
+#define DWC_GSBUSCFG0_INCR128BRSTENA_SHFT 0x6
+#define DWC_GSBUSCFG0_INCR64BRSTENA_BMSK 0x20
+#define DWC_GSBUSCFG0_INCR64BRSTENA_SHFT 0x5
+#define DWC_GSBUSCFG0_INCR32BRSTENA_BMSK 0x10
+#define DWC_GSBUSCFG0_INCR32BRSTENA_SHFT 0x4
+#define DWC_GSBUSCFG0_INCR16BRSTENA_BMSK 0x8
+#define DWC_GSBUSCFG0_INCR16BRSTENA_SHFT 0x3
+#define DWC_GSBUSCFG0_INCR8BRSTENA_BMSK 0x4
+#define DWC_GSBUSCFG0_INCR8BRSTENA_SHFT 0x2
+#define DWC_GSBUSCFG0_INCR4BRSTENA_BMSK 0x2
+#define DWC_GSBUSCFG0_INCR4BRSTENA_SHFT 0x1
+#define DWC_GSBUSCFG0_INCRBRSTENA_BMSK 0x1
+#define DWC_GSBUSCFG0_INCRBRSTENA_SHFT 0x0
+
+#define DWC_GSBUSCFG1_ADDR(x) ((x) + 0x0000c104)
+#define DWC_GSBUSCFG1_OFFS (0x0000c104)
+#define DWC_GSBUSCFG1_RMSK 0xffffffff
+#define DWC_GSBUSCFG1_POR 0x00001700
+#define DWC_GSBUSCFG1_RSVD0_BMSK 0xffffe000
+#define DWC_GSBUSCFG1_RSVD0_SHFT 0xd
+#define DWC_GSBUSCFG1_EN1KPAGE_BMSK 0x1000
+#define DWC_GSBUSCFG1_EN1KPAGE_SHFT 0xc
+#define DWC_GSBUSCFG1_PIPETRANSLIMIT_BMSK 0xf00
+#define DWC_GSBUSCFG1_PIPETRANSLIMIT_SHFT 0x8
+#define DWC_GSBUSCFG1_RSVD1_BMSK 0xff
+#define DWC_GSBUSCFG1_RSVD1_SHFT 0x0
+
+#define DWC_GTXTHRCFG_ADDR(x) ((x) + 0x0000c108)
+#define DWC_GTXTHRCFG_OFFS (0x0000c108)
+#define DWC_GTXTHRCFG_RMSK 0xffffffff
+#define DWC_GTXTHRCFG_POR 0x00000000
+#define DWC_GTXTHRCFG_USBISOTHREN_BMSK 0x80000000
+#define DWC_GTXTHRCFG_USBISOTHREN_SHFT 0x1f
+#define DWC_GTXTHRCFG_USBNONISOTHREN_BMSK 0x40000000
+#define DWC_GTXTHRCFG_USBNONISOTHREN_SHFT 0x1e
+#define DWC_GTXTHRCFG_USBTXPKTCNTSEL_BMSK 0x20000000
+#define DWC_GTXTHRCFG_USBTXPKTCNTSEL_SHFT 0x1d
+#define DWC_GTXTHRCFG_RSVD3_BMSK 0x10000000
+#define DWC_GTXTHRCFG_RSVD3_SHFT 0x1c
+#define DWC_GTXTHRCFG_USBTXPKTCNT_BMSK 0xf000000
+#define DWC_GTXTHRCFG_USBTXPKTCNT_SHFT 0x18
+#define DWC_GTXTHRCFG_USBMAXTXBURSTSIZE_BMSK 0xff0000
+#define DWC_GTXTHRCFG_USBMAXTXBURSTSIZE_SHFT 0x10
+#define DWC_GTXTHRCFG_SBUSISOTHREN_BMSK 0x8000
+#define DWC_GTXTHRCFG_SBUSISOTHREN_SHFT 0xf
+#define DWC_GTXTHRCFG_SBUSNONISOTHREN_BMSK 0x4000
+#define DWC_GTXTHRCFG_SBUSNONISOTHREN_SHFT 0xe
+#define DWC_GTXTHRCFG_RSVD2_BMSK 0x3800
+#define DWC_GTXTHRCFG_RSVD2_SHFT 0xb
+#define DWC_GTXTHRCFG_RSVD1_BMSK 0x7ff
+#define DWC_GTXTHRCFG_RSVD1_SHFT 0x0
+
+#define DWC_GRXTHRCFG_ADDR(x) ((x) + 0x0000c10c)
+#define DWC_GRXTHRCFG_OFFS (0x0000c10c)
+#define DWC_GRXTHRCFG_RMSK 0xffffffff
+#define DWC_GRXTHRCFG_POR 0x00000000
+#define DWC_GRXTHRCFG_RSVD5_BMSK 0xc0000000
+#define DWC_GRXTHRCFG_RSVD5_SHFT 0x1e
+#define DWC_GRXTHRCFG_USBRXPKTCNTSEL_BMSK 0x20000000
+#define DWC_GRXTHRCFG_USBRXPKTCNTSEL_SHFT 0x1d
+#define DWC_GRXTHRCFG_RSVD4_BMSK 0x10000000
+#define DWC_GRXTHRCFG_RSVD4_SHFT 0x1c
+#define DWC_GRXTHRCFG_USBRXPKTCNT_BMSK 0xf000000
+#define DWC_GRXTHRCFG_USBRXPKTCNT_SHFT 0x18
+#define DWC_GRXTHRCFG_USBMAXRXBURSTSIZE_BMSK 0xf80000
+#define DWC_GRXTHRCFG_USBMAXRXBURSTSIZE_SHFT 0x13
+#define DWC_GRXTHRCFG_RSVD3_BMSK 0x70000
+#define DWC_GRXTHRCFG_RSVD3_SHFT 0x10
+#define DWC_GRXTHRCFG_RXTHREN_BMSK 0x8000
+#define DWC_GRXTHRCFG_RXTHREN_SHFT 0xf
+#define DWC_GRXTHRCFG_RSVD2_BMSK 0x7800
+#define DWC_GRXTHRCFG_RSVD2_SHFT 0xb
+#define DWC_GRXTHRCFG_RSVD1_BMSK 0x7ff
+#define DWC_GRXTHRCFG_RSVD1_SHFT 0x0
+
+#define DWC_GCTL_ADDR(x) ((x) + 0x0000c110)
+#define DWC_GCTL_OFFS (0x0000c110)
+#define DWC_GCTL_RMSK 0xffffffff
+#define DWC_GCTL_POR 0x30c02000
+#define DWC_GCTL_PWRDNSCALE_BMSK 0xfff80000
+#define DWC_GCTL_PWRDNSCALE_SHFT 0x13
+#define DWC_GCTL_MASTERFILTBYPASS_BMSK 0x40000
+#define DWC_GCTL_MASTERFILTBYPASS_SHFT 0x12
+#define DWC_GCTL_BYPSSETADDR_BMSK 0x20000
+#define DWC_GCTL_BYPSSETADDR_SHFT 0x11
+#define DWC_GCTL_U2RSTECN_BMSK 0x10000
+#define DWC_GCTL_U2RSTECN_SHFT 0x10
+#define DWC_GCTL_FRMSCLDWN_BMSK 0xc000
+#define DWC_GCTL_FRMSCLDWN_SHFT 0xe
+#define DWC_GCTL_PRTCAPDIR_BMSK 0x3000
+#define DWC_GCTL_PRTCAPDIR_SHFT 0xc
+#define DWC_GCTL_CORESOFTRESET_BMSK 0x800
+#define DWC_GCTL_CORESOFTRESET_SHFT 0xb
+#define DWC_GCTL_SOFITPSYNC_BMSK 0x400
+#define DWC_GCTL_SOFITPSYNC_SHFT 0xa
+#define DWC_GCTL_U1U2TIMERSCALE_BMSK 0x200
+#define DWC_GCTL_U1U2TIMERSCALE_SHFT 0x9
+#define DWC_GCTL_DEBUGATTACH_BMSK 0x100
+#define DWC_GCTL_DEBUGATTACH_SHFT 0x8
+#define DWC_GCTL_RAMCLKSEL_BMSK 0xc0
+#define DWC_GCTL_RAMCLKSEL_SHFT 0x6
+#define DWC_GCTL_SCALEDOWN_BMSK 0x30
+#define DWC_GCTL_SCALEDOWN_SHFT 0x4
+#define DWC_GCTL_DISSCRAMBLE_BMSK 0x8
+#define DWC_GCTL_DISSCRAMBLE_SHFT 0x3
+#define DWC_GCTL_RSVD6_BMSK 0x4
+#define DWC_GCTL_RSVD6_SHFT 0x2
+#define DWC_GCTL_GBLHIBERNATIONEN_BMSK 0x2
+#define DWC_GCTL_GBLHIBERNATIONEN_SHFT 0x1
+#define DWC_GCTL_DSBLCLKGTNG_BMSK 0x1
+#define DWC_GCTL_DSBLCLKGTNG_SHFT 0x0
+
+#define DWC_GSTS_ADDR(x) ((x) + 0x0000c118)
+#define DWC_GSTS_OFFS (0x0000c118)
+#define DWC_GSTS_RMSK 0xffffffff
+#define DWC_GSTS_POR 0x3e800002
+#define DWC_GSTS_CBELT_BMSK 0xfff00000
+#define DWC_GSTS_CBELT_SHFT 0x14
+#define DWC_GSTS_RSVD7_BMSK 0xff800
+#define DWC_GSTS_RSVD7_SHFT 0xb
+#define DWC_GSTS_OTG_IP_BMSK 0x400
+#define DWC_GSTS_OTG_IP_SHFT 0xa
+#define DWC_GSTS_BC_IP_BMSK 0x200
+#define DWC_GSTS_BC_IP_SHFT 0x9
+#define DWC_GSTS_ADP_IP_BMSK 0x100
+#define DWC_GSTS_ADP_IP_SHFT 0x8
+#define DWC_GSTS_HOST_IP_BMSK 0x80
+#define DWC_GSTS_HOST_IP_SHFT 0x7
+#define DWC_GSTS_DEVICE_IP_BMSK 0x40
+#define DWC_GSTS_DEVICE_IP_SHFT 0x6
+#define DWC_GSTS_CSRTIMEOUT_BMSK 0x20
+#define DWC_GSTS_CSRTIMEOUT_SHFT 0x5
+#define DWC_GSTS_BUSERRADDRVLD_BMSK 0x10
+#define DWC_GSTS_BUSERRADDRVLD_SHFT 0x4
+#define DWC_GSTS_R6_BMSK 0xc
+#define DWC_GSTS_R6_SHFT 0x2
+#define DWC_GSTS_CURMOD_BMSK 0x3
+#define DWC_GSTS_CURMOD_SHFT 0x0
+
+#define DWC_GSNPSID_ADDR(x) ((x) + 0x0000c120)
+#define DWC_GSNPSID_OFFS (0x0000c120)
+#define DWC_GSNPSID_RMSK 0xffffffff
+#define DWC_GSNPSID_POR 0x5533203a
+#define DWC_GSNPSID_SYNOPSYSID_BMSK 0xffffffff
+#define DWC_GSNPSID_SYNOPSYSID_SHFT 0x0
+
+#define DWC_GGPIO_ADDR(x) ((x) + 0x0000c124)
+#define DWC_GGPIO_OFFS (0x0000c124)
+#define DWC_GGPIO_RMSK 0xffffffff
+#define DWC_GGPIO_POR 0x00000000
+#define DWC_GGPIO_GPO_BMSK 0xffff0000
+#define DWC_GGPIO_GPO_SHFT 0x10
+#define DWC_GGPIO_GPI_BMSK 0xffff
+#define DWC_GGPIO_GPI_SHFT 0x0
+
+#define DWC_GUID_ADDR(x) ((x) + 0x0000c128)
+#define DWC_GUID_OFFS (0x0000c128)
+#define DWC_GUID_RMSK 0xffffffff
+#define DWC_GUID_POR 0x11203a27
+#define DWC_GUID_USERID_BMSK 0xffffffff
+#define DWC_GUID_USERID_SHFT 0x0
+
+#define DWC_GUCTL_ADDR(x) ((x) + 0x0000c12c)
+#define DWC_GUCTL_OFFS (0x0000c12c)
+#define DWC_GUCTL_RMSK 0xffdfffff
+#define DWC_GUCTL_POR 0x00008010
+#define DWC_GUCTL_REFCLKPER_BMSK 0xffc00000
+#define DWC_GUCTL_REFCLKPER_SHFT 0x16
+#define DWC_GUCTL_RSVD_BMSK 0x1c0000
+#define DWC_GUCTL_RSVD_SHFT 0x12
+#define DWC_GUCTL_SPRSCTRLTRANSEN_BMSK 0x20000
+#define DWC_GUCTL_SPRSCTRLTRANSEN_SHFT 0x11
+#define DWC_GUCTL_RESBWHSEPS_BMSK 0x10000
+#define DWC_GUCTL_RESBWHSEPS_SHFT 0x10
+#define DWC_GUCTL_CMDEVADDR_BMSK 0x8000
+#define DWC_GUCTL_CMDEVADDR_SHFT 0xf
+#define DWC_GUCTL_USBHSTINAUTORETRYEN_BMSK 0x4000
+#define DWC_GUCTL_USBHSTINAUTORETRYEN_SHFT 0xe
+#define DWC_GUCTL_RSVD7_BMSK 0x3000
+#define DWC_GUCTL_RSVD7_SHFT 0xc
+#define DWC_GUCTL_INSRTEXTRFSBODI_BMSK 0x800
+#define DWC_GUCTL_INSRTEXTRFSBODI_SHFT 0xb
+#define DWC_GUCTL_DTCT_BMSK 0x600
+#define DWC_GUCTL_DTCT_SHFT 0x9
+#define DWC_GUCTL_DTFT_BMSK 0x1ff
+#define DWC_GUCTL_DTFT_SHFT 0x0
+
+#define DWC_GBUSERRADDRLO_ADDR(x) ((x) + 0x0000c130)
+#define DWC_GBUSERRADDRLO_OFFS (0x0000c130)
+#define DWC_GBUSERRADDRLO_RMSK 0xffffffff
+#define DWC_GBUSERRADDRLO_POR 0x00000000
+#define DWC_GBUSERRADDRLO_BUSERRADDR_BMSK 0xffffffff
+#define DWC_GBUSERRADDRLO_BUSERRADDR_SHFT 0x0
+
+#define DWC_GBUSERRADDRHI_ADDR(x) ((x) + 0x0000c134)
+#define DWC_GBUSERRADDRHI_OFFS (0x0000c134)
+#define DWC_GBUSERRADDRHI_RMSK 0xffffffff
+#define DWC_GBUSERRADDRHI_POR 0x00000000
+#define DWC_GBUSERRADDRHI_BUSERRADDR_BMSK 0xffffffff
+#define DWC_GBUSERRADDRHI_BUSERRADDR_SHFT 0x0
+
+#define DWC_GPRTBIMAPLO_ADDR(x) ((x) + 0x0000c138)
+#define DWC_GPRTBIMAPLO_OFFS (0x0000c138)
+#define DWC_GPRTBIMAPLO_RMSK 0xffffffff
+#define DWC_GPRTBIMAPLO_POR 0x00000000
+#define DWC_GPRTBIMAPLO_BINUM8_BMSK 0xf0000000
+#define DWC_GPRTBIMAPLO_BINUM8_SHFT 0x1c
+#define DWC_GPRTBIMAPLO_BINUM7_BMSK 0xf000000
+#define DWC_GPRTBIMAPLO_BINUM7_SHFT 0x18
+#define DWC_GPRTBIMAPLO_BINUM6_BMSK 0xf00000
+#define DWC_GPRTBIMAPLO_BINUM6_SHFT 0x14
+#define DWC_GPRTBIMAPLO_BINUM5_BMSK 0xf0000
+#define DWC_GPRTBIMAPLO_BINUM5_SHFT 0x10
+#define DWC_GPRTBIMAPLO_BINUM4_BMSK 0xf000
+#define DWC_GPRTBIMAPLO_BINUM4_SHFT 0xc
+#define DWC_GPRTBIMAPLO_BINUM3_BMSK 0xf00
+#define DWC_GPRTBIMAPLO_BINUM3_SHFT 0x8
+#define DWC_GPRTBIMAPLO_BINUM2_BMSK 0xf0
+#define DWC_GPRTBIMAPLO_BINUM2_SHFT 0x4
+#define DWC_GPRTBIMAPLO_BINUM1_BMSK 0xf
+#define DWC_GPRTBIMAPLO_BINUM1_SHFT 0x0
+
+#define DWC_GPRTBIMAPHI_ADDR(x) ((x) + 0x0000c13c)
+#define DWC_GPRTBIMAPHI_OFFS (0x0000c13c)
+#define DWC_GPRTBIMAPHI_RMSK 0xffffffff
+#define DWC_GPRTBIMAPHI_POR 0x00000000
+#define DWC_GPRTBIMAPHI_RSVD16_BMSK 0xf0000000
+#define DWC_GPRTBIMAPHI_RSVD16_SHFT 0x1c
+#define DWC_GPRTBIMAPHI_BINUM15_BMSK 0xf000000
+#define DWC_GPRTBIMAPHI_BINUM15_SHFT 0x18
+#define DWC_GPRTBIMAPHI_BINUM14_BMSK 0xf00000
+#define DWC_GPRTBIMAPHI_BINUM14_SHFT 0x14
+#define DWC_GPRTBIMAPHI_BINUM13_BMSK 0xf0000
+#define DWC_GPRTBIMAPHI_BINUM13_SHFT 0x10
+#define DWC_GPRTBIMAPHI_BINUM12_BMSK 0xf000
+#define DWC_GPRTBIMAPHI_BINUM12_SHFT 0xc
+#define DWC_GPRTBIMAPHI_BINUM11_BMSK 0xf00
+#define DWC_GPRTBIMAPHI_BINUM11_SHFT 0x8
+#define DWC_GPRTBIMAPHI_BINUM10_BMSK 0xf0
+#define DWC_GPRTBIMAPHI_BINUM10_SHFT 0x4
+#define DWC_GPRTBIMAPHI_BINUM9_BMSK 0xf
+#define DWC_GPRTBIMAPHI_BINUM9_SHFT 0x0
+
+#define DWC_GHWPARAMS0_ADDR(x) ((x) + 0x0000c140)
+#define DWC_GHWPARAMS0_OFFS (0x0000c140)
+#define DWC_GHWPARAMS0_RMSK 0xfffffffb
+#define DWC_GHWPARAMS0_POR 0x00000000
+#define DWC_GHWPARAMS0_GHWPARAMS0_31_24_BMSK 0xff000000
+#define DWC_GHWPARAMS0_GHWPARAMS0_31_24_SHFT 0x18
+#define DWC_GHWPARAMS0_GHWPARAMS0_23_16_BMSK 0xff0000
+#define DWC_GHWPARAMS0_GHWPARAMS0_23_16_SHFT 0x10
+#define DWC_GHWPARAMS0_GHWPARAMS0_15_8_BMSK 0xff00
+#define DWC_GHWPARAMS0_GHWPARAMS0_15_8_SHFT 0x8
+#define DWC_GHWPARAMS0_GHWPARAMS0_7_6_BMSK 0xc0
+#define DWC_GHWPARAMS0_GHWPARAMS0_7_6_SHFT 0x6
+#define DWC_GHWPARAMS0_GHWPARAMS0_5_3_BMSK 0x38
+#define DWC_GHWPARAMS0_GHWPARAMS0_5_3_SHFT 0x3
+#define DWC_GHWPARAMS0_GHWPARAMS0_2_0_BMSK 0x3
+#define DWC_GHWPARAMS0_GHWPARAMS0_2_0_SHFT 0x0
+
+#define DWC_GHWPARAMS1_ADDR(x) ((x) + 0x0000c144)
+#define DWC_GHWPARAMS1_OFFS (0x0000c144)
+#define DWC_GHWPARAMS1_RMSK 0xffffffff
+#define DWC_GHWPARAMS1_POR 0x01614938
+#define DWC_GHWPARAMS1_GHWPARAMS1_31_BMSK 0x80000000
+#define DWC_GHWPARAMS1_GHWPARAMS1_31_SHFT 0x1f
+#define DWC_GHWPARAMS1_GHWPARAMS1_30_BMSK 0x40000000
+#define DWC_GHWPARAMS1_GHWPARAMS1_30_SHFT 0x1e
+#define DWC_GHWPARAMS1_GHWPARAMS1_29_BMSK 0x20000000
+#define DWC_GHWPARAMS1_GHWPARAMS1_29_SHFT 0x1d
+#define DWC_GHWPARAMS1_GHWPARAMS1_28_BMSK 0x10000000
+#define DWC_GHWPARAMS1_GHWPARAMS1_28_SHFT 0x1c
+#define DWC_GHWPARAMS1_GHWPARAMS1_27_BMSK 0x8000000
+#define DWC_GHWPARAMS1_GHWPARAMS1_27_SHFT 0x1b
+#define DWC_GHWPARAMS1_GHWPARAMS1_26_BMSK 0x4000000
+#define DWC_GHWPARAMS1_GHWPARAMS1_26_SHFT 0x1a
+#define DWC_GHWPARAMS1_GHWPARAMS1_25_24_BMSK 0x3000000
+#define DWC_GHWPARAMS1_GHWPARAMS1_25_24_SHFT 0x18
+#define DWC_GHWPARAMS1_GHWPARAMS1_23_BMSK 0x800000
+#define DWC_GHWPARAMS1_GHWPARAMS1_23_SHFT 0x17
+#define DWC_GHWPARAMS1_GHWPARAMS1_22_21_BMSK 0x600000
+#define DWC_GHWPARAMS1_GHWPARAMS1_22_21_SHFT 0x15
+#define DWC_GHWPARAMS1_GHWPARAMS1_20_15_BMSK 0x1f8000
+#define DWC_GHWPARAMS1_GHWPARAMS1_20_15_SHFT 0xf
+#define DWC_GHWPARAMS1_GHWPARAMS1_14_12_BMSK 0x7000
+#define DWC_GHWPARAMS1_GHWPARAMS1_14_12_SHFT 0xc
+#define DWC_GHWPARAMS1_GHWPARAMS1_11_9_BMSK 0xe00
+#define DWC_GHWPARAMS1_GHWPARAMS1_11_9_SHFT 0x9
+#define DWC_GHWPARAMS1_GHWPARAMS1_8_6_BMSK 0x1c0
+#define DWC_GHWPARAMS1_GHWPARAMS1_8_6_SHFT 0x6
+#define DWC_GHWPARAMS1_GHWPARAMS1_5_3_BMSK 0x38
+#define DWC_GHWPARAMS1_GHWPARAMS1_5_3_SHFT 0x3
+#define DWC_GHWPARAMS1_GHWPARAMS1_2_0_BMSK 0x7
+#define DWC_GHWPARAMS1_GHWPARAMS1_2_0_SHFT 0x0
+
+#define DWC_GHWPARAMS2_ADDR(x) ((x) + 0x0000c148)
+#define DWC_GHWPARAMS2_OFFS (0x0000c148)
+#define DWC_GHWPARAMS2_RMSK 0xffffffff
+#define DWC_GHWPARAMS2_POR 0x11203a27
+#define DWC_GHWPARAMS2_GHWPARAMS2_31_0_BMSK 0xffffffff
+#define DWC_GHWPARAMS2_GHWPARAMS2_31_0_SHFT 0x0
+
+#define DWC_GHWPARAMS3_ADDR(x) ((x) + 0x0000c14c)
+#define DWC_GHWPARAMS3_OFFS (0x0000c14c)
+#define DWC_GHWPARAMS3_RMSK 0xffffffff
+#define DWC_GHWPARAMS3_POR 0x10420085
+#define DWC_GHWPARAMS3_GHWPARAMS3_31_BMSK 0x80000000
+#define DWC_GHWPARAMS3_GHWPARAMS3_31_SHFT 0x1f
+#define DWC_GHWPARAMS3_GHWPARAMS3_30_23_BMSK 0x7f800000
+#define DWC_GHWPARAMS3_GHWPARAMS3_30_23_SHFT 0x17
+#define DWC_GHWPARAMS3_GHWPARAMS3_22_18_BMSK 0x7c0000
+#define DWC_GHWPARAMS3_GHWPARAMS3_22_18_SHFT 0x12
+#define DWC_GHWPARAMS3_GHWPARAMS3_17_12_BMSK 0x3f000
+#define DWC_GHWPARAMS3_GHWPARAMS3_17_12_SHFT 0xc
+#define DWC_GHWPARAMS3_GHWPARAMS3_11_BMSK 0x800
+#define DWC_GHWPARAMS3_GHWPARAMS3_11_SHFT 0xb
+#define DWC_GHWPARAMS3_GHWPARAMS3_10_BMSK 0x400
+#define DWC_GHWPARAMS3_GHWPARAMS3_10_SHFT 0xa
+#define DWC_GHWPARAMS3_GHWPARAMS3_9_8_BMSK 0x300
+#define DWC_GHWPARAMS3_GHWPARAMS3_9_8_SHFT 0x8
+#define DWC_GHWPARAMS3_GHWPARAMS3_7_6_BMSK 0xc0
+#define DWC_GHWPARAMS3_GHWPARAMS3_7_6_SHFT 0x6
+#define DWC_GHWPARAMS3_GHWPARAMS3_5_4_BMSK 0x30
+#define DWC_GHWPARAMS3_GHWPARAMS3_5_4_SHFT 0x4
+#define DWC_GHWPARAMS3_GHWPARAMS3_3_2_BMSK 0xc
+#define DWC_GHWPARAMS3_GHWPARAMS3_3_2_SHFT 0x2
+#define DWC_GHWPARAMS3_GHWPARAMS3_1_0_BMSK 0x3
+#define DWC_GHWPARAMS3_GHWPARAMS3_1_0_SHFT 0x0
+
+#define DWC_GHWPARAMS4_ADDR(x) ((x) + 0x0000c150)
+#define DWC_GHWPARAMS4_OFFS (0x0000c150)
+#define DWC_GHWPARAMS4_RMSK 0xffffffff
+#define DWC_GHWPARAMS4_POR 0x48822005
+#define DWC_GHWPARAMS4_GHWPARAMS4_31_28_BMSK 0xf0000000
+#define DWC_GHWPARAMS4_GHWPARAMS4_31_28_SHFT 0x1c
+#define DWC_GHWPARAMS4_GHWPARAMS4_27_24_BMSK 0xf000000
+#define DWC_GHWPARAMS4_GHWPARAMS4_27_24_SHFT 0x18
+#define DWC_GHWPARAMS4_GHWPARAMS4_23_BMSK 0x800000
+#define DWC_GHWPARAMS4_GHWPARAMS4_23_SHFT 0x17
+#define DWC_GHWPARAMS4_GHWPARAMS4_22_BMSK 0x400000
+#define DWC_GHWPARAMS4_GHWPARAMS4_22_SHFT 0x16
+#define DWC_GHWPARAMS4_GHWPARAMS4_21_BMSK 0x200000
+#define DWC_GHWPARAMS4_GHWPARAMS4_21_SHFT 0x15
+#define DWC_GHWPARAMS4_GHWPARAMS4_20_17_BMSK 0x1e0000
+#define DWC_GHWPARAMS4_GHWPARAMS4_20_17_SHFT 0x11
+#define DWC_GHWPARAMS4_GHWPARAMS4_16_13_BMSK 0x1e000
+#define DWC_GHWPARAMS4_GHWPARAMS4_16_13_SHFT 0xd
+#define DWC_GHWPARAMS4_GHWPARAMS4_12_6_BMSK 0x1fc0
+#define DWC_GHWPARAMS4_GHWPARAMS4_12_6_SHFT 0x6
+#define DWC_GHWPARAMS4_GHWPARAMS4_5_0_BMSK 0x3f
+#define DWC_GHWPARAMS4_GHWPARAMS4_5_0_SHFT 0x0
+
+#define DWC_GHWPARAMS5_ADDR(x) ((x) + 0x0000c154)
+#define DWC_GHWPARAMS5_OFFS (0x0000c154)
+#define DWC_GHWPARAMS5_RMSK 0xffffffff
+#define DWC_GHWPARAMS5_POR 0x04202088
+#define DWC_GHWPARAMS5_GHWPARAMS5_31_28_BMSK 0xf0000000
+#define DWC_GHWPARAMS5_GHWPARAMS5_31_28_SHFT 0x1c
+#define DWC_GHWPARAMS5_GHWPARAMS5_27_22_BMSK 0xfc00000
+#define DWC_GHWPARAMS5_GHWPARAMS5_27_22_SHFT 0x16
+#define DWC_GHWPARAMS5_GHWPARAMS5_21_16_BMSK 0x3f0000
+#define DWC_GHWPARAMS5_GHWPARAMS5_21_16_SHFT 0x10
+#define DWC_GHWPARAMS5_GHWPARAMS5_15_10_BMSK 0xfc00
+#define DWC_GHWPARAMS5_GHWPARAMS5_15_10_SHFT 0xa
+#define DWC_GHWPARAMS5_GHWPARAMS5_9_4_BMSK 0x3f0
+#define DWC_GHWPARAMS5_GHWPARAMS5_9_4_SHFT 0x4
+#define DWC_GHWPARAMS5_GHWPARAMS5_3_0_BMSK 0xf
+#define DWC_GHWPARAMS5_GHWPARAMS5_3_0_SHFT 0x0
+
+#define DWC_GHWPARAMS6_ADDR(x) ((x) + 0x0000c158)
+#define DWC_GHWPARAMS6_OFFS (0x0000c158)
+#define DWC_GHWPARAMS6_RMSK 0xffffffff
+#define DWC_GHWPARAMS6_POR 0x065c8c20
+#define DWC_GHWPARAMS6_GHWPARAMS6_31_16_BMSK 0xffff0000
+#define DWC_GHWPARAMS6_GHWPARAMS6_31_16_SHFT 0x10
+#define DWC_GHWPARAMS6_BUSFLTRSSUPPORT_BMSK 0x8000
+#define DWC_GHWPARAMS6_BUSFLTRSSUPPORT_SHFT 0xf
+#define DWC_GHWPARAMS6_BCSUPPORT_BMSK 0x4000
+#define DWC_GHWPARAMS6_BCSUPPORT_SHFT 0xe
+#define DWC_GHWPARAMS6_OTG_SS_SUPPORT_BMSK 0x2000
+#define DWC_GHWPARAMS6_OTG_SS_SUPPORT_SHFT 0xd
+#define DWC_GHWPARAMS6_ADPSUPPORT_BMSK 0x1000
+#define DWC_GHWPARAMS6_ADPSUPPORT_SHFT 0xc
+#define DWC_GHWPARAMS6_HNPSUPPORT_BMSK 0x800
+#define DWC_GHWPARAMS6_HNPSUPPORT_SHFT 0xb
+#define DWC_GHWPARAMS6_SRPSUPPORT_BMSK 0x400
+#define DWC_GHWPARAMS6_SRPSUPPORT_SHFT 0xa
+#define DWC_GHWPARAMS6_GHWPARAMS6_9_8_BMSK 0x300
+#define DWC_GHWPARAMS6_GHWPARAMS6_9_8_SHFT 0x8
+#define DWC_GHWPARAMS6_GHWPARAMS6_7_BMSK 0x80
+#define DWC_GHWPARAMS6_GHWPARAMS6_7_SHFT 0x7
+#define DWC_GHWPARAMS6_GHWPARAMS6_6_BMSK 0x40
+#define DWC_GHWPARAMS6_GHWPARAMS6_6_SHFT 0x6
+#define DWC_GHWPARAMS6_GHWPARAMS6_5_0_BMSK 0x3f
+#define DWC_GHWPARAMS6_GHWPARAMS6_5_0_SHFT 0x0
+
+#define DWC_GHWPARAMS7_ADDR(x) ((x) + 0x0000c15c)
+#define DWC_GHWPARAMS7_OFFS (0x0000c15c)
+#define DWC_GHWPARAMS7_RMSK 0xffffffff
+#define DWC_GHWPARAMS7_POR 0x03080cea
+#define DWC_GHWPARAMS7_GHWPARAMS7_31_16_BMSK 0xffff0000
+#define DWC_GHWPARAMS7_GHWPARAMS7_31_16_SHFT 0x10
+#define DWC_GHWPARAMS7_GHWPARAMS7_15_0_BMSK 0xffff
+#define DWC_GHWPARAMS7_GHWPARAMS7_15_0_SHFT 0x0
+
+#define DWC_GDBGFIFOSPACE_ADDR(x) ((x) + 0x0000c160)
+#define DWC_GDBGFIFOSPACE_OFFS (0x0000c160)
+#define DWC_GDBGFIFOSPACE_RMSK 0xffffffff
+#define DWC_GDBGFIFOSPACE_POR 0x00820000
+#define DWC_GDBGFIFOSPACE_SPACE_AVAILABLE_BMSK 0xffff0000
+#define DWC_GDBGFIFOSPACE_SPACE_AVAILABLE_SHFT 0x10
+#define DWC_GDBGFIFOSPACE_RSVD8_BMSK 0xff00
+#define DWC_GDBGFIFOSPACE_RSVD8_SHFT 0x8
+#define DWC_GDBGFIFOSPACE_FIFO_QUEUE_SELECT_BMSK 0xff
+#define DWC_GDBGFIFOSPACE_FIFO_QUEUE_SELECT_SHFT 0x0
+
+#define DWC_GDBGLTSSM_ADDR(x) ((x) + 0x0000c164)
+#define DWC_GDBGLTSSM_OFFS (0x0000c164)
+#define DWC_GDBGLTSSM_RMSK 0xfddfffdf
+#define DWC_GDBGLTSSM_POR 0x00000000
+#define DWC_GDBGLTSSM_RSVD14_BMSK 0xc0000000
+#define DWC_GDBGLTSSM_RSVD14_SHFT 0x1e
+#define DWC_GDBGLTSSM_X3_XS_SWAPPING_BMSK 0x20000000
+#define DWC_GDBGLTSSM_X3_XS_SWAPPING_SHFT 0x1d
+#define DWC_GDBGLTSSM_X3_DS_HOST_SHUTDOWN_BMSK 0x10000000
+#define DWC_GDBGLTSSM_X3_DS_HOST_SHUTDOWN_SHFT 0x1c
+#define DWC_GDBGLTSSM_PRTDIRECTION_BMSK 0x8000000
+#define DWC_GDBGLTSSM_PRTDIRECTION_SHFT 0x1b
+#define DWC_GDBGLTSSM_LTDBTIMEOUT_BMSK 0x4000000
+#define DWC_GDBGLTSSM_LTDBTIMEOUT_SHFT 0x1a
+#define DWC_GDBGLTSSM_LTDBLINKSTATE_BMSK 0x1c00000
+#define DWC_GDBGLTSSM_LTDBLINKSTATE_SHFT 0x16
+#define DWC_GDBGLTSSM_LTDBSUBSTATE_BMSK 0x1c0000
+#define DWC_GDBGLTSSM_LTDBSUBSTATE_SHFT 0x12
+#define DWC_GDBGLTSSM_ELASTICBUFFERMODE_BMSK 0x20000
+#define DWC_GDBGLTSSM_ELASTICBUFFERMODE_SHFT 0x11
+#define DWC_GDBGLTSSM_TXELECLDLE_BMSK 0x10000
+#define DWC_GDBGLTSSM_TXELECLDLE_SHFT 0x10
+#define DWC_GDBGLTSSM_RXPOLARITY_BMSK 0x8000
+#define DWC_GDBGLTSSM_RXPOLARITY_SHFT 0xf
+#define DWC_GDBGLTSSM_TXDETRXLOOPBACK_BMSK 0x4000
+#define DWC_GDBGLTSSM_TXDETRXLOOPBACK_SHFT 0xe
+#define DWC_GDBGLTSSM_RSVD12_BMSK 0x2000
+#define DWC_GDBGLTSSM_RSVD12_SHFT 0xd
+#define DWC_GDBGLTSSM_LTDBPHYCMDSTATE_BMSK 0x1800
+#define DWC_GDBGLTSSM_LTDBPHYCMDSTATE_SHFT 0xb
+#define DWC_GDBGLTSSM_POWERDOWN_BMSK 0x600
+#define DWC_GDBGLTSSM_POWERDOWN_SHFT 0x9
+#define DWC_GDBGLTSSM_RXEQTRAIN_BMSK 0x100
+#define DWC_GDBGLTSSM_RXEQTRAIN_SHFT 0x8
+#define DWC_GDBGLTSSM_TXDEEMPHASIS_BMSK 0xc0
+#define DWC_GDBGLTSSM_TXDEEMPHASIS_SHFT 0x6
+#define DWC_GDBGLTSSM_LTDBCLKSTATE_BMSK 0x18
+#define DWC_GDBGLTSSM_LTDBCLKSTATE_SHFT 0x3
+#define DWC_GDBGLTSSM_TXSWING_BMSK 0x4
+#define DWC_GDBGLTSSM_TXSWING_SHFT 0x2
+#define DWC_GDBGLTSSM_RXTERMINATION_BMSK 0x2
+#define DWC_GDBGLTSSM_RXTERMINATION_SHFT 0x1
+#define DWC_GDBGLTSSM_TXONESZEROS_BMSK 0x1
+#define DWC_GDBGLTSSM_TXONESZEROS_SHFT 0x0
+
+#define DWC_GDBGLNMCC_ADDR(x) ((x) + 0x0000c168)
+#define DWC_GDBGLNMCC_OFFS (0x0000c168)
+#define DWC_GDBGLNMCC_RMSK 0x7ffffeff
+#define DWC_GDBGLNMCC_POR 0x00000000
+#define DWC_GDBGLNMCC_RSVD2_BMSK 0x7ffffe00
+#define DWC_GDBGLNMCC_RSVD2_SHFT 0x9
+#define DWC_GDBGLNMCC_LNMCC_BERC_BMSK 0xff
+#define DWC_GDBGLNMCC_LNMCC_BERC_SHFT 0x0
+
+#define DWC_GDBGBMU_ADDR(x) ((x) + 0x0000c16c)
+#define DWC_GDBGBMU_OFFS (0x0000c16c)
+#define DWC_GDBGBMU_RMSK 0xffffffff
+#define DWC_GDBGBMU_POR 0x00000000
+#define DWC_GDBGBMU_BMU_BCU_BMSK 0xffffff00
+#define DWC_GDBGBMU_BMU_BCU_SHFT 0x8
+#define DWC_GDBGBMU_BMU_DCU_BMSK 0xf0
+#define DWC_GDBGBMU_BMU_DCU_SHFT 0x4
+#define DWC_GDBGBMU_BMU_CCU_BMSK 0xf
+#define DWC_GDBGBMU_BMU_CCU_SHFT 0x0
+
+#define DWC_GDBGLSPMUX_HST_ADDR(x) ((x) + 0x0000c170)
+#define DWC_GDBGLSPMUX_HST_OFFS (0x0000c170)
+#define DWC_GDBGLSPMUX_HST_RMSK 0xffffffff
+#define DWC_GDBGLSPMUX_HST_POR 0x00000000
+#define DWC_GDBGLSPMUX_HST_RSVD3_BMSK 0xffffc000
+#define DWC_GDBGLSPMUX_HST_RSVD3_SHFT 0xe
+#define DWC_GDBGLSPMUX_HST_HOSTSELECT_BMSK 0x3fff
+#define DWC_GDBGLSPMUX_HST_HOSTSELECT_SHFT 0x0
+
+#define DWC_GDBGLSP_ADDR(x) ((x) + 0x0000c174)
+#define DWC_GDBGLSP_OFFS (0x0000c174)
+#define DWC_GDBGLSP_RMSK 0xffffffff
+#define DWC_GDBGLSP_POR 0x00000000
+#define DWC_GDBGLSP_LSPDEBUG_BMSK 0xffffffff
+#define DWC_GDBGLSP_LSPDEBUG_SHFT 0x0
+
+#define DWC_GDBGEPINFO0_ADDR(x) ((x) + 0x0000c178)
+#define DWC_GDBGEPINFO0_OFFS (0x0000c178)
+#define DWC_GDBGEPINFO0_RMSK 0xffffffff
+#define DWC_GDBGEPINFO0_POR 0x00000000
+#define DWC_GDBGEPINFO0_EPDEBUG_BMSK 0xffffffff
+#define DWC_GDBGEPINFO0_EPDEBUG_SHFT 0x0
+
+#define DWC_GDBGEPINFO1_ADDR(x) ((x) + 0x0000c17c)
+#define DWC_GDBGEPINFO1_OFFS (0x0000c17c)
+#define DWC_GDBGEPINFO1_RMSK 0xffffffff
+#define DWC_GDBGEPINFO1_POR 0x00000000
+#define DWC_GDBGEPINFO1_EPDEBUG_BMSK 0xffffffff
+#define DWC_GDBGEPINFO1_EPDEBUG_SHFT 0x0
+
+#define DWC_GPRTBIMAP_HSLO_ADDR(x) ((x) + 0x0000c180)
+#define DWC_GPRTBIMAP_HSLO_OFFS (0x0000c180)
+#define DWC_GPRTBIMAP_HSLO_RMSK 0xffffffff
+#define DWC_GPRTBIMAP_HSLO_POR 0x00000000
+#define DWC_GPRTBIMAP_HSLO_BINUM8_BMSK 0xf0000000
+#define DWC_GPRTBIMAP_HSLO_BINUM8_SHFT 0x1c
+#define DWC_GPRTBIMAP_HSLO_BINUM7_BMSK 0xf000000
+#define DWC_GPRTBIMAP_HSLO_BINUM7_SHFT 0x18
+#define DWC_GPRTBIMAP_HSLO_BINUM6_BMSK 0xf00000
+#define DWC_GPRTBIMAP_HSLO_BINUM6_SHFT 0x14
+#define DWC_GPRTBIMAP_HSLO_BINUM5_BMSK 0xf0000
+#define DWC_GPRTBIMAP_HSLO_BINUM5_SHFT 0x10
+#define DWC_GPRTBIMAP_HSLO_BINUM4_BMSK 0xf000
+#define DWC_GPRTBIMAP_HSLO_BINUM4_SHFT 0xc
+#define DWC_GPRTBIMAP_HSLO_BINUM3_BMSK 0xf00
+#define DWC_GPRTBIMAP_HSLO_BINUM3_SHFT 0x8
+#define DWC_GPRTBIMAP_HSLO_BINUM2_BMSK 0xf0
+#define DWC_GPRTBIMAP_HSLO_BINUM2_SHFT 0x4
+#define DWC_GPRTBIMAP_HSLO_BINUM1_BMSK 0xf
+#define DWC_GPRTBIMAP_HSLO_BINUM1_SHFT 0x0
+
+#define DWC_GPRTBIMAP_HSHI_ADDR(x) ((x) + 0x0000c184)
+#define DWC_GPRTBIMAP_HSHI_OFFS (0x0000c184)
+#define DWC_GPRTBIMAP_HSHI_RMSK 0xffffffff
+#define DWC_GPRTBIMAP_HSHI_POR 0x00000000
+#define DWC_GPRTBIMAP_HSHI_RSVD16_BMSK 0xf0000000
+#define DWC_GPRTBIMAP_HSHI_RSVD16_SHFT 0x1c
+#define DWC_GPRTBIMAP_HSHI_BINUM15_BMSK 0xf000000
+#define DWC_GPRTBIMAP_HSHI_BINUM15_SHFT 0x18
+#define DWC_GPRTBIMAP_HSHI_BINUM14_BMSK 0xf00000
+#define DWC_GPRTBIMAP_HSHI_BINUM14_SHFT 0x14
+#define DWC_GPRTBIMAP_HSHI_BINUM13_BMSK 0xf0000
+#define DWC_GPRTBIMAP_HSHI_BINUM13_SHFT 0x10
+#define DWC_GPRTBIMAP_HSHI_BINUM12_BMSK 0xf000
+#define DWC_GPRTBIMAP_HSHI_BINUM12_SHFT 0xc
+#define DWC_GPRTBIMAP_HSHI_BINUM11_BMSK 0xf00
+#define DWC_GPRTBIMAP_HSHI_BINUM11_SHFT 0x8
+#define DWC_GPRTBIMAP_HSHI_BINUM10_BMSK 0xf0
+#define DWC_GPRTBIMAP_HSHI_BINUM10_SHFT 0x4
+#define DWC_GPRTBIMAP_HSHI_BINUM9_BMSK 0xf
+#define DWC_GPRTBIMAP_HSHI_BINUM9_SHFT 0x0
+
+#define DWC_GPRTBIMAP_FSLO_ADDR(x) ((x) + 0x0000c188)
+#define DWC_GPRTBIMAP_FSLO_OFFS (0x0000c188)
+#define DWC_GPRTBIMAP_FSLO_RMSK 0xffffffff
+#define DWC_GPRTBIMAP_FSLO_POR 0x00000000
+#define DWC_GPRTBIMAP_FSLO_BINUM8_BMSK 0xf0000000
+#define DWC_GPRTBIMAP_FSLO_BINUM8_SHFT 0x1c
+#define DWC_GPRTBIMAP_FSLO_BINUM7_BMSK 0xf000000
+#define DWC_GPRTBIMAP_FSLO_BINUM7_SHFT 0x18
+#define DWC_GPRTBIMAP_FSLO_BINUM6_BMSK 0xf00000
+#define DWC_GPRTBIMAP_FSLO_BINUM6_SHFT 0x14
+#define DWC_GPRTBIMAP_FSLO_BINUM5_BMSK 0xf0000
+#define DWC_GPRTBIMAP_FSLO_BINUM5_SHFT 0x10
+#define DWC_GPRTBIMAP_FSLO_BINUM4_BMSK 0xf000
+#define DWC_GPRTBIMAP_FSLO_BINUM4_SHFT 0xc
+#define DWC_GPRTBIMAP_FSLO_BINUM3_BMSK 0xf00
+#define DWC_GPRTBIMAP_FSLO_BINUM3_SHFT 0x8
+#define DWC_GPRTBIMAP_FSLO_BINUM2_BMSK 0xf0
+#define DWC_GPRTBIMAP_FSLO_BINUM2_SHFT 0x4
+#define DWC_GPRTBIMAP_FSLO_BINUM1_BMSK 0xf
+#define DWC_GPRTBIMAP_FSLO_BINUM1_SHFT 0x0
+
+#define DWC_GPRTBIMAP_FSHI_ADDR(x) ((x) + 0x0000c18c)
+#define DWC_GPRTBIMAP_FSHI_OFFS (0x0000c18c)
+#define DWC_GPRTBIMAP_FSHI_RMSK 0xffffffff
+#define DWC_GPRTBIMAP_FSHI_POR 0x00000000
+#define DWC_GPRTBIMAP_FSHI_RSVD16_BMSK 0xf0000000
+#define DWC_GPRTBIMAP_FSHI_RSVD16_SHFT 0x1c
+#define DWC_GPRTBIMAP_FSHI_BINUM15_BMSK 0xf000000
+#define DWC_GPRTBIMAP_FSHI_BINUM15_SHFT 0x18
+#define DWC_GPRTBIMAP_FSHI_BINUM14_BMSK 0xf00000
+#define DWC_GPRTBIMAP_FSHI_BINUM14_SHFT 0x14
+#define DWC_GPRTBIMAP_FSHI_BINUM13_BMSK 0xf0000
+#define DWC_GPRTBIMAP_FSHI_BINUM13_SHFT 0x10
+#define DWC_GPRTBIMAP_FSHI_BINUM12_BMSK 0xf000
+#define DWC_GPRTBIMAP_FSHI_BINUM12_SHFT 0xc
+#define DWC_GPRTBIMAP_FSHI_BINUM11_BMSK 0xf00
+#define DWC_GPRTBIMAP_FSHI_BINUM11_SHFT 0x8
+#define DWC_GPRTBIMAP_FSHI_BINUM10_BMSK 0xf0
+#define DWC_GPRTBIMAP_FSHI_BINUM10_SHFT 0x4
+#define DWC_GPRTBIMAP_FSHI_BINUM9_BMSK 0xf
+#define DWC_GPRTBIMAP_FSHI_BINUM9_SHFT 0x0
+
+#define DWC_GHWPARAMS8_ADDR(x) ((x) + 0x0000c600)
+#define DWC_GHWPARAMS8_OFFS (0x0000c600)
+#define DWC_GHWPARAMS8_RMSK 0xffffffff
+#define DWC_GHWPARAMS8_POR 0x0000065c
+#define DWC_GHWPARAMS8_GHWPARAMS8_32_0_BMSK 0xffffffff
+#define DWC_GHWPARAMS8_GHWPARAMS8_32_0_SHFT 0x0
+
+#define DWC_DEPCMDPAR2_ADDR(base,p) ((base) + 0x0000c800 + 0x10 * (p))
+#define DWC_DEPCMDPAR2_OFFS(p) (0x0000c800 + 0x10 * (p))
+#define DWC_DEPCMDPAR2_RMSK 0xffffffff
+#define DWC_DEPCMDPAR2_MAXp 31
+#define DWC_DEPCMDPAR2_POR 0x00000000
+#define DWC_DEPCMDPAR2_PARAMETER_BMSK 0xffffffff
+#define DWC_DEPCMDPAR2_PARAMETER_SHFT 0x0
+
+#define DWC_DEPCMDPAR1_ADDR(base,p) ((base) + 0x0000c804 + 0x10 * (p))
+#define DWC_DEPCMDPAR1_OFFS(p) (0x0000c804 + 0x10 * (p))
+#define DWC_DEPCMDPAR1_RMSK 0xffffffff
+#define DWC_DEPCMDPAR1_MAXp 31
+#define DWC_DEPCMDPAR1_POR 0x00000000
+#define DWC_DEPCMDPAR1_PARAMETER_BMSK 0xffffffff
+#define DWC_DEPCMDPAR1_PARAMETER_SHFT 0x0
+
+#define DWC_DEPCMDPAR0_ADDR(base,p) ((base) + 0x0000c808 + 0x10 * (p))
+#define DWC_DEPCMDPAR0_OFFS(p) (0x0000c808 + 0x10 * (p))
+#define DWC_DEPCMDPAR0_RMSK 0xffffffff
+#define DWC_DEPCMDPAR0_MAXp 31
+#define DWC_DEPCMDPAR0_POR 0x00000000
+#define DWC_DEPCMDPAR0_PARAMETER_BMSK 0xffffffff
+#define DWC_DEPCMDPAR0_PARAMETER_SHFT 0x0
+
+#define DWC_DEPCMD_ADDR(base,p) ((base) + 0x0000c80c + 0x10 * (p))
+#define DWC_DEPCMD_OFFS(p) (0x0000c80c + 0x10 * (p))
+#define DWC_DEPCMD_RMSK 0xffffffff
+#define DWC_DEPCMD_MAXp 31
+#define DWC_DEPCMD_POR 0x00000000
+#define DWC_DEPCMD_COMMANDPARAM_BMSK 0xffff0000
+#define DWC_DEPCMD_COMMANDPARAM_SHFT 0x10
+#define DWC_DEPCMD_CMDSTATUS_BMSK 0xf000
+#define DWC_DEPCMD_CMDSTATUS_SHFT 0xc
+#define DWC_DEPCMD_HIPRI_FORCERM_BMSK 0x800
+#define DWC_DEPCMD_HIPRI_FORCERM_SHFT 0xb
+#define DWC_DEPCMD_CMDACT_BMSK 0x400
+#define DWC_DEPCMD_CMDACT_SHFT 0xa
+#define DWC_DEPCMD_R39_BMSK 0x200
+#define DWC_DEPCMD_R39_SHFT 0x9
+#define DWC_DEPCMD_CMDIOC_BMSK 0x100
+#define DWC_DEPCMD_CMDIOC_SHFT 0x8
+#define DWC_DEPCMD_RSVD90_BMSK 0xf0
+#define DWC_DEPCMD_RSVD90_SHFT 0x4
+#define DWC_DEPCMD_CMDTYP_BMSK 0xf
+#define DWC_DEPCMD_CMDTYP_SHFT 0x0
+
+#define DWC_DCFG_ADDR(x) ((x) + 0x0000c700)
+#define DWC_DCFG_OFFS (0x0000c700)
+#define DWC_DCFG_RMSK 0xffffffff
+#define DWC_DCFG_POR 0x00080804
+#define DWC_DCFG_RSVD9_BMSK 0xff000000
+#define DWC_DCFG_RSVD9_SHFT 0x18
+#define DWC_DCFG_IGNSTRMPP_BMSK 0x800000
+#define DWC_DCFG_IGNSTRMPP_SHFT 0x17
+#define DWC_DCFG_LPMCAP_BMSK 0x400000
+#define DWC_DCFG_LPMCAP_SHFT 0x16
+#define DWC_DCFG_NUMP_BMSK 0x3e0000
+#define DWC_DCFG_NUMP_SHFT 0x11
+#define DWC_DCFG_INTRNUM_BMSK 0x1f000
+#define DWC_DCFG_INTRNUM_SHFT 0xc
+#define DWC_DCFG_PERFRINT_BMSK 0xc00
+#define DWC_DCFG_PERFRINT_SHFT 0xa
+#define DWC_DCFG_DEVADDR_BMSK 0x3f8
+#define DWC_DCFG_DEVADDR_SHFT 0x3
+#define DWC_DCFG_DEVSPD_BMSK 0x7
+#define DWC_DCFG_DEVSPD_SHFT 0x0
+
+#define DWC_DCTL_ADDR(x) ((x) + 0x0000c704)
+#define DWC_DCTL_OFFS (0x0000c704)
+#define DWC_DCTL_RMSK 0xffffffff
+#define DWC_DCTL_POR 0x00000000
+#define DWC_DCTL_RUN_STOP_BMSK 0x80000000
+#define DWC_DCTL_RUN_STOP_SHFT 0x1f
+#define DWC_DCTL_CSFTRST_BMSK 0x40000000
+#define DWC_DCTL_CSFTRST_SHFT 0x1e
+#define DWC_DCTL_LSFTRST_BMSK 0x20000000
+#define DWC_DCTL_LSFTRST_SHFT 0x1d
+#define DWC_DCTL_HIRDTHRES_BMSK 0x1f000000
+#define DWC_DCTL_HIRDTHRES_SHFT 0x18
+#define DWC_DCTL_APPL1RES_BMSK 0x800000
+#define DWC_DCTL_APPL1RES_SHFT 0x17
+#define DWC_DCTL_RSVD40_BMSK 0x700000
+#define DWC_DCTL_RSVD40_SHFT 0x14
+#define DWC_DCTL_HIBERNATIONEN_BMSK 0x80000
+#define DWC_DCTL_HIBERNATIONEN_SHFT 0x13
+#define DWC_DCTL_L1HIBERNATIONEN_BMSK 0x40000
+#define DWC_DCTL_L1HIBERNATIONEN_SHFT 0x12
+#define DWC_DCTL_CRS_BMSK 0x20000
+#define DWC_DCTL_CRS_SHFT 0x11
+#define DWC_DCTL_CSS_BMSK 0x10000
+#define DWC_DCTL_CSS_SHFT 0x10
+#define DWC_DCTL_RSVD41_BMSK 0xe000
+#define DWC_DCTL_RSVD41_SHFT 0xd
+#define DWC_DCTL_INITU2ENA_BMSK 0x1000
+#define DWC_DCTL_INITU2ENA_SHFT 0xc
+#define DWC_DCTL_ACCEPTU2ENA_BMSK 0x800
+#define DWC_DCTL_ACCEPTU2ENA_SHFT 0xb
+#define DWC_DCTL_INITU1ENA_BMSK 0x400
+#define DWC_DCTL_INITU1ENA_SHFT 0xa
+#define DWC_DCTL_ACCEPTU1ENA_BMSK 0x200
+#define DWC_DCTL_ACCEPTU1ENA_SHFT 0x9
+#define DWC_DCTL_ULSTCHNGREQ_BMSK 0x1e0
+#define DWC_DCTL_ULSTCHNGREQ_SHFT 0x5
+#define DWC_DCTL_TSTCTL_BMSK 0x1e
+#define DWC_DCTL_TSTCTL_SHFT 0x1
+#define DWC_DCTL_RSVD0_BMSK 0x1
+#define DWC_DCTL_RSVD0_SHFT 0x0
+
+#define DWC_DEVTEN_ADDR(x) ((x) + 0x0000c708)
+#define DWC_DEVTEN_OFFS (0x0000c708)
+#define DWC_DEVTEN_RMSK 0xffffffff
+#define DWC_DEVTEN_POR 0x00000000
+#define DWC_DEVTEN_RSVD2_BMSK 0xffffc000
+#define DWC_DEVTEN_RSVD2_SHFT 0xe
+#define DWC_DEVTEN_U2INACTTIMOUTRCVDEN_BMSK 0x2000
+#define DWC_DEVTEN_U2INACTTIMOUTRCVDEN_SHFT 0xd
+#define DWC_DEVTEN_VENDEVTSTRCVDEN_BMSK 0x1000
+#define DWC_DEVTEN_VENDEVTSTRCVDEN_SHFT 0xc
+#define DWC_DEVTEN_EVNTOVERFLOWEN_BMSK 0x800
+#define DWC_DEVTEN_EVNTOVERFLOWEN_SHFT 0xb
+#define DWC_DEVTEN_CMDCMPLTEN_BMSK 0x400
+#define DWC_DEVTEN_CMDCMPLTEN_SHFT 0xa
+#define DWC_DEVTEN_ERRTICERREVTEN_BMSK 0x200
+#define DWC_DEVTEN_ERRTICERREVTEN_SHFT 0x9
+#define DWC_DEVTEN_RSVD39_BMSK 0x100
+#define DWC_DEVTEN_RSVD39_SHFT 0x8
+#define DWC_DEVTEN_SOFTEVTEN_BMSK 0x80
+#define DWC_DEVTEN_SOFTEVTEN_SHFT 0x7
+#define DWC_DEVTEN_EOPFEVTEN_BMSK 0x40
+#define DWC_DEVTEN_EOPFEVTEN_SHFT 0x6
+#define DWC_DEVTEN_HIBERNATIONREQEVTEN_BMSK 0x20
+#define DWC_DEVTEN_HIBERNATIONREQEVTEN_SHFT 0x5
+#define DWC_DEVTEN_WKUPEVTEN_BMSK 0x10
+#define DWC_DEVTEN_WKUPEVTEN_SHFT 0x4
+#define DWC_DEVTEN_ULSTCNGEN_BMSK 0x8
+#define DWC_DEVTEN_ULSTCNGEN_SHFT 0x3
+#define DWC_DEVTEN_CONNECTDONEEVTEN_BMSK 0x4
+#define DWC_DEVTEN_CONNECTDONEEVTEN_SHFT 0x2
+#define DWC_DEVTEN_USBRSTEVTEN_BMSK 0x2
+#define DWC_DEVTEN_USBRSTEVTEN_SHFT 0x1
+#define DWC_DEVTEN_DISSCONNEVTEN_BMSK 0x1
+#define DWC_DEVTEN_DISSCONNEVTEN_SHFT 0x0
+
+#define DWC_DSTS_ADDR(x) ((x) + 0x0000c70c)
+#define DWC_DSTS_OFFS (0x0000c70c)
+#define DWC_DSTS_RMSK 0xffffffff
+#define DWC_DSTS_POR 0x20820004
+#define DWC_DSTS_RSVD4_BMSK 0xc0000000
+#define DWC_DSTS_RSVD4_SHFT 0x1e
+#define DWC_DSTS_DCNRD_BMSK 0x20000000
+#define DWC_DSTS_DCNRD_SHFT 0x1d
+#define DWC_DSTS_RSVD3_BMSK 0x10000000
+#define DWC_DSTS_RSVD3_SHFT 0x1c
+#define DWC_DSTS_PLC_BMSK 0x8000000
+#define DWC_DSTS_PLC_SHFT 0x1b
+#define DWC_DSTS_CSC_BMSK 0x4000000
+#define DWC_DSTS_CSC_SHFT 0x1a
+#define DWC_DSTS_RSS_BMSK 0x2000000
+#define DWC_DSTS_RSS_SHFT 0x19
+#define DWC_DSTS_SSS_BMSK 0x1000000
+#define DWC_DSTS_SSS_SHFT 0x18
+#define DWC_DSTS_COREIDLE_BMSK 0x800000
+#define DWC_DSTS_COREIDLE_SHFT 0x17
+#define DWC_DSTS_DEVCTRLHLT_BMSK 0x400000
+#define DWC_DSTS_DEVCTRLHLT_SHFT 0x16
+#define DWC_DSTS_USBLNKST_BMSK 0x3c0000
+#define DWC_DSTS_USBLNKST_SHFT 0x12
+#define DWC_DSTS_RXFIFOEMPTY_BMSK 0x20000
+#define DWC_DSTS_RXFIFOEMPTY_SHFT 0x11
+#define DWC_DSTS_SOFFN_BMSK 0x1fff8
+#define DWC_DSTS_SOFFN_SHFT 0x3
+#define DWC_DSTS_CONNECTSPD_BMSK 0x7
+#define DWC_DSTS_CONNECTSPD_SHFT 0x0
+
+#define DWC_DGCMDPAR_ADDR(x) ((x) + 0x0000c710)
+#define DWC_DGCMDPAR_OFFS (0x0000c710)
+#define DWC_DGCMDPAR_RMSK 0xffffffff
+#define DWC_DGCMDPAR_POR 0x00000000
+#define DWC_DGCMDPAR_PARAMETER_BMSK 0xffffffff
+#define DWC_DGCMDPAR_PARAMETER_SHFT 0x0
+
+#define DWC_DGCMD_ADDR(x) ((x) + 0x0000c714)
+#define DWC_DGCMD_OFFS (0x0000c714)
+#define DWC_DGCMD_RMSK 0xffffffff
+#define DWC_DGCMD_POR 0x00000000
+#define DWC_DGCMD_RSVD6_BMSK 0xffff0000
+#define DWC_DGCMD_RSVD6_SHFT 0x10
+#define DWC_DGCMD_CMDSTATUS_BMSK 0xf000
+#define DWC_DGCMD_CMDSTATUS_SHFT 0xc
+#define DWC_DGCMD_RSVD5_BMSK 0x800
+#define DWC_DGCMD_RSVD5_SHFT 0xb
+#define DWC_DGCMD_CMDACT_BMSK 0x400
+#define DWC_DGCMD_CMDACT_SHFT 0xa
+#define DWC_DGCMD_RSVD4_BMSK 0x200
+#define DWC_DGCMD_RSVD4_SHFT 0x9
+#define DWC_DGCMD_CMDIOC_BMSK 0x100
+#define DWC_DGCMD_CMDIOC_SHFT 0x8
+#define DWC_DGCMD_CMDTYP_BMSK 0xff
+#define DWC_DGCMD_CMDTYP_SHFT 0x0
+
+#define DWC_DALEPENA_ADDR(x) ((x) + 0x0000c720)
+#define DWC_DALEPENA_OFFS (0x0000c720)
+#define DWC_DALEPENA_RMSK 0xffffffff
+#define DWC_DALEPENA_POR 0x00000000
+#define DWC_DALEPENA_USBACTEP_BMSK 0xffffffff
+#define DWC_DALEPENA_USBACTEP_SHFT 0x0
+
+#define DWC_OCFG_ADDR(x) ((x) + 0x0000cc00)
+#define DWC_OCFG_OFFS (0x0000cc00)
+#define DWC_OCFG_RMSK 0xffffffff
+#define DWC_OCFG_POR 0x00000000
+#define DWC_OCFG_RSVD0_BMSK 0xffffffc0
+#define DWC_OCFG_RSVD0_SHFT 0x6
+#define DWC_OCFG_DISPRTPWRCUTOFF_BMSK 0x20
+#define DWC_OCFG_DISPRTPWRCUTOFF_SHFT 0x5
+#define DWC_OCFG_OTGHIBDISMASK_BMSK 0x10
+#define DWC_OCFG_OTGHIBDISMASK_SHFT 0x4
+#define DWC_OCFG_OTGSFTRSTMSK_BMSK 0x8
+#define DWC_OCFG_OTGSFTRSTMSK_SHFT 0x3
+#define DWC_OCFG_OTG_VERSION_BMSK 0x4
+#define DWC_OCFG_OTG_VERSION_SHFT 0x2
+#define DWC_OCFG_HNPCAP_BMSK 0x2
+#define DWC_OCFG_HNPCAP_SHFT 0x1
+#define DWC_OCFG_SRPCAP_BMSK 0x1
+#define DWC_OCFG_SRPCAP_SHFT 0x0
+
+#define DWC_OCTL_ADDR(x) ((x) + 0x0000cc04)
+#define DWC_OCTL_OFFS (0x0000cc04)
+#define DWC_OCTL_RMSK 0xffffffff
+#define DWC_OCTL_POR 0x00000040
+#define DWC_OCTL_RSVD0_BMSK 0xffffff00
+#define DWC_OCTL_RSVD0_SHFT 0x8
+#define DWC_OCTL_OTG3_GOERR_BMSK 0x80
+#define DWC_OCTL_OTG3_GOERR_SHFT 0x7
+#define DWC_OCTL_PERIMODE_BMSK 0x40
+#define DWC_OCTL_PERIMODE_SHFT 0x6
+#define DWC_OCTL_PRTPWRCTL_BMSK 0x20
+#define DWC_OCTL_PRTPWRCTL_SHFT 0x5
+#define DWC_OCTL_HNPREQ_BMSK 0x10
+#define DWC_OCTL_HNPREQ_SHFT 0x4
+#define DWC_OCTL_SESREQ_BMSK 0x8
+#define DWC_OCTL_SESREQ_SHFT 0x3
+#define DWC_OCTL_TERMSELDLPULSE_BMSK 0x4
+#define DWC_OCTL_TERMSELDLPULSE_SHFT 0x2
+#define DWC_OCTL_DEVSETHNPEN_BMSK 0x2
+#define DWC_OCTL_DEVSETHNPEN_SHFT 0x1
+#define DWC_OCTL_HSTSETHNPEN_BMSK 0x1
+#define DWC_OCTL_HSTSETHNPEN_SHFT 0x0
+
+#define DWC_OEVT_ADDR(x) ((x) + 0x0000cc08)
+#define DWC_OEVT_OFFS (0x0000cc08)
+#define DWC_OEVT_RMSK 0xffffffff
+#define DWC_OEVT_POR 0x00000000
+#define DWC_OEVT_DEVICEMODE_BMSK 0x80000000
+#define DWC_OEVT_DEVICEMODE_SHFT 0x1f
+#define DWC_OEVT_RSVD0_BMSK 0x70000000
+#define DWC_OEVT_RSVD0_SHFT 0x1c
+#define DWC_OEVT_OTGXHCIRUNSTPSETEVNT_BMSK 0x8000000
+#define DWC_OEVT_OTGXHCIRUNSTPSETEVNT_SHFT 0x1b
+#define DWC_OEVT_OTGDEVRUNSTPSETEVNT_BMSK 0x4000000
+#define DWC_OEVT_OTGDEVRUNSTPSETEVNT_SHFT 0x1a
+#define DWC_OEVT_OTGHIBENTRYEVNT_BMSK 0x2000000
+#define DWC_OEVT_OTGHIBENTRYEVNT_SHFT 0x19
+#define DWC_OEVT_OTGCONIDSTSCHNGEVNT_BMSK 0x1000000
+#define DWC_OEVT_OTGCONIDSTSCHNGEVNT_SHFT 0x18
+#define DWC_OEVT_HRRCONFNOTIFEVNT_BMSK 0x800000
+#define DWC_OEVT_HRRCONFNOTIFEVNT_SHFT 0x17
+#define DWC_OEVT_HRRINITNOTIFEVNT_BMSK 0x400000
+#define DWC_OEVT_HRRINITNOTIFEVNT_SHFT 0x16
+#define DWC_OEVT_OTGADEVIDLEEVNT_BMSK 0x200000
+#define DWC_OEVT_OTGADEVIDLEEVNT_SHFT 0x15
+#define DWC_OEVT_OTGADEVBHOSTENDEVNT_BMSK 0x100000
+#define DWC_OEVT_OTGADEVBHOSTENDEVNT_SHFT 0x14
+#define DWC_OEVT_OTGADEVHOSTEVNT_BMSK 0x80000
+#define DWC_OEVT_OTGADEVHOSTEVNT_SHFT 0x13
+#define DWC_OEVT_OTGADEVHNPCHNGEVNT_BMSK 0x40000
+#define DWC_OEVT_OTGADEVHNPCHNGEVNT_SHFT 0x12
+#define DWC_OEVT_OTGADEVSRPDETEVNT_BMSK 0x20000
+#define DWC_OEVT_OTGADEVSRPDETEVNT_SHFT 0x11
+#define DWC_OEVT_OTGADEVSESSENDDETEVNT_BMSK 0x10000
+#define DWC_OEVT_OTGADEVSESSENDDETEVNT_SHFT 0x10
+#define DWC_OEVT_RSVD2_BMSK 0xf000
+#define DWC_OEVT_RSVD2_SHFT 0xc
+#define DWC_OEVT_OTGBDEVBHOSTENDEVNT_BMSK 0x800
+#define DWC_OEVT_OTGBDEVBHOSTENDEVNT_SHFT 0xb
+#define DWC_OEVT_OTGBDEVHNPCHNGEVNT_BMSK 0x400
+#define DWC_OEVT_OTGBDEVHNPCHNGEVNT_SHFT 0xa
+#define DWC_OEVT_OTGBDEVSESSVLDDETEVNT_BMSK 0x200
+#define DWC_OEVT_OTGBDEVSESSVLDDETEVNT_SHFT 0x9
+#define DWC_OEVT_OTGBDEVVBUSCHNGEVNT_BMSK 0x100
+#define DWC_OEVT_OTGBDEVVBUSCHNGEVNT_SHFT 0x8
+#define DWC_OEVT_RSVD3_BMSK 0xf0
+#define DWC_OEVT_RSVD3_SHFT 0x4
+#define DWC_OEVT_BSESVLD_BMSK 0x8
+#define DWC_OEVT_BSESVLD_SHFT 0x3
+#define DWC_OEVT_HSTNEGSTS_BMSK 0x4
+#define DWC_OEVT_HSTNEGSTS_SHFT 0x2
+#define DWC_OEVT_SESREQSTS_BMSK 0x2
+#define DWC_OEVT_SESREQSTS_SHFT 0x1
+#define DWC_OEVT_OEVTERROR_BMSK 0x1
+#define DWC_OEVT_OEVTERROR_SHFT 0x0
+
+#define DWC_OEVTEN_ADDR(x) ((x) + 0x0000cc0c)
+#define DWC_OEVTEN_OFFS (0x0000cc0c)
+#define DWC_OEVTEN_RMSK 0xffffffff
+#define DWC_OEVTEN_POR 0x00000000
+#define DWC_OEVTEN_RSVD0_BMSK 0xf0000000
+#define DWC_OEVTEN_RSVD0_SHFT 0x1c
+#define DWC_OEVTEN_OTGXHCIRUNSTPSETEVNTEN_BMSK 0x8000000
+#define DWC_OEVTEN_OTGXHCIRUNSTPSETEVNTEN_SHFT 0x1b
+#define DWC_OEVTEN_OTGDEVRUNSTPSETEVNTEN_BMSK 0x4000000
+#define DWC_OEVTEN_OTGDEVRUNSTPSETEVNTEN_SHFT 0x1a
+#define DWC_OEVTEN_OTGHIBENTRYEVNTEN_BMSK 0x2000000
+#define DWC_OEVTEN_OTGHIBENTRYEVNTEN_SHFT 0x19
+#define DWC_OEVTEN_OTGCONIDSTSCHNGEVNTEN_BMSK 0x1000000
+#define DWC_OEVTEN_OTGCONIDSTSCHNGEVNTEN_SHFT 0x18
+#define DWC_OEVTEN_HRRCONFNOTIFEVNTEN_BMSK 0x800000
+#define DWC_OEVTEN_HRRCONFNOTIFEVNTEN_SHFT 0x17
+#define DWC_OEVTEN_HRRINITNOTIFEVNTEN_BMSK 0x400000
+#define DWC_OEVTEN_HRRINITNOTIFEVNTEN_SHFT 0x16
+#define DWC_OEVTEN_OTGADEVIDLEEVNTEN_BMSK 0x200000
+#define DWC_OEVTEN_OTGADEVIDLEEVNTEN_SHFT 0x15
+#define DWC_OEVTEN_OTGADEVBHOSTENDEVNTEN_BMSK 0x100000
+#define DWC_OEVTEN_OTGADEVBHOSTENDEVNTEN_SHFT 0x14
+#define DWC_OEVTEN_OTGADEVHOSTEVNTEN_BMSK 0x80000
+#define DWC_OEVTEN_OTGADEVHOSTEVNTEN_SHFT 0x13
+#define DWC_OEVTEN_OTGADEVHNPCHNGEVNTEN_BMSK 0x40000
+#define DWC_OEVTEN_OTGADEVHNPCHNGEVNTEN_SHFT 0x12
+#define DWC_OEVTEN_OTGADEVSRPDETEVNTEN_BMSK 0x20000
+#define DWC_OEVTEN_OTGADEVSRPDETEVNTEN_SHFT 0x11
+#define DWC_OEVTEN_OTGADEVSESSENDDETEVNTEN_BMSK 0x10000
+#define DWC_OEVTEN_OTGADEVSESSENDDETEVNTEN_SHFT 0x10
+#define DWC_OEVTEN_RSVD2_BMSK 0xf000
+#define DWC_OEVTEN_RSVD2_SHFT 0xc
+#define DWC_OEVTEN_OTGBDEVBHOSTENDEVNTEN_BMSK 0x800
+#define DWC_OEVTEN_OTGBDEVBHOSTENDEVNTEN_SHFT 0xb
+#define DWC_OEVTEN_OTGBDEVHNPCHNGEVNTEN_BMSK 0x400
+#define DWC_OEVTEN_OTGBDEVHNPCHNGEVNTEN_SHFT 0xa
+#define DWC_OEVTEN_OTGBDEVSESSVLDDETEVNTEN_BMSK 0x200
+#define DWC_OEVTEN_OTGBDEVSESSVLDDETEVNTEN_SHFT 0x9
+#define DWC_OEVTEN_OTGBDEVVBUSCHNGEVNTEN_BMSK 0x100
+#define DWC_OEVTEN_OTGBDEVVBUSCHNGEVNTEN_SHFT 0x8
+#define DWC_OEVTEN_RSVD3_BMSK 0xff
+#define DWC_OEVTEN_RSVD3_SHFT 0x0
+
+#define DWC_OSTS_ADDR(x) ((x) + 0x0000cc10)
+#define DWC_OSTS_OFFS (0x0000cc10)
+#define DWC_OSTS_RMSK 0xffffffff
+#define DWC_OSTS_POR 0x00000819
+#define DWC_OSTS_RSVD0_BMSK 0xffffc000
+#define DWC_OSTS_RSVD0_SHFT 0xe
+#define DWC_OSTS_DEVRUNSTP_BMSK 0x2000
+#define DWC_OSTS_DEVRUNSTP_SHFT 0xd
+#define DWC_OSTS_XHCIRUNSTP_BMSK 0x1000
+#define DWC_OSTS_XHCIRUNSTP_SHFT 0xc
+#define DWC_OSTS_OTGSTATE_BMSK 0xf00
+#define DWC_OSTS_OTGSTATE_SHFT 0x8
+#define DWC_OSTS_RSVD1_BMSK 0xe0
+#define DWC_OSTS_RSVD1_SHFT 0x5
+#define DWC_OSTS_PERIPHERALSTATE_BMSK 0x10
+#define DWC_OSTS_PERIPHERALSTATE_SHFT 0x4
+#define DWC_OSTS_XHCIPRTPOWER_BMSK 0x8
+#define DWC_OSTS_XHCIPRTPOWER_SHFT 0x3
+#define DWC_OSTS_BSESVLD_BMSK 0x4
+#define DWC_OSTS_BSESVLD_SHFT 0x2
+#define DWC_OSTS_ASESVLD_BMSK 0x2
+#define DWC_OSTS_ASESVLD_SHFT 0x1
+#define DWC_OSTS_CONIDSTS_BMSK 0x1
+#define DWC_OSTS_CONIDSTS_SHFT 0x0
+
+#define DWC_ADPCFG_ADDR(x) ((x) + 0x0000cc20)
+#define DWC_ADPCFG_OFFS (0x0000cc20)
+#define DWC_ADPCFG_RMSK 0xffffffff
+#define DWC_ADPCFG_POR 0x00000000
+#define DWC_ADPCFG_PRBPER_BMSK 0xc0000000
+#define DWC_ADPCFG_PRBPER_SHFT 0x1e
+#define DWC_ADPCFG_PRBDELTA_BMSK 0x30000000
+#define DWC_ADPCFG_PRBDELTA_SHFT 0x1c
+#define DWC_ADPCFG_PRBDSCHG_BMSK 0xc000000
+#define DWC_ADPCFG_PRBDSCHG_SHFT 0x1a
+#define DWC_ADPCFG_RSVD0_BMSK 0x3ffffff
+#define DWC_ADPCFG_RSVD0_SHFT 0x0
+
+#define DWC_ADPCTL_ADDR(x) ((x) + 0x0000cc24)
+#define DWC_ADPCTL_OFFS (0x0000cc24)
+#define DWC_ADPCTL_RMSK 0xffffffff
+#define DWC_ADPCTL_POR 0x00000000
+#define DWC_ADPCTL_RSVD0_BMSK 0xe0000000
+#define DWC_ADPCTL_RSVD0_SHFT 0x1d
+#define DWC_ADPCTL_ENAPRB_BMSK 0x10000000
+#define DWC_ADPCTL_ENAPRB_SHFT 0x1c
+#define DWC_ADPCTL_ENASNS_BMSK 0x8000000
+#define DWC_ADPCTL_ENASNS_SHFT 0x1b
+#define DWC_ADPCTL_ADPEN_BMSK 0x4000000
+#define DWC_ADPCTL_ADPEN_SHFT 0x1a
+#define DWC_ADPCTL_ADPRES_BMSK 0x2000000
+#define DWC_ADPCTL_ADPRES_SHFT 0x19
+#define DWC_ADPCTL_WB_BMSK 0x1000000
+#define DWC_ADPCTL_WB_SHFT 0x18
+#define DWC_ADPCTL_RSVD1_BMSK 0xffffff
+#define DWC_ADPCTL_RSVD1_SHFT 0x0
+
+#define DWC_ADPEVT_ADDR(x) ((x) + 0x0000cc28)
+#define DWC_ADPEVT_OFFS (0x0000cc28)
+#define DWC_ADPEVT_RMSK 0xffffffff
+#define DWC_ADPEVT_POR 0x00000000
+#define DWC_ADPEVT_RSVD0_BMSK 0xe0000000
+#define DWC_ADPEVT_RSVD0_SHFT 0x1d
+#define DWC_ADPEVT_ADPPRBEVNT_BMSK 0x10000000
+#define DWC_ADPEVT_ADPPRBEVNT_SHFT 0x1c
+#define DWC_ADPEVT_ADPSNSEVNT_BMSK 0x8000000
+#define DWC_ADPEVT_ADPSNSEVNT_SHFT 0x1b
+#define DWC_ADPEVT_ADPTMOUTEVNT_BMSK 0x4000000
+#define DWC_ADPEVT_ADPTMOUTEVNT_SHFT 0x1a
+#define DWC_ADPEVT_ADPRSTCMPLTEVNT_BMSK 0x2000000
+#define DWC_ADPEVT_ADPRSTCMPLTEVNT_SHFT 0x19
+#define DWC_ADPEVT_RSVD1_BMSK 0x1fff800
+#define DWC_ADPEVT_RSVD1_SHFT 0xb
+#define DWC_ADPEVT_RTIM_BMSK 0x7ff
+#define DWC_ADPEVT_RTIM_SHFT 0x0
+
+#define DWC_ADPEVTEN_ADDR(x) ((x) + 0x0000cc2c)
+#define DWC_ADPEVTEN_OFFS (0x0000cc2c)
+#define DWC_ADPEVTEN_RMSK 0xffffffff
+#define DWC_ADPEVTEN_POR 0x00000000
+#define DWC_ADPEVTEN_RSVD0_BMSK 0xe0000000
+#define DWC_ADPEVTEN_RSVD0_SHFT 0x1d
+#define DWC_ADPEVTEN_ADPPRBEVNTEN_BMSK 0x10000000
+#define DWC_ADPEVTEN_ADPPRBEVNTEN_SHFT 0x1c
+#define DWC_ADPEVTEN_ADPSNSEVNTEN_BMSK 0x8000000
+#define DWC_ADPEVTEN_ADPSNSEVNTEN_SHFT 0x1b
+#define DWC_ADPEVTEN_ADPTMOUTEVNTEN_BMSK 0x4000000
+#define DWC_ADPEVTEN_ADPTMOUTEVNTEN_SHFT 0x1a
+#define DWC_ADPEVTEN_ADPRSTCMPLTEVNTEN_BMSK 0x2000000
+#define DWC_ADPEVTEN_ADPRSTCMPLTEVNTEN_SHFT 0x19
+#define DWC_ADPEVTEN_RSVD1_BMSK 0x1ffffff
+#define DWC_ADPEVTEN_RSVD1_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: USB30_QSCRATCH
+ *--------------------------------------------------------------------------*/
+#define USB30_QSCRATCH_REG_BASE_OFFS 0x000f8800
+#define DWC_HS_PHY_CTRL_ADDR(x) ((x) + 0x00000010)
+#define DWC_HS_PHY_CTRL_OFFS (0x00000010)
+#define DWC_HS_PHY_CTRL_RMSK 0x7ffffff
+#define DWC_HS_PHY_CTRL_POR 0x072203b2
+#define DWC_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_BMSK 0x4000000
+#define DWC_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_SHFT 0x1a
+#define DWC_HS_PHY_CTRL_FREECLK_SEL_BMSK 0x2000000
+#define DWC_HS_PHY_CTRL_FREECLK_SEL_SHFT 0x19
+#define DWC_HS_PHY_CTRL_DMSEHV_CLAMP_EN_N_BMSK 0x1000000
+#define DWC_HS_PHY_CTRL_DMSEHV_CLAMP_EN_N_SHFT 0x18
+#define DWC_HS_PHY_CTRL_USB2_SUSPEND_N_SEL_BMSK 0x800000
+#define DWC_HS_PHY_CTRL_USB2_SUSPEND_N_SEL_SHFT 0x17
+#define DWC_HS_PHY_CTRL_USB2_SUSPEND_N_BMSK 0x400000
+#define DWC_HS_PHY_CTRL_USB2_SUSPEND_N_SHFT 0x16
+#define DWC_HS_PHY_CTRL_USB2_UTMI_CLK_EN_BMSK 0x200000
+#define DWC_HS_PHY_CTRL_USB2_UTMI_CLK_EN_SHFT 0x15
+#define DWC_HS_PHY_CTRL_UTMI_OTG_VBUS_VALID_BMSK 0x100000
+#define DWC_HS_PHY_CTRL_UTMI_OTG_VBUS_VALID_SHFT 0x14
+#define DWC_HS_PHY_CTRL_AUTORESUME_BMSK 0x80000
+#define DWC_HS_PHY_CTRL_AUTORESUME_SHFT 0x13
+#define DWC_HS_PHY_CTRL_USE_CLKCORE_BMSK 0x40000
+#define DWC_HS_PHY_CTRL_USE_CLKCORE_SHFT 0x12
+#define DWC_HS_PHY_CTRL_DPSEHV_CLAMP_EN_N_BMSK 0x20000
+#define DWC_HS_PHY_CTRL_DPSEHV_CLAMP_EN_N_SHFT 0x11
+#define DWC_HS_PHY_CTRL_IDHV_INTEN_BMSK 0x10000
+#define DWC_HS_PHY_CTRL_IDHV_INTEN_SHFT 0x10
+#define DWC_HS_PHY_CTRL_OTGSESSVLDHV_INTEN_BMSK 0x8000
+#define DWC_HS_PHY_CTRL_OTGSESSVLDHV_INTEN_SHFT 0xf
+#define DWC_HS_PHY_CTRL_VBUSVLDEXTSEL0_BMSK 0x4000
+#define DWC_HS_PHY_CTRL_VBUSVLDEXTSEL0_SHFT 0xe
+#define DWC_HS_PHY_CTRL_VBUSVLDEXT0_BMSK 0x2000
+#define DWC_HS_PHY_CTRL_VBUSVLDEXT0_SHFT 0xd
+#define DWC_HS_PHY_CTRL_OTGDISABLE0_BMSK 0x1000
+#define DWC_HS_PHY_CTRL_OTGDISABLE0_SHFT 0xc
+#define DWC_HS_PHY_CTRL_COMMONONN_BMSK 0x800
+#define DWC_HS_PHY_CTRL_COMMONONN_SHFT 0xb
+#define DWC_HS_PHY_CTRL_ULPIPOR_BMSK 0x400
+#define DWC_HS_PHY_CTRL_ULPIPOR_SHFT 0xa
+#define DWC_HS_PHY_CTRL_ID_HV_CLAMP_EN_N_BMSK 0x200
+#define DWC_HS_PHY_CTRL_ID_HV_CLAMP_EN_N_SHFT 0x9
+#define DWC_HS_PHY_CTRL_OTGSESSVLD_HV_CLAMP_EN_N_BMSK 0x100
+#define DWC_HS_PHY_CTRL_OTGSESSVLD_HV_CLAMP_EN_N_SHFT 0x8
+#define DWC_HS_PHY_CTRL_CLAMP_EN_N_BMSK 0x80
+#define DWC_HS_PHY_CTRL_CLAMP_EN_N_SHFT 0x7
+#define DWC_HS_PHY_CTRL_FSEL_BMSK 0x70
+#define DWC_HS_PHY_CTRL_FSEL_SHFT 0x4
+#define DWC_HS_PHY_CTRL_REFCLKOUT_EN_BMSK 0x8
+#define DWC_HS_PHY_CTRL_REFCLKOUT_EN_SHFT 0x3
+#define DWC_HS_PHY_CTRL_SIDDQ_BMSK 0x4
+#define DWC_HS_PHY_CTRL_SIDDQ_SHFT 0x2
+#define DWC_HS_PHY_CTRL_RETENABLEN_BMSK 0x2
+#define DWC_HS_PHY_CTRL_RETENABLEN_SHFT 0x1
+#define DWC_HS_PHY_CTRL_POR_BMSK 0x1
+#define DWC_HS_PHY_CTRL_POR_SHFT 0x0
+
+#define DWC_CHARGING_DET_CTRL_ADDR(x) ((x) + 0x00000018)
+#define DWC_CHARGING_DET_CTRL_PHYS(x) ((x) + 0x00000018)
+#define DWC_CHARGING_DET_CTRL_OFFS (0x00000018)
+#define DWC_CHARGING_DET_CTRL_RMSK 0x3f
+#define DWC_CHARGING_DET_CTRL_POR 0x00000000
+#define DWC_CHARGING_DET_CTRL_VDATDETENB0_BMSK 0x20
+#define DWC_CHARGING_DET_CTRL_VDATDETENB0_SHFT 0x5
+#define DWC_CHARGING_DET_CTRL_VDATSRCENB0_BMSK 0x10
+#define DWC_CHARGING_DET_CTRL_VDATSRCENB0_SHFT 0x4
+#define DWC_CHARGING_DET_CTRL_VDMSRCAUTO_BMSK 0x8
+#define DWC_CHARGING_DET_CTRL_VDMSRCAUTO_SHFT 0x3
+#define DWC_CHARGING_DET_CTRL_CHRGSEL0_BMSK 0x4
+#define DWC_CHARGING_DET_CTRL_CHRGSEL0_SHFT 0x2
+#define DWC_CHARGING_DET_CTRL_DCDENB0_BMSK 0x2
+#define DWC_CHARGING_DET_CTRL_DCDENB0_SHFT 0x1
+#define DWC_CHARGING_DET_CTRL_ACAENB0_BMSK 0x1
+#define DWC_CHARGING_DET_CTRL_ACAENB0_SHFT 0x0
+
+#define DWC_CHARGING_DET_OUTPUT_ADDR(x) ((x) + 0x0000001c)
+#define DWC_CHARGING_DET_OUTPUT_PHYS(x) ((x) + 0x0000001c)
+#define DWC_CHARGING_DET_OUTPUT_OFFS (0x0000001c)
+#define DWC_CHARGING_DET_OUTPUT_RMSK 0xfff
+#define DWC_CHARGING_DET_OUTPUT_POR 0x00000000
+#define DWC_CHARGING_DET_OUTPUT_DMSEHV_BMSK 0x800
+#define DWC_CHARGING_DET_OUTPUT_DMSEHV_SHFT 0xb
+#define DWC_CHARGING_DET_OUTPUT_DPSEHV_BMSK 0x400
+#define DWC_CHARGING_DET_OUTPUT_DPSEHV_SHFT 0xa
+#define DWC_CHARGING_DET_OUTPUT_LINESTATE_BMSK 0x300
+#define DWC_CHARGING_DET_OUTPUT_LINESTATE_SHFT 0x8
+#define DWC_CHARGING_DET_OUTPUT_RIDFLOAT_N_BMSK 0x80
+#define DWC_CHARGING_DET_OUTPUT_RIDFLOAT_N_SHFT 0x7
+#define DWC_CHARGING_DET_OUTPUT_RIDFLOAT_BMSK 0x40
+#define DWC_CHARGING_DET_OUTPUT_RIDFLOAT_SHFT 0x6
+#define DWC_CHARGING_DET_OUTPUT_RIDGND_BMSK 0x20
+#define DWC_CHARGING_DET_OUTPUT_RIDGND_SHFT 0x5
+#define DWC_CHARGING_DET_OUTPUT_RIDC_BMSK 0x10
+#define DWC_CHARGING_DET_OUTPUT_RIDC_SHFT 0x4
+#define DWC_CHARGING_DET_OUTPUT_RIDB_BMSK 0x8
+#define DWC_CHARGING_DET_OUTPUT_RIDB_SHFT 0x3
+#define DWC_CHARGING_DET_OUTPUT_RIDA_BMSK 0x4
+#define DWC_CHARGING_DET_OUTPUT_RIDA_SHFT 0x2
+#define DWC_CHARGING_DET_OUTPUT_DCDOUT_BMSK 0x2
+#define DWC_CHARGING_DET_OUTPUT_DCDOUT_SHFT 0x1
+#define DWC_CHARGING_DET_OUTPUT_CHGDET_BMSK 0x1
+#define DWC_CHARGING_DET_OUTPUT_CHGDET_SHFT 0x0
+
+#define DWC_ALT_INTERRUPT_EN_ADDR(x) ((x) + 0x00000020)
+#define DWC_ALT_INTERRUPT_EN_PHYS(x) ((x) + 0x00000020)
+#define DWC_ALT_INTERRUPT_EN_OFFS (0x00000020)
+#define DWC_ALT_INTERRUPT_EN_RMSK 0xfff
+#define DWC_ALT_INTERRUPT_EN_POR 0x00000000
+#define DWC_ALT_INTERRUPT_EN_DMSEHV_LO_INTEN_BMSK 0x800
+#define DWC_ALT_INTERRUPT_EN_DMSEHV_LO_INTEN_SHFT 0xb
+#define DWC_ALT_INTERRUPT_EN_DMSEHV_HI_INTEN_BMSK 0x400
+#define DWC_ALT_INTERRUPT_EN_DMSEHV_HI_INTEN_SHFT 0xa
+#define DWC_ALT_INTERRUPT_EN_DPSEHV_LO_INTEN_BMSK 0x200
+#define DWC_ALT_INTERRUPT_EN_DPSEHV_LO_INTEN_SHFT 0x9
+#define DWC_ALT_INTERRUPT_EN_DPSEHV_HI_INTEN_BMSK 0x100
+#define DWC_ALT_INTERRUPT_EN_DPSEHV_HI_INTEN_SHFT 0x8
+#define DWC_ALT_INTERRUPT_EN_DMSEHV_INTEN_BMSK 0x80
+#define DWC_ALT_INTERRUPT_EN_DMSEHV_INTEN_SHFT 0x7
+#define DWC_ALT_INTERRUPT_EN_DPSEHV_INTEN_BMSK 0x40
+#define DWC_ALT_INTERRUPT_EN_DPSEHV_INTEN_SHFT 0x6
+#define DWC_ALT_INTERRUPT_EN_RIDFLOATNINTEN_BMSK 0x20
+#define DWC_ALT_INTERRUPT_EN_RIDFLOATNINTEN_SHFT 0x5
+#define DWC_ALT_INTERRUPT_EN_CHGDETINTEN_BMSK 0x10
+#define DWC_ALT_INTERRUPT_EN_CHGDETINTEN_SHFT 0x4
+#define DWC_ALT_INTERRUPT_EN_DPINTEN_BMSK 0x8
+#define DWC_ALT_INTERRUPT_EN_DPINTEN_SHFT 0x3
+#define DWC_ALT_INTERRUPT_EN_DCDINTEN_BMSK 0x4
+#define DWC_ALT_INTERRUPT_EN_DCDINTEN_SHFT 0x2
+#define DWC_ALT_INTERRUPT_EN_DMINTEN_BMSK 0x2
+#define DWC_ALT_INTERRUPT_EN_DMINTEN_SHFT 0x1
+#define DWC_ALT_INTERRUPT_EN_ACAINTEN_BMSK 0x1
+#define DWC_ALT_INTERRUPT_EN_ACAINTEN_SHFT 0x0
+
+#define DWC_HS_PHY_IRQ_STAT_ADDR(x) ((x) + 0x00000024)
+#define DWC_HS_PHY_IRQ_STAT_PHYS(x) ((x) + 0x00000024)
+#define DWC_HS_PHY_IRQ_STAT_OFFS (0x00000024)
+#define DWC_HS_PHY_IRQ_STAT_RMSK 0xfff
+#define DWC_HS_PHY_IRQ_STAT_POR 0x00000000
+#define DWC_HS_PHY_IRQ_STAT_DMSEHV_LO_INTLCH_BMSK 0x800
+#define DWC_HS_PHY_IRQ_STAT_DMSEHV_LO_INTLCH_SHFT 0xb
+#define DWC_HS_PHY_IRQ_STAT_DMSEHV_HI_INTLCH_BMSK 0x400
+#define DWC_HS_PHY_IRQ_STAT_DMSEHV_HI_INTLCH_SHFT 0xa
+#define DWC_HS_PHY_IRQ_STAT_DPSEHV_LO_INTLCH_BMSK 0x200
+#define DWC_HS_PHY_IRQ_STAT_DPSEHV_LO_INTLCH_SHFT 0x9
+#define DWC_HS_PHY_IRQ_STAT_DPSEHV_HI_INTLCH_BMSK 0x100
+#define DWC_HS_PHY_IRQ_STAT_DPSEHV_HI_INTLCH_SHFT 0x8
+#define DWC_HS_PHY_IRQ_STAT_DMSEHV_INTLCH_BMSK 0x80
+#define DWC_HS_PHY_IRQ_STAT_DMSEHV_INTLCH_SHFT 0x7
+#define DWC_HS_PHY_IRQ_STAT_DPSEHV_INTLCH_BMSK 0x40
+#define DWC_HS_PHY_IRQ_STAT_DPSEHV_INTLCH_SHFT 0x6
+#define DWC_HS_PHY_IRQ_STAT_RIDFLOATNINTLCH_BMSK 0x20
+#define DWC_HS_PHY_IRQ_STAT_RIDFLOATNINTLCH_SHFT 0x5
+#define DWC_HS_PHY_IRQ_STAT_CHGDETINTLCH_BMSK 0x10
+#define DWC_HS_PHY_IRQ_STAT_CHGDETINTLCH_SHFT 0x4
+#define DWC_HS_PHY_IRQ_STAT_DPINTLCH_BMSK 0x8
+#define DWC_HS_PHY_IRQ_STAT_DPINTLCH_SHFT 0x3
+#define DWC_HS_PHY_IRQ_STAT_DCDINTLCH_BMSK 0x4
+#define DWC_HS_PHY_IRQ_STAT_DCDINTLCH_SHFT 0x2
+#define DWC_HS_PHY_IRQ_STAT_DMINTLCH_BMSK 0x2
+#define DWC_HS_PHY_IRQ_STAT_DMINTLCH_SHFT 0x1
+#define DWC_HS_PHY_IRQ_STAT_ACAINTLCH_BMSK 0x1
+#define DWC_HS_PHY_IRQ_STAT_ACAINTLCH_SHFT 0x0
+
+
+#define DWC_SS_PHY_CTRL_ADDR(x) ((x) + 0x00000030)
+#define DWC_SS_PHY_CTRL_OFFS (0x00000030)
+#define DWC_SS_PHY_CTRL_RMSK 0x1fffffff
+#define DWC_SS_PHY_CTRL_POR 0x10108002
+#define DWC_SS_PHY_CTRL_REF_USE_PAD_BMSK 0x10000000
+#define DWC_SS_PHY_CTRL_REF_USE_PAD_SHFT 0x1c
+#define DWC_SS_PHY_CTRL_TEST_BURNIN_BMSK 0x8000000
+#define DWC_SS_PHY_CTRL_TEST_BURNIN_SHFT 0x1b
+#define DWC_SS_PHY_CTRL_TEST_POWERDOWN_BMSK 0x4000000
+#define DWC_SS_PHY_CTRL_TEST_POWERDOWN_SHFT 0x1a
+#define DWC_SS_PHY_CTRL_RTUNE_REQ_BMSK 0x2000000
+#define DWC_SS_PHY_CTRL_RTUNE_REQ_SHFT 0x19
+#define DWC_SS_PHY_CTRL_LANE0_PWR_PRESENT_BMSK 0x1000000
+#define DWC_SS_PHY_CTRL_LANE0_PWR_PRESENT_SHFT 0x18
+#define DWC_SS_PHY_CTRL_USB2_REF_CLK_EN_BMSK 0x800000
+#define DWC_SS_PHY_CTRL_USB2_REF_CLK_EN_SHFT 0x17
+#define DWC_SS_PHY_CTRL_USB2_REF_CLK_SEL_BMSK 0x400000
+#define DWC_SS_PHY_CTRL_USB2_REF_CLK_SEL_SHFT 0x16
+#define DWC_SS_PHY_CTRL_SSC_REF_CLK_SEL_BMSK 0x3fe000
+#define DWC_SS_PHY_CTRL_SSC_REF_CLK_SEL_SHFT 0xd
+#define DWC_SS_PHY_CTRL_SSC_RANGE_BMSK 0x1c00
+#define DWC_SS_PHY_CTRL_SSC_RANGE_SHFT 0xa
+#define DWC_SS_PHY_CTRL_REF_USB2_EN_BMSK 0x200
+#define DWC_SS_PHY_CTRL_REF_USB2_EN_SHFT 0x9
+#define DWC_SS_PHY_CTRL_REF_SS_PHY_EN_BMSK 0x100
+#define DWC_SS_PHY_CTRL_REF_SS_PHY_EN_SHFT 0x8
+#define DWC_SS_PHY_CTRL_SS_PHY_RESET_BMSK 0x80
+#define DWC_SS_PHY_CTRL_SS_PHY_RESET_SHFT 0x7
+#define DWC_SS_PHY_CTRL_MPLL_MULTI_BMSK 0x7f
+#define DWC_SS_PHY_CTRL_MPLL_MULTI_SHFT 0x0
+
+
+#endif /* _DWC_DWC_H_ */
diff --git a/platform/msm_shared/usb30_udc.c b/platform/msm_shared/usb30_udc.c
new file mode 100644
index 0000000..e873ac2
--- /dev/null
+++ b/platform/msm_shared/usb30_udc.c
@@ -0,0 +1,1083 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* This file implements the UDC (usb device controller) layer to be used with
+ * the new dwc controller.
+ * It exposes APIs to initialize UDC (and thus usb) and perform data transfer
+ * over usb.
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <string.h>
+#include <malloc.h>
+#include <stdlib.h>
+#include <arch/defines.h>
+#include <dev/udc.h>
+#include <platform/iomap.h>
+#include <usb30_dwc.h>
+#include <usb30_wrapper.h>
+#include <usb30_udc.h>
+
+//#define DEBUG_USB
+
+#ifdef DEBUG_USB
+#define DBG(...) dprintf(ALWAYS, __VA_ARGS__)
+#else
+#define DBG(...)
+#endif
+
+#define ERR(...) dprintf(ALWAYS, __VA_ARGS__)
+
+/* control data transfer is max 512 bytes */
+#define UDC_CONTROL_RX_BUF_SIZE 512
+#define UDC_CONTROL_TX_BUF_SIZE 512
+
+/* Buffer used by dwc driver to process events.
+ * Must be multiple of 4: snps 6.2.7.2.
+ */
+#define UDC_DWC_EVENT_BUF_SIZE 4096
+
+/* macro to parse setup request */
+#define SETUP(type,request) (((type) << 8) | (request))
+
+/* macro to generate bit representation of an EP */
+#define EPT_TX(n) (1 << ((n) + 16))
+#define EPT_RX(n) (1 << (n))
+
+/* Local functions */
+static struct udc_descriptor *udc_descriptor_alloc(uint32_t type,
+ uint32_t num,
+ uint32_t len,
+ udc_desc_spec_t spec);
+static uint8_t udc_string_desc_alloc(udc_t *udc, const char *str);
+
+static void udc_descriptor_register(udc_t *udc, struct udc_descriptor *desc);
+static void udc_register_language_desc(udc_t *udc);
+static void udc_register_bos_desc(udc_t *udc);
+static void udc_register_device_desc_usb_20(udc_t *udc, struct udc_device *dev_info);
+static void udc_register_device_desc_usb_30(udc_t *udc, struct udc_device *dev_info);
+static void udc_register_config_desc_usb20(udc_t *udc, struct udc_gadget *gadget);
+static void udc_register_config_desc_usb30(udc_t *udc, struct udc_gadget *gadget);
+
+static void udc_ept_desc_fill(struct udc_endpoint *ept, uint8_t *data);
+static void udc_ept_comp_desc_fill(struct udc_endpoint *ept, uint8_t *data);
+
+static void udc_dwc_notify(void *context, dwc_notify_event_t event);
+static int udc_handle_setup(void *context, uint8_t *data);
+
+/* TODO: This must be the only global var in this file, for now.
+ * Ideally, all APIs should be sending
+ * this to us and this ptr should be kept outside of this code.
+ * This needs change in the common udc APIs and thus keeping it here until that
+ * is done.
+ */
+static udc_t *udc_dev = NULL;
+
+
+/* TODO: need to find right place for the tcsr functions. */
+
+/* UTMI MUX configuration to connect PHY to SNPS controller:
+ * Configure primary HS phy mux to use UTMI interface
+ * (connected to usb30 controller).
+ */
+void tcsr_hs_phy_mux_configure(void)
+{
+ uint32_t reg;
+
+ reg = readl(USB2_PHY_SEL);
+
+ writel(reg | 0x1, USB2_PHY_SEL);
+}
+
+void tcsr_hs_phy_mux_de_configure(void)
+{
+ writel(0x0, USB2_PHY_SEL);
+}
+
+
+/* Initialize usb wrapper and dwc h/w blocks. */
+static void usb30_init(void)
+{
+ usb_wrapper_dev_t* wrapper;
+ usb_wrapper_config_t wrapper_config;
+
+ dwc_dev_t *dwc;
+ dwc_config_t dwc_config;
+
+ /* initialize the usb wrapper h/w block */
+ wrapper_config.qscratch_base = (void*) MSM_USB30_QSCRATCH_BASE;
+
+ wrapper = usb_wrapper_init(&wrapper_config);
+ ASSERT(wrapper);
+
+ /* save the wrapper ptr */
+ udc_dev->wrapper_dev = wrapper;
+
+ /* initialize the dwc device block */
+ dwc_config.base = (void*) MSM_USB30_BASE;
+
+ /* buffer must be aligned to buf size. snps 8.2.2 */
+ dwc_config.event_buf = memalign(lcm(CACHE_LINE, UDC_DWC_EVENT_BUF_SIZE),
+ ROUNDUP(UDC_DWC_EVENT_BUF_SIZE, CACHE_LINE));
+ ASSERT(dwc_config.event_buf);
+
+ dwc_config.event_buf_size = UDC_DWC_EVENT_BUF_SIZE;
+
+ /* notify handler */
+ dwc_config.notify_context = udc_dev;
+ dwc_config.notify = udc_dwc_notify;
+
+ /* setup handler */
+ dwc_config.setup_context = udc_dev;
+ dwc_config.setup_handler = udc_handle_setup;
+
+ dwc = dwc_init(&dwc_config);
+ ASSERT(dwc);
+
+ /* save the dwc dev ptr */
+ udc_dev->dwc = dwc;
+
+
+ /* USB3.0 core and phy initialization as described in HPG */
+
+ /* section 4.4.1 Control sequence */
+ usb_wrapper_dbm_mode(wrapper, DBM_MODE_BYPASS);
+
+ /* section 4.4.1: use config 0 - all of RAM1 */
+ usb_wrapper_ram_configure(wrapper);
+
+ /* section 4.4.2: Initialization and configuration sequences */
+
+ /* 1. UTMI Mux configuration */
+ tcsr_hs_phy_mux_configure();
+
+ /* 2. Put controller in reset */
+ dwc_reset(dwc, 1);
+
+ /* PHY reset (steps 3 - 7) must be done while dwc is in reset condition */
+
+ /* 3. Reset SS PHY */
+ usb_wrapper_ss_phy_reset(wrapper);
+
+ /* HS PHY is reset as part of soft reset. No need for explicit reset. */
+
+ /* 4. SS phy config */
+ usb_wrapper_ss_phy_configure(wrapper);
+
+ /* 5. HS phy init */
+ usb_wrapper_hs_phy_init(wrapper);
+
+ /* 5.d */
+ dwc_usb2_phy_soft_reset(dwc);
+
+ /* 6. hs phy config */
+ usb_wrapper_hs_phy_configure(wrapper);
+
+ /* 7. Reset PHY digital interface */
+ dwc_phy_digital_reset(dwc);
+
+ /* 8. Bring dwc controller out of reset */
+ dwc_reset(dwc, 0);
+
+ /* 9. */
+ usb_wrapper_ss_phy_electrical_config(wrapper);
+
+ /* 10. */
+ usb_wrapper_workaround_10(wrapper);
+
+ /* 11. */
+ usb_wrapper_workaround_11(wrapper);
+
+ /* 12. */
+ dwc_ss_phy_workaround_12(dwc);
+
+ /* 13. */
+ usb_wrapper_workaround_13(wrapper);
+
+ /* 14. needed only for host mode. ignored. */
+
+ /* 15 - 20 */
+ dwc_device_init(dwc);
+}
+
+/* udc_init: creates and registers various usb descriptor */
+int udc_init(struct udc_device *dev_info)
+{
+ /* create and initialize udc instance */
+ udc_dev = (udc_t*) malloc(sizeof(udc_t));
+ ASSERT(udc_dev);
+
+ /* initialize everything to 0 */
+ memset(udc_dev, 0 , sizeof(udc_t));
+
+ /* malloc control data buffers */
+ udc_dev->ctrl_rx_buf = memalign(CACHE_LINE, ROUNDUP(UDC_CONTROL_RX_BUF_SIZE, CACHE_LINE));
+ ASSERT(udc_dev->ctrl_rx_buf);
+
+ udc_dev->ctrl_tx_buf = memalign(CACHE_LINE, ROUNDUP(UDC_CONTROL_TX_BUF_SIZE, CACHE_LINE));
+ ASSERT(udc_dev->ctrl_tx_buf);
+
+ /* initialize string id */
+ udc_dev->next_string_id = 1;
+
+ /* Initialize ept data */
+ /* alloc table to assume EP0 In/OUT are already allocated.*/
+ udc_dev->ept_alloc_table = EPT_TX(0) | EPT_RX(0);
+ udc_dev->ept_list = NULL;
+
+ usb30_init();
+
+ /* register descriptors */
+ udc_register_language_desc(udc_dev);
+ udc_register_device_desc_usb_20(udc_dev, dev_info);
+ udc_register_device_desc_usb_30(udc_dev, dev_info);
+ udc_register_bos_desc(udc_dev);
+
+ return 0;
+}
+
+/* application registers its gadget by calling this func.
+ * gadget == interface descriptor
+ */
+int udc_register_gadget(struct udc_gadget *gadget)
+{
+ ASSERT(gadget);
+
+ /* check if already registered */
+ if (udc_dev->gadget)
+ {
+ ERR("\nonly one gadget supported\n");
+ return -1;
+ }
+
+ /* create our configuration descriptors based on this gadget data */
+ udc_register_config_desc_usb20(udc_dev, gadget);
+ udc_register_config_desc_usb30(udc_dev, gadget);
+
+ /* save the gadget */
+ udc_dev->gadget = gadget;
+
+ return 0;
+}
+
+/* udc_start: */
+int udc_start(void)
+{
+ /* 19. run
+ * enable device to receive SOF packets and
+ * respond to control transfers on EP0 and generate events.
+ */
+ dwc_device_run(udc_dev->dwc, 1);
+
+ return 0;
+}
+
+/* Control data rx callback. Called by DWC layer when it receives control
+ * data from host.
+ */
+void udc_control_rx_callback(void *context, unsigned actual, int status)
+{
+ udc_t *udc = (udc_t *) context;
+
+ /* Force reload of buffer update by controller from memory */
+ arch_invalidate_cache_range((addr_t) udc->ctrl_rx_buf, actual);
+
+ /* TODO: for now, there is only one 3-stage write during 3.0 enumeration
+ * (SET_SEL), which causes this callback. Ideally, set_periodic() must
+ * be based on which control rx just happened.
+ * Also, the value of 0x65 should depend on the data received for SET_SEL.
+ * For now, this value works just fine.
+ */
+ dwc_device_set_periodic_param(udc->dwc, 0x65);
+}
+
+/* lookup request name for debug purposes */
+static const char *reqname(uint32_t r)
+{
+ switch (r) {
+ case GET_STATUS:
+ return "GET_STATUS";
+ case CLEAR_FEATURE:
+ return "CLEAR_FEATURE";
+ case SET_FEATURE:
+ return "SET_FEATURE";
+ case SET_ADDRESS:
+ return "SET_ADDRESS";
+ case GET_DESCRIPTOR:
+ return "GET_DESCRIPTOR";
+ case SET_DESCRIPTOR:
+ return "SET_DESCRIPTOR";
+ case GET_CONFIGURATION:
+ return "GET_CONFIGURATION";
+ case SET_CONFIGURATION:
+ return "SET_CONFIGURATION";
+ case GET_INTERFACE:
+ return "GET_INTERFACE";
+ case SET_INTERFACE:
+ return "SET_INTERFACE";
+ case SET_SEL:
+ return "SET_SEL";
+ default:
+ return "*UNKNOWN*";
+ }
+}
+
+/* callback function called by DWC layer when a setup packed is received.
+ * the return value tells dwc layer whether this setup pkt results in
+ * a 2-stage or a 3-stage control transfer or stall.
+ */
+static int udc_handle_setup(void *context, uint8_t *data)
+{
+ udc_t *udc = (udc_t *) context;
+ uint32_t len;
+
+ ASSERT(udc);
+
+ dwc_dev_t *dwc = udc->dwc;
+ ASSERT(dwc);
+
+ struct setup_packet s = *((struct setup_packet*) data);
+
+ DBG("\n SETUP request: \n type = 0x%x \n request = 0x%x \n value = 0x%x"
+ " \n index = 0x%x \n length = 0x%x\n",
+ s.type, s.request, s.value, s.index, s.length);
+
+ switch (SETUP(s.type, s.request))
+ {
+ case SETUP(DEVICE_READ, GET_STATUS):
+ {
+ DBG("\n DEVICE_READ : GET_STATUS: value = %d index = %d"
+ " length = %d", s.value, s.index, s.length);
+
+ if (s.length == 2) {
+
+ uint16_t zero = 0;
+ len = 2;
+
+ /* copy to tx buffer */
+ memcpy(udc->ctrl_tx_buf, &zero, len);
+
+ /* flush buffer to main memory before queueing the request */
+ arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len);
+
+ dwc_transfer_request(udc->dwc,
+ 0,
+ DWC_EP_DIRECTION_IN,
+ udc->ctrl_tx_buf,
+ len,
+ NULL,
+ NULL);
+
+ return DWC_SETUP_3_STAGE;
+ }
+ }
+ break;
+ case SETUP(DEVICE_READ, GET_DESCRIPTOR):
+ {
+ DBG("\n DEVICE_READ : GET_DESCRIPTOR: value = %d", s.value);
+
+ /* setup usb ep0-IN to send our device descriptor */
+ struct udc_descriptor *desc;
+
+ for (desc = udc->desc_list; desc; desc = desc->next)
+ {
+ /* tag must match the value AND
+ * if speed is SS, desc must comply with 30 spec OR
+ * if speed is not SS, desc must comply with 20 spec.
+ */
+ if ((desc->tag == s.value) &&
+ (((udc->speed == UDC_SPEED_SS) && (desc->spec & UDC_DESC_SPEC_30)) ||
+ ((udc->speed != UDC_SPEED_SS) && (desc->spec & UDC_DESC_SPEC_20)))
+ )
+ {
+ if (desc->len > s.length)
+ len = s.length;
+ else
+ len = desc->len;
+
+ /* copy to tx buffer */
+ memcpy(udc->ctrl_tx_buf, desc->data, len);
+
+ /* flush buffer to main memory before queueing the request */
+ arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len);
+
+ dwc_transfer_request(udc->dwc,
+ 0,
+ DWC_EP_DIRECTION_IN,
+ udc->ctrl_tx_buf,
+ len,
+ NULL,
+ NULL);
+
+ return DWC_SETUP_3_STAGE;
+ }
+ }
+ DBG("\n Did not find matching descriptor: = 0x%x", s.value);
+ }
+ break;
+ case SETUP(DEVICE_READ, GET_CONFIGURATION):
+ {
+ DBG("\n DEVICE_READ : GET_CONFIGURATION");
+
+ if ((s.value == 0) && (s.index == 0) && (s.length == 1)) {
+
+ len = 1;
+
+ /* copy to tx buffer */
+ memcpy(udc->ctrl_tx_buf, &udc->config_selected, len);
+
+ /* flush buffer to main memory before queueing the request */
+ arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len);
+
+ dwc_transfer_request(udc->dwc,
+ 0,
+ DWC_EP_DIRECTION_IN,
+ udc->ctrl_tx_buf,
+ len,
+ NULL,
+ NULL);
+
+ return DWC_SETUP_3_STAGE;
+ }
+ else
+ {
+ ASSERT(0);
+ }
+ }
+ break;
+ case SETUP(DEVICE_WRITE, SET_CONFIGURATION):
+ {
+ DBG("\n DEVICE_WRITE : SET_CONFIGURATION");
+
+ /* select configuration 1 */
+ if (s.value == 1) {
+ struct udc_endpoint *ept;
+ /* enable endpoints */
+ for (ept = udc->ept_list; ept; ept = ept->next) {
+ if (ept->num == 0)
+ continue;
+ else
+ {
+ /* add this ep to dwc ep list */
+ dwc_ep_t ep;
+
+ ep.number = ept->num;
+ ep.dir = ept->in;
+ ep.type = EP_TYPE_BULK; /* the only one supported */
+ ep.max_pkt_size = ept->maxpkt;
+ ep.burst_size = ept->maxburst;
+ ep.zlp = 0; /* TODO: zlp could be made part of ept */
+ ep.trb_count = ept->trb_count;
+ ep.trb = ept->trb;
+
+ dwc_device_add_ep(dwc, ep);
+ }
+ }
+
+ /* now that we have saved the non-control EP details, set config */
+ dwc_device_set_configuration(dwc);
+
+ /* inform client that we are configured. */
+ udc->gadget->notify(udc_dev->gadget, UDC_EVENT_ONLINE);
+
+ udc->config_selected = 1;
+
+ return DWC_SETUP_2_STAGE;
+ }
+ else if (s.value == 0)
+ {
+ /* 0 == de-configure. */
+ udc->config_selected = 0;
+ DBG("\n\n CONFIG = 0 !!!!!!!!!\n\n");
+ return DWC_SETUP_2_STAGE;
+ /* TODO: do proper handling for de-config */
+ }
+ else
+ {
+ ERR("\n CONFIG = %d not supported\n", s.value);
+ ASSERT(0);
+ }
+ }
+ break;
+ case SETUP(DEVICE_WRITE, SET_ADDRESS):
+ {
+ DBG("\n DEVICE_WRITE : SET_ADDRESS");
+
+ dwc_device_set_addr(dwc, s.value);
+ return DWC_SETUP_2_STAGE;
+ }
+ break;
+ case SETUP(INTERFACE_WRITE, SET_INTERFACE):
+ {
+ DBG("\n DEVICE_WRITE : SET_INTERFACE");
+ /* if we ack this everything hangs */
+ /* per spec, STALL is valid if there is not alt func */
+ goto stall;
+ }
+ break;
+ case SETUP(DEVICE_WRITE, SET_FEATURE):
+ {
+ DBG("\n DEVICE_WRITE : SET_FEATURE");
+ goto stall;
+ }
+ break;
+ case SETUP(DEVICE_WRITE, CLEAR_FEATURE):
+ {
+ DBG("\n DEVICE_WRITE : CLEAR_FEATURE");
+ goto stall;
+ }
+ break;
+ case SETUP(ENDPOINT_WRITE, CLEAR_FEATURE):
+ {
+ DBG("\n DEVICE_WRITE : CLEAR_FEATURE");
+ goto stall;
+ }
+ break;
+ case SETUP(DEVICE_WRITE, SET_SEL):
+ {
+ DBG("\n DEVICE_WRITE : SET_SEL");
+
+ /* this is 3-stage write. need to receive data of s.length size. */
+ if (s.length > 0) {
+ dwc_transfer_request(udc->dwc,
+ 0,
+ DWC_EP_DIRECTION_OUT,
+ udc->ctrl_rx_buf,
+ UDC_CONTROL_RX_BUF_SIZE,
+ udc_control_rx_callback,
+ (void *) udc);
+ return DWC_SETUP_3_STAGE;
+ }
+ else
+ {
+ /* length must be non-zero */
+ ASSERT(0);
+ }
+ }
+ break;
+
+ default:
+ ERR("\n Unknown setup req.\n type = 0x%x value = %d index = %d"
+ " length = %d\n", s.type, s.value, s.index, s.length);
+ ASSERT(0);
+ }
+
+stall:
+ ERR("\nSTALL. Unsupported setup req: %s %d %d %d %d %d\n",
+ reqname(s.request), s.type, s.request, s.value, s.index, s.length);
+
+ return DWC_SETUP_ERROR;
+}
+
+/* Callback function called by DWC layer when a request to transfer data
+ * on non-control EP is completed.
+ */
+void udc_request_complete(void *context, uint32_t actual, int status)
+{
+ struct udc_request *req = ((udc_t *) context)->queued_req;
+
+ DBG("\n UDC: udc_request_callback: xferred %d bytes status = %d\n",
+ actual, status);
+
+ /* clear the queued request. */
+ ((udc_t *) context)->queued_req = NULL;
+
+ if (req->complete)
+ {
+ req->complete(req, actual, status);
+ }
+
+ DBG("\n UDC: udc_request_callback: done fastboot callback\n");
+}
+
+/* App interface to queue in data transfer requests for control and data ep */
+int udc_request_queue(struct udc_endpoint *ept, struct udc_request *req)
+{
+ int ret;
+ dwc_dev_t *dwc_dev = udc_dev->dwc;
+
+ /* ensure device is initialized before queuing request */
+ ASSERT(dwc_dev);
+
+ /* if device is not configured, return error */
+ if(udc_dev->config_selected == 0)
+ {
+ return -1;
+ }
+
+ /* only one request at a time is supported.
+ * check if a request is already queued.
+ */
+ if(udc_dev->queued_req)
+ {
+ return -1;
+ }
+
+ DBG("\n udc_request_queue: entry: ep_usb_num = %d", ept->num);
+
+ /* save the queued request. */
+ udc_dev->queued_req = req;
+
+ ret = dwc_transfer_request(dwc_dev,
+ ept->num,
+ ept->in ? DWC_EP_DIRECTION_IN : DWC_EP_DIRECTION_OUT,
+ req->buf,
+ req->length,
+ udc_request_complete,
+ (void *) udc_dev);
+
+ DBG("\n udc_request_queue: exit: ep_usb_num = %d", ept->num);
+
+ return ret;
+}
+
+/* callback function called by dwc layer if any dwc event occurs */
+void udc_dwc_notify(void *context, dwc_notify_event_t event)
+{
+ udc_t *udc = (udc_t *) context;
+
+ switch (event)
+ {
+ case DWC_NOTIFY_EVENT_CONNECTED_LS:
+ udc->speed = UDC_SPEED_LS;
+ break;
+ case DWC_NOTIFY_EVENT_CONNECTED_FS:
+ udc->speed = UDC_SPEED_FS;
+ break;
+ case DWC_NOTIFY_EVENT_CONNECTED_HS:
+ udc->speed = UDC_SPEED_HS;
+ break;
+ case DWC_NOTIFY_EVENT_CONNECTED_SS:
+ udc->speed = UDC_SPEED_SS;
+ break;
+ case DWC_NOTIFY_EVENT_DISCONNECTED:
+ case DWC_NOTIFY_EVENT_OFFLINE:
+ udc->config_selected = 0;
+ if (udc->gadget && udc->gadget->notify)
+ udc->gadget->notify(udc->gadget, UDC_EVENT_OFFLINE);
+ break;
+ default:
+ ASSERT(0);
+ }
+}
+
+
+/******************* Function related to descriptor allocation etc.************/
+
+static struct udc_endpoint *_udc_endpoint_alloc(uint8_t num,
+ uint8_t in,
+ uint16_t max_pkt)
+{
+ struct udc_endpoint *ept;
+ udc_t *udc = udc_dev;
+
+ ept = malloc(sizeof(*ept));
+ ASSERT(ept);
+
+ ept->maxpkt = max_pkt;
+ ept->num = num;
+ ept->in = !!in;
+ ept->maxburst = 4; /* no performance improvement is seen beyond burst size of 4 */
+ ept->trb_count = 66; /* each trb can transfer (16MB - 1). 65 for 1GB transfer + 1 for roundup/zero length pkt. */
+ ept->trb = memalign(lcm(CACHE_LINE, 16), ROUNDUP(ept->trb_count*sizeof(dwc_trb_t), CACHE_LINE)); /* TRB must be aligned to 16 */
+ ASSERT(ept->trb);
+
+ /* push it on top of ept_list */
+ ept->next = udc->ept_list;
+ udc->ept_list = ept;
+
+ return ept;
+}
+
+/* Called to create non-control in/out End Point structures by the APP */
+struct udc_endpoint *udc_endpoint_alloc(unsigned type, unsigned maxpkt)
+{
+ struct udc_endpoint *ept;
+ uint8_t in;
+ uint8_t n;
+ udc_t *udc = udc_dev;
+
+ if (type == UDC_TYPE_BULK_IN) {
+ in = 1;
+ } else if (type == UDC_TYPE_BULK_OUT) {
+ in = 0;
+ } else {
+ return 0;
+ }
+
+ for (n = 1; n < 16; n++) {
+ uint32_t bit = in ? EPT_TX(n) : EPT_RX(n);
+ if (udc->ept_alloc_table & bit)
+ continue;
+ ept = _udc_endpoint_alloc(n, in, maxpkt);
+ if (ept)
+ udc->ept_alloc_table |= bit;
+ return ept;
+ }
+ return 0;
+}
+
+
+/* create config + interface + ep desc for 2.0 */
+static void udc_register_config_desc_usb20(udc_t *udc,
+ struct udc_gadget *gadget)
+{
+ uint8_t *data;
+ uint16_t size;
+ struct udc_descriptor *desc;
+
+ ASSERT(udc);
+ ASSERT(gadget);
+
+ /* create our configuration descriptor */
+
+ /* size is the total size of (config + interface + all EPs) descriptor */
+ size = UDC_DESC_SIZE_CONFIGURATION +
+ UDC_DESC_SIZE_INTERFACE +
+ (gadget->ifc_endpoints*UDC_DESC_SIZE_ENDPOINT);
+
+ desc = udc_descriptor_alloc(TYPE_CONFIGURATION, 0, size, UDC_DESC_SPEC_20);
+
+ data = desc->data;
+
+ /* Config desc */
+ data[0] = 0x09;
+ data[1] = TYPE_CONFIGURATION;
+ data[2] = size;
+ data[3] = size >> 8;
+ data[4] = 0x01; /* number of interfaces */
+ data[5] = 0x01; /* configuration value */
+ data[6] = 0x00; /* configuration string */
+ data[7] = 0xC0; /* attributes: reserved and self-powered set */
+ data[8] = 0x00; /* max power: 0ma since we are self powered */
+ data += 9;
+
+ /* Interface desc */
+ data[0] = 0x09;
+ data[1] = TYPE_INTERFACE;
+ data[2] = 0x00; /* ifc number */
+ data[3] = 0x00; /* alt number */
+ data[4] = gadget->ifc_endpoints;
+ data[5] = gadget->ifc_class;
+ data[6] = gadget->ifc_subclass;
+ data[7] = gadget->ifc_protocol;
+ data[8] = udc_string_desc_alloc(udc, gadget->ifc_string);
+ data += 9;
+
+ for (uint8_t n = 0; n < gadget->ifc_endpoints; n++) {
+ udc_ept_desc_fill(gadget->ept[n], data);
+ data += UDC_DESC_SIZE_ENDPOINT;
+ }
+
+ udc_descriptor_register(udc, desc);
+}
+
+/* create config + interface + ep desc for 3.0 */
+static void udc_register_config_desc_usb30(udc_t *udc,
+ struct udc_gadget *gadget)
+{
+ uint8_t *data;
+ uint16_t size;
+ struct udc_descriptor *desc;
+
+ ASSERT(udc);
+ ASSERT(gadget);
+
+ /* create our configuration descriptor */
+
+ /* size is the total size of (config + interface + all EPs) descriptor */
+ size = UDC_DESC_SIZE_CONFIGURATION +
+ UDC_DESC_SIZE_INTERFACE +
+ (gadget->ifc_endpoints*(UDC_DESC_SIZE_ENDPOINT + UDC_DESC_SIZE_ENDPOINT_COMP));
+
+ desc = udc_descriptor_alloc(TYPE_CONFIGURATION, 0, size, UDC_DESC_SPEC_30);
+
+ data = desc->data;
+
+ /* Config desc */
+ data[0] = 0x09;
+ data[1] = TYPE_CONFIGURATION;
+ data[2] = size;
+ data[3] = size >> 8;
+ data[4] = 0x01; /* number of interfaces */
+ data[5] = 0x01; /* configuration value */
+ data[6] = 0x00; /* configuration string */
+ data[7] = 0xC0; /* attributes: reserved and self-powered set */
+ data[8] = 0x00; /* max power: 0ma since we are self powered */
+ data += 9;
+
+ /* Interface desc */
+ data[0] = 0x09;
+ data[1] = TYPE_INTERFACE;
+ data[2] = 0x00; /* ifc number */
+ data[3] = 0x00; /* alt number */
+ data[4] = gadget->ifc_endpoints;
+ data[5] = gadget->ifc_class;
+ data[6] = gadget->ifc_subclass;
+ data[7] = gadget->ifc_protocol;
+ data[8] = udc_string_desc_alloc(udc, gadget->ifc_string);
+ data += 9;
+
+ for (uint8_t n = 0; n < gadget->ifc_endpoints; n++)
+ {
+ /* fill EP desc */
+ udc_ept_desc_fill(gadget->ept[n], data);
+ data += UDC_DESC_SIZE_ENDPOINT;
+
+ /* fill EP companion desc */
+ udc_ept_comp_desc_fill(gadget->ept[n], data);
+ data += UDC_DESC_SIZE_ENDPOINT_COMP;
+ }
+
+ udc_descriptor_register(udc, desc);
+}
+
+
+static void udc_register_device_desc_usb_20(udc_t *udc,
+ struct udc_device *dev_info)
+{
+ uint8_t *data;
+ struct udc_descriptor *desc;
+
+ /* create our device descriptor */
+ desc = udc_descriptor_alloc(TYPE_DEVICE, 0, 18, UDC_DESC_SPEC_20);
+ data = desc->data;
+
+ /* data 0 and 1 is filled by descriptor alloc routine.
+ * fill in the remaining entries.
+ */
+ data[2] = 0x00; /* usb spec minor rev */
+ data[3] = 0x02; /* usb spec major rev */
+ data[4] = 0x00; /* class */
+ data[5] = 0x00; /* subclass */
+ data[6] = 0x00; /* protocol */
+ data[7] = 0x40; /* max packet size on ept 0 */
+
+ memcpy(data + 8, &dev_info->vendor_id, sizeof(short));
+ memcpy(data + 10, &dev_info->product_id, sizeof(short));
+ memcpy(data + 12, &dev_info->version_id, sizeof(short));
+
+ data[14] = udc_string_desc_alloc(udc, dev_info->manufacturer);
+ data[15] = udc_string_desc_alloc(udc, dev_info->product);
+ data[16] = udc_string_desc_alloc(udc, dev_info->serialno);
+ data[17] = 1; /* number of configurations */
+
+ udc_descriptor_register(udc, desc);
+}
+
+static void udc_register_device_desc_usb_30(udc_t *udc, struct udc_device *dev_info)
+{
+ uint8_t *data;
+ struct udc_descriptor *desc;
+
+ /* create our device descriptor */
+ desc = udc_descriptor_alloc(TYPE_DEVICE, 0, 18, UDC_DESC_SPEC_30);
+ data = desc->data;
+
+ /* data 0 and 1 is filled by descriptor alloc routine.
+ * fill in the remaining entries.
+ */
+ data[2] = 0x00; /* usb spec minor rev */
+ data[3] = 0x03; /* usb spec major rev */
+ data[4] = 0x00; /* class */
+ data[5] = 0x00; /* subclass */
+ data[6] = 0x00; /* protocol */
+ data[7] = 0x09; /* max packet size on ept 0 */
+ memcpy(data + 8, &dev_info->vendor_id, sizeof(short));
+ memcpy(data + 10, &dev_info->product_id, sizeof(short));
+ memcpy(data + 12, &dev_info->version_id, sizeof(short));
+ data[14] = udc_string_desc_alloc(udc, dev_info->manufacturer);
+ data[15] = udc_string_desc_alloc(udc, dev_info->product);
+ data[16] = udc_string_desc_alloc(udc, dev_info->serialno);
+ data[17] = 1; /* number of configurations */
+
+ udc_descriptor_register(udc, desc);
+}
+
+static void udc_register_bos_desc(udc_t *udc)
+{
+ uint8_t *data;
+ struct udc_descriptor *desc;
+
+ /* create our device descriptor */
+ desc = udc_descriptor_alloc(TYPE_BOS, 0, 15, UDC_DESC_SPEC_30); /* 15 is total length of bos + other descriptors inside it */
+ data = desc->data;
+
+ /* data 0 and 1 is filled by descriptor alloc routine.
+ * fill in the remaining entries.
+ */
+ data[0] = 0x05; /* BOS desc len */
+ data[1] = TYPE_BOS; /* BOS desc type */
+ data[2] = 0x0F; /* total len of bos desc and its sub desc */
+ data[3] = 0x00; /* total len of bos desc and its sub desc */
+ data[4] = 0x01; /* num of sub desc inside bos */
+
+ data[5] = 0x0A; /* desc len */
+ data[6] = 0x10; /* Device Capability desc */
+ data[7] = 0x03; /* 3 == SuperSpeed capable */
+ data[8] = 0x00; /* Attribute: latency tolerance msg: No */
+ data[9] = 0x0F; /* Supported Speeds (bit mask): LS, FS, HS, SS */
+ data[10] = 0x00; /* Reserved part of supported wSupportedSpeeds */
+ data[11] = 0x01; /* lowest supported speed with full functionality: FS */
+ data[12] = 0x00; /* U1 device exit latency */
+ data[13] = 0x00; /* U2 device exit latency (lsb) */
+ data[14] = 0x00; /* U2 device exit latency (msb) */
+
+ udc_descriptor_register(udc, desc);
+}
+
+static void udc_register_language_desc(udc_t *udc)
+{
+ /* create and register a language table descriptor */
+ /* language 0x0409 is US English */
+ struct udc_descriptor *desc = udc_descriptor_alloc(TYPE_STRING,
+ 0,
+ 4,
+ UDC_DESC_SPEC_20 | UDC_DESC_SPEC_30);
+ desc->data[2] = 0x09;
+ desc->data[3] = 0x04;
+ udc_descriptor_register(udc, desc);
+}
+
+static void udc_ept_desc_fill(struct udc_endpoint *ept, uint8_t *data)
+{
+ data[0] = 7;
+ data[1] = TYPE_ENDPOINT;
+ data[2] = ept->num | (ept->in ? 0x80 : 0x00);
+ data[3] = 0x02; /* bulk -- the only kind we support */
+ data[4] = ept->maxpkt;
+ data[5] = ept->maxpkt >> 8;
+ data[6] = 0; /* bInterval: must be 0 for bulk. */
+}
+
+static void udc_ept_comp_desc_fill(struct udc_endpoint *ept, uint8_t *data)
+{
+ data[0] = 6; /* bLength */
+ data[1] = TYPE_SS_EP_COMP; /* ep type */
+ data[2] = ept->maxburst; /* maxBurst */
+ data[3] = 0x0; /* maxStreams */
+ data[4] = 0x0; /* wBytesPerInterval */
+ data[5] = 0x0; /* wBytesPerInterval */
+}
+
+static uint8_t udc_string_desc_alloc(udc_t *udc, const char *str)
+{
+ uint32_t len;
+ struct udc_descriptor *desc;
+ uint8_t *data;
+
+ if (udc->next_string_id > 255)
+ return 0;
+
+ if (!str)
+ return 0;
+
+ len = strlen(str);
+ desc = udc_descriptor_alloc(TYPE_STRING,
+ udc->next_string_id,
+ len * 2 + 2,
+ UDC_DESC_SPEC_20 | UDC_DESC_SPEC_30);
+ if (!desc)
+ return 0;
+ udc->next_string_id++;
+
+ /* expand ascii string to utf16 */
+ data = desc->data + 2;
+ while (len-- > 0) {
+ *data++ = *str++;
+ *data++ = 0;
+ }
+
+ udc_descriptor_register(udc, desc);
+ return desc->tag & 0xff;
+}
+
+
+static struct udc_descriptor *udc_descriptor_alloc(uint32_t type,
+ uint32_t num,
+ uint32_t len,
+ udc_desc_spec_t spec)
+{
+ struct udc_descriptor *desc;
+ if ((len > 255) || (len < 2) || (num > 255) || (type > 255))
+ return 0;
+
+ if (!(desc = malloc(sizeof(struct udc_descriptor) + len)))
+ return 0;
+
+ desc->next = 0;
+ desc->tag = (type << 8) | num;
+ desc->len = len;
+ desc->spec = spec;
+
+ /* descriptor data */
+ desc->data[0] = len;
+ desc->data[1] = type;
+
+ return desc;
+}
+
+static void udc_descriptor_register(udc_t *udc, struct udc_descriptor *desc)
+{
+ desc->next = udc->desc_list;
+ udc->desc_list = desc;
+}
+
+
+struct udc_request *udc_request_alloc(void)
+{
+ struct udc_request *req;
+
+ req = malloc(sizeof(*req));
+ ASSERT(req);
+
+ req->buf = 0;
+ req->length = 0;
+ req->complete = NULL;
+ req->context = 0;
+
+ return req;
+}
+
+void udc_request_free(struct udc_request *req)
+{
+ free(req);
+}
+
+void udc_endpoint_free(struct udc_endpoint *ept)
+{
+ /* TODO */
+}
+
+int udc_stop(void)
+{
+ dwc_device_run(udc_dev->dwc, 0);
+
+ return 0;
+}
diff --git a/platform/msm_shared/usb30_udc.h b/platform/msm_shared/usb30_udc.h
new file mode 100644
index 0000000..273bb96
--- /dev/null
+++ b/platform/msm_shared/usb30_udc.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _USB30_UDC_H
+#define _USB30_UDC_H
+
+#include <bits.h>
+#include <usb30_dwc.h>
+#include <usb30_wrapper.h>
+
+#define UDC_DESC_SIZE_CONFIGURATION 9
+#define UDC_DESC_SIZE_INTERFACE 9
+#define UDC_DESC_SIZE_ENDPOINT 7
+#define UDC_DESC_SIZE_ENDPOINT_COMP 6
+
+typedef enum
+{
+ UDC_DESC_SPEC_20 = BIT(0),
+ UDC_DESC_SPEC_30 = BIT(1),
+} udc_desc_spec_t;
+
+typedef enum
+{
+ UDC_SPEED_LS,
+ UDC_SPEED_FS,
+ UDC_SPEED_HS,
+ UDC_SPEED_SS
+} udc_device_speed_t;
+
+typedef struct
+{
+ usb_wrapper_dev_t *wrapper_dev; /* store the wrapper device ptr */
+ dwc_dev_t *dwc; /* store the dwc device ptr */
+
+ struct udc_gadget *gadget; /* store the registered gadget. */
+ struct udc_descriptor *desc_list; /* linked list of all descriptors: device, config, string, language table, bos etc. */
+ struct udc_endpoint *ept_list; /* linked list of all eps */
+ uint32_t ept_alloc_table; /* keep track of which usb EPs are allocated. Initialized to assume EP0 In/OUT are already allocated.*/
+ uint32_t next_string_id; /* keeps track of string id for string descriptor */
+ void *ctrl_rx_buf; /* buffer pointer to receive ctrl data. */
+ void *ctrl_tx_buf; /* buffer pointer to send ctrl data. */
+
+
+ udc_device_speed_t speed; /* keeps track of usb connection speed. */
+ uint8_t config_selected; /* keeps track of the selected configuration */
+
+ struct udc_request *queued_req; /* pointer to the currently queued request. NULL indicates no request is queued. */
+
+} udc_t;
+
+
+struct udc_descriptor {
+ struct udc_descriptor *next;
+ uint16_t tag; /* ((TYPE << 8) | NUM) */
+ uint16_t len; /* total length */
+ udc_desc_spec_t spec; /* bit map of spec that this desc complies with. */
+ uint8_t data[0]; /* descriptor contents. */
+};
+
+struct udc_endpoint {
+ struct udc_endpoint *next;
+ uint8_t num;
+ uint8_t in;
+ uint16_t maxpkt;
+ uint32_t maxburst; /* max pkts that this ep can transfer before waiting for ack. */
+
+ dwc_trb_t *trb; /* pointer to buffer used for TRB chain */
+ uint32_t trb_count; /* size of TRB chain. */
+};
+
+#endif
diff --git a/platform/msm_shared/usb30_wrapper.c b/platform/msm_shared/usb30_wrapper.c
new file mode 100644
index 0000000..f0f271b
--- /dev/null
+++ b/platform/msm_shared/usb30_wrapper.c
@@ -0,0 +1,239 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * The USB 3.0 core wrapper in MSM chipset includes:
+ * - DWC core
+ * - PHY control and configuration
+ * - Configuration and buffers to be provided to the DWC core.
+ *
+ * This file implements the USB30 core wrapper configuration functions.
+ * Core wrapper glues the dwc usb controller into msm chip.
+*/
+
+
+#include <debug.h>
+#include <reg.h>
+#include <malloc.h>
+#include <assert.h>
+#include <board.h>
+#include <pm8x41.h>
+#include <platform/iomap.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+#include <platform/clock.h>
+#include <usb30_wrapper.h>
+#include <usb30_wrapper_hwio.h>
+
+
+/* Configure DBM mode: by-pass or DBM */
+void usb_wrapper_dbm_mode(usb_wrapper_dev_t *dev, dbm_mode_t mode)
+{
+ if (mode == DBM_MODE_BYPASS)
+ {
+ REG_WRITE_FIELD(dev, GENERAL_CFG, DBM_EN, 0);
+ }
+ else
+ {
+ REG_WRITE_FIELD(dev, GENERAL_CFG, DBM_EN, 1);
+ }
+}
+
+/* use config 0: all of RAM1 */
+void usb_wrapper_ram_configure(usb_wrapper_dev_t *dev)
+{
+ REG_WRITE(dev, RAM1_REG, 0x0);
+}
+
+/* reset SS phy */
+void usb_wrapper_ss_phy_reset(usb_wrapper_dev_t *dev)
+{
+ REG_WRITE_FIELD(dev, SS_PHY_CTRL, SS_PHY_RESET, 1);
+
+ /* per HPG */
+ udelay(10);
+
+ REG_WRITE_FIELD(dev, SS_PHY_CTRL, SS_PHY_RESET, 0);
+}
+
+/* configure SS phy as specified in HPG */
+void usb_wrapper_ss_phy_configure(usb_wrapper_dev_t *dev)
+{
+ /* 4.a */
+ REG_WRITE_FIELD(dev, SS_PHY_CTRL, REF_USE_PAD, 1);
+ /* .b */
+ REG_WRITE_FIELD(dev, SS_PHY_CTRL, LANE0_PWR_PRESENT, 1);
+ /* .c */
+ REG_WRITE_FIELD(dev, SS_PHY_CTRL, REF_SS_PHY_EN, 1);
+
+ /* For Aragorn V1, reset value fix is required.*/
+ if ( (board_platform_id() == MSM8974) &&
+ (board_soc_version() < BOARD_SOC_VERSION2))
+ {
+ REG_WRITE_FIELD(dev, SS_PHY_CTRL, SSC_REF_CLK_SEL, 0x108);
+ }
+}
+
+/* configure SS phy electrical params */
+void usb_wrapper_ss_phy_electrical_config(usb_wrapper_dev_t *dev)
+{
+ /* reset value seems to work just fine for now. */
+}
+
+/* Initialize HS phy */
+void usb_wrapper_hs_phy_init(usb_wrapper_dev_t *dev)
+{
+ /* 5.a */
+ REG_WRITE_FIELD(dev, HS_PHY_CTRL, FREECLK_SEL, 0x0);
+
+ /* 5.b */
+ REG_WRITE_FIELD(dev, HS_PHY_CTRL, COMMONONN, 0x1);
+}
+
+/* configure HS phy as specified in HPG */
+void usb_wrapper_hs_phy_configure(usb_wrapper_dev_t *dev)
+{
+ /* 6.a */
+ REG_WRITE(dev, PARAMETER_OVERRIDE_X, 0xD190E4);
+}
+
+void usb_wrapper_workaround_10(usb_wrapper_dev_t *dev)
+{
+ /* 10. */
+ if ( (board_platform_id() == MSM8974) &&
+ (board_soc_version() < BOARD_SOC_VERSION2))
+ {
+ /* TODO: confirm if V1 in HPG only applies to 8974 */
+ REG_WRITE(dev, GENERAL_CFG, 0x78);
+ }
+}
+
+void usb_wrapper_workaround_11(usb_wrapper_dev_t *dev)
+{
+ /*
+ * 11. Apply WA for QCTDD00335018 -
+ * a. Description: Enables the Tx for alt bus mode, powers up the pmos_bias block, and so on; required if manually running the alt bus features.
+ * b. Assert LANE0.TX_ALT_BLOCK (102D) EN_ALT_BUS (bit 7);
+ * c. To be replaced in V2 with other WA (which will be applied during suspend sequence)
+ *
+ */
+
+ /* Not implemented. required if manually running the alt bus features.*/
+}
+
+/* workaround #13 as described in HPG */
+void usb_wrapper_workaround_13(usb_wrapper_dev_t *dev)
+{
+ REG_WRITE_FIELD(dev, SS_PHY_PARAM_CTRL_1, LOS_BIAS, 0x5);
+}
+
+
+/* API to read SS PHY registers */
+uint16_t usb_wrapper_ss_phy_read(usb_wrapper_dev_t *dev, uint16_t addr)
+{
+ uint16_t data;
+
+ /* write address to be read */
+ REG_WRITE(dev, SS_CR_PROTOCOL_DATA_IN, addr);
+
+ /* trigger capture of address in addr reg and wait until done */
+ REG_WRITE(dev, SS_CR_PROTOCOL_CAP_ADDR, 0x1);
+ while(REG_READ(dev, SS_CR_PROTOCOL_CAP_ADDR) & 0x1);
+
+ /* read from referenced register */
+ REG_WRITE(dev, SS_CR_PROTOCOL_READ, 0x1);
+
+ /* wait until read is done */
+ while(REG_READ(dev, SS_CR_PROTOCOL_READ) & 0x1);
+ data = REG_READ(dev, SS_CR_PROTOCOL_DATA_OUT);
+
+ /* TODO: hpg 4.14.2 note: reading ss phy register must be performed twice.
+ * does this whole sequence need to be done twice or just the reading from
+ * data_out??
+ * QCTDD00516153
+ */
+ ASSERT(0);
+
+ return data;
+}
+
+/* API to write to SS PHY registers */
+void usb_wrapper_ss_phy_write(usb_wrapper_dev_t *dev, uint16_t addr, uint16_t data)
+{
+ /* write address to be read */
+ REG_WRITE(dev, SS_CR_PROTOCOL_DATA_IN, addr);
+
+ /* trigger capture of address in addr reg and wait until done */
+ REG_WRITE(dev, SS_CR_PROTOCOL_CAP_ADDR, 0x1);
+ while(REG_READ(dev, SS_CR_PROTOCOL_CAP_ADDR) & 0x1);
+
+ /* write address to be read */
+ REG_WRITE(dev, SS_CR_PROTOCOL_DATA_IN, data);
+
+ /* trigger capture of data in addr reg and wait until done */
+ REG_WRITE(dev, SS_CR_PROTOCOL_CAP_DATA, 0x1);
+ while(REG_READ(dev, SS_CR_PROTOCOL_CAP_DATA) & 0x1);
+
+ /* write to referenced register and wait until done */
+ REG_WRITE(dev, SS_CR_PROTOCOL_WRITE, 0x1);
+ while(REG_READ(dev, SS_CR_PROTOCOL_READ) & 0x1);
+
+ /* TODO: hpg 4.14.2 note: reading ss phy register must be performed twice.
+ * does this whole sequence need to be done twice or just the reading from
+ * data_out??
+ * QCTDD00516153
+ */
+ ASSERT(0);
+}
+
+/* initialize the wrapper core */
+usb_wrapper_dev_t * usb_wrapper_init(usb_wrapper_config_t *config)
+{
+ usb_wrapper_dev_t *wrapper;
+
+ /* create a wrapper device */
+ wrapper = (usb_wrapper_dev_t*) malloc(sizeof(usb_wrapper_dev_t));
+ ASSERT(wrapper);
+
+ /* save qscratch base */
+ wrapper->base = config->qscratch_base;
+
+ /* initialize usb clocks */
+ clock_usb30_init();
+
+ /* enable ss phy clock */
+ pm8x41_diff_clock_ctrl(1);
+
+ /* HPG: section 4.4.1 Control sequence */
+ usb_wrapper_dbm_mode(wrapper, DBM_MODE_BYPASS);
+
+ /* HPG: section 4.4.1: use config 0 - all of RAM1 */
+ usb_wrapper_ram_configure(wrapper);
+
+ return wrapper;
+}
diff --git a/platform/msm_shared/usb30_wrapper.h b/platform/msm_shared/usb30_wrapper.h
new file mode 100644
index 0000000..d274e51
--- /dev/null
+++ b/platform/msm_shared/usb30_wrapper.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _USB30_WRAPPER_H
+#define _USB30_WRAPPER_H
+
+typedef enum
+{
+ DBM_MODE_BYPASS = 0,
+ DBM_MODE_ENABLED
+} dbm_mode_t;
+
+
+typedef struct {
+ void *qscratch_base;
+
+} usb_wrapper_config_t;
+
+typedef struct
+{
+ void *base;
+
+} usb_wrapper_dev_t;
+
+
+usb_wrapper_dev_t *usb_wrapper_init(usb_wrapper_config_t *config);
+
+void usb_wrapper_dbm_mode(usb_wrapper_dev_t *dev, dbm_mode_t mode);
+void usb_wrapper_ram_configure(usb_wrapper_dev_t *dev);
+
+void usb_wrapper_ss_phy_reset(usb_wrapper_dev_t *dev);
+void usb_wrapper_ss_phy_configure(usb_wrapper_dev_t *dev);
+void usb_wrapper_ss_phy_electrical_config(usb_wrapper_dev_t *dev);
+
+void usb_wrapper_hs_phy_init(usb_wrapper_dev_t *dev);
+void usb_wrapper_hs_phy_configure(usb_wrapper_dev_t *dev);
+
+void usb_wrapper_workaround_10(usb_wrapper_dev_t *dev);
+void usb_wrapper_workaround_11(usb_wrapper_dev_t *dev);
+void usb_wrapper_workaround_13(usb_wrapper_dev_t *dev);
+
+#endif
diff --git a/platform/msm_shared/usb30_wrapper_hwio.h b/platform/msm_shared/usb30_wrapper_hwio.h
new file mode 100644
index 0000000..addfed8
--- /dev/null
+++ b/platform/msm_shared/usb30_wrapper_hwio.h
@@ -0,0 +1,726 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __DWC_USB30_QSCRATCH_HWIO_H__
+#define __DWC_USB30_QSCRATCH_HWIO_H__
+
+
+/* Macros to simplify wrapper reg read */
+#define REG_READ(_dev, _reg) readl(HWIO_##_reg##_ADDR(_dev->base))
+#define REG_READI(_dev, _reg, _index) readl(HWIO_##_reg##_ADDR(_dev->base, _index))
+
+/* Macros to simplify wrapper reg write */
+#define REG_WRITE(_dev, _reg, _value) writel(_value, HWIO_##_reg##_ADDR(_dev->base))
+#define REG_WRITEI(_dev, _reg, _index, _value) writel(_value, HWIO_##_reg##_ADDR(_dev->base, _index))
+
+#define REG_BMSK(_reg, _field) HWIO_##_reg##_##_field##_BMSK
+#define REG_SHFT(_reg, _field) HWIO_##_reg##_##_field##_SHFT
+
+/* Macros to simplify wrapper reg field read */
+#define REG_READ_FIELD(_dev, _reg, _field) ((REG_READ(_dev,_reg) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field))
+#define REG_READ_FIELDI(_dev, _reg, _index, _field) ((REG_READI(_dev,_reg, _index) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field))
+
+/* Macros to simplify wrapper reg field write: implementes read/modify/write */
+#define REG_WRITE_FIELD(_dev, _reg, _field, _value) REG_WRITE(_dev, _reg, ((REG_READ(_dev, _reg) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field))))
+#define REG_WRITE_FIELDI(_dev, _reg, _index, _field, _value) REG_WRITEI(_dev, _reg, _index, ((REG_READI(_dev, _reg, _index) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field))))
+
+
+/* The following defines are auto generated. */
+
+/**
+ @brief Auto-generated HWIO interface include file.
+
+ This file contains HWIO register definitions for the following modules:
+ USB30_QSCRATCH
+*/
+/*----------------------------------------------------------------------------
+ * MODULE: USB30_QSCRATCH
+ *--------------------------------------------------------------------------*/
+
+#define USB30_QSCRATCH_REG_BASE (USB30_WRAPPER_BASE + 0x000f8800)
+
+#define HWIO_IPCAT_REG_ADDR(x) ((x) + 0x00000000)
+#define HWIO_IPCAT_REG_RMSK 0xffffffff
+#define HWIO_IPCAT_REG_POR 0x10010001
+#define HWIO_IPCAT_REG_IN(x) \
+ in_dword_masked(HWIO_IPCAT_REG_ADDR(x), HWIO_IPCAT_REG_RMSK)
+#define HWIO_IPCAT_REG_INM(x, m) \
+ in_dword_masked(HWIO_IPCAT_REG_ADDR(x), m)
+#define HWIO_IPCAT_REG_IPCAT_BMSK 0xffffffff
+#define HWIO_IPCAT_REG_IPCAT_SHFT 0x0
+
+#define HWIO_CTRL_REG_ADDR(x) ((x) + 0x00000004)
+#define HWIO_CTRL_REG_RMSK 0x33ff
+#define HWIO_CTRL_REG_POR 0x00000190
+#define HWIO_CTRL_REG_IN(x) \
+ in_dword_masked(HWIO_CTRL_REG_ADDR(x), HWIO_CTRL_REG_RMSK)
+#define HWIO_CTRL_REG_INM(x, m) \
+ in_dword_masked(HWIO_CTRL_REG_ADDR(x), m)
+#define HWIO_CTRL_REG_OUT(x, v) \
+ out_dword(HWIO_CTRL_REG_ADDR(x),v)
+#define HWIO_CTRL_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_CTRL_REG_ADDR(x),m,v,HWIO_CTRL_REG_IN(x))
+#define HWIO_CTRL_REG_HSIC_PLL_CTRL_SUSPEND_BMSK 0x2000
+#define HWIO_CTRL_REG_HSIC_PLL_CTRL_SUSPEND_SHFT 0xd
+#define HWIO_CTRL_REG_HSIC_PLL_CTRL_SLEEP_BMSK 0x1000
+#define HWIO_CTRL_REG_HSIC_PLL_CTRL_SLEEP_SHFT 0xc
+#define HWIO_CTRL_REG_BC_XCVR_SELECT_BMSK 0x300
+#define HWIO_CTRL_REG_BC_XCVR_SELECT_SHFT 0x8
+#define HWIO_CTRL_REG_BC_TERM_SELECT_BMSK 0x80
+#define HWIO_CTRL_REG_BC_TERM_SELECT_SHFT 0x7
+#define HWIO_CTRL_REG_BC_TX_VALID_BMSK 0x40
+#define HWIO_CTRL_REG_BC_TX_VALID_SHFT 0x6
+#define HWIO_CTRL_REG_BC_OPMODE_BMSK 0x30
+#define HWIO_CTRL_REG_BC_OPMODE_SHFT 0x4
+#define HWIO_CTRL_REG_BC_DMPULLDOWN_BMSK 0x8
+#define HWIO_CTRL_REG_BC_DMPULLDOWN_SHFT 0x3
+#define HWIO_CTRL_REG_BC_DPPULLDOWN_BMSK 0x4
+#define HWIO_CTRL_REG_BC_DPPULLDOWN_SHFT 0x2
+#define HWIO_CTRL_REG_BC_IDPULLUP_BMSK 0x2
+#define HWIO_CTRL_REG_BC_IDPULLUP_SHFT 0x1
+#define HWIO_CTRL_REG_BC_SEL_BMSK 0x1
+#define HWIO_CTRL_REG_BC_SEL_SHFT 0x0
+
+#define HWIO_GENERAL_CFG_ADDR(x) ((x) + 0x00000008)
+#define HWIO_GENERAL_CFG_RMSK 0x6
+#define HWIO_GENERAL_CFG_POR 0x00000000
+#define HWIO_GENERAL_CFG_IN(x) \
+ in_dword_masked(HWIO_GENERAL_CFG_ADDR(x), HWIO_GENERAL_CFG_RMSK)
+#define HWIO_GENERAL_CFG_INM(x, m) \
+ in_dword_masked(HWIO_GENERAL_CFG_ADDR(x), m)
+#define HWIO_GENERAL_CFG_OUT(x, v) \
+ out_dword(HWIO_GENERAL_CFG_ADDR(x),v)
+#define HWIO_GENERAL_CFG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_GENERAL_CFG_ADDR(x),m,v,HWIO_GENERAL_CFG_IN(x))
+#define HWIO_GENERAL_CFG_XHCI_REV_BMSK 0x4
+#define HWIO_GENERAL_CFG_XHCI_REV_SHFT 0x2
+#define HWIO_GENERAL_CFG_DBM_EN_BMSK 0x2
+#define HWIO_GENERAL_CFG_DBM_EN_SHFT 0x1
+
+#define HWIO_RAM1_REG_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_RAM1_REG_RMSK 0x7
+#define HWIO_RAM1_REG_POR 0x00000000
+#define HWIO_RAM1_REG_IN(x) \
+ in_dword_masked(HWIO_RAM1_REG_ADDR(x), HWIO_RAM1_REG_RMSK)
+#define HWIO_RAM1_REG_INM(x, m) \
+ in_dword_masked(HWIO_RAM1_REG_ADDR(x), m)
+#define HWIO_RAM1_REG_OUT(x, v) \
+ out_dword(HWIO_RAM1_REG_ADDR(x),v)
+#define HWIO_RAM1_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_RAM1_REG_ADDR(x),m,v,HWIO_RAM1_REG_IN(x))
+#define HWIO_RAM1_REG_RAM13_EN_BMSK 0x4
+#define HWIO_RAM1_REG_RAM13_EN_SHFT 0x2
+#define HWIO_RAM1_REG_RAM12_EN_BMSK 0x2
+#define HWIO_RAM1_REG_RAM12_EN_SHFT 0x1
+#define HWIO_RAM1_REG_RAM11_EN_BMSK 0x1
+#define HWIO_RAM1_REG_RAM11_EN_SHFT 0x0
+
+#define HWIO_HS_PHY_CTRL_ADDR(x) ((x) + 0x00000010)
+#define HWIO_HS_PHY_CTRL_RMSK 0x7ffffff
+#define HWIO_HS_PHY_CTRL_POR 0x072203b2
+#define HWIO_HS_PHY_CTRL_IN(x) \
+ in_dword_masked(HWIO_HS_PHY_CTRL_ADDR(x), HWIO_HS_PHY_CTRL_RMSK)
+#define HWIO_HS_PHY_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_HS_PHY_CTRL_ADDR(x), m)
+#define HWIO_HS_PHY_CTRL_OUT(x, v) \
+ out_dword(HWIO_HS_PHY_CTRL_ADDR(x),v)
+#define HWIO_HS_PHY_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_HS_PHY_CTRL_ADDR(x),m,v,HWIO_HS_PHY_CTRL_IN(x))
+#define HWIO_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_BMSK 0x4000000
+#define HWIO_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_SHFT 0x1a
+#define HWIO_HS_PHY_CTRL_FREECLK_SEL_BMSK 0x2000000
+#define HWIO_HS_PHY_CTRL_FREECLK_SEL_SHFT 0x19
+#define HWIO_HS_PHY_CTRL_DMSEHV_CLAMP_EN_N_BMSK 0x1000000
+#define HWIO_HS_PHY_CTRL_DMSEHV_CLAMP_EN_N_SHFT 0x18
+#define HWIO_HS_PHY_CTRL_USB2_SUSPEND_N_SEL_BMSK 0x800000
+#define HWIO_HS_PHY_CTRL_USB2_SUSPEND_N_SEL_SHFT 0x17
+#define HWIO_HS_PHY_CTRL_USB2_SUSPEND_N_BMSK 0x400000
+#define HWIO_HS_PHY_CTRL_USB2_SUSPEND_N_SHFT 0x16
+#define HWIO_HS_PHY_CTRL_USB2_UTMI_CLK_EN_BMSK 0x200000
+#define HWIO_HS_PHY_CTRL_USB2_UTMI_CLK_EN_SHFT 0x15
+#define HWIO_HS_PHY_CTRL_UTMI_OTG_VBUS_VALID_BMSK 0x100000
+#define HWIO_HS_PHY_CTRL_UTMI_OTG_VBUS_VALID_SHFT 0x14
+#define HWIO_HS_PHY_CTRL_AUTORESUME_BMSK 0x80000
+#define HWIO_HS_PHY_CTRL_AUTORESUME_SHFT 0x13
+#define HWIO_HS_PHY_CTRL_USE_CLKCORE_BMSK 0x40000
+#define HWIO_HS_PHY_CTRL_USE_CLKCORE_SHFT 0x12
+#define HWIO_HS_PHY_CTRL_DPSEHV_CLAMP_EN_N_BMSK 0x20000
+#define HWIO_HS_PHY_CTRL_DPSEHV_CLAMP_EN_N_SHFT 0x11
+#define HWIO_HS_PHY_CTRL_IDHV_INTEN_BMSK 0x10000
+#define HWIO_HS_PHY_CTRL_IDHV_INTEN_SHFT 0x10
+#define HWIO_HS_PHY_CTRL_OTGSESSVLDHV_INTEN_BMSK 0x8000
+#define HWIO_HS_PHY_CTRL_OTGSESSVLDHV_INTEN_SHFT 0xf
+#define HWIO_HS_PHY_CTRL_VBUSVLDEXTSEL0_BMSK 0x4000
+#define HWIO_HS_PHY_CTRL_VBUSVLDEXTSEL0_SHFT 0xe
+#define HWIO_HS_PHY_CTRL_VBUSVLDEXT0_BMSK 0x2000
+#define HWIO_HS_PHY_CTRL_VBUSVLDEXT0_SHFT 0xd
+#define HWIO_HS_PHY_CTRL_OTGDISABLE0_BMSK 0x1000
+#define HWIO_HS_PHY_CTRL_OTGDISABLE0_SHFT 0xc
+#define HWIO_HS_PHY_CTRL_COMMONONN_BMSK 0x800
+#define HWIO_HS_PHY_CTRL_COMMONONN_SHFT 0xb
+#define HWIO_HS_PHY_CTRL_ULPIPOR_BMSK 0x400
+#define HWIO_HS_PHY_CTRL_ULPIPOR_SHFT 0xa
+#define HWIO_HS_PHY_CTRL_ID_HV_CLAMP_EN_N_BMSK 0x200
+#define HWIO_HS_PHY_CTRL_ID_HV_CLAMP_EN_N_SHFT 0x9
+#define HWIO_HS_PHY_CTRL_OTGSESSVLD_HV_CLAMP_EN_N_BMSK 0x100
+#define HWIO_HS_PHY_CTRL_OTGSESSVLD_HV_CLAMP_EN_N_SHFT 0x8
+#define HWIO_HS_PHY_CTRL_CLAMP_EN_N_BMSK 0x80
+#define HWIO_HS_PHY_CTRL_CLAMP_EN_N_SHFT 0x7
+#define HWIO_HS_PHY_CTRL_FSEL_BMSK 0x70
+#define HWIO_HS_PHY_CTRL_FSEL_SHFT 0x4
+#define HWIO_HS_PHY_CTRL_REFCLKOUT_EN_BMSK 0x8
+#define HWIO_HS_PHY_CTRL_REFCLKOUT_EN_SHFT 0x3
+#define HWIO_HS_PHY_CTRL_SIDDQ_BMSK 0x4
+#define HWIO_HS_PHY_CTRL_SIDDQ_SHFT 0x2
+#define HWIO_HS_PHY_CTRL_RETENABLEN_BMSK 0x2
+#define HWIO_HS_PHY_CTRL_RETENABLEN_SHFT 0x1
+#define HWIO_HS_PHY_CTRL_POR_BMSK 0x1
+#define HWIO_HS_PHY_CTRL_POR_SHFT 0x0
+
+#define HWIO_PARAMETER_OVERRIDE_X_ADDR(x) ((x) + 0x00000014)
+#define HWIO_PARAMETER_OVERRIDE_X_RMSK 0x3ffffff
+#define HWIO_PARAMETER_OVERRIDE_X_POR 0x00de06e4
+#define HWIO_PARAMETER_OVERRIDE_X_IN(x) \
+ in_dword_masked(HWIO_PARAMETER_OVERRIDE_X_ADDR(x), HWIO_PARAMETER_OVERRIDE_X_RMSK)
+#define HWIO_PARAMETER_OVERRIDE_X_INM(x, m) \
+ in_dword_masked(HWIO_PARAMETER_OVERRIDE_X_ADDR(x), m)
+#define HWIO_PARAMETER_OVERRIDE_X_OUT(x, v) \
+ out_dword(HWIO_PARAMETER_OVERRIDE_X_ADDR(x),v)
+#define HWIO_PARAMETER_OVERRIDE_X_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_PARAMETER_OVERRIDE_X_ADDR(x),m,v,HWIO_PARAMETER_OVERRIDE_X_IN(x))
+#define HWIO_PARAMETER_OVERRIDE_X_TXFSLSTUNE0_BMSK 0x3c00000
+#define HWIO_PARAMETER_OVERRIDE_X_TXFSLSTUNE0_SHFT 0x16
+#define HWIO_PARAMETER_OVERRIDE_X_TXRESTUNE0_BMSK 0x300000
+#define HWIO_PARAMETER_OVERRIDE_X_TXRESTUNE0_SHFT 0x14
+#define HWIO_PARAMETER_OVERRIDE_X_TXHSXVTUNE0_BMSK 0xc0000
+#define HWIO_PARAMETER_OVERRIDE_X_TXHSXVTUNE0_SHFT 0x12
+#define HWIO_PARAMETER_OVERRIDE_X_TXRISETUNE0_BMSK 0x30000
+#define HWIO_PARAMETER_OVERRIDE_X_TXRISETUNE0_SHFT 0x10
+#define HWIO_PARAMETER_OVERRIDE_X_TXPREEMPAMPTUNE0_BMSK 0xc000
+#define HWIO_PARAMETER_OVERRIDE_X_TXPREEMPAMPTUNE0_SHFT 0xe
+#define HWIO_PARAMETER_OVERRIDE_X_TXPREEMPPULSETUNE0_BMSK 0x2000
+#define HWIO_PARAMETER_OVERRIDE_X_TXPREEMPPULSETUNE0_SHFT 0xd
+#define HWIO_PARAMETER_OVERRIDE_X_TXVREFTUNE0_BMSK 0x1e00
+#define HWIO_PARAMETER_OVERRIDE_X_TXVREFTUNE0_SHFT 0x9
+#define HWIO_PARAMETER_OVERRIDE_X_SQRXTUNE0_BMSK 0x1c0
+#define HWIO_PARAMETER_OVERRIDE_X_SQRXTUNE0_SHFT 0x6
+#define HWIO_PARAMETER_OVERRIDE_X_OTGTUNE0_BMSK 0x38
+#define HWIO_PARAMETER_OVERRIDE_X_OTGTUNE0_SHFT 0x3
+#define HWIO_PARAMETER_OVERRIDE_X_COMPDISTUNE0_BMSK 0x7
+#define HWIO_PARAMETER_OVERRIDE_X_COMPDISTUNE0_SHFT 0x0
+
+#define HWIO_CHARGING_DET_CTRL_ADDR(x) ((x) + 0x00000018)
+#define HWIO_CHARGING_DET_CTRL_RMSK 0x3f
+#define HWIO_CHARGING_DET_CTRL_POR 0x00000000
+#define HWIO_CHARGING_DET_CTRL_IN(x) \
+ in_dword_masked(HWIO_CHARGING_DET_CTRL_ADDR(x), HWIO_CHARGING_DET_CTRL_RMSK)
+#define HWIO_CHARGING_DET_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_CHARGING_DET_CTRL_ADDR(x), m)
+#define HWIO_CHARGING_DET_CTRL_OUT(x, v) \
+ out_dword(HWIO_CHARGING_DET_CTRL_ADDR(x),v)
+#define HWIO_CHARGING_DET_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_CHARGING_DET_CTRL_ADDR(x),m,v,HWIO_CHARGING_DET_CTRL_IN(x))
+#define HWIO_CHARGING_DET_CTRL_VDATDETENB0_BMSK 0x20
+#define HWIO_CHARGING_DET_CTRL_VDATDETENB0_SHFT 0x5
+#define HWIO_CHARGING_DET_CTRL_VDATSRCENB0_BMSK 0x10
+#define HWIO_CHARGING_DET_CTRL_VDATSRCENB0_SHFT 0x4
+#define HWIO_CHARGING_DET_CTRL_VDMSRCAUTO_BMSK 0x8
+#define HWIO_CHARGING_DET_CTRL_VDMSRCAUTO_SHFT 0x3
+#define HWIO_CHARGING_DET_CTRL_CHRGSEL0_BMSK 0x4
+#define HWIO_CHARGING_DET_CTRL_CHRGSEL0_SHFT 0x2
+#define HWIO_CHARGING_DET_CTRL_DCDENB0_BMSK 0x2
+#define HWIO_CHARGING_DET_CTRL_DCDENB0_SHFT 0x1
+#define HWIO_CHARGING_DET_CTRL_ACAENB0_BMSK 0x1
+#define HWIO_CHARGING_DET_CTRL_ACAENB0_SHFT 0x0
+
+#define HWIO_CHARGING_DET_OUTPUT_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_CHARGING_DET_OUTPUT_RMSK 0xfff
+#define HWIO_CHARGING_DET_OUTPUT_POR 0x00000000
+#define HWIO_CHARGING_DET_OUTPUT_IN(x) \
+ in_dword_masked(HWIO_CHARGING_DET_OUTPUT_ADDR(x), HWIO_CHARGING_DET_OUTPUT_RMSK)
+#define HWIO_CHARGING_DET_OUTPUT_INM(x, m) \
+ in_dword_masked(HWIO_CHARGING_DET_OUTPUT_ADDR(x), m)
+#define HWIO_CHARGING_DET_OUTPUT_DMSEHV_BMSK 0x800
+#define HWIO_CHARGING_DET_OUTPUT_DMSEHV_SHFT 0xb
+#define HWIO_CHARGING_DET_OUTPUT_DPSEHV_BMSK 0x400
+#define HWIO_CHARGING_DET_OUTPUT_DPSEHV_SHFT 0xa
+#define HWIO_CHARGING_DET_OUTPUT_LINESTATE_BMSK 0x300
+#define HWIO_CHARGING_DET_OUTPUT_LINESTATE_SHFT 0x8
+#define HWIO_CHARGING_DET_OUTPUT_RIDFLOAT_N_BMSK 0x80
+#define HWIO_CHARGING_DET_OUTPUT_RIDFLOAT_N_SHFT 0x7
+#define HWIO_CHARGING_DET_OUTPUT_RIDFLOAT_BMSK 0x40
+#define HWIO_CHARGING_DET_OUTPUT_RIDFLOAT_SHFT 0x6
+#define HWIO_CHARGING_DET_OUTPUT_RIDGND_BMSK 0x20
+#define HWIO_CHARGING_DET_OUTPUT_RIDGND_SHFT 0x5
+#define HWIO_CHARGING_DET_OUTPUT_RIDC_BMSK 0x10
+#define HWIO_CHARGING_DET_OUTPUT_RIDC_SHFT 0x4
+#define HWIO_CHARGING_DET_OUTPUT_RIDB_BMSK 0x8
+#define HWIO_CHARGING_DET_OUTPUT_RIDB_SHFT 0x3
+#define HWIO_CHARGING_DET_OUTPUT_RIDA_BMSK 0x4
+#define HWIO_CHARGING_DET_OUTPUT_RIDA_SHFT 0x2
+#define HWIO_CHARGING_DET_OUTPUT_DCDOUT_BMSK 0x2
+#define HWIO_CHARGING_DET_OUTPUT_DCDOUT_SHFT 0x1
+#define HWIO_CHARGING_DET_OUTPUT_CHGDET_BMSK 0x1
+#define HWIO_CHARGING_DET_OUTPUT_CHGDET_SHFT 0x0
+
+#define HWIO_ALT_INTERRUPT_EN_ADDR(x) ((x) + 0x00000020)
+#define HWIO_ALT_INTERRUPT_EN_RMSK 0xfff
+#define HWIO_ALT_INTERRUPT_EN_POR 0x00000000
+#define HWIO_ALT_INTERRUPT_EN_IN(x) \
+ in_dword_masked(HWIO_ALT_INTERRUPT_EN_ADDR(x), HWIO_ALT_INTERRUPT_EN_RMSK)
+#define HWIO_ALT_INTERRUPT_EN_INM(x, m) \
+ in_dword_masked(HWIO_ALT_INTERRUPT_EN_ADDR(x), m)
+#define HWIO_ALT_INTERRUPT_EN_OUT(x, v) \
+ out_dword(HWIO_ALT_INTERRUPT_EN_ADDR(x),v)
+#define HWIO_ALT_INTERRUPT_EN_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_ALT_INTERRUPT_EN_ADDR(x),m,v,HWIO_ALT_INTERRUPT_EN_IN(x))
+#define HWIO_ALT_INTERRUPT_EN_DMSEHV_LO_INTEN_BMSK 0x800
+#define HWIO_ALT_INTERRUPT_EN_DMSEHV_LO_INTEN_SHFT 0xb
+#define HWIO_ALT_INTERRUPT_EN_DMSEHV_HI_INTEN_BMSK 0x400
+#define HWIO_ALT_INTERRUPT_EN_DMSEHV_HI_INTEN_SHFT 0xa
+#define HWIO_ALT_INTERRUPT_EN_DPSEHV_LO_INTEN_BMSK 0x200
+#define HWIO_ALT_INTERRUPT_EN_DPSEHV_LO_INTEN_SHFT 0x9
+#define HWIO_ALT_INTERRUPT_EN_DPSEHV_HI_INTEN_BMSK 0x100
+#define HWIO_ALT_INTERRUPT_EN_DPSEHV_HI_INTEN_SHFT 0x8
+#define HWIO_ALT_INTERRUPT_EN_DMSEHV_INTEN_BMSK 0x80
+#define HWIO_ALT_INTERRUPT_EN_DMSEHV_INTEN_SHFT 0x7
+#define HWIO_ALT_INTERRUPT_EN_DPSEHV_INTEN_BMSK 0x40
+#define HWIO_ALT_INTERRUPT_EN_DPSEHV_INTEN_SHFT 0x6
+#define HWIO_ALT_INTERRUPT_EN_RIDFLOATNINTEN_BMSK 0x20
+#define HWIO_ALT_INTERRUPT_EN_RIDFLOATNINTEN_SHFT 0x5
+#define HWIO_ALT_INTERRUPT_EN_CHGDETINTEN_BMSK 0x10
+#define HWIO_ALT_INTERRUPT_EN_CHGDETINTEN_SHFT 0x4
+#define HWIO_ALT_INTERRUPT_EN_DPINTEN_BMSK 0x8
+#define HWIO_ALT_INTERRUPT_EN_DPINTEN_SHFT 0x3
+#define HWIO_ALT_INTERRUPT_EN_DCDINTEN_BMSK 0x4
+#define HWIO_ALT_INTERRUPT_EN_DCDINTEN_SHFT 0x2
+#define HWIO_ALT_INTERRUPT_EN_DMINTEN_BMSK 0x2
+#define HWIO_ALT_INTERRUPT_EN_DMINTEN_SHFT 0x1
+#define HWIO_ALT_INTERRUPT_EN_ACAINTEN_BMSK 0x1
+#define HWIO_ALT_INTERRUPT_EN_ACAINTEN_SHFT 0x0
+
+#define HWIO_HS_PHY_IRQ_STAT_ADDR(x) ((x) + 0x00000024)
+#define HWIO_HS_PHY_IRQ_STAT_RMSK 0xfff
+#define HWIO_HS_PHY_IRQ_STAT_POR 0x00000000
+#define HWIO_HS_PHY_IRQ_STAT_IN(x) \
+ in_dword_masked(HWIO_HS_PHY_IRQ_STAT_ADDR(x), HWIO_HS_PHY_IRQ_STAT_RMSK)
+#define HWIO_HS_PHY_IRQ_STAT_INM(x, m) \
+ in_dword_masked(HWIO_HS_PHY_IRQ_STAT_ADDR(x), m)
+#define HWIO_HS_PHY_IRQ_STAT_OUT(x, v) \
+ out_dword(HWIO_HS_PHY_IRQ_STAT_ADDR(x),v)
+#define HWIO_HS_PHY_IRQ_STAT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_HS_PHY_IRQ_STAT_ADDR(x),m,v,HWIO_HS_PHY_IRQ_STAT_IN(x))
+#define HWIO_HS_PHY_IRQ_STAT_DMSEHV_LO_INTLCH_BMSK 0x800
+#define HWIO_HS_PHY_IRQ_STAT_DMSEHV_LO_INTLCH_SHFT 0xb
+#define HWIO_HS_PHY_IRQ_STAT_DMSEHV_HI_INTLCH_BMSK 0x400
+#define HWIO_HS_PHY_IRQ_STAT_DMSEHV_HI_INTLCH_SHFT 0xa
+#define HWIO_HS_PHY_IRQ_STAT_DPSEHV_LO_INTLCH_BMSK 0x200
+#define HWIO_HS_PHY_IRQ_STAT_DPSEHV_LO_INTLCH_SHFT 0x9
+#define HWIO_HS_PHY_IRQ_STAT_DPSEHV_HI_INTLCH_BMSK 0x100
+#define HWIO_HS_PHY_IRQ_STAT_DPSEHV_HI_INTLCH_SHFT 0x8
+#define HWIO_HS_PHY_IRQ_STAT_DMSEHV_INTLCH_BMSK 0x80
+#define HWIO_HS_PHY_IRQ_STAT_DMSEHV_INTLCH_SHFT 0x7
+#define HWIO_HS_PHY_IRQ_STAT_DPSEHV_INTLCH_BMSK 0x40
+#define HWIO_HS_PHY_IRQ_STAT_DPSEHV_INTLCH_SHFT 0x6
+#define HWIO_HS_PHY_IRQ_STAT_RIDFLOATNINTLCH_BMSK 0x20
+#define HWIO_HS_PHY_IRQ_STAT_RIDFLOATNINTLCH_SHFT 0x5
+#define HWIO_HS_PHY_IRQ_STAT_CHGDETINTLCH_BMSK 0x10
+#define HWIO_HS_PHY_IRQ_STAT_CHGDETINTLCH_SHFT 0x4
+#define HWIO_HS_PHY_IRQ_STAT_DPINTLCH_BMSK 0x8
+#define HWIO_HS_PHY_IRQ_STAT_DPINTLCH_SHFT 0x3
+#define HWIO_HS_PHY_IRQ_STAT_DCDINTLCH_BMSK 0x4
+#define HWIO_HS_PHY_IRQ_STAT_DCDINTLCH_SHFT 0x2
+#define HWIO_HS_PHY_IRQ_STAT_DMINTLCH_BMSK 0x2
+#define HWIO_HS_PHY_IRQ_STAT_DMINTLCH_SHFT 0x1
+#define HWIO_HS_PHY_IRQ_STAT_ACAINTLCH_BMSK 0x1
+#define HWIO_HS_PHY_IRQ_STAT_ACAINTLCH_SHFT 0x0
+
+#define HWIO_CGCTL_REG_ADDR(x) ((x) + 0x00000028)
+#define HWIO_CGCTL_REG_RMSK 0x1f
+#define HWIO_CGCTL_REG_POR 0x00000000
+#define HWIO_CGCTL_REG_IN(x) \
+ in_dword_masked(HWIO_CGCTL_REG_ADDR(x), HWIO_CGCTL_REG_RMSK)
+#define HWIO_CGCTL_REG_INM(x, m) \
+ in_dword_masked(HWIO_CGCTL_REG_ADDR(x), m)
+#define HWIO_CGCTL_REG_OUT(x, v) \
+ out_dword(HWIO_CGCTL_REG_ADDR(x),v)
+#define HWIO_CGCTL_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_CGCTL_REG_ADDR(x),m,v,HWIO_CGCTL_REG_IN(x))
+#define HWIO_CGCTL_REG_RAM13_EN_BMSK 0x10
+#define HWIO_CGCTL_REG_RAM13_EN_SHFT 0x4
+#define HWIO_CGCTL_REG_RAM1112_EN_BMSK 0x8
+#define HWIO_CGCTL_REG_RAM1112_EN_SHFT 0x3
+#define HWIO_CGCTL_REG_BAM_NDP_EN_BMSK 0x4
+#define HWIO_CGCTL_REG_BAM_NDP_EN_SHFT 0x2
+#define HWIO_CGCTL_REG_DBM_FSM_EN_BMSK 0x2
+#define HWIO_CGCTL_REG_DBM_FSM_EN_SHFT 0x1
+#define HWIO_CGCTL_REG_DBM_REG_EN_BMSK 0x1
+#define HWIO_CGCTL_REG_DBM_REG_EN_SHFT 0x0
+
+#define HWIO_DBG_BUS_REG_ADDR(x) ((x) + 0x0000002c)
+#define HWIO_DBG_BUS_REG_RMSK 0xf1ff001
+#define HWIO_DBG_BUS_REG_POR 0x00000000
+#define HWIO_DBG_BUS_REG_IN(x) \
+ in_dword_masked(HWIO_DBG_BUS_REG_ADDR(x), HWIO_DBG_BUS_REG_RMSK)
+#define HWIO_DBG_BUS_REG_INM(x, m) \
+ in_dword_masked(HWIO_DBG_BUS_REG_ADDR(x), m)
+#define HWIO_DBG_BUS_REG_OUT(x, v) \
+ out_dword(HWIO_DBG_BUS_REG_ADDR(x),v)
+#define HWIO_DBG_BUS_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_DBG_BUS_REG_ADDR(x),m,v,HWIO_DBG_BUS_REG_IN(x))
+#define HWIO_DBG_BUS_REG_GENERAL_DBG_SEL_BMSK 0xf000000
+#define HWIO_DBG_BUS_REG_GENERAL_DBG_SEL_SHFT 0x18
+#define HWIO_DBG_BUS_REG_DBM_DBG_EN_BMSK 0x100000
+#define HWIO_DBG_BUS_REG_DBM_DBG_EN_SHFT 0x14
+#define HWIO_DBG_BUS_REG_DBM_DBG_SEL_BMSK 0xff000
+#define HWIO_DBG_BUS_REG_DBM_DBG_SEL_SHFT 0xc
+#define HWIO_DBG_BUS_REG_CTRL_DBG_SEL_BMSK 0x1
+#define HWIO_DBG_BUS_REG_CTRL_DBG_SEL_SHFT 0x0
+
+#define HWIO_SS_PHY_CTRL_ADDR(x) ((x) + 0x00000030)
+#define HWIO_SS_PHY_CTRL_RMSK 0x1fffffff
+#define HWIO_SS_PHY_CTRL_POR 0x10210002
+#define HWIO_SS_PHY_CTRL_IN(x) \
+ in_dword_masked(HWIO_SS_PHY_CTRL_ADDR(x), HWIO_SS_PHY_CTRL_RMSK)
+#define HWIO_SS_PHY_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_SS_PHY_CTRL_ADDR(x), m)
+#define HWIO_SS_PHY_CTRL_OUT(x, v) \
+ out_dword(HWIO_SS_PHY_CTRL_ADDR(x),v)
+#define HWIO_SS_PHY_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_SS_PHY_CTRL_ADDR(x),m,v,HWIO_SS_PHY_CTRL_IN(x))
+#define HWIO_SS_PHY_CTRL_REF_USE_PAD_BMSK 0x10000000
+#define HWIO_SS_PHY_CTRL_REF_USE_PAD_SHFT 0x1c
+#define HWIO_SS_PHY_CTRL_TEST_BURNIN_BMSK 0x8000000
+#define HWIO_SS_PHY_CTRL_TEST_BURNIN_SHFT 0x1b
+#define HWIO_SS_PHY_CTRL_TEST_POWERDOWN_BMSK 0x4000000
+#define HWIO_SS_PHY_CTRL_TEST_POWERDOWN_SHFT 0x1a
+#define HWIO_SS_PHY_CTRL_RTUNE_REQ_BMSK 0x2000000
+#define HWIO_SS_PHY_CTRL_RTUNE_REQ_SHFT 0x19
+#define HWIO_SS_PHY_CTRL_LANE0_PWR_PRESENT_BMSK 0x1000000
+#define HWIO_SS_PHY_CTRL_LANE0_PWR_PRESENT_SHFT 0x18
+#define HWIO_SS_PHY_CTRL_USB2_REF_CLK_EN_BMSK 0x800000
+#define HWIO_SS_PHY_CTRL_USB2_REF_CLK_EN_SHFT 0x17
+#define HWIO_SS_PHY_CTRL_USB2_REF_CLK_SEL_BMSK 0x400000
+#define HWIO_SS_PHY_CTRL_USB2_REF_CLK_SEL_SHFT 0x16
+#define HWIO_SS_PHY_CTRL_SSC_REF_CLK_SEL_BMSK 0x3fe000
+#define HWIO_SS_PHY_CTRL_SSC_REF_CLK_SEL_SHFT 0xd
+#define HWIO_SS_PHY_CTRL_SSC_RANGE_BMSK 0x1c00
+#define HWIO_SS_PHY_CTRL_SSC_RANGE_SHFT 0xa
+#define HWIO_SS_PHY_CTRL_REF_USB2_EN_BMSK 0x200
+#define HWIO_SS_PHY_CTRL_REF_USB2_EN_SHFT 0x9
+#define HWIO_SS_PHY_CTRL_REF_SS_PHY_EN_BMSK 0x100
+#define HWIO_SS_PHY_CTRL_REF_SS_PHY_EN_SHFT 0x8
+#define HWIO_SS_PHY_CTRL_SS_PHY_RESET_BMSK 0x80
+#define HWIO_SS_PHY_CTRL_SS_PHY_RESET_SHFT 0x7
+#define HWIO_SS_PHY_CTRL_MPLL_MULTI_BMSK 0x7f
+#define HWIO_SS_PHY_CTRL_MPLL_MULTI_SHFT 0x0
+
+#define HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_SS_PHY_PARAM_CTRL_1_RMSK 0xffffffff
+#define HWIO_SS_PHY_PARAM_CTRL_1_POR 0x0718154a
+#define HWIO_SS_PHY_PARAM_CTRL_1_IN(x) \
+ in_dword_masked(HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x), HWIO_SS_PHY_PARAM_CTRL_1_RMSK)
+#define HWIO_SS_PHY_PARAM_CTRL_1_INM(x, m) \
+ in_dword_masked(HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x), m)
+#define HWIO_SS_PHY_PARAM_CTRL_1_OUT(x, v) \
+ out_dword(HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x),v)
+#define HWIO_SS_PHY_PARAM_CTRL_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x),m,v,HWIO_SS_PHY_PARAM_CTRL_1_IN(x))
+#define HWIO_SS_PHY_PARAM_CTRL_1_LANE0_TX_TERM_OFFSET_BMSK 0xf8000000
+#define HWIO_SS_PHY_PARAM_CTRL_1_LANE0_TX_TERM_OFFSET_SHFT 0x1b
+#define HWIO_SS_PHY_PARAM_CTRL_1_TX_SWING_FULL_BMSK 0x7f00000
+#define HWIO_SS_PHY_PARAM_CTRL_1_TX_SWING_FULL_SHFT 0x14
+#define HWIO_SS_PHY_PARAM_CTRL_1_TX_DEEMPH_6DB_BMSK 0xfc000
+#define HWIO_SS_PHY_PARAM_CTRL_1_TX_DEEMPH_6DB_SHFT 0xe
+#define HWIO_SS_PHY_PARAM_CTRL_1_TX_DEEMPH_3_5DB_BMSK 0x3f00
+#define HWIO_SS_PHY_PARAM_CTRL_1_TX_DEEMPH_3_5DB_SHFT 0x8
+#define HWIO_SS_PHY_PARAM_CTRL_1_LOS_LEVEL_BMSK 0xf8
+#define HWIO_SS_PHY_PARAM_CTRL_1_LOS_LEVEL_SHFT 0x3
+#define HWIO_SS_PHY_PARAM_CTRL_1_LOS_BIAS_BMSK 0x7
+#define HWIO_SS_PHY_PARAM_CTRL_1_LOS_BIAS_SHFT 0x0
+
+#define HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x) ((x) + 0x00000038)
+#define HWIO_SS_PHY_PARAM_CTRL_2_RMSK 0x37
+#define HWIO_SS_PHY_PARAM_CTRL_2_POR 0x00000004
+#define HWIO_SS_PHY_PARAM_CTRL_2_IN(x) \
+ in_dword_masked(HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x), HWIO_SS_PHY_PARAM_CTRL_2_RMSK)
+#define HWIO_SS_PHY_PARAM_CTRL_2_INM(x, m) \
+ in_dword_masked(HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x), m)
+#define HWIO_SS_PHY_PARAM_CTRL_2_OUT(x, v) \
+ out_dword(HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x),v)
+#define HWIO_SS_PHY_PARAM_CTRL_2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x),m,v,HWIO_SS_PHY_PARAM_CTRL_2_IN(x))
+#define HWIO_SS_PHY_PARAM_CTRL_2_LANE0_TX2RX_LOOPBACK_BMSK 0x20
+#define HWIO_SS_PHY_PARAM_CTRL_2_LANE0_TX2RX_LOOPBACK_SHFT 0x5
+#define HWIO_SS_PHY_PARAM_CTRL_2_LANE0_EXT_PCLK_REQ_BMSK 0x10
+#define HWIO_SS_PHY_PARAM_CTRL_2_LANE0_EXT_PCLK_REQ_SHFT 0x4
+#define HWIO_SS_PHY_PARAM_CTRL_2_TX_VBOOST_LEVEL_BMSK 0x7
+#define HWIO_SS_PHY_PARAM_CTRL_2_TX_VBOOST_LEVEL_SHFT 0x0
+
+#define HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_SS_CR_PROTOCOL_DATA_IN_RMSK 0xffff
+#define HWIO_SS_CR_PROTOCOL_DATA_IN_POR 0x00000000
+#define HWIO_SS_CR_PROTOCOL_DATA_IN_IN(x) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x), HWIO_SS_CR_PROTOCOL_DATA_IN_RMSK)
+#define HWIO_SS_CR_PROTOCOL_DATA_IN_INM(x, m) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x), m)
+#define HWIO_SS_CR_PROTOCOL_DATA_IN_OUT(x, v) \
+ out_dword(HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x),v)
+#define HWIO_SS_CR_PROTOCOL_DATA_IN_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_DATA_IN_IN(x))
+#define HWIO_SS_CR_PROTOCOL_DATA_IN_SS_CR_DATA_IN_REG_BMSK 0xffff
+#define HWIO_SS_CR_PROTOCOL_DATA_IN_SS_CR_DATA_IN_REG_SHFT 0x0
+
+#define HWIO_SS_CR_PROTOCOL_DATA_OUT_ADDR(x) ((x) + 0x00000040)
+#define HWIO_SS_CR_PROTOCOL_DATA_OUT_RMSK 0xffff
+#define HWIO_SS_CR_PROTOCOL_DATA_OUT_POR 0x00000000
+#define HWIO_SS_CR_PROTOCOL_DATA_OUT_IN(x) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_DATA_OUT_ADDR(x), HWIO_SS_CR_PROTOCOL_DATA_OUT_RMSK)
+#define HWIO_SS_CR_PROTOCOL_DATA_OUT_INM(x, m) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_DATA_OUT_ADDR(x), m)
+#define HWIO_SS_CR_PROTOCOL_DATA_OUT_SS_CR_DATA_OUT_REG_BMSK 0xffff
+#define HWIO_SS_CR_PROTOCOL_DATA_OUT_SS_CR_DATA_OUT_REG_SHFT 0x0
+
+#define HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x) ((x) + 0x00000044)
+#define HWIO_SS_CR_PROTOCOL_CAP_ADDR_RMSK 0x1
+#define HWIO_SS_CR_PROTOCOL_CAP_ADDR_POR 0x00000000
+#define HWIO_SS_CR_PROTOCOL_CAP_ADDR_IN(x) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x), HWIO_SS_CR_PROTOCOL_CAP_ADDR_RMSK)
+#define HWIO_SS_CR_PROTOCOL_CAP_ADDR_INM(x, m) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x), m)
+#define HWIO_SS_CR_PROTOCOL_CAP_ADDR_OUT(x, v) \
+ out_dword(HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x),v)
+#define HWIO_SS_CR_PROTOCOL_CAP_ADDR_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_CAP_ADDR_IN(x))
+#define HWIO_SS_CR_PROTOCOL_CAP_ADDR_SS_CR_CAP_ADDR_REG_BMSK 0x1
+#define HWIO_SS_CR_PROTOCOL_CAP_ADDR_SS_CR_CAP_ADDR_REG_SHFT 0x0
+
+#define HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x) ((x) + 0x00000048)
+#define HWIO_SS_CR_PROTOCOL_CAP_DATA_RMSK 0x1
+#define HWIO_SS_CR_PROTOCOL_CAP_DATA_POR 0x00000000
+#define HWIO_SS_CR_PROTOCOL_CAP_DATA_IN(x) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x), HWIO_SS_CR_PROTOCOL_CAP_DATA_RMSK)
+#define HWIO_SS_CR_PROTOCOL_CAP_DATA_INM(x, m) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x), m)
+#define HWIO_SS_CR_PROTOCOL_CAP_DATA_OUT(x, v) \
+ out_dword(HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x),v)
+#define HWIO_SS_CR_PROTOCOL_CAP_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_CAP_DATA_IN(x))
+#define HWIO_SS_CR_PROTOCOL_CAP_DATA_SS_CR_CAP_DATA_REG_BMSK 0x1
+#define HWIO_SS_CR_PROTOCOL_CAP_DATA_SS_CR_CAP_DATA_REG_SHFT 0x0
+
+#define HWIO_SS_CR_PROTOCOL_READ_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_SS_CR_PROTOCOL_READ_RMSK 0x1
+#define HWIO_SS_CR_PROTOCOL_READ_POR 0x00000000
+#define HWIO_SS_CR_PROTOCOL_READ_IN(x) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_READ_ADDR(x), HWIO_SS_CR_PROTOCOL_READ_RMSK)
+#define HWIO_SS_CR_PROTOCOL_READ_INM(x, m) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_READ_ADDR(x), m)
+#define HWIO_SS_CR_PROTOCOL_READ_OUT(x, v) \
+ out_dword(HWIO_SS_CR_PROTOCOL_READ_ADDR(x),v)
+#define HWIO_SS_CR_PROTOCOL_READ_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_READ_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_READ_IN(x))
+#define HWIO_SS_CR_PROTOCOL_READ_SS_CR_READ_REG_BMSK 0x1
+#define HWIO_SS_CR_PROTOCOL_READ_SS_CR_READ_REG_SHFT 0x0
+
+#define HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x) ((x) + 0x00000050)
+#define HWIO_SS_CR_PROTOCOL_WRITE_RMSK 0x1
+#define HWIO_SS_CR_PROTOCOL_WRITE_POR 0x00000000
+#define HWIO_SS_CR_PROTOCOL_WRITE_IN(x) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x), HWIO_SS_CR_PROTOCOL_WRITE_RMSK)
+#define HWIO_SS_CR_PROTOCOL_WRITE_INM(x, m) \
+ in_dword_masked(HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x), m)
+#define HWIO_SS_CR_PROTOCOL_WRITE_OUT(x, v) \
+ out_dword(HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x),v)
+#define HWIO_SS_CR_PROTOCOL_WRITE_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_WRITE_IN(x))
+#define HWIO_SS_CR_PROTOCOL_WRITE_SS_CR_WRITE_REG_BMSK 0x1
+#define HWIO_SS_CR_PROTOCOL_WRITE_SS_CR_WRITE_REG_SHFT 0x0
+
+#define HWIO_SS_STATUS_READ_ONLY_ADDR(x) ((x) + 0x00000054)
+#define HWIO_SS_STATUS_READ_ONLY_RMSK 0x3
+#define HWIO_SS_STATUS_READ_ONLY_POR 0x00000000
+#define HWIO_SS_STATUS_READ_ONLY_IN(x) \
+ in_dword_masked(HWIO_SS_STATUS_READ_ONLY_ADDR(x), HWIO_SS_STATUS_READ_ONLY_RMSK)
+#define HWIO_SS_STATUS_READ_ONLY_INM(x, m) \
+ in_dword_masked(HWIO_SS_STATUS_READ_ONLY_ADDR(x), m)
+#define HWIO_SS_STATUS_READ_ONLY_REF_CLKREQ_N_BMSK 0x2
+#define HWIO_SS_STATUS_READ_ONLY_REF_CLKREQ_N_SHFT 0x1
+#define HWIO_SS_STATUS_READ_ONLY_RTUNE_ACK_BMSK 0x1
+#define HWIO_SS_STATUS_READ_ONLY_RTUNE_ACK_SHFT 0x0
+
+#define HWIO_PWR_EVNT_IRQ_STAT_ADDR(x) ((x) + 0x00000058)
+#define HWIO_PWR_EVNT_IRQ_STAT_RMSK 0x3f
+#define HWIO_PWR_EVNT_IRQ_STAT_POR 0x00000000
+#define HWIO_PWR_EVNT_IRQ_STAT_IN(x) \
+ in_dword_masked(HWIO_PWR_EVNT_IRQ_STAT_ADDR(x), HWIO_PWR_EVNT_IRQ_STAT_RMSK)
+#define HWIO_PWR_EVNT_IRQ_STAT_INM(x, m) \
+ in_dword_masked(HWIO_PWR_EVNT_IRQ_STAT_ADDR(x), m)
+#define HWIO_PWR_EVNT_IRQ_STAT_OUT(x, v) \
+ out_dword(HWIO_PWR_EVNT_IRQ_STAT_ADDR(x),v)
+#define HWIO_PWR_EVNT_IRQ_STAT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_PWR_EVNT_IRQ_STAT_ADDR(x),m,v,HWIO_PWR_EVNT_IRQ_STAT_IN(x))
+#define HWIO_PWR_EVNT_IRQ_STAT_LPM_OUT_L2_IRQ_STAT_BMSK 0x20
+#define HWIO_PWR_EVNT_IRQ_STAT_LPM_OUT_L2_IRQ_STAT_SHFT 0x5
+#define HWIO_PWR_EVNT_IRQ_STAT_LPM_IN_L2_IRQ_STAT_BMSK 0x10
+#define HWIO_PWR_EVNT_IRQ_STAT_LPM_IN_L2_IRQ_STAT_SHFT 0x4
+#define HWIO_PWR_EVNT_IRQ_STAT_POWERDOWN_OUT_P3_IRQ_STAT_BMSK 0x8
+#define HWIO_PWR_EVNT_IRQ_STAT_POWERDOWN_OUT_P3_IRQ_STAT_SHFT 0x3
+#define HWIO_PWR_EVNT_IRQ_STAT_POWERDOWN_IN_P3_IRQ_STAT_BMSK 0x4
+#define HWIO_PWR_EVNT_IRQ_STAT_POWERDOWN_IN_P3_IRQ_STAT_SHFT 0x2
+#define HWIO_PWR_EVNT_IRQ_STAT_CLK_REQ_IN_P3_IRQ_STAT_BMSK 0x2
+#define HWIO_PWR_EVNT_IRQ_STAT_CLK_REQ_IN_P3_IRQ_STAT_SHFT 0x1
+#define HWIO_PWR_EVNT_IRQ_STAT_CLK_GATE_IN_P3_IRQ_STAT_BMSK 0x1
+#define HWIO_PWR_EVNT_IRQ_STAT_CLK_GATE_IN_P3_IRQ_STAT_SHFT 0x0
+
+#define HWIO_PWR_EVNT_IRQ_MASK_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_PWR_EVNT_IRQ_MASK_RMSK 0x3f
+#define HWIO_PWR_EVNT_IRQ_MASK_POR 0x00000000
+#define HWIO_PWR_EVNT_IRQ_MASK_IN(x) \
+ in_dword_masked(HWIO_PWR_EVNT_IRQ_MASK_ADDR(x), HWIO_PWR_EVNT_IRQ_MASK_RMSK)
+#define HWIO_PWR_EVNT_IRQ_MASK_INM(x, m) \
+ in_dword_masked(HWIO_PWR_EVNT_IRQ_MASK_ADDR(x), m)
+#define HWIO_PWR_EVNT_IRQ_MASK_OUT(x, v) \
+ out_dword(HWIO_PWR_EVNT_IRQ_MASK_ADDR(x),v)
+#define HWIO_PWR_EVNT_IRQ_MASK_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_PWR_EVNT_IRQ_MASK_ADDR(x),m,v,HWIO_PWR_EVNT_IRQ_MASK_IN(x))
+#define HWIO_PWR_EVNT_IRQ_MASK_LPM_OUT_L2_IRQ_MASK_BMSK 0x20
+#define HWIO_PWR_EVNT_IRQ_MASK_LPM_OUT_L2_IRQ_MASK_SHFT 0x5
+#define HWIO_PWR_EVNT_IRQ_MASK_LPM_IN_L2_IRQ_MASK_BMSK 0x10
+#define HWIO_PWR_EVNT_IRQ_MASK_LPM_IN_L2_IRQ_MASK_SHFT 0x4
+#define HWIO_PWR_EVNT_IRQ_MASK_POWERDOWN_OUT_P3_IRQ_MASK_BMSK 0x8
+#define HWIO_PWR_EVNT_IRQ_MASK_POWERDOWN_OUT_P3_IRQ_MASK_SHFT 0x3
+#define HWIO_PWR_EVNT_IRQ_MASK_POWERDOWN_IN_P3_IRQ_MASK_BMSK 0x4
+#define HWIO_PWR_EVNT_IRQ_MASK_POWERDOWN_IN_P3_IRQ_MASK_SHFT 0x2
+#define HWIO_PWR_EVNT_IRQ_MASK_CLK_REQ_IN_P3_IRQ_MASK_BMSK 0x2
+#define HWIO_PWR_EVNT_IRQ_MASK_CLK_REQ_IN_P3_IRQ_MASK_SHFT 0x1
+#define HWIO_PWR_EVNT_IRQ_MASK_CLK_GATE_IN_P3_IRQ_MASK_BMSK 0x1
+#define HWIO_PWR_EVNT_IRQ_MASK_CLK_GATE_IN_P3_IRQ_MASK_SHFT 0x0
+
+#define HWIO_HW_SW_EVT_CTRL_REG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_HW_SW_EVT_CTRL_REG_RMSK 0x131
+#define HWIO_HW_SW_EVT_CTRL_REG_POR 0x00000001
+#define HWIO_HW_SW_EVT_CTRL_REG_IN(x) \
+ in_dword_masked(HWIO_HW_SW_EVT_CTRL_REG_ADDR(x), HWIO_HW_SW_EVT_CTRL_REG_RMSK)
+#define HWIO_HW_SW_EVT_CTRL_REG_INM(x, m) \
+ in_dword_masked(HWIO_HW_SW_EVT_CTRL_REG_ADDR(x), m)
+#define HWIO_HW_SW_EVT_CTRL_REG_OUT(x, v) \
+ out_dword(HWIO_HW_SW_EVT_CTRL_REG_ADDR(x),v)
+#define HWIO_HW_SW_EVT_CTRL_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_HW_SW_EVT_CTRL_REG_ADDR(x),m,v,HWIO_HW_SW_EVT_CTRL_REG_IN(x))
+#define HWIO_HW_SW_EVT_CTRL_REG_SW_EVT_MUX_SEL_BMSK 0x100
+#define HWIO_HW_SW_EVT_CTRL_REG_SW_EVT_MUX_SEL_SHFT 0x8
+#define HWIO_HW_SW_EVT_CTRL_REG_HW_EVT_MUX_CTRL_BMSK 0x30
+#define HWIO_HW_SW_EVT_CTRL_REG_HW_EVT_MUX_CTRL_SHFT 0x4
+#define HWIO_HW_SW_EVT_CTRL_REG_EVENT_BUS_HALT_BMSK 0x1
+#define HWIO_HW_SW_EVT_CTRL_REG_EVENT_BUS_HALT_SHFT 0x0
+
+#define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x) ((x) + 0x00000064)
+#define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_RMSK 0x7
+#define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_POR 0x00000000
+#define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_IN(x) \
+ in_dword_masked(HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x), HWIO_VMIDMT_AMEMTYPE_CTRL_REG_RMSK)
+#define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_INM(x, m) \
+ in_dword_masked(HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x), m)
+#define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_OUT(x, v) \
+ out_dword(HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x),v)
+#define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x),m,v,HWIO_VMIDMT_AMEMTYPE_CTRL_REG_IN(x))
+#define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_VMIDMT_AMEMTYPE_VALUE_BMSK 0x7
+#define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_VMIDMT_AMEMTYPE_VALUE_SHFT 0x0
+
+#define HWIO_FLADJ_30MHZ_REG_ADDR(x) ((x) + 0x00000068)
+#define HWIO_FLADJ_30MHZ_REG_RMSK 0x3f
+#define HWIO_FLADJ_30MHZ_REG_POR 0x00000020
+#define HWIO_FLADJ_30MHZ_REG_IN(x) \
+ in_dword_masked(HWIO_FLADJ_30MHZ_REG_ADDR(x), HWIO_FLADJ_30MHZ_REG_RMSK)
+#define HWIO_FLADJ_30MHZ_REG_INM(x, m) \
+ in_dword_masked(HWIO_FLADJ_30MHZ_REG_ADDR(x), m)
+#define HWIO_FLADJ_30MHZ_REG_OUT(x, v) \
+ out_dword(HWIO_FLADJ_30MHZ_REG_ADDR(x),v)
+#define HWIO_FLADJ_30MHZ_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_FLADJ_30MHZ_REG_ADDR(x),m,v,HWIO_FLADJ_30MHZ_REG_IN(x))
+#define HWIO_FLADJ_30MHZ_REG_FLADJ_30MHZ_VALUE_BMSK 0x3f
+#define HWIO_FLADJ_30MHZ_REG_FLADJ_30MHZ_VALUE_SHFT 0x0
+
+#define HWIO_M_AW_USER_REG_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_M_AW_USER_REG_RMSK 0x97f
+#define HWIO_M_AW_USER_REG_POR 0x00000122
+#define HWIO_M_AW_USER_REG_IN(x) \
+ in_dword_masked(HWIO_M_AW_USER_REG_ADDR(x), HWIO_M_AW_USER_REG_RMSK)
+#define HWIO_M_AW_USER_REG_INM(x, m) \
+ in_dword_masked(HWIO_M_AW_USER_REG_ADDR(x), m)
+#define HWIO_M_AW_USER_REG_OUT(x, v) \
+ out_dword(HWIO_M_AW_USER_REG_ADDR(x),v)
+#define HWIO_M_AW_USER_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_M_AW_USER_REG_ADDR(x),m,v,HWIO_M_AW_USER_REG_IN(x))
+#define HWIO_M_AW_USER_REG_AW_MEMTYPE_1_SEL_BMSK 0x800
+#define HWIO_M_AW_USER_REG_AW_MEMTYPE_1_SEL_SHFT 0xb
+#define HWIO_M_AW_USER_REG_AW_NOALLOACATE_BMSK 0x100
+#define HWIO_M_AW_USER_REG_AW_NOALLOACATE_SHFT 0x8
+#define HWIO_M_AW_USER_REG_AW_MEMTYPE_BMSK 0x70
+#define HWIO_M_AW_USER_REG_AW_MEMTYPE_SHFT 0x4
+#define HWIO_M_AW_USER_REG_AW_CACHE_BMSK 0xf
+#define HWIO_M_AW_USER_REG_AW_CACHE_SHFT 0x0
+
+#define HWIO_M_AR_USER_REG_ADDR(x) ((x) + 0x00000070)
+#define HWIO_M_AR_USER_REG_RMSK 0x97f
+#define HWIO_M_AR_USER_REG_POR 0x00000122
+#define HWIO_M_AR_USER_REG_IN(x) \
+ in_dword_masked(HWIO_M_AR_USER_REG_ADDR(x), HWIO_M_AR_USER_REG_RMSK)
+#define HWIO_M_AR_USER_REG_INM(x, m) \
+ in_dword_masked(HWIO_M_AR_USER_REG_ADDR(x), m)
+#define HWIO_M_AR_USER_REG_OUT(x, v) \
+ out_dword(HWIO_M_AR_USER_REG_ADDR(x),v)
+#define HWIO_M_AR_USER_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_M_AR_USER_REG_ADDR(x),m,v,HWIO_M_AR_USER_REG_IN(x))
+#define HWIO_M_AR_USER_REG_AR_MEMTYPE_1_SEL_BMSK 0x800
+#define HWIO_M_AR_USER_REG_AR_MEMTYPE_1_SEL_SHFT 0xb
+#define HWIO_M_AR_USER_REG_AR_NOALLOACATE_BMSK 0x100
+#define HWIO_M_AR_USER_REG_AR_NOALLOACATE_SHFT 0x8
+#define HWIO_M_AR_USER_REG_AR_MEMTYPE_BMSK 0x70
+#define HWIO_M_AR_USER_REG_AR_MEMTYPE_SHFT 0x4
+#define HWIO_M_AR_USER_REG_AR_CACHE_BMSK 0xf
+#define HWIO_M_AR_USER_REG_AR_CACHE_SHFT 0x0
+
+#define HWIO_QSCRTCH_REG_n_ADDR(base,n) ((base) + 0x00000074 + 0x4 * (n))
+#define HWIO_QSCRTCH_REG_n_RMSK 0xffffffff
+#define HWIO_QSCRTCH_REG_n_MAXn 2
+#define HWIO_QSCRTCH_REG_n_POR 0x00000000
+#define HWIO_QSCRTCH_REG_n_INI(base,n) \
+ in_dword_masked(HWIO_QSCRTCH_REG_n_ADDR(base,n), HWIO_QSCRTCH_REG_n_RMSK)
+#define HWIO_QSCRTCH_REG_n_INMI(base,n,mask) \
+ in_dword_masked(HWIO_QSCRTCH_REG_n_ADDR(base,n), mask)
+#define HWIO_QSCRTCH_REG_n_OUTI(base,n,val) \
+ out_dword(HWIO_QSCRTCH_REG_n_ADDR(base,n),val)
+#define HWIO_QSCRTCH_REG_n_OUTMI(base,n,mask,val) \
+ out_dword_masked_ns(HWIO_QSCRTCH_REG_n_ADDR(base,n),mask,val,HWIO_QSCRTCH_REG_n_INI(base,n))
+#define HWIO_QSCRTCH_REG_n_QSCRTCH_REG_BMSK 0xffffffff
+#define HWIO_QSCRTCH_REG_n_QSCRTCH_REG_SHFT 0x0
+
+
+#endif /* __DWC_USB30_QSCRATCH_HWIO_H__ */
diff --git a/project/mpq8092.mk b/project/mpq8092.mk
index 0ad0671..d96b150 100644
--- a/project/mpq8092.mk
+++ b/project/mpq8092.mk
@@ -14,3 +14,4 @@
DEFINES += DEVICE_TREE=1
#DEFINES += MMC_BOOT_BAM=1
#DEFINES += CRYPTO_BAM=1
+ENABLE_THUMB := false
diff --git a/project/msm8226.mk b/project/msm8226.mk
index a4315ad..1e94e03 100644
--- a/project/msm8226.mk
+++ b/project/msm8226.mk
@@ -7,6 +7,7 @@
MODULES += app/aboot
DEBUG := 1
+EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
#DEFINES += WITH_DEBUG_DCC=1
@@ -16,6 +17,11 @@
DEFINES += DEVICE_TREE=1
#DEFINES += MMC_BOOT_BAM=1
DEFINES += CRYPTO_BAM=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x00008000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x02000000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x01e00000
#Disable thumb mode
ENABLE_THUMB := false
diff --git a/project/msm8610.mk b/project/msm8610.mk
index 02676ef..b53a77f 100644
--- a/project/msm8610.mk
+++ b/project/msm8610.mk
@@ -7,6 +7,7 @@
MODULES += app/aboot
DEBUG := 1
+EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
#DEFINES += WITH_DEBUG_DCC=1
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index da3ca04..0de99e1 100644
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -56,7 +56,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(1, 0, BLSP1_UART1_BASE);
+ uart_dm_init(2, 0, BLSP1_UART1_BASE);
#endif
}
diff --git a/target/init.c b/target/init.c
index a2c1d93..57181d4 100644
--- a/target/init.c
+++ b/target/init.c
@@ -140,3 +140,8 @@
__WEAK void target_uninit(void)
{
}
+
+__WEAK bool target_display_panel_node(char *pbuf, uint16_t buf_size)
+{
+ return false;
+}
diff --git a/target/mpq8092/rules.mk b/target/mpq8092/rules.mk
index 0d56e4d..2bf8320 100644
--- a/target/mpq8092/rules.mk
+++ b/target/mpq8092/rules.mk
@@ -9,10 +9,10 @@
BASE_ADDR := 0x00000
-TAGS_ADDR := BASE_ADDR+0x00000100
+TAGS_ADDR := BASE_ADDR+0x01000000
KERNEL_ADDR := BASE_ADDR+0x00008000
-RAMDISK_ADDR := BASE_ADDR+0x01000000
-SCRATCH_ADDR := 0x10000000
+RAMDISK_ADDR := BASE_ADDR+0x01100000
+SCRATCH_ADDR := 0x20000000
MODULES += \
dev/keys \
diff --git a/target/msm8226/include/target/display.h b/target/msm8226/include/target/display.h
index a2cb92d..48b145b 100755
--- a/target/msm8226/include/target/display.h
+++ b/target/msm8226/include/target/display.h
@@ -53,11 +53,6 @@
0, 0, 0, 0, 0, 0
};
-static struct panel_reset_sequence reset_sequence = {
- { 1, 0, 1, }, { 20, 20, 20, }, 2
-};
-
-
/*---------------------------------------------------------------------------*/
/* LDO configuration */
/*---------------------------------------------------------------------------*/
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 9ca4cf5..d33aa95 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -317,9 +317,15 @@
case MSM8926:
case MSM8126:
case MSM8326:
+ case MSM8528:
+ case MSM8628:
+ case MSM8228:
+ case MSM8928:
+ case MSM8128:
board->baseband = BASEBAND_MSM;
break;
case APQ8026:
+ case APQ8028:
board->baseband = BASEBAND_APQ;
break;
default:
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 5b719cc..3cdc936 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -40,6 +40,7 @@
#include <platform/iomap.h>
#include <target/display.h>
+#include "include/panel.h"
#include "include/display_resource.h"
#define HFPLL_LDO_ID 8
@@ -49,7 +50,8 @@
.led1_brightness = (0x0F << 8) | 0xEF,
.max_duty_cycle = 0x01,
.ovp = 0x0,
- .full_current_scale = 0x19
+ .full_current_scale = 0x19,
+ .fdbck = 0x1
};
int target_backlight_ctrl(uint8_t enable)
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index b662767..a116dbe 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -43,6 +43,12 @@
#include <pm8x41.h>
#include <hsusb.h>
#include <kernel/thread.h>
+#include <arch/defines.h>
+#include <stdlib.h>
+#include <scm.h>
+#include <partition_parser.h>
+#include <platform/clock.h>
+#include <platform/timer.h>
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
@@ -169,11 +175,62 @@
{
mmc_put_card_to_sleep(dev);
}
+
+#define SSD_CE_INSTANCE 1
+
+void target_load_ssd_keystore(void)
+{
+ uint64_t ptn;
+ int index;
+ uint64_t size;
+ uint32_t *buffer;
+
+ if (!target_is_ssd_enabled())
+ return;
+
+ index = partition_get_index("ssd");
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0){
+ dprintf(CRITICAL, "Error: ssd partition not found\n");
+ return;
+ }
+
+ size = partition_get_size(index);
+ if (size == 0) {
+ dprintf(CRITICAL, "Error: invalid ssd partition size\n");
+ return;
+ }
+
+ buffer = memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
+ if (!buffer) {
+ dprintf(CRITICAL, "Error: allocating memory for ssd buffer\n");
+ return;
+ }
+
+ if (mmc_read(ptn, buffer, size)) {
+ dprintf(CRITICAL, "Error: cannot read data\n");
+ free(buffer);
+ return;
+ }
+
+ clock_ce_enable(SSD_CE_INSTANCE);
+ scm_protect_keystore(buffer, size);
+ clock_ce_disable(SSD_CE_INSTANCE);
+ free(buffer);
+}
+
/* Do any target specific intialization needed before entering fastboot mode */
void target_fastboot_init(void)
{
/* Set the BOOT_DONE flag in PM8110 */
pm8x41_set_boot_done();
+
+ if (target_is_ssd_enabled()) {
+ clock_ce_enable(SSD_CE_INSTANCE);
+ target_load_ssd_keystore();
+ }
+
}
/* Detect the target type */
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index 80d8316..6e6f412 100644
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -179,33 +179,30 @@
else if (3 == platform_subtype)
mipi_otm8018b_video_wvga_init(&(panel.panel_info));
- panel.clk_func = msm8610_mdss_dsi_panel_clock;
- panel.power_func = msm8610_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_304;
break;
case HW_PLATFORM_MTP:
+ if (0 == platform_subtype)
+ mipi_truly_video_wvga_init(&(panel.panel_info));
+ else
+ mipi_nt35590_video_720p_init(&(panel.panel_info));
+ break;
case HW_PLATFORM_SURF:
mipi_truly_video_wvga_init(&(panel.panel_info));
- panel.clk_func = msm8610_mdss_dsi_panel_clock;
- panel.power_func = msm8610_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_304;
break;
default:
return;
};
+ panel.clk_func = msm8610_mdss_dsi_panel_clock;
+ panel.power_func = msm8610_mipi_panel_power;
+ panel.fb.base = MIPI_FB_ADDR;
+ panel.fb.width = panel.panel_info.xres;
+ panel.fb.height = panel.panel_info.yres;
+ panel.fb.stride = panel.panel_info.xres;
+ panel.fb.bpp = panel.panel_info.bpp;
+ panel.fb.format = FB_FORMAT_RGB888;
+ panel.mdp_rev = MDP_REV_304;
+
if (msm_display_init(&panel))
{
dprintf(CRITICAL, "Display init failed!\n");
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index 6b1c61b..64e9f9e 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -51,6 +51,11 @@
#include <platform/gpio.h>
#include <stdlib.h>
+enum hw_platform_subtype
+{
+ HW_PLATFORM_SUBTYPE_CDP_INTERPOSER = 8,
+};
+
extern bool target_use_signed_kernel(void);
static void set_sdc_power_ctrl();
@@ -339,7 +344,10 @@
/* Display splash screen if enabled */
#if DISPLAY_SPLASH_SCREEN
dprintf(INFO, "Display Init: Start\n");
- display_init();
+ if (board_hardware_subtype() != HW_PLATFORM_SUBTYPE_CDP_INTERPOSER)
+ {
+ display_init();
+ }
dprintf(INFO, "Display Init: Done\n");
#endif
@@ -423,21 +431,6 @@
uint32_t platform_subtype;
platform = board->platform;
- platform_subtype = board->platform_subtype;
-
- /*
- * Look for platform subtype if present, else
- * check for platform type to decide on the
- * baseband type
- */
- switch(platform_subtype) {
- case HW_PLATFORM_SUBTYPE_UNKNOWN:
- case HW_PLATFORM_SUBTYPE_8974PRO_PM8084:
- break;
- default:
- dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
- ASSERT(0);
- };
switch(platform) {
case MSM8974:
@@ -452,12 +445,15 @@
case MSM8974AA:
case MSM8974AB:
case MSM8974AC:
+ case MSMSAMARIUM2:
+ case MSMSAMARIUM9:
board->baseband = BASEBAND_MSM;
break;
case APQ8074:
case APQ8074AA:
case APQ8074AB:
case APQ8074AC:
+ case MSMSAMARIUM0:
board->baseband = BASEBAND_APQ;
break;
default: