Merge "platform/target: ferrum: Add API to detect board info"
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index f41277f..d1695f2 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -90,12 +90,13 @@
return ret;
}
-static int mdss_dsi_panel_power(uint8_t enable)
+static int mdss_dsi_panel_power(uint8_t enable,
+ struct msm_panel_info *pinfo)
{
int ret = NO_ERROR;
if (enable) {
- ret = target_ldo_ctrl(enable);
+ ret = target_ldo_ctrl(enable, pinfo);
if (ret) {
dprintf(CRITICAL, "LDO control enable failed\n");
return ret;
@@ -118,7 +119,7 @@
return ret;
}
- ret = target_ldo_ctrl(enable);
+ ret = target_ldo_ctrl(enable, pinfo);
if (ret) {
dprintf(CRITICAL, "ldo control disable failed\n");
return ret;
@@ -297,12 +298,13 @@
return target_edp_panel_disable();
}
-static int mdss_edp_panel_power(uint8_t enable)
+static int mdss_edp_panel_power(uint8_t enable,
+ struct msm_panel_info *pinfo)
{
int ret = NO_ERROR;
if (enable) {
- ret = target_ldo_ctrl(enable);
+ ret = target_ldo_ctrl(enable, pinfo);
if (ret) {
dprintf(CRITICAL, "LDO control enable failed\n");
return ret;
@@ -322,7 +324,7 @@
return ret;
}
- ret = target_ldo_ctrl(enable);
+ ret = target_ldo_ctrl(enable, pinfo);
if (ret) {
dprintf(CRITICAL, "%s: ldo control disable failed\n", __func__);
return ret;
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 23c2811..3b112e3 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -54,7 +54,7 @@
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo);
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo);
-int target_ldo_ctrl(uint8_t enable);
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo);
int gcdb_display_init(const char *panel_name, uint32_t rev, void *base);
bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size);
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index 241285f..6d02af3 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -271,4 +271,26 @@
#define VIDEO_MODE_CTRL 0x010
#define HS_TIMER_CTRL 0x0BC
+/* HDMI reg addresses */
+#define HDMI_BASE 0xFD922100
+#define REG_HDMI(off) (HDMI_BASE + (off))
+
+#define HDMI_USEC_REFTIMER REG_HDMI(0x208)
+#define HDMI_CTRL REG_HDMI(0x000)
+#define HDMI_HPD_INT_STATUS REG_HDMI(0x250)
+#define HDMI_HPD_INT_CTRL REG_HDMI(0x254)
+#define HDMI_HPD_CTRL REG_HDMI(0x258)
+#define HDMI_PHY_CTRL REG_HDMI(0x2D4)
+#define HDMI_TOTAL REG_HDMI(0x2C0)
+#define HDMI_ACTIVE_H REG_HDMI(0x2B4)
+#define HDMI_ACTIVE_V REG_HDMI(0x2B8)
+#define HDMI_V_TOTAL_F2 REG_HDMI(0x2C4)
+#define HDMI_ACTIVE_V_F2 REG_HDMI(0x2BC)
+#define HDMI_FRAME_CTRL REG_HDMI(0x2C8)
+
+#define HDMI_AVI_INFO0 REG_HDMI(0x06C)
+#define HDMI_AVI_INFO1 REG_HDMI(0x070)
+#define HDMI_AVI_INFO2 REG_HDMI(0x074)
+#define HDMI_AVI_INFO3 REG_HDMI(0x078)
+#define HDMI_INFOFRAME_CTRL0 REG_HDMI(0x02C)
#endif
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index c73b06f..849b294 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -33,23 +33,6 @@
#include <mipi_dsi.h>
#include <boot_stats.h>
-#ifndef DISPLAY_TYPE_HDMI
-static int hdmi_dtv_init(void)
-{
- return 0;
-}
-
-static int hdmi_dtv_on(void)
-{
- return 0;
-}
-
-static int hdmi_msm_turn_on(void)
-{
- return 0;
-}
-#endif
-
static struct msm_fb_panel_data *panel;
extern int lvds_on(struct msm_fb_panel_data *pdata);
@@ -132,7 +115,7 @@
break;
case HDMI_PANEL:
dprintf(INFO, "Config HDMI PANEL.\n");
- ret = hdmi_dtv_init();
+ ret = mdss_hdmi_config(pinfo, &(panel->fb));
if (ret)
goto msm_display_config_out;
break;
@@ -211,11 +194,11 @@
break;
case HDMI_PANEL:
dprintf(INFO, "Turn on HDMI PANEL.\n");
- ret = hdmi_dtv_on();
+ ret = mdss_hdmi_init();
if (ret)
goto msm_display_on_out;
- ret = hdmi_msm_turn_on();
+ ret = mdss_hdmi_on();
if (ret)
goto msm_display_on_out;
break;
@@ -248,7 +231,7 @@
/* Turn on panel */
if (pdata->power_func)
- ret = pdata->power_func(1);
+ ret = pdata->power_func(1, &(panel->panel_info));
if (ret)
goto msm_display_init_out;
@@ -390,7 +373,7 @@
/* Disable panel */
if (panel->power_func)
- ret = panel->power_func(0);
+ ret = panel->power_func(0, pinfo);
msm_display_off_out:
return ret;
diff --git a/platform/msm_shared/hdmi.c b/platform/msm_shared/hdmi.c
deleted file mode 100644
index 422a506..0000000
--- a/platform/msm_shared/hdmi.c
+++ /dev/null
@@ -1,454 +0,0 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of The Linux Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#include <hdmi.h>
-#include <msm_panel.h>
-#include <platform/timer.h>
-#include <platform/clock.h>
-#include <platform/iomap.h>
-
-#define MDP4_OVERLAYPROC1_BASE 0x18000
-#define MDP4_RGB_BASE 0x40000
-#define MDP4_RGB_OFF 0x10000
-
-struct hdmi_disp_mode_timing_type hdmi_timing_default = {
- .height = 1080,
- .hsync_porch_fp = 88,
- .hsync_width = 44,
- .hsync_porch_bp = 148,
- .width = 1920,
- .vsync_porch_fp = 4,
- .vsync_width = 5,
- .vsync_porch_bp = 36,
- .bpp = 24,
-};
-
-static uint8_t hdmi_msm_avi_iframe_lut[][16] = {
-/* 480p60 480i60 576p50 576i50 720p60 720p50 1080p60 1080i60 1080p50
- 1080i50 1080p24 1080p30 1080p25 640x480p 480p60_16_9 576p50_4_3 */
- {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, /*00*/
- {0x18, 0x18, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
- 0x28, 0x28, 0x28, 0x28, 0x18, 0x28, 0x18}, /*01*/
- {0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
- 0x04, 0x04, 0x04, 0x04, 0x88, 0x00, 0x04}, /*02*/
- {0x02, 0x06, 0x11, 0x15, 0x04, 0x13, 0x10, 0x05, 0x1F,
- 0x14, 0x20, 0x22, 0x21, 0x01, 0x03, 0x11}, /*03*/
- {0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*04*/
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*05*/
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*06*/
- {0xE1, 0xE1, 0x41, 0x41, 0xD1, 0xd1, 0x39, 0x39, 0x39,
- 0x39, 0x39, 0x39, 0x39, 0xe1, 0xE1, 0x41}, /*07*/
- {0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x04, 0x04, 0x04,
- 0x04, 0x04, 0x04, 0x04, 0x01, 0x01, 0x02}, /*08*/
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*09*/
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*10*/
- {0xD1, 0xD1, 0xD1, 0xD1, 0x01, 0x01, 0x81, 0x81, 0x81,
- 0x81, 0x81, 0x81, 0x81, 0x81, 0xD1, 0xD1}, /*11*/
- {0x02, 0x02, 0x02, 0x02, 0x05, 0x05, 0x07, 0x07, 0x07,
- 0x07, 0x07, 0x07, 0x07, 0x02, 0x02, 0x02} /*12*/
-};
-
-void hdmi_msm_set_mode(int on)
-{
- uint32_t val = 0;
- if (on) {
- val |= 0x00000003;
- writel(val, HDMI_CTRL);
- } else {
- val &= ~0x00000002;
- writel(val, HDMI_CTRL);
- }
-}
-
-struct hdmi_disp_mode_timing_type *hdmi_common_init_panel_info()
-{
- return &hdmi_timing_default;
-}
-
-void hdmi_set_fb_addr(void *addr)
-{
- hdmi_timing_default.base = addr;
-}
-
-void hdmi_msm_panel_init(struct msm_panel_info *pinfo)
-{
- if (!pinfo)
- return;
-
- pinfo->xres = hdmi_timing_default.width;
- pinfo->yres = hdmi_timing_default.height;
- pinfo->bpp = hdmi_timing_default.bpp;
- pinfo->type = HDMI_PANEL;
-
- pinfo->hdmi.h_back_porch = hdmi_timing_default.hsync_porch_bp;
- pinfo->hdmi.h_front_porch = hdmi_timing_default.hsync_porch_fp;
- pinfo->hdmi.h_pulse_width = hdmi_timing_default.hsync_width;
- pinfo->hdmi.v_back_porch = hdmi_timing_default.vsync_porch_bp;
- pinfo->hdmi.v_front_porch = hdmi_timing_default.vsync_porch_fp;
- pinfo->hdmi.v_pulse_width = hdmi_timing_default.vsync_width;
-}
-
-void hdmi_frame_ctrl_reg()
-{
- uint32_t hdmi_frame_ctrl;
-
- hdmi_frame_ctrl = ((0 << 31) & 0x80000000);
- hdmi_frame_ctrl |= ((0 << 29) & 0x20000000);
- hdmi_frame_ctrl |= ((0 << 28) & 0x10000000);
- writel(hdmi_frame_ctrl, HDMI_FRAME_CTRL);
-}
-
-void hdmi_video_setup()
-{
- uint32_t hsync_total = 0;
- uint32_t vsync_total = 0;
- uint32_t hsync_start = 0;
- uint32_t hsync_end = 0;
- uint32_t vsync_start = 0;
- uint32_t vsync_end = 0;
- uint32_t hvsync_total = 0;
- uint32_t hsync_active = 0;
- uint32_t vsync_active = 0;
- uint32_t hdmi_frame_ctrl = 0;
- uint32_t val;
- struct hdmi_disp_mode_timing_type *hdmi_timing =
- hdmi_common_init_panel_info();
-
- hsync_total = hdmi_timing->width + hdmi_timing->hsync_porch_fp
- + hdmi_timing->hsync_porch_bp + hdmi_timing->hsync_width - 1;
- vsync_total = hdmi_timing->height + hdmi_timing->vsync_porch_fp
- + hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1;
-
- hvsync_total = (vsync_total << 16) & 0x0FFF0000;
- hvsync_total |= (hsync_total << 0) & 0x00000FFF;
- writel(hvsync_total, HDMI_TOTAL);
-
- hsync_start = hdmi_timing->hsync_porch_bp + hdmi_timing->hsync_width;
- hsync_end = (hsync_total + 1) - hdmi_timing->hsync_porch_fp;
- hsync_active = (hsync_end << 16) & 0x0FFF0000;
- hsync_active |= (hsync_start << 0) & 0x00000FFF;
- writel(hsync_active, HDMI_ACTIVE_HSYNC);
-
- vsync_start =
- hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1;
- vsync_end = vsync_total - hdmi_timing->vsync_porch_fp;
- vsync_active = (vsync_end << 16) & 0x0FFF0000;
- vsync_active |= (vsync_start << 0) & 0x00000FFF;
- writel(vsync_active, HDMI_ACTIVE_VSYNC);
-
- writel(0, HDMI_VSYNC_TOTAL_F2);
- writel(0, HDMI_VSYNC_ACTIVE_F2);
- hdmi_frame_ctrl_reg();
-}
-
-void hdmi_msm_avi_info_frame(void)
-{
- /* two header + length + 13 data */
- uint8_t aviInfoFrame[16];
- uint8_t checksum;
- uint32_t sum;
- uint32_t regVal;
- uint8_t i;
- uint8_t mode = 6; //HDMI_VFRMT_1920x1080p60_16_9
-
- /* InfoFrame Type = 82 */
- aviInfoFrame[0] = 0x82;
- /* Version = 2 */
- aviInfoFrame[1] = 2;
- /* Length of AVI InfoFrame = 13 */
- aviInfoFrame[2] = 13;
-
- /* Data Byte 01: 0 Y1 Y0 A0 B1 B0 S1 S0 */
- aviInfoFrame[3] = hdmi_msm_avi_iframe_lut[0][mode];
-
- /* Setting underscan bit */
- aviInfoFrame[3] |= 0x02;
-
- /* Data Byte 02: C1 C0 M1 M0 R3 R2 R1 R0 */
- aviInfoFrame[4] = hdmi_msm_avi_iframe_lut[1][mode];
- /* Data Byte 03: ITC EC2 EC1 EC0 Q1 Q0 SC1 SC0 */
- aviInfoFrame[5] = hdmi_msm_avi_iframe_lut[2][mode];
- /* Data Byte 04: 0 VIC6 VIC5 VIC4 VIC3 VIC2 VIC1 VIC0 */
- aviInfoFrame[6] = hdmi_msm_avi_iframe_lut[3][mode];
- /* Data Byte 05: 0 0 0 0 PR3 PR2 PR1 PR0 */
- aviInfoFrame[7] = hdmi_msm_avi_iframe_lut[4][mode];
- /* Data Byte 06: LSB Line No of End of Top Bar */
- aviInfoFrame[8] = hdmi_msm_avi_iframe_lut[5][mode];
- /* Data Byte 07: MSB Line No of End of Top Bar */
- aviInfoFrame[9] = hdmi_msm_avi_iframe_lut[6][mode];
- /* Data Byte 08: LSB Line No of Start of Bottom Bar */
- aviInfoFrame[10] = hdmi_msm_avi_iframe_lut[7][mode];
- /* Data Byte 09: MSB Line No of Start of Bottom Bar */
- aviInfoFrame[11] = hdmi_msm_avi_iframe_lut[8][mode];
- /* Data Byte 10: LSB Pixel Number of End of Left Bar */
- aviInfoFrame[12] = hdmi_msm_avi_iframe_lut[9][mode];
- /* Data Byte 11: MSB Pixel Number of End of Left Bar */
- aviInfoFrame[13] = hdmi_msm_avi_iframe_lut[10][mode];
- /* Data Byte 12: LSB Pixel Number of Start of Right Bar */
- aviInfoFrame[14] = hdmi_msm_avi_iframe_lut[11][mode];
- /* Data Byte 13: MSB Pixel Number of Start of Right Bar */
- aviInfoFrame[15] = hdmi_msm_avi_iframe_lut[12][mode];
-
- sum = 0;
- for (i = 0; i < 16; i++)
- sum += aviInfoFrame[i];
- sum &= 0xFF;
- sum = 256 - sum;
- checksum = (uint8_t) sum;
-
- regVal = aviInfoFrame[5];
- regVal = regVal << 8 | aviInfoFrame[4];
- regVal = regVal << 8 | aviInfoFrame[3];
- regVal = regVal << 8 | checksum;
- writel(regVal, MSM_HDMI_BASE + 0x006C);
-
- regVal = aviInfoFrame[9];
- regVal = regVal << 8 | aviInfoFrame[8];
- regVal = regVal << 8 | aviInfoFrame[7];
- regVal = regVal << 8 | aviInfoFrame[6];
- writel(regVal, MSM_HDMI_BASE + 0x0070);
-
- regVal = aviInfoFrame[13];
- regVal = regVal << 8 | aviInfoFrame[12];
- regVal = regVal << 8 | aviInfoFrame[11];
- regVal = regVal << 8 | aviInfoFrame[10];
- writel(regVal, MSM_HDMI_BASE + 0x0074);
-
- regVal = aviInfoFrame[1];
- regVal = regVal << 16 | aviInfoFrame[15];
- regVal = regVal << 8 | aviInfoFrame[14];
- writel(regVal, MSM_HDMI_BASE + 0x0078);
-
- /* INFOFRAME_CTRL0[0x002C] */
- /* 0x3 for AVI InfFrame enable (every frame) */
- writel(readl(0x002C) | 0x00000003L, MSM_HDMI_BASE + 0x002C);
-}
-
-void hdmi_app_clk_init(int on)
-{
- uint32_t val = 0;
- if (on) {
- /* Enable hdmi apps clock */
- val = readl(MISC_CC2_REG);
- val = BIT(11);
- writel(val, MISC_CC2_REG);
- udelay(10);
-
- /* Enable hdmi master clock */
- val = readl(MMSS_AHB_EN_REG);
- val |= BIT(14);
- writel(val, MMSS_AHB_EN_REG);
- udelay(10);
-
- /* Enable hdmi slave clock */
- val = readl(MMSS_AHB_EN_REG);
- val |= BIT(4);
- writel(val, MMSS_AHB_EN_REG);
- udelay(10);
- } else {
- // Disable clocks
- val = readl(MISC_CC2_REG);
- val &= ~(BIT(11));
- writel(val, MISC_CC2_REG);
- udelay(10);
- val = readl(MMSS_AHB_EN_REG);
- val &= ~(BIT(14));
- writel(val, MMSS_AHB_EN_REG);
- udelay(10);
- val = readl(MMSS_AHB_EN_REG);
- val &= ~(BIT(4));
- writel(val, MMSS_AHB_EN_REG);
- udelay(10);
- }
-}
-
-int hdmi_msm_turn_on(void)
-{
- uint32_t hotplug_control;
-
- hdmi_msm_set_mode(0);
-
- hdmi_msm_reset_core(); // Reset the core
- hdmi_msm_init_phy();
-
- // Enable USEC REF timer
- writel(0x0001001B, HDMI_USEC_REFTIMER);
-
- // Write 1 to HDMI_CTRL to enable HDMI
- hdmi_msm_set_mode(1);
-
- // Video setup for HDMI
- hdmi_video_setup();
-
- // AVI info setup
- hdmi_msm_avi_info_frame();
-
- return 0;
-}
-
-int hdmi_dtv_init()
-{
- uint32_t hsync_period;
- uint32_t hsync_ctrl;
- uint32_t hsync_start_x;
- uint32_t hsync_end_x;
- uint32_t display_hctl;
- uint32_t vsync_period;
- uint32_t display_v_start;
- uint32_t display_v_end;
- uint32_t hsync_polarity;
- uint32_t vsync_polarity;
- uint32_t data_en_polarity;
- uint32_t ctrl_polarity;
- uint32_t dtv_border_clr = 0;
- uint32_t dtv_underflow_clr = 0;
- uint32_t active_v_start = 0;
- uint32_t active_v_end = 0;
- uint32_t dtv_hsync_skew = 0;
- uint32_t intf, stage, snum, mask, data;
- unsigned char *rgb_base;
- unsigned char *overlay_base;
- uint32_t val;
-
- struct hdmi_disp_mode_timing_type *timing =
- hdmi_common_init_panel_info();
-
- // MDP E config
- writel((unsigned)timing->base, MDP_BASE + 0xb0008); //FB Address
- writel(((timing->height << 16) | timing->width), MDP_BASE + 0xb0004);
- writel((timing->width * timing->bpp / 8), MDP_BASE + 0xb000c);
- writel(0, MDP_BASE + 0xb0010);
-
- writel(DMA_PACK_PATTERN_RGB | DMA_DSTC0G_8BITS | DMA_DSTC1B_8BITS |
- DMA_DSTC2R_8BITS, MDP_BASE + 0xb0000);
- writel(0xff0000, MDP_BASE + 0xb0070);
- writel(0xff0000, MDP_BASE + 0xb0074);
- writel(0xff0000, MDP_BASE + 0xb0078);
-
- // overlay rgb setup RGB2
- rgb_base = MDP_BASE + MDP4_RGB_BASE;
- rgb_base += (MDP4_RGB_OFF * 1);
- writel(((timing->height << 16) | timing->width), rgb_base + 0x0000);
- writel(0x0, rgb_base + 0x0004);
- writel(((timing->height << 16) | timing->width), rgb_base + 0x0008);
- writel(0x0, rgb_base + 0x000c);
- writel(timing->base, rgb_base + 0x0010); //FB address
- writel((timing->width * timing->bpp / 8), rgb_base + 0x0040);
- writel(0x2443F, rgb_base + 0x0050); //format
- writel(0x20001, rgb_base + 0x0054); //pattern
- writel(0x0, rgb_base + 0x0058);
- writel(0x20000000, rgb_base + 0x005c); //phaseX
- writel(0x20000000, rgb_base + 0x0060); // phaseY
-
- // mdp4 mixer setup MDP4_MIXER1
- data = readl(MDP_BASE + 0x10100);
- stage = 9;
- snum = 12;
- mask = 0x0f;
- mask <<= snum;
- stage <<= snum;
- data &= ~mask;
- data |= stage;
- writel(data, MDP_BASE + 0x10100); // Overlay CFG conf
- data = readl(MDP_BASE + 0x10100);
-
- // Overlay cfg
- overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;
-
- writel(0x0, MDP_BASE + 0x0038); //EXternal interface select
-
- data = ((timing->height << 16) | timing->width);
- writel(data, overlay_base + 0x0008);
- writel(timing->base, overlay_base + 0x000c);
- writel((timing->width * timing->bpp / 8), overlay_base + 0x0010);
- writel(0x10, overlay_base + 0x104);
- writel(0x10, overlay_base + 0x124);
- writel(0x10, overlay_base + 0x144);
- writel(0x01, overlay_base + 0x0004); /* directout */
-
- hsync_period =
- timing->hsync_width + timing->hsync_porch_bp + timing->width +
- timing->hsync_porch_fp;
- hsync_ctrl = (hsync_period << 16) | timing->hsync_width;
- hsync_start_x = timing->hsync_width + timing->hsync_porch_bp;
- hsync_end_x = hsync_period - timing->hsync_porch_fp - 1;
- display_hctl = (hsync_end_x << 16) | hsync_start_x;
-
- vsync_period =
- (timing->vsync_width + timing->vsync_porch_bp + timing->height +
- timing->vsync_porch_fp) * hsync_period;
- display_v_start =
- (timing->vsync_width + timing->vsync_porch_bp) * hsync_period;
- display_v_end =
- vsync_period - (timing->vsync_porch_bp * hsync_period) - 1;
-
- dtv_underflow_clr |= 0x80000000;
- hsync_polarity = 0;
- vsync_polarity = 0;
- data_en_polarity = 0;
- ctrl_polarity =
- (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
-
- writel(hsync_ctrl, MDP_BASE + DTV_BASE + 0x4);
- writel(vsync_period, MDP_BASE + DTV_BASE + 0x8);
- writel(timing->vsync_width * hsync_period,
- MDP_BASE + DTV_BASE + 0xc);
- writel(display_hctl, MDP_BASE + DTV_BASE + 0x18);
- writel(display_v_start, MDP_BASE + DTV_BASE + 0x1c);
- writel(0x25a197, MDP_BASE + DTV_BASE + 0x20);
- writel(dtv_border_clr, MDP_BASE + DTV_BASE + 0x40);
- writel(0x8fffffff, MDP_BASE + DTV_BASE + 0x44);
- writel(dtv_hsync_skew, MDP_BASE + DTV_BASE + 0x48);
- writel(ctrl_polarity, MDP_BASE + DTV_BASE + 0x50);
- writel(0x0, MDP_BASE + DTV_BASE + 0x2c);
- writel(active_v_start, MDP_BASE + DTV_BASE + 0x30);
- writel(active_v_end, MDP_BASE + DTV_BASE + 0x38);
-
- /* Enable DTV block */
- writel(0x01, MDP_BASE + DTV_BASE);
-
- /* Flush mixer/pipes configurations */
- val = BIT(1);
- val |= BIT(5);
- writel(val, MDP_BASE + 0x18000);
-
- return 0;
-}
-
-void hdmi_display_shutdown()
-{
- writel(0x0, MDP_BASE + DTV_BASE);
- writel(0x8, MDP_BASE + 0x0038);
- writel(0x0, MDP_BASE + 0x10100);
-}
diff --git a/platform/msm_shared/hdmi_pll_28nm.c b/platform/msm_shared/hdmi_pll_28nm.c
new file mode 100644
index 0000000..02b69bb
--- /dev/null
+++ b/platform/msm_shared/hdmi_pll_28nm.c
@@ -0,0 +1,260 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <reg.h>
+#include <smem.h>
+#include <bits.h>
+#include <msm_panel.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+
+#define HDMI_PHY_BASE 0xFD922500
+#define HDMI_PLL_BASE 0xFD922700
+
+/* hdmi phy registers */
+#define HDMI_PHY_ANA_CFG0 (0x0000)
+#define HDMI_PHY_ANA_CFG1 (0x0004)
+#define HDMI_PHY_ANA_CFG2 (0x0008)
+#define HDMI_PHY_ANA_CFG3 (0x000C)
+#define HDMI_PHY_PD_CTRL0 (0x0010)
+#define HDMI_PHY_PD_CTRL1 (0x0014)
+#define HDMI_PHY_GLB_CFG (0x0018)
+#define HDMI_PHY_DCC_CFG0 (0x001C)
+#define HDMI_PHY_DCC_CFG1 (0x0020)
+#define HDMI_PHY_TXCAL_CFG0 (0x0024)
+#define HDMI_PHY_TXCAL_CFG1 (0x0028)
+#define HDMI_PHY_TXCAL_CFG2 (0x002C)
+#define HDMI_PHY_TXCAL_CFG3 (0x0030)
+#define HDMI_PHY_BIST_CFG0 (0x0034)
+#define HDMI_PHY_BIST_CFG1 (0x0038)
+#define HDMI_PHY_BIST_PATN0 (0x003C)
+#define HDMI_PHY_BIST_PATN1 (0x0040)
+#define HDMI_PHY_BIST_PATN2 (0x0044)
+#define HDMI_PHY_BIST_PATN3 (0x0048)
+#define HDMI_PHY_STATUS (0x005C)
+
+/* hdmi phy unified pll registers */
+#define HDMI_UNI_PLL_REFCLK_CFG (0x0000)
+#define HDMI_UNI_PLL_POSTDIV1_CFG (0x0004)
+#define HDMI_UNI_PLL_CHFPUMP_CFG (0x0008)
+#define HDMI_UNI_PLL_VCOLPF_CFG (0x000C)
+#define HDMI_UNI_PLL_VREG_CFG (0x0010)
+#define HDMI_UNI_PLL_PWRGEN_CFG (0x0014)
+#define HDMI_UNI_PLL_GLB_CFG (0x0020)
+#define HDMI_UNI_PLL_POSTDIV2_CFG (0x0024)
+#define HDMI_UNI_PLL_POSTDIV3_CFG (0x0028)
+#define HDMI_UNI_PLL_LPFR_CFG (0x002C)
+#define HDMI_UNI_PLL_LPFC1_CFG (0x0030)
+#define HDMI_UNI_PLL_LPFC2_CFG (0x0034)
+#define HDMI_UNI_PLL_SDM_CFG0 (0x0038)
+#define HDMI_UNI_PLL_SDM_CFG1 (0x003C)
+#define HDMI_UNI_PLL_SDM_CFG2 (0x0040)
+#define HDMI_UNI_PLL_SDM_CFG3 (0x0044)
+#define HDMI_UNI_PLL_SDM_CFG4 (0x0048)
+#define HDMI_UNI_PLL_SSC_CFG0 (0x004C)
+#define HDMI_UNI_PLL_SSC_CFG1 (0x0050)
+#define HDMI_UNI_PLL_SSC_CFG2 (0x0054)
+#define HDMI_UNI_PLL_SSC_CFG3 (0x0058)
+#define HDMI_UNI_PLL_LKDET_CFG0 (0x005C)
+#define HDMI_UNI_PLL_LKDET_CFG1 (0x0060)
+#define HDMI_UNI_PLL_LKDET_CFG2 (0x0064)
+#define HDMI_UNI_PLL_CAL_CFG0 (0x006C)
+#define HDMI_UNI_PLL_CAL_CFG1 (0x0070)
+#define HDMI_UNI_PLL_CAL_CFG2 (0x0074)
+#define HDMI_UNI_PLL_CAL_CFG3 (0x0078)
+#define HDMI_UNI_PLL_CAL_CFG4 (0x007C)
+#define HDMI_UNI_PLL_CAL_CFG5 (0x0080)
+#define HDMI_UNI_PLL_CAL_CFG6 (0x0084)
+#define HDMI_UNI_PLL_CAL_CFG7 (0x0088)
+#define HDMI_UNI_PLL_CAL_CFG8 (0x008C)
+#define HDMI_UNI_PLL_CAL_CFG9 (0x0090)
+#define HDMI_UNI_PLL_CAL_CFG10 (0x0094)
+#define HDMI_UNI_PLL_CAL_CFG11 (0x0098)
+#define HDMI_UNI_PLL_STATUS (0x00C0)
+
+#define SW_RESET BIT(2)
+#define SW_RESET_PLL BIT(0)
+
+void hdmi_phy_reset(void)
+{
+ uint32_t phy_reset_polarity = 0x0;
+ uint32_t pll_reset_polarity = 0x0;
+ uint32_t val;
+
+ val = readl(HDMI_PHY_CTRL);
+
+ phy_reset_polarity = val >> 3 & 0x1;
+ pll_reset_polarity = val >> 1 & 0x1;
+
+ if (phy_reset_polarity == 0)
+ writel(val | SW_RESET, HDMI_PHY_CTRL);
+ else
+ writel(val & (~SW_RESET), HDMI_PHY_CTRL);
+
+ if (pll_reset_polarity == 0)
+ writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);
+ else
+ writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);
+
+ if (phy_reset_polarity == 0)
+ writel(val & (~SW_RESET), HDMI_PHY_CTRL);
+ else
+ writel(val | SW_RESET, HDMI_PHY_CTRL);
+
+ if (pll_reset_polarity == 0)
+ writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);
+ else
+ writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);
+}
+
+void hdmi_phy_init(void)
+{
+ writel(0x1B, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG0);
+ writel(0xF2, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG1);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_CFG0);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN0);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN1);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN2);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN3);
+
+ writel(0x20, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL1);
+}
+
+void hdmi_phy_powerdown(void)
+{
+ writel(0x7F, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL0);
+}
+
+static uint32_t hdmi_poll_status(uint32_t addr)
+{
+ uint32_t count;
+
+ for (count = 20; count > 0; count--) {
+ if (readl(addr) & 0x1) {
+ return NO_ERROR;
+ }
+ udelay(100);
+ }
+ return ERR_TIMED_OUT;
+}
+
+void hdmi_vco_disable(void)
+{
+ writel(0x0, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ udelay(5);
+ writel(0x0, HDMI_PHY_BASE + HDMI_PHY_GLB_CFG);
+}
+
+int hdmi_vco_enable(void)
+{
+ /* Global Enable */
+ writel(0x81, HDMI_PHY_BASE + HDMI_PHY_GLB_CFG);
+ /* Power up power gen */
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL0);
+ udelay(350);
+
+ /* PLL Power-Up */
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ udelay(5);
+
+ /* Power up PLL LDO */
+ writel(0x03, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ udelay(350);
+
+ /* PLL Power-Up */
+ writel(0x0F, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ udelay(350);
+
+ /* poll for PLL ready status */
+ if (hdmi_poll_status(HDMI_PLL_BASE + HDMI_UNI_PLL_STATUS)) {
+ dprintf(CRITICAL, "%s: hdmi phy pll failed to Lock\n",
+ __func__);
+ hdmi_vco_disable();
+ return ERROR;
+ }
+
+ udelay(350);
+ /* poll for PHY ready status */
+ if (hdmi_poll_status(HDMI_PHY_BASE + HDMI_PHY_STATUS)) {
+ dprintf(CRITICAL, "%s: hdmi phy failed to Lock\n",
+ __func__);
+ hdmi_vco_disable();
+ return ERROR;
+ }
+
+ return NO_ERROR;
+}
+
+uint32_t hdmi_pll_config(void)
+{
+ writel(0x81, HDMI_PHY_BASE + HDMI_PHY_GLB_CFG);
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_REFCLK_CFG);
+ writel(0x19, HDMI_PLL_BASE + HDMI_UNI_PLL_VCOLPF_CFG);
+ writel(0x0E, HDMI_PLL_BASE + HDMI_UNI_PLL_LPFR_CFG);
+ writel(0x20, HDMI_PLL_BASE + HDMI_UNI_PLL_LPFC1_CFG);
+ writel(0x0D, HDMI_PLL_BASE + HDMI_UNI_PLL_LPFC2_CFG);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG0);
+ writel(0x52, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG1);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG2);
+ writel(0x56, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG3);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG4);
+ writel(0x10, HDMI_PLL_BASE + HDMI_UNI_PLL_LKDET_CFG0);
+ writel(0x1A, HDMI_PLL_BASE + HDMI_UNI_PLL_LKDET_CFG1);
+ writel(0x05, HDMI_PLL_BASE + HDMI_UNI_PLL_LKDET_CFG2);
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_POSTDIV1_CFG);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_POSTDIV2_CFG);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_POSTDIV3_CFG);
+ writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG2);
+ writel(0x60, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG8);
+ writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG9);
+ writel(0xE6, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG10);
+ writel(0x02, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG11);
+ writel(0x1F, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL0);
+ udelay(50);
+
+ writel(0x0F, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG);
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL1);
+ writel(0x10, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG2);
+ writel(0xDB, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG0);
+ writel(0x43, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG1);
+ writel(0x02, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG2);
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG3);
+ writel(0x04, HDMI_PLL_BASE + HDMI_UNI_PLL_VREG_CFG);
+ writel(0xD0, HDMI_PHY_BASE + HDMI_PHY_DCC_CFG0);
+ writel(0x1A, HDMI_PHY_BASE + HDMI_PHY_DCC_CFG1);
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG0);
+ writel(0x00, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG1);
+ writel(0x02, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG2);
+ writel(0x05, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG3);
+ udelay(200);
+}
+
diff --git a/platform/msm_shared/include/hdmi.h b/platform/msm_shared/include/hdmi.h
deleted file mode 100644
index 0b4fd5b..0000000
--- a/platform/msm_shared/include/hdmi.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of The Linux Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef __PLATFORM_MSM_SHARED_HDMI_H
-#define __PLATFORM_MSM_SHARED_HDMI_H
-
-#include <reg.h>
-#include <debug.h>
-#include <bits.h>
-#include <dev/fbcon.h>
-#include <target/display.h>
-
-#define MDP_GET_PACK_PATTERN(a,x,y,z,bit) (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
-#define DMA_PACK_ALIGN_LSB 0
-#define DMA_PACK_PATTERN_RGB \
- (MDP_GET_PACK_PATTERN(0,CLR_R,CLR_G,CLR_B,2)<<8)
-#define CLR_G 0x0
-#define CLR_B 0x1
-#define CLR_R 0x2
-#define DMA_DSTC0G_8BITS (BIT(1)|BIT(0))
-#define DMA_DSTC1B_8BITS (BIT(3)|BIT(2))
-#define DMA_DSTC2R_8BITS (BIT(5)|BIT(4))
-#define BM(m, l) (((((uint32_t)-1) << (31-m)) >> (31-m+l)) << l)
-#define BVAL(m, l, val) (((val) << l) & BM(m, l))
-#define CC(m, n) (BVAL((m+1), m, 0x2) * !!(n))
-#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
- (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
- | BVAL(s_msb, s_lsb, s))
-
-extern int pm8901_mpp_enable();
-extern int pm8901_vs_enable();
-extern int pm8058_ldo_set_voltage();
-extern int pm8058_vreg_enable();
-void gpio_tlmm_config(uint32_t gpio, uint8_t func,
- uint8_t dir, uint8_t pull,
- uint8_t drvstr, uint32_t enable);
-
-int hdmi_dtv_on(void);
-void hdmi_msm_set_mode(int on);
-void hdmi_msm_init_phy(void);
-void hdmi_display_shutdown(void);
-void hdmi_msm_reset_core(void);
-void hdmi_set_fb_addr(void *addr);
-
-struct hdmi_disp_mode_timing_type {
- uint32_t height;
- uint32_t hsync_porch_fp;
- uint32_t hsync_width;
- uint32_t hsync_porch_bp;
- uint32_t width;
- uint32_t vsync_porch_fp;
- uint32_t vsync_width;
- uint32_t vsync_porch_bp;
- uint32_t refresh_rate;
- uint32_t bpp;
- void *base;
-};
-#endif /* __PLATFORM_MSM_SHARED_HDMI_H */
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index ac389ee..8ade9c8 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -97,6 +97,7 @@
#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x12500)
#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x12700)
+#define MDP_INTF_3_TIMING_ENGINE_EN REG_MDP(0x12B00)
#define MDP_CTL_0_BASE REG_MDP(0x600)
#define MDP_CTL_1_BASE REG_MDP(0x700)
@@ -117,6 +118,7 @@
#define MDP_INTF_0_BASE REG_MDP(0x12500)
#define MDP_INTF_1_BASE REG_MDP(0x12700)
#define MDP_INTF_2_BASE REG_MDP(0x12900)
+#define MDP_INTF_3_BASE REG_MDP(0x12B00)
#define MDP_HSYNC_CTL 0x08
#define MDP_VSYNC_PERIOD_F0 0x0C
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 8b7af72..6befefd 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -199,6 +199,7 @@
/* Select pipe type for handoff */
uint32_t pipe_type;
char lowpowerstop;
+ char lcd_reg_en;
struct lcd_panel_info lcd;
struct lcdc_panel_info lcdc;
@@ -224,7 +225,7 @@
int rotate;
/* function entry chain */
- int (*power_func) (int enable);
+ int (*power_func) (int enable, struct msm_panel_info *);
int (*clk_func) (int enable);
int (*bl_func) (int enable);
int (*pll_clk_func) (int enable, struct msm_panel_info *);
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index 2cde8ea..b53b3d8 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -211,3 +211,18 @@
{
return NO_ERROR;
}
+
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+ return NO_ERROR;
+}
+
+int mdss_hdmi_on(void)
+{
+ return NO_ERROR;
+}
+
+int mdss_hdmi_off(void)
+{
+ return NO_ERROR;
+}
diff --git a/platform/msm_shared/mdp4.c b/platform/msm_shared/mdp4.c
index 7b7c0cf..705819e 100644
--- a/platform/msm_shared/mdp4.c
+++ b/platform/msm_shared/mdp4.c
@@ -423,3 +423,18 @@
{
return NO_ERROR;
}
+
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+ return NO_ERROR;
+}
+
+int mdss_hdmi_on(void)
+{
+ return NO_ERROR;
+}
+
+int mdss_hdmi_off(void)
+{
+ return NO_ERROR;
+}
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 6e8fea4..801f7b6 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -602,6 +602,41 @@
return 0;
}
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+ int ret = NO_ERROR;
+ struct lcdc_panel_info *lcdc = NULL;
+ uint32_t left_pipe, right_pipe;
+
+ mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE);
+ mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
+
+ mdp_clk_gating_ctrl();
+ mdss_vbif_setup();
+
+ mdss_smp_setup(pinfo, left_pipe, right_pipe);
+
+ mdss_qos_remapper_setup();
+
+ mdss_source_pipe_config(fb, pinfo, left_pipe);
+ if (pinfo->lcdc.dual_pipe)
+ mdss_source_pipe_config(fb, pinfo, right_pipe);
+
+ mdss_layer_mixer_setup(fb, pinfo);
+
+ if (pinfo->lcdc.dual_pipe)
+ writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP);
+ else
+ writel(0x40, MDP_CTL_0_BASE + CTL_TOP);
+
+ writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL);
+ writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
+ writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
+ writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
+
+ return 0;
+}
+
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
@@ -730,6 +765,18 @@
return NO_ERROR;
}
+int mdss_hdmi_on(struct msm_panel_info *pinfo)
+{
+ uint32_t ctl0_reg_val, ctl1_reg_val;
+
+ mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
+ writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
+
+ writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
+
+ return NO_ERROR;
+}
+
int mdp_edp_off(void)
{
if (!target_cont_splash_screen()) {
diff --git a/platform/msm_shared/mdss_hdmi.c b/platform/msm_shared/mdss_hdmi.c
new file mode 100644
index 0000000..c6a5bab
--- /dev/null
+++ b/platform/msm_shared/mdss_hdmi.c
@@ -0,0 +1,315 @@
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <err.h>
+#include <debug.h>
+#include <reg.h>
+#include <msm_panel.h>
+#include <platform/timer.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+static struct msm_fb_panel_data panel;
+
+/* AVI INFOFRAME DATA */
+#define NUM_MODES_AVI 20
+#define AVI_MAX_DATA_BYTES 13
+
+enum {
+ DATA_BYTE_1,
+ DATA_BYTE_2,
+ DATA_BYTE_3,
+ DATA_BYTE_4,
+ DATA_BYTE_5,
+ DATA_BYTE_6,
+ DATA_BYTE_7,
+ DATA_BYTE_8,
+ DATA_BYTE_9,
+ DATA_BYTE_10,
+ DATA_BYTE_11,
+ DATA_BYTE_12,
+ DATA_BYTE_13,
+};
+
+#define IFRAME_PACKET_OFFSET 0x80
+/*
+ * InfoFrame Type Code:
+ * 0x0 - Reserved
+ * 0x1 - Vendor Specific
+ * 0x2 - Auxiliary Video Information
+ * 0x3 - Source Product Description
+ * 0x4 - AUDIO
+ * 0x5 - MPEG Source
+ * 0x6 - NTSC VBI
+ * 0x7 - 0xFF - Reserved
+ */
+#define AVI_IFRAME_TYPE 0x2
+#define AVI_IFRAME_VERSION 0x2
+#define LEFT_SHIFT_BYTE(x) ((x) << 8)
+#define LEFT_SHIFT_WORD(x) ((x) << 16)
+#define LEFT_SHIFT_24BITS(x) ((x) << 24)
+
+struct mdss_hdmi_timing_info {
+ uint32_t video_format;
+ uint32_t active_h;
+ uint32_t front_porch_h;
+ uint32_t pulse_width_h;
+ uint32_t back_porch_h;
+ uint32_t active_low_h;
+ uint32_t active_v;
+ uint32_t front_porch_v;
+ uint32_t pulse_width_v;
+ uint32_t back_porch_v;
+ uint32_t active_low_v;
+ /* Must divide by 1000 to get the actual frequency in MHZ */
+ uint32_t pixel_freq;
+ /* Must divide by 1000 to get the actual frequency in HZ */
+ uint32_t refresh_rate;
+ uint32_t interlaced;
+ uint32_t supported;
+};
+
+#define HDMI_VFRMT_1280x720p60_16_9 4
+#define HDMI_RESOLUTION_DATA HDMI_VFRMT_1280x720p60_16_9##_TIMING
+
+#define HDMI_VFRMT_1280x720p60_16_9_TIMING \
+ {HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, \
+ 720, 5, 5, 20, false, 74250, 60000, false, true}
+
+uint32_t mdss_hdmi_avi_info_db[] = {
+ 0x10, 0x28, 0x00, 0x04, 0x00, 0x00, 0x00,
+ 0xD1, 0x02, 0x00, 0x00, 0x01, 0x05};
+
+static int mdss_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ return target_hdmi_panel_clock(enable, pinfo);
+}
+
+static int mdss_hdmi_enable_power(uint8_t enable)
+{
+ int ret = NO_ERROR;
+
+ ret = target_ldo_ctrl(enable);
+ if (ret) {
+ dprintf(CRITICAL, "LDO control enable failed\n");
+ return ret;
+ }
+
+ ret = target_hdmi_regulator_ctrl(enable);
+ if (ret) {
+ dprintf(CRITICAL, "hdmi regulator control enable failed\n");
+ return ret;
+ }
+
+ dprintf(SPEW, "HDMI Panel power %s done\n", enable ? "on" : "off");
+
+ return ret;
+}
+
+static void mdss_hdmi_set_mode(bool on)
+{
+ uint32_t val = 0;
+
+ if (on) {
+ val = 0x3;
+ writel(val, HDMI_CTRL);
+ } else {
+ writel(val, HDMI_CTRL);
+ }
+}
+
+static void mdss_hdmi_panel_init(struct msm_panel_info *pinfo)
+{
+ struct mdss_hdmi_timing_info tinfo = HDMI_RESOLUTION_DATA;
+
+ if (!pinfo)
+ return;
+
+ pinfo->xres = tinfo.active_h;
+ pinfo->yres = tinfo.active_v;
+ pinfo->bpp = 24;
+ pinfo->type = HDMI_PANEL;
+
+ pinfo->lcdc.h_back_porch = tinfo.back_porch_h;
+ pinfo->lcdc.h_front_porch = tinfo.front_porch_h;
+ pinfo->lcdc.h_pulse_width = tinfo.pulse_width_h;
+ pinfo->lcdc.v_back_porch = tinfo.back_porch_v;
+ pinfo->lcdc.v_front_porch = tinfo.front_porch_v;
+ pinfo->lcdc.v_pulse_width = tinfo.pulse_width_v;
+
+ pinfo->lcdc.hsync_skew = 0;
+ pinfo->lcdc.xres_pad = 0;
+ pinfo->lcdc.yres_pad = 0;
+ pinfo->lcdc.dual_pipe = 0;
+}
+
+void mdss_hdmi_display_init(uint32_t rev, void *base)
+{
+ mdss_hdmi_panel_init(&(panel.panel_info));
+
+ panel.clk_func = mdss_hdmi_panel_clock;
+ panel.power_func = mdss_hdmi_enable_power;
+
+ panel.fb.width = panel.panel_info.xres;
+ panel.fb.height = panel.panel_info.yres;
+ panel.fb.stride = panel.panel_info.xres;
+ panel.fb.bpp = panel.panel_info.bpp;
+ panel.fb.format = FB_FORMAT_RGB888;
+
+ panel.fb.base = base;
+ panel.mdp_rev = rev;
+
+ msm_display_init(&panel);
+}
+
+static int mdss_hdmi_video_setup(void)
+{
+ uint32_t total_v = 0;
+ uint32_t total_h = 0;
+ uint32_t start_h = 0;
+ uint32_t end_h = 0;
+ uint32_t start_v = 0;
+ uint32_t end_v = 0;
+
+ struct mdss_hdmi_timing_info tinfo = HDMI_RESOLUTION_DATA;
+
+ total_h = tinfo.active_h + tinfo.front_porch_h +
+ tinfo.back_porch_h + tinfo.pulse_width_h - 1;
+ total_v = tinfo.active_v + tinfo.front_porch_v +
+ tinfo.back_porch_v + tinfo.pulse_width_v - 1;
+ if (((total_v << 16) & 0xE0000000) || (total_h & 0xFFFFE000)) {
+ dprintf(CRITICAL,
+ "%s: total v=%d or h=%d is larger than supported\n",
+ __func__, total_v, total_h);
+ return ERROR;
+ }
+ writel((total_v << 16) | (total_h << 0), HDMI_TOTAL);
+
+ start_h = tinfo.back_porch_h + tinfo.pulse_width_h;
+ end_h = (total_h + 1) - tinfo.front_porch_h;
+ if (((end_h << 16) & 0xE0000000) || (start_h & 0xFFFFE000)) {
+ dprintf(CRITICAL,
+ "%s: end_h=%d or start_h=%d is larger than supported\n",
+ __func__, end_h, start_h);
+ return ERROR;
+ }
+ writel((end_h << 16) | (start_h << 0), HDMI_ACTIVE_H);
+
+ start_v = tinfo.back_porch_v + tinfo.pulse_width_v - 1;
+ end_v = total_v - tinfo.front_porch_v;
+ if (((end_v << 16) & 0xE0000000) || (start_v & 0xFFFFE000)) {
+ dprintf(CRITICAL,
+ "%s: end_v=%d or start_v=%d is larger than supported\n",
+ __func__, end_v, start_v);
+ return ERROR;
+ }
+ writel((end_v << 16) | (start_v << 0), HDMI_ACTIVE_V);
+
+ if (tinfo.interlaced) {
+ writel((total_v + 1) << 0, HDMI_V_TOTAL_F2);
+ writel(((end_v + 1) << 16) | ((start_v + 1) << 0),
+ HDMI_ACTIVE_V_F2);
+ } else {
+ writel(0, HDMI_V_TOTAL_F2);
+ writel(0, HDMI_ACTIVE_V_F2);
+ }
+
+ writel(((tinfo.interlaced << 31) & 0x80000000) |
+ ((tinfo.active_low_h << 29) & 0x20000000) |
+ ((tinfo.active_low_v << 28) & 0x10000000), HDMI_FRAME_CTRL);
+
+ return 0;
+}
+
+void mdss_hdmi_avi_info_frame(void)
+{
+ uint32_t sum;
+ uint32_t reg_val;
+ uint8_t checksum;
+ uint32_t i;
+
+ sum = IFRAME_PACKET_OFFSET + AVI_IFRAME_TYPE +
+ AVI_IFRAME_VERSION + AVI_MAX_DATA_BYTES;
+
+ for (i = 0; i < AVI_MAX_DATA_BYTES; i++)
+ sum += mdss_hdmi_avi_info_db[i];
+
+ sum &= 0xFF;
+ sum = 256 - sum;
+ checksum = (uint8_t) sum;
+
+ reg_val = checksum |
+ LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_1]) |
+ LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[DATA_BYTE_2]) |
+ LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[DATA_BYTE_3]);
+ writel(reg_val, HDMI_AVI_INFO0);
+
+ reg_val = mdss_hdmi_avi_info_db[DATA_BYTE_4] |
+ LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_5]) |
+ LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[DATA_BYTE_6]) |
+ LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[DATA_BYTE_7]);
+ writel(reg_val, HDMI_AVI_INFO1);
+
+ reg_val = mdss_hdmi_avi_info_db[DATA_BYTE_8] |
+ LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_9]) |
+ LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[DATA_BYTE_10]) |
+ LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[DATA_BYTE_11]);
+ writel(reg_val, HDMI_AVI_INFO2);
+
+ reg_val = mdss_hdmi_avi_info_db[DATA_BYTE_12] |
+ LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_13]) |
+ LEFT_SHIFT_24BITS(AVI_IFRAME_VERSION);
+ writel(reg_val, HDMI_AVI_INFO3);
+
+ /* AVI InfFrame enable (every frame) */
+ writel(readl(HDMI_INFOFRAME_CTRL0) | BIT(1) | BIT(0),
+ HDMI_INFOFRAME_CTRL0);
+}
+
+int mdss_hdmi_init(void)
+{
+ uint32_t hotplug_control;
+
+ mdss_hdmi_set_mode(false);
+
+ hdmi_phy_init();
+
+ // Enable USEC REF timer
+ writel(0x0001001B, HDMI_USEC_REFTIMER);
+
+ // Video setup for HDMI
+ mdss_hdmi_video_setup();
+
+ // AVI info setup
+ mdss_hdmi_avi_info_frame();
+
+ // Write 1 to HDMI_CTRL to enable HDMI
+ mdss_hdmi_set_mode(true);
+
+ return 0;
+}
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index f5f6dce..bf6d42e 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -224,6 +224,8 @@
$(LOCAL_DIR)/mipi_dsi.o \
$(LOCAL_DIR)/mipi_dsi_phy.o \
$(LOCAL_DIR)/mipi_dsi_autopll.o \
+ $(LOCAL_DIR)/mdss_hdmi.o \
+ $(LOCAL_DIR)/hdmi_pll_28nm.o \
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
diff --git a/project/msm8226.mk b/project/msm8226.mk
index a165ec1..0476594 100644
--- a/project/msm8226.mk
+++ b/project/msm8226.mk
@@ -6,7 +6,12 @@
MODULES += app/aboot
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
+
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
diff --git a/target/apq8084/include/target/display.h b/target/apq8084/include/target/display.h
index 8d6eb87..38baf50 100644
--- a/target/apq8084/include/target/display.h
+++ b/target/apq8084/include/target/display.h
@@ -106,6 +106,7 @@
#define DISPLAY_CMDLINE_PREFIX " mdss_mdp.panel="
#define MIPI_FB_ADDR 0x03200000
+#define HDMI_FB_ADDR 0x03200000
#define MIPI_HSYNC_PULSE_WIDTH 12
#define MIPI_HSYNC_BACK_PORCH_DCLK 32
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index 88b0a9a..a67e97f 100755
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -233,7 +233,7 @@
return NO_ERROR;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ldocounter = 0;
uint32_t pm8x41_ldo_base = 0x13F00;
@@ -289,6 +289,77 @@
return NO_ERROR;
}
+int target_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ uint32_t ret;
+
+ dprintf(SPEW, "%s: target_panel_clock\n", __func__);
+
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mmss_bus_clock_enable();
+ mdp_clock_enable();
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(0);
+ return ret;
+ }
+
+ hdmi_phy_reset();
+ hdmi_pll_config();
+ hdmi_vco_enable();
+ hdmi_clk_enable();
+ } else if(!target_cont_splash_screen()) {
+ /* Disable clocks if continuous splash off */
+ hdmi_clk_disable();
+ hdmi_vco_disable();
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return NO_ERROR;
+}
+
+static void target_hdmi_mvs_enable(bool enable)
+{
+ struct pm8x41_mvs mvs;
+ mvs.base = PM8x41_MVS1_BASE;
+
+ if (enable)
+ pm8x41_enable_mvs(&mvs, MVS_ENABLE);
+ else
+ pm8x41_enable_mvs(&mvs, MVS_DISABLE);
+}
+
+static void target_hdmi_vreg_enable(bool enable)
+{
+ struct pm8x41_mpp mpp;
+ mpp.base = PM8x41_MMP3_BASE;
+
+ if (enable) {
+ mpp.mode = MPP_HIGH;
+ mpp.vin = MPP_VIN2;
+ pm8x41_config_output_mpp(&mpp);
+ pm8x41_enable_mpp(&mpp, MPP_ENABLE);
+ } else {
+ pm8x41_enable_mpp(&mpp, MPP_DISABLE);
+ }
+}
+
+int target_hdmi_regulator_ctrl(bool enable)
+{
+ target_hdmi_mvs_enable(enable);
+ target_hdmi_vreg_enable(enable);
+
+ return 0;
+}
+
void target_edp_panel_init(struct msm_panel_info *pinfo)
{
edp_panel_init(pinfo);
@@ -402,6 +473,7 @@
return;
} else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
dprintf(INFO, "%s: HDMI is primary\n", __func__);
+ mdss_hdmi_display_init(MDP_REV_50, HDMI_FB_ADDR);
return;
}
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 355d8c9..5265f7d 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -356,7 +356,7 @@
return ret;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ret = NO_ERROR;
uint32_t ldocounter = 0;
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index 66dbbdd..0db3e9e 100755
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -135,7 +135,7 @@
return 0;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ldocounter = 0;
uint32_t pm8x41_ldo_base = 0x13F00;
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index ba16ac1..644b750 100755
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -352,7 +352,7 @@
return ret;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
/*
* The PMIC regulators needed for display are enabled in SBL.
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 1c236b6..fab0122 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -279,7 +279,7 @@
return NO_ERROR;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ldocounter = 0;
uint32_t pm8x41_ldo_base = 0x13F00;
diff --git a/target/msm8994/include/target/display.h b/target/msm8994/include/target/display.h
index 70e5d76..8449ee0 100644
--- a/target/msm8994/include/target/display.h
+++ b/target/msm8994/include/target/display.h
@@ -41,7 +41,7 @@
"msmgpio", 78, 3, 1, 0, 1
};
-static struct gpio_pin enable_gpio = { /* lcd_reg_en */
+static struct gpio_pin lcd_reg_en = { /* boost regulator */
"pm8994_gpios", 14, 3, 1, 0, 1
};
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
index 15049a8..f0d7ba5 100644
--- a/target/msm8994/oem_panel.c
+++ b/target/msm8994/oem_panel.c
@@ -103,6 +103,7 @@
switch (panel_id) {
case SHARP_WQXGA_DUALDSI_VIDEO_PANEL:
pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 0;
panelstruct->paneldata = &sharp_wqxga_dualdsi_video_panel_data;
panelstruct->paneldata->panel_operating_mode = 11;
panelstruct->paneldata->panel_with_enable_gpio = 0;
@@ -126,6 +127,7 @@
break;
case JDI_QHD_DUALDSI_VIDEO_PANEL:
pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 1;
panelstruct->paneldata = &jdi_qhd_dualdsi_video_panel_data;
panelstruct->panelres = &jdi_qhd_dualdsi_video_panel_res;
panelstruct->color = &jdi_qhd_dualdsi_video_color;
@@ -151,6 +153,7 @@
break;
case JDI_QHD_DUALDSI_CMD_PANEL:
pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 1;
panelstruct->paneldata = &jdi_qhd_dualdsi_cmd_panel_data;
panelstruct->panelres = &jdi_qhd_dualdsi_cmd_panel_res;
panelstruct->color = &jdi_qhd_dualdsi_cmd_color;
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 57dfe20..43612bc 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -124,7 +124,7 @@
return NO_ERROR;
}
-void lcd_reg_en(void)
+void lcd_reg_enable(void)
{
struct pm8x41_gpio gpio = {
.direction = PM_GPIO_DIR_OUT,
@@ -134,8 +134,13 @@
.out_strength = PM_GPIO_OUT_DRIVE_MED,
};
- pm8x41_gpio_config(14, &gpio);
- pm8x41_gpio_set(14, 1);
+ pm8x41_gpio_config(lcd_reg_en.pin_id, &gpio);
+ pm8x41_gpio_set(lcd_reg_en.pin_id, 1);
+}
+
+void lcd_reg_disable(void)
+{
+ pm8x41_gpio_set(lcd_reg_en.pin_id, 0);
}
int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
@@ -250,14 +255,20 @@
return NO_ERROR;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
if (enable) {
regulator_enable(); /* L2, L12, L14, and L28 */
mdelay(10);
qpnp_ibb_enable(true); /* +5V and -5V */
mdelay(50);
+
+ if (pinfo->lcd_reg_en)
+ lcd_reg_enable();
} else {
+ if (pinfo->lcd_reg_en)
+ lcd_reg_disable();
+
regulator_disable();
}
diff --git a/target/target_display.c b/target/target_display.c
index bac8a52..a4e15e2 100644
--- a/target/target_display.c
+++ b/target/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -62,6 +62,10 @@
{
return 0;
}
+__WEAK int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ return 0;
+}
__WEAK void target_edp_panel_init(struct msm_panel_info *pinfo)
{
@@ -87,3 +91,17 @@
{
return 0;
}
+
+__WEAK int target_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ return 0;
+}
+
+__WEAK int target_hdmi_regulator_ctrl(bool enable)
+{
+ return 0;
+}
+__WEAK int mdss_hdmi_init(void)
+{
+ return 0;
+}