Merge "app: aboot: Simplify the code to use reboot reason"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 6ff67f5..df9a6be 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -1011,7 +1011,8 @@
* 4. Sanity Check on kernel_addr and ramdisk_addr and copy data.
*/
- dprintf(INFO, "Loading boot image (%d): start\n", imagesize_actual);
+ dprintf(INFO, "Loading (%s) image (%d): start\n",
+ (!boot_into_recovery ? "boot" : "recovery"),imagesize_actual);
bs_set_timestamp(BS_KERNEL_LOAD_START);
/* Read image without signature */
@@ -1021,7 +1022,9 @@
return -1;
}
- dprintf(INFO, "Loading boot image (%d): done\n", imagesize_actual);
+ dprintf(INFO, "Loading (%s) image (%d): done\n",
+ (!boot_into_recovery ? "boot" : "recovery"),imagesize_actual);
+
bs_set_timestamp(BS_KERNEL_LOAD_DONE);
/* Authenticate Kernel */
@@ -1077,16 +1080,7 @@
*/
if (is_gzip_package((unsigned char *)(image_addr + page_size), hdr->kernel_size))
{
-#ifdef ABOOT_IGNORE_BOOT_HEADER_ADDRS
- /* Set default kernel decompression output address to be ABOOT_FORCE_KERNEL64_ADDR.
- * Most likely gzip compressed kernel is used by arm64 kernel,
- * and it is using ABOOT_FORCE_KERNEL64_ADDR for kernel start address.
- * It can avoid an unnecessary memmove afterwords.
- */
- out_addr = (unsigned char *) ABOOT_FORCE_KERNEL64_ADDR;
-#else
out_addr = (unsigned char *)(image_addr + imagesize_actual + page_size);
-#endif
out_avai_len = target_get_max_flash_size() - imagesize_actual - page_size;
dprintf(INFO, "decompressing kernel image: start\n");
rc = decompress((unsigned char *)(image_addr + page_size),
@@ -1340,7 +1334,8 @@
imagesize_actual = (page_size + kernel_actual + ramdisk_actual);
#endif
- dprintf(INFO, "Loading boot image (%d): start\n", imagesize_actual);
+ dprintf(INFO, "Loading (%s) image (%d): start\n",
+ (!boot_into_recovery ? "boot" : "recovery"),imagesize_actual);
bs_set_timestamp(BS_KERNEL_LOAD_START);
/* Read image without signature */
@@ -1350,7 +1345,8 @@
return -1;
}
- dprintf(INFO, "Loading boot image (%d): done\n", imagesize_actual);
+ dprintf(INFO, "Loading (%s) image (%d): done\n",
+ (!boot_into_recovery ? "boot" : "recovery"), imagesize_actual);
bs_set_timestamp(BS_KERNEL_LOAD_DONE);
offset = imagesize_actual;
@@ -1394,8 +1390,9 @@
ramdisk_actual = ROUND_TO_PAGE(hdr->ramdisk_size, page_mask);
second_actual = ROUND_TO_PAGE(hdr->second_size, page_mask);
- dprintf(INFO, "Loading boot image (%d): start\n",
- kernel_actual + ramdisk_actual);
+ dprintf(INFO, "Loading (%s) image (%d): start\n",
+ (!boot_into_recovery ? "boot" : "recovery"), kernel_actual + ramdisk_actual);
+
bs_set_timestamp(BS_KERNEL_LOAD_START);
if (flash_read(ptn, offset, (void *)hdr->kernel_addr, kernel_actual)) {
@@ -1410,8 +1407,9 @@
}
offset += ramdisk_actual;
- dprintf(INFO, "Loading boot image (%d): done\n",
- kernel_actual + ramdisk_actual);
+ dprintf(INFO, "Loading (%s) image (%d): done\n",
+ (!boot_into_recovery ? "boot" : "recovery"), kernel_actual + ramdisk_actual);
+
bs_set_timestamp(BS_KERNEL_LOAD_DONE);
if(hdr->second_size != 0) {
@@ -1598,7 +1596,7 @@
unsigned long long ptn;
unsigned long long ptn_size;
unsigned blocksize = mmc_get_device_blocksize();
- char buf[blocksize];
+ STACKBUF_DMA_ALIGN(buf, blocksize);
index = partition_get_index(frp_ptns[0]);
if (index == INVALID_PTN)
@@ -1615,7 +1613,7 @@
ptn_size = partition_get_size(index);
offset = ptn_size - blocksize;
- if (mmc_read(ptn + offset, (void *)buf, sizeof(buf)))
+ if (mmc_read(ptn + offset, (void *)buf, blocksize))
{
dprintf(CRITICAL, "Reading MMC failed\n");
return -1;
@@ -1633,7 +1631,7 @@
unsigned long long ptn;
unsigned long long ptn_size;
unsigned blocksize = mmc_get_device_blocksize();
- char buf[blocksize];
+ STACKBUF_DMA_ALIGN(buf, blocksize);
index = partition_get_index(frp_ptns[0]);
if (index == INVALID_PTN)
@@ -1650,7 +1648,7 @@
ptn_size = partition_get_size(index);
offset = ptn_size - blocksize;
- if (mmc_read(ptn + offset, (void *)buf, sizeof(buf)))
+ if (mmc_read(ptn + offset, (void *)buf, blocksize))
{
dprintf(CRITICAL, "Reading MMC failed\n");
return -1;
@@ -1882,6 +1880,9 @@
void cmd_boot(const char *arg, void *data, unsigned sz)
{
+#ifdef MDTP_SUPPORT
+ static bool is_mdtp_activated = 0;
+#endif /* MDTP_SUPPORT */
unsigned kernel_actual;
unsigned ramdisk_actual;
uint32_t image_actual;
@@ -1955,18 +1956,14 @@
else
{
/* fastboot boot is not allowed when MDTP is activated */
-
mdtp_ext_partition_verification_t ext_partition;
- ext_partition.partition = boot_into_recovery ? MDTP_PARTITION_RECOVERY : MDTP_PARTITION_BOOT;
- ext_partition.integrity_state = MDTP_PARTITION_STATE_UNSET;
- ext_partition.page_size = page_size;
- ext_partition.image_addr = (uint32_t)data;
- ext_partition.image_size = image_actual - sig_actual;
- ext_partition.sig_avail = TRUE;
- mdtp_fwlock_verify_lock(&ext_partition);
+
+ if (!is_mdtp_activated) {
+ ext_partition.partition = MDTP_PARTITION_NONE;
+ mdtp_fwlock_verify_lock(&ext_partition);
+ }
}
- bool is_mdtp_activated = 0;
mdtp_activated(&is_mdtp_activated);
if(is_mdtp_activated){
dprintf(CRITICAL, "fastboot boot command is not available.\n");
@@ -1980,17 +1977,8 @@
*/
if (is_gzip_package((unsigned char *)(data + page_size), hdr->kernel_size))
{
-#ifdef ABOOT_IGNORE_BOOT_HEADER_ADDRS
- /* Set default kernel decompression output address to be ABOOT_FORCE_KERNEL64_ADDR.
- * Most likely gzip compressed kernel is used by arm64 kernel,
- * and it is using ABOOT_FORCE_KERNEL64_ADDR for kernel start address.
- * It can avoid an unnecessary memmove afterwords.
- */
- out_addr = (unsigned char *) ABOOT_FORCE_KERNEL64_ADDR;
-#else
out_addr = (unsigned char *)target_get_scratch_address();
out_addr = (unsigned char *)(out_addr + image_actual + page_size);
-#endif
out_avai_len = target_get_max_flash_size() - image_actual - page_size;
dprintf(INFO, "decompressing kernel image: start\n");
ret = decompress((unsigned char *)(ptr + page_size),
diff --git a/app/aboot/mdtp.c b/app/aboot/mdtp.c
index 578f4de..01f907a 100644
--- a/app/aboot/mdtp.c
+++ b/app/aboot/mdtp.c
@@ -570,38 +570,40 @@
}
else
{
- for(i=0; i<MAX_PARTITIONS; i++)
+ if (ext_partition->partition != MDTP_PARTITION_NONE)
{
- if(dip->partition_cfg[i].lock_enabled && dip->partition_cfg[i].size)
+ for(i=0; i<MAX_PARTITIONS; i++)
{
- total_num_blocks = ((dip->partition_cfg[i].size - 1) / MDTP_FWLOCK_BLOCK_SIZE);
- if (validate_partition_params(dip->partition_cfg[i].size,
- dip->partition_cfg[i].hash_mode,
- dip->partition_cfg[i].verify_ratio))
+ if(dip->partition_cfg[i].lock_enabled && dip->partition_cfg[i].size)
{
- dprintf(CRITICAL, "mdtp: verify_all_partitions: Wrong partition parameters\n");
- verify_failure = TRUE;
- break;
- }
+ total_num_blocks = ((dip->partition_cfg[i].size - 1) / MDTP_FWLOCK_BLOCK_SIZE);
+ if (validate_partition_params(dip->partition_cfg[i].size,
+ dip->partition_cfg[i].hash_mode,
+ dip->partition_cfg[i].verify_ratio))
+ {
+ dprintf(CRITICAL, "mdtp: verify_all_partitions: Wrong partition parameters\n");
+ verify_failure = TRUE;
+ break;
+ }
- verify_failure |= (verify_partition(dip->partition_cfg[i].name,
- dip->partition_cfg[i].size,
- dip->partition_cfg[i].hash_mode,
- (dip->partition_cfg[i].verify_ratio * total_num_blocks) / 100,
- dip->partition_cfg[i].hash_table,
- dip->partition_cfg[i].force_verify_block) != 0);
+ verify_failure |= (verify_partition(dip->partition_cfg[i].name,
+ dip->partition_cfg[i].size,
+ dip->partition_cfg[i].hash_mode,
+ (dip->partition_cfg[i].verify_ratio * total_num_blocks) / 100,
+ dip->partition_cfg[i].hash_table,
+ dip->partition_cfg[i].force_verify_block) != 0);
+ }
+ }
+
+ ext_partition_verify_failure = verify_ext_partition(ext_partition);
+
+ if (verify_failure || ext_partition_verify_failure)
+ {
+ dprintf(CRITICAL, "mdtp: verify_all_partitions: Failed partition verification\n");
+ return;
}
}
-
- ext_partition_verify_failure = verify_ext_partition(ext_partition);
-
- if (verify_failure || ext_partition_verify_failure)
- {
- dprintf(CRITICAL, "mdtp: verify_all_partitions: Failed partition verification\n");
- return;
- }
is_mdtp_activated = 1;
-
}
*verify_result = VERIFY_OK;
@@ -728,7 +730,7 @@
/* Disallow CIPHER_DIP SCM call from this point, unless we are in recovery */
/* The recovery image will disallow CIPHER_DIP SCM call by itself. */
- if (ext_partition->partition != MDTP_PARTITION_RECOVERY)
+ if (ext_partition->partition == MDTP_PARTITION_BOOT)
{
mdtp_tzbsp_disallow_cipher_DIP();
}
diff --git a/app/aboot/mdtp.h b/app/aboot/mdtp.h
index c29dcc2..03e3b7c 100644
--- a/app/aboot/mdtp.h
+++ b/app/aboot/mdtp.h
@@ -113,6 +113,7 @@
typedef enum {
MDTP_PARTITION_BOOT = 0,
MDTP_PARTITION_RECOVERY,
+ MDTP_PARTITION_NONE,
MDTP_PARTITION_NUM,
} mdtp_ext_partition_t;
diff --git a/arch/arm/include/arch/arm/mmu.h b/arch/arm/include/arch/arm/mmu.h
index 12bcd23..43a474e 100644
--- a/arch/arm/include/arch/arm/mmu.h
+++ b/arch/arm/include/arch/arm/mmu.h
@@ -88,6 +88,7 @@
#define MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_NO_ALLOCATE ATTR_INDEX(5)
#define MMU_MEMORY_AP_READ_WRITE (1 << 6) /* Read/Write at any priveledge */
+#define MMU_MEMORY_AP_READ_ONLY (0x3 << 6) /* Read only priveledge */
#define MMU_MEMORY_XN (1ULL << 54)
#define MMU_MEMORY_PXN (1ULL << 53)
diff --git a/lib/libc/malloc.c b/lib/libc/malloc.c
index 9cec44c..b8857b4 100644
--- a/lib/libc/malloc.c
+++ b/lib/libc/malloc.c
@@ -36,7 +36,7 @@
void *ptr;
ptr = heap_alloc(size, boundary);
/* Clean the cache before giving the memory */
- arch_invalidate_cache_range((addr_t) ptr, size);
+ arch_clean_invalidate_cache_range((addr_t) ptr, size);
return ptr;
}
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index e6d40c9..e645ca6 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -40,6 +40,12 @@
#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
#define RESTART_REASON_ADDR2 (MSM_SHARED_IMEM_BASE2 + 0x65C)
+#define DLOAD_MODE_ADDR (MSM_SHARED_IMEM_BASE + 0x0)
+#define EMERGENCY_DLOAD_MODE_ADDR (MSM_SHARED_IMEM_BASE + 0xFE0)
+#define DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE2 + 0x0)
+#define EMERGENCY_DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE2 + 0xFE0)
+
+
#define BS_INFO_OFFSET (0x6B0)
#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
#define BS_INFO_ADDR2 (MSM_SHARED_IMEM_BASE2 + BS_INFO_OFFSET)
diff --git a/platform/msm8996/include/platform/iomap.h b/platform/msm8996/include/platform/iomap.h
index 758182e..2ae1d17 100644
--- a/platform/msm8996/include/platform/iomap.h
+++ b/platform/msm8996/include/platform/iomap.h
@@ -191,7 +191,7 @@
* as device memory, define the start address
* and size in MB
*/
-#define RPMB_SND_RCV_BUF 0x90F00000
+#define RPMB_SND_RCV_BUF 0x91400000
#define RPMB_SND_RCV_BUF_SZ 0x2
#define TCSR_BOOT_MISC_DETECT 0x007B3000
diff --git a/platform/msm8996/platform.c b/platform/msm8996/platform.c
index dcf5fc8..08c0025 100644
--- a/platform/msm8996/platform.c
+++ b/platform/msm8996/platform.c
@@ -41,22 +41,26 @@
#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
#define MSM_SHARED_SIZE 2
-/* LK memory - cacheable, write through */
-#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+/* LK memory - cacheable, write back */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
MMU_MEMORY_AP_READ_WRITE)
/* Peripherals - non-shared device */
#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN | MMU_MEMORY_PXN)
-/* SCRATCH memory - cacheable, write through */
-#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+/* SCRATCH memory - cacheable, write back */
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
/* COMMON memory - cacheable, write through */
#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+/* downlaod mode memory - cacheable, write through */
+#define DLOAD_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_ONLY | MMU_MEMORY_XN)
+
static uint64_t ddr_start;
static mmu_section_t default_mmu_section_table[] =
@@ -77,10 +81,12 @@
};
+/* Map the ddr for download mode, this region belongs to non-hlos images and pil */
static mmu_section_t dload_mmu_section_table[] =
{
-/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
- { 0x85800000, 0x85800000, MMU_L2_NS_SECTION_MAPPING, 178, COMMON_MEMORY},
+/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
+ { 0x85800000, 0x85800000, MMU_L2_NS_SECTION_MAPPING, 8, DLOAD_MEMORY},
+ { 0x86200000, 0x86200000, MMU_L2_NS_SECTION_MAPPING, 174, DLOAD_MEMORY},
};
void platform_early_init(void)
@@ -119,14 +125,23 @@
int table_sz = ARRAY_SIZE(default_mmu_section_table);
mmu_section_t kernel_mmu_section_table;
uint64_t ddr_size = smem_get_ddr_size();
+ uint32_t kernel_size = 0;
if (ddr_size == MEM_4GB)
{
ddr_start = 0x80000000;
+ /* As per the memory map when DDR is 4GB first 88 MB is hlos memory
+ * use this for loading the kernel
+ */
+ kernel_size = 88;
}
else if (ddr_size == MEM_3GB)
{
ddr_start = 0x20000000;
+ /* As per memory map wheh DDR is 3GB the first 512 MB is assigned to hlos
+ * use this region for loading kernel
+ */
+ kernel_size = 512;
}
else
{
@@ -137,8 +152,8 @@
kernel_mmu_section_table.paddress = ddr_start;
kernel_mmu_section_table.vaddress = ddr_start;
kernel_mmu_section_table.type = MMU_L2_NS_SECTION_MAPPING;
- kernel_mmu_section_table.size = KERNEL_SIZE;
- kernel_mmu_section_table.flags = COMMON_MEMORY;
+ kernel_mmu_section_table.size = kernel_size;
+ kernel_mmu_section_table.flags = SCRATCH_MEMORY;
/* Map kernel entry */
arm_mmu_map_entry(&kernel_mmu_section_table);
diff --git a/platform/msm8996/rules.mk b/platform/msm8996/rules.mk
index 8db37d5..66d6af7 100644
--- a/platform/msm8996/rules.mk
+++ b/platform/msm8996/rules.mk
@@ -4,7 +4,7 @@
ARM_CPU := cortex-a8
CPU := generic
-DEFINES += ARM_CPU_CORE_KRAIT
+DEFINES += ARM_CPU_CORE_KRYO
MMC_SLOT := 1
diff --git a/platform/msm_shared/dme.c b/platform/msm_shared/dme.c
index 47e94b0..f83ee93 100644
--- a/platform/msm_shared/dme.c
+++ b/platform/msm_shared/dme.c
@@ -291,19 +291,19 @@
int dme_set_fdeviceinit(struct ufs_dev *dev)
{
- STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
+ uint32_t result;
uint32_t try_again = DME_FDEVICEINIT_RETRIES;
struct utp_query_req_upiu_type read_query = {UPIU_QUERY_OP_READ_FLAG,
UFS_IDX_fDeviceInit,
0,
0,
- (addr_t) result,
+ (addr_t) &result,
sizeof(uint32_t)};
struct utp_query_req_upiu_type set_query = {UPIU_QUERY_OP_SET_FLAG,
UFS_IDX_fDeviceInit,
0,
0,
- (addr_t) result,
+ (addr_t) &result,
sizeof(uint32_t)};
@@ -313,9 +313,7 @@
return -UFS_FAILURE;
}
- arch_invalidate_cache_range((addr_t) result, sizeof(uint32_t));
-
- if (*result == 1)
+ if (result == 1)
goto utp_set_fdeviceinit_done;
do
@@ -334,7 +332,7 @@
return -UFS_FAILURE;
}
- if (*result == 1)
+ if (result == 1)
break;
} while (try_again);
@@ -383,15 +381,13 @@
int dme_read_device_desc(struct ufs_dev *dev)
{
- STACKBUF_DMA_ALIGN(dev_desc, sizeof(struct ufs_dev_desc));
- STACKBUF_DMA_ALIGN(desc, sizeof(struct ufs_string_desc));
- struct ufs_dev_desc *device_desc = (struct ufs_dev_desc *) dev_desc;
- struct ufs_string_desc *str_desc = (struct ufs_string_desc *) desc;
+ struct ufs_dev_desc device_desc;
+ struct ufs_string_desc str_desc;
struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
UFS_DESC_IDN_DEVICE,
0,
0,
- (addr_t) dev_desc,
+ (addr_t) &device_desc,
sizeof(struct ufs_dev_desc)};
if (dme_send_query_upiu(dev, &query))
@@ -400,20 +396,14 @@
return -UFS_FAILURE;
}
- /* Flush buffer. */
- arch_invalidate_cache_range((addr_t) device_desc, sizeof(struct ufs_dev_desc));
-
/* Store all relevant data */
- dev->num_lus = device_desc->num_lu;
+ dev->num_lus = device_desc.num_lu;
/* Get serial number for the device based on the string index. */
- if (dme_read_string_desc(dev, device_desc->serial_num, (struct ufs_string_desc *) desc))
+ if (dme_read_string_desc(dev, device_desc.serial_num, (struct ufs_string_desc *) &str_desc))
return -UFS_FAILURE;
- /* Flush buffer. */
- arch_invalidate_cache_range((addr_t) str_desc, sizeof(struct ufs_string_desc));
-
- dev->serial_num = dme_parse_serial_no(str_desc);
+ dev->serial_num = dme_parse_serial_no(&str_desc);
return UFS_SUCCESS;
}
@@ -437,21 +427,19 @@
return -UFS_FAILURE;
}
- // Flush buffer.
- arch_invalidate_cache_range((addr_t) desc, sizeof(struct ufs_geometry_desc));
dev->rpmb_rw_size = desc->rpmb_read_write_size;
return UFS_SUCCESS;
}
int dme_read_unit_desc(struct ufs_dev *dev, uint8_t index)
{
- STACKBUF_DMA_ALIGN(unit_desc, sizeof(struct ufs_unit_desc));
- struct ufs_unit_desc *desc = (struct ufs_unit_desc *) unit_desc;
+ struct ufs_unit_desc unit_desc;
+ struct ufs_unit_desc *desc = (struct ufs_unit_desc *) &unit_desc;
struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
UFS_DESC_IDN_UNIT,
index,
0,
- (addr_t) unit_desc,
+ (addr_t) &unit_desc,
sizeof(struct ufs_unit_desc)};
if (dme_send_query_upiu(dev, &query))
@@ -459,8 +447,6 @@
dprintf(CRITICAL, "%s:%d DME Read Unit Descriptor request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
}
- /* Flush buffer. */
- arch_invalidate_cache_range((addr_t) desc, sizeof(struct ufs_unit_desc));
dev->lun_cfg[index].logical_blk_cnt = BE64(desc->logical_blk_cnt);
diff --git a/platform/msm_shared/qseecom_lk.c b/platform/msm_shared/qseecom_lk.c
index 4374601..0c9077b 100644
--- a/platform/msm_shared/qseecom_lk.c
+++ b/platform/msm_shared/qseecom_lk.c
@@ -1346,6 +1346,8 @@
goto err;
}
memset(buf, 0, ROUNDUP(QSEE_LOG_BUF_SIZE, PAGE_SIZE));
+ /* Make sure the buffer given to TZ is flushed */
+ arch_clean_invalidate_cache_range((addr_t) buf, QSEE_LOG_BUF_SIZE);
logbuf_req.qsee_cmd_id = QSEE_REGISTER_LOG_BUF_COMMAND;
logbuf_req.phy_addr = (uint32_t)__qseecom_uvirt_to_kphys((uint32_t) buf);
logbuf_req.len = QSEE_LOG_BUF_SIZE;
diff --git a/platform/msm_shared/rpm-glink.c b/platform/msm_shared/rpm-glink.c
index 406f2ea..2635cd1 100644
--- a/platform/msm_shared/rpm-glink.c
+++ b/platform/msm_shared/rpm-glink.c
@@ -137,8 +137,6 @@
}
resp = (rpm_ack_msg *)rx_buffer;
- arch_invalidate_cache_range((addr_t)resp, sizeof(rpm_gen_hdr));
-
if(resp->hdr.type == RPM_CMD_MAGIC)
{
type = RPM_CMD_TYPE;
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 8978664..eb7107d 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -473,7 +473,8 @@
$(LOCAL_DIR)/mipi_dsi_autopll.o \
$(LOCAL_DIR)/mipi_dsi_autopll_20nm.o \
$(LOCAL_DIR)/mdss_hdmi.o \
- $(LOCAL_DIR)/hdmi_pll_20nm.o
+ $(LOCAL_DIR)/hdmi_pll_20nm.o \
+ $(LOCAL_DIR)/dload_util.o
endif
ifeq ($(PLATFORM),msm8909)
@@ -601,6 +602,24 @@
$(LOCAL_DIR)/mipi_dsi_autopll.o
endif
+ifeq ($(PLATFORM),msmtitanium)
+ OBJS += $(LOCAL_DIR)/qgic.o \
+ $(LOCAL_DIR)/qtimer.o \
+ $(LOCAL_DIR)/qtimer_mmap.o \
+ $(LOCAL_DIR)/interrupts.o \
+ $(LOCAL_DIR)/clock.o \
+ $(LOCAL_DIR)/clock_pll.o \
+ $(LOCAL_DIR)/clock_lib2.o \
+ $(LOCAL_DIR)/uart_dm.o \
+ $(LOCAL_DIR)/board.o \
+ $(LOCAL_DIR)/spmi.o \
+ $(LOCAL_DIR)/bam.o \
+ $(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/scm.o \
+ $(LOCAL_DIR)/dev_tree.o \
+ $(LOCAL_DIR)/gpio.o
+endif
+
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
OBJS += \
$(LOCAL_DIR)/boot_device.o
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index 2dda14e..df4b136 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -1202,7 +1202,7 @@
{
indir_arg[i] = arg->x5[i];
}
- arch_clean_invalidate_cache_range((addr_t) indir_arg, ROUNDUP((SCM_INDIR_MAX_LEN * sizeof(uint32_t)), CACHE_LINE));
+ arch_clean_invalidate_cache_range((addr_t) indir_arg, (SCM_INDIR_MAX_LEN * sizeof(uint32_t)));
x5 = (addr_t) indir_arg;
}
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 7fbe57f..0afa45f 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -430,6 +430,7 @@
APQ8052 = 289,
MDMFERMIUM = 290,
APQ8096 = 291,
+ MSMTITANIUM = 293,
};
enum platform {
diff --git a/platform/msm_shared/ucs.c b/platform/msm_shared/ucs.c
index a1ab6f3..aaf17a8 100644
--- a/platform/msm_shared/ucs.c
+++ b/platform/msm_shared/ucs.c
@@ -429,7 +429,7 @@
/* Flush cdb to memory. */
dsb();
- arch_invalidate_cache_range((addr_t) cdb_param, SCSI_CDB_PARAM_LEN);
+ arch_clean_invalidate_cache_range((addr_t) cdb_param, SCSI_CDB_PARAM_LEN);
memset(&req_upiu, 0 , sizeof(struct scsi_req_build_type));
@@ -479,7 +479,7 @@
/* Flush cdb to memory. */
dsb();
- arch_invalidate_cache_range((addr_t) cdb_param, SCSI_CDB_PARAM_LEN);
+ arch_clean_invalidate_cache_range((addr_t) cdb_param, SCSI_CDB_PARAM_LEN);
memset(&req_upiu, 0 , sizeof(struct scsi_req_build_type));
diff --git a/platform/msmtitanium/acpuclock.c b/platform/msmtitanium/acpuclock.c
new file mode 100755
index 0000000..25c1eff
--- /dev/null
+++ b/platform/msmtitanium/acpuclock.c
@@ -0,0 +1,90 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <err.h>
+#include <assert.h>
+#include <debug.h>
+#include <reg.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/clock.h>
+#include <platform.h>
+
+#define MAX_LOOPS 500
+
+void hsusb_clock_init(void)
+{
+}
+
+void clock_init_mmc(uint32_t interface)
+{
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+}
+
+/* Function to asynchronously reset CE.
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+}
+
+void clock_config_ce(uint8_t instance)
+{
+ /* Need to enable the clock before disabling since the clk_disable()
+ * has a check to default to nop when the clk_enable() is not called
+ * on that particular clock.
+ */
+ clock_ce_enable(instance);
+
+ clock_ce_disable(instance);
+
+ ce_async_reset(instance);
+
+ clock_ce_enable(instance);
+}
diff --git a/platform/msmtitanium/gpio.c b/platform/msmtitanium/gpio.c
new file mode 100644
index 0000000..05b4977
--- /dev/null
+++ b/platform/msmtitanium/gpio.c
@@ -0,0 +1,72 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+#include <blsp_qup.h>
+
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable)
+{
+ uint32_t val = 0;
+
+ val |= pull;
+ val |= func << 2;
+ val |= drvstr << 6;
+ val |= enable << 9;
+
+ writel(val, (uint32_t *)GPIO_CONFIG_ADDR(gpio));
+ return;
+}
+
+void gpio_set_dir(uint32_t gpio, uint32_t dir)
+{
+ writel(dir, (uint32_t *)GPIO_IN_OUT_ADDR(gpio));
+
+ return;
+}
+
+uint32_t gpio_status(uint32_t gpio)
+{
+ return readl(GPIO_IN_OUT_ADDR(gpio)) & GPIO_IN;
+}
+
+/* Configure gpio for blsp uart 2 */
+void gpio_config_uart_dm(uint8_t id)
+{
+ /* configure rx gpio */
+ gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure tx gpio */
+ gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+}
diff --git a/platform/msmtitanium/include/platform/clock.h b/platform/msmtitanium/include/platform/clock.h
new file mode 100644
index 0000000..4174744
--- /dev/null
+++ b/platform/msmtitanium/include/platform/clock.h
@@ -0,0 +1,44 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MSMTITANIUM_CLOCK_H
+#define __MSMTITANIUM_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+#endif
diff --git a/platform/msmtitanium/include/platform/gpio.h b/platform/msmtitanium/include/platform/gpio.h
new file mode 100644
index 0000000..1d05ede
--- /dev/null
+++ b/platform/msmtitanium/include/platform/gpio.h
@@ -0,0 +1,72 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSMTITANIUM_GPIO_H
+#define __PLATFORM_MSMTITANIUM_GPIO_H
+
+#include <bits.h>
+#include <gpio.h>
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE 0
+#define GPIO_DISABLE 1
+
+/* GPIO_IN_OUT register shifts. */
+#define GPIO_IN BIT(0)
+#define GPIO_OUT BIT(1)
+
+void gpio_config_uart_dm(uint8_t id);
+uint32_t gpio_status(uint32_t gpio);
+void gpio_set_dir(uint32_t gpio, uint32_t dir);
+void gpio_tlmm_config(uint32_t gpio,
+ uint8_t func,
+ uint8_t dir,
+ uint8_t pull,
+ uint8_t drvstr,
+ uint32_t enable);
+#endif
diff --git a/platform/msmtitanium/include/platform/iomap.h b/platform/msmtitanium/include/platform/iomap.h
new file mode 100755
index 0000000..c429f35
--- /dev/null
+++ b/platform/msmtitanium/include/platform/iomap.h
@@ -0,0 +1,154 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSMTITANIUM_IOMAP_H_
+#define _PLATFORM_MSMTITANIUM_IOMAP_H_
+
+#define MSM_IOMAP_BASE 0x00000000
+#define MSM_IOMAP_END 0x08000000
+
+#define SDRAM_START_ADDR 0x80000000
+
+#define MSM_SHARED_BASE 0x86300000
+#define MSM_SHARED_IMEM_BASE 0x08600000
+
+#define BS_INFO_OFFSET (0x6B0)
+#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
+
+#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+
+#define APPS_SS_BASE 0x0B000000
+
+#define MSM_GIC_DIST_BASE APPS_SS_BASE
+#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
+#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
+#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
+#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
+#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00111008)
+
+#define PERIPH_SS_BASE 0x07800000
+
+#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
+#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000)
+
+#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
+#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
+#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
+
+#define CLK_CTL_BASE 0x1800000
+
+#define SPMI_BASE 0x02000000
+#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
+#define PMIC_ARB_CORE 0x200F000
+
+#define TLMM_BASE_ADDR 0x1000000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
+
+#define MPM2_MPM_CTRL_BASE 0x004A0000
+#define MPM2_MPM_PS_HOLD 0x004AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
+
+/* CRYPTO ENGINE */
+#define MSM_CE1_BASE 0x073A000
+#define MSM_CE1_BAM_BASE 0x0704000
+#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
+#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
+#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
+#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
+#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
+#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
+
+
+/* GPLL */
+#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
+#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
+#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
+#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
+#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
+
+/* SDCC */
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
+#define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/
+#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */
+#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
+#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */
+#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */
+#define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */
+#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
+#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
+
+/* SDHCI */
+#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
+#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
+
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+
+#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
+
+/* UART */
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
+#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
+#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
+#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
+#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
+#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
+#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
+
+/* USB */
+#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
+#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
+#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
+#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
+#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
+#define MSM_USB30_QSCRATCH_BASE 0x070F8800
+#define MSM_USB30_BASE 0x7000000
+#define USB2_PHY_SEL 0x01937000
+
+#define TCSR_TZ_WONCE 0x193D000
+#define TCSR_BOOT_MISC_DETECT 0x193D100
+
+#define DDR_START 0x80000000
+#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
+#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
+#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
+#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
+#endif
diff --git a/platform/msmtitanium/include/platform/irqs.h b/platform/msmtitanium/include/platform/irqs.h
new file mode 100755
index 0000000..db33501
--- /dev/null
+++ b/platform/msmtitanium/include/platform/irqs.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IRQS_MSMTITANIUM_H
+#define __IRQS_MSMTITANIUM_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 257)
+
+#define USB30_EE1_IRQ (GIC_SPI_START + 134)
+#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
+#define USB1_HS_IRQ (GIC_SPI_START + 134)
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 173
+#define NR_BOARD_IRQS 0
+
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
+ NR_BOARD_IRQS)
+
+#define SMD_IRQ (GIC_SPI_START + 168)
+#endif /* __IRQS_MSMTITANIUM_H */
diff --git a/platform/msmtitanium/msmtitanium-clock.c b/platform/msmtitanium/msmtitanium-clock.c
new file mode 100644
index 0000000..092ca54
--- /dev/null
+++ b/platform/msmtitanium/msmtitanium-clock.c
@@ -0,0 +1,419 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+#include <platform.h>
+
+/* Mux source select values */
+#define cxo_source_val 0
+#define gpll0_source_val 1
+#define gpll4_source_val 2
+#define cxo_mm_source_val 0
+#define gpll0_mm_source_val 6
+#define gpll6_mm_source_val 3
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+ .enable = clock_lib2_branch_clk_enable,
+ .disable = clock_lib2_branch_clk_disable,
+ .set_rate = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+ .enable = cxo_clk_enable,
+ .disable = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 800000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+static struct pll_vote_clk gpll4_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(5),
+ .status_reg = (void *) GPLL4_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1152000000,
+ .dbg_name = "gpll4_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 10, 1, 4),
+ F( 25000000, gpll0, 16, 1, 2),
+ F( 50000000, gpll0, 16, 0, 0),
+ F(100000000, gpll0, 8, 0, 0),
+ F(177770000, gpll0, 4.5, 0, 0),
+ F(200000000, gpll0, 4, 0, 0),
+ F(384000000, gpll4, 3, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 10, 1, 4),
+ F( 25000000, gpll0, 16, 1, 2),
+ F( 50000000, gpll0, 16, 0, 0),
+ F(100000000, gpll0, 8, 0, 0),
+ F(177770000, gpll0, 4.5, 0, 0),
+ F(200000000, gpll0, 4, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC2_M,
+ .n_reg = (uint32_t *) SDCC2_N,
+ .d_reg = (uint32_t *) SDCC2_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc2_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR,
+ .parent = &sdcc2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 72, 15625),
+ F( 7372800, gpll0, 1, 144, 15625),
+ F(14745600, gpll0, 1, 288, 15625),
+ F(16000000, gpll0, 10, 1, 5),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 1, 3, 100),
+ F(25000000, gpll0, 16, 1, 2),
+ F(32000000, gpll0, 1, 1, 25),
+ F(40000000, gpll0, 1, 1, 20),
+ F(46400000, gpll0, 1, 29, 500),
+ F(48000000, gpll0, 1, 3, 50),
+ F(51200000, gpll0, 1, 8, 125),
+ F(56000000, gpll0, 1, 7, 100),
+ F(58982400, gpll0, 1,1152, 15625),
+ F(60000000, gpll0, 1, 3, 40),
+ F_END
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+ .parent = &blsp1_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(10),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+ F(100000000, gpll0, 10, 0, 0),
+ F(133330000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+ .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb_hs_system_clk",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
+ .parent = &usb_hs_system_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_system_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+ F(160000000, gpll0, 5, 0, 0),
+ F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_CRYPTO_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_CRYPTO_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_ce1_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "ce1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct vote_clk gcc_ce1_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CRYPTO_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(2),
+
+ .c = {
+ .dbg_name = "gcc_ce1_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(0),
+
+ .c = {
+ .dbg_name = "gcc_ce1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CRYPTO_AXI_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(1),
+
+ .c = {
+ .dbg_name = "gcc_ce1_axi_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_titanium[] =
+{
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+
+ CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+ CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+
+ CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+
+ CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
+ CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+
+ CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
+ CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
+ CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+ CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
+};
+
+void platform_clock_init(void)
+{
+ clk_init(msm_clocks_titanium, ARRAY_SIZE(msm_clocks_titanium));
+}
diff --git a/platform/msmtitanium/platform.c b/platform/msmtitanium/platform.c
new file mode 100755
index 0000000..6e851b1
--- /dev/null
+++ b/platform/msmtitanium/platform.c
@@ -0,0 +1,76 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/clock.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+#include <boot_stats.h>
+#include <platform.h>
+
+void platform_early_init(void)
+{
+ board_init();
+ platform_clock_init();
+ qgic_init();
+ qtimer_init();
+ scm_init();
+}
+
+void platform_init(void)
+{
+ dprintf(INFO, "platform_init()\n");
+}
+
+void platform_uninit(void)
+{
+ qtimer_uninit();
+}
+
+uint32_t platform_get_sclk_count(void)
+{
+ return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+addr_t get_bs_info_addr()
+{
+ return ((addr_t)BS_INFO_ADDR);
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 1;
+}
diff --git a/platform/msmtitanium/rules.mk b/platform/msmtitanium/rules.mk
new file mode 100755
index 0000000..2734fb6
--- /dev/null
+++ b/platform/msmtitanium/rules.mk
@@ -0,0 +1,24 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH := arm
+#Compiling this as cortex-a8 until the compiler supports krait
+ARM_CPU := cortex-a8
+CPU := generic
+
+DEFINES += ARM_CPU_CORE_A7
+DEFINES += ARM_CORE_V8
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+OBJS += \
+ $(LOCAL_DIR)/platform.o \
+ $(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/msmtitanium-clock.o \
+ $(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/project/msmtitanium.mk b/project/msmtitanium.mk
new file mode 100755
index 0000000..fd4c29b
--- /dev/null
+++ b/project/msmtitanium.mk
@@ -0,0 +1,72 @@
+# top level project rules for the MSMTITANIUM project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := msmtitanium
+
+MODULES += app/aboot
+
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
+DEBUG := 1
+endif
+
+EMMC_BOOT := 1
+
+ENABLE_SMD_SUPPORT := 1
+#ENABLE_PWM_SUPPORT := true
+
+#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_LOG_BUF=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+#DEFINES += MMC_BOOT_BAM=1
+DEFINES += CRYPTO_BAM=1
+DEFINES += SPMI_CORE_V2=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+
+DEFINES += BAM_V170=1
+
+#Enable the feature of long press power on
+#DEFINES += LONG_PRESS_POWER_ON=1
+
+#Disable thumb mode
+ENABLE_THUMB := false
+
+ENABLE_SDHCI_SUPPORT := 1
+ENABLE_USB30_SUPPORT := 1
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
+
+#enable power on vibrator feature
+#ENABLE_PON_VIB_SUPPORT := true
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
+
+ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
+DEFINES += PON_VIB_SUPPORT=1
+endif
+
+ifeq ($(ENABLE_SMD_SUPPORT),1)
+DEFINES += SMD_SUPPORT=1
+endif
+
+ifeq ($(ENABLE_USB30_SUPPORT),1)
+DEFINES += USB30_SUPPORT=1
+endif
+
+#SCM call before entering DLOAD mode
+DEFINES += PLATFORM_USE_SCM_DLOAD=1
+
+CFLAGS += -Werror
+
+DEFINES += USE_TARGET_HS200_DELAY=1
+
+#Enable the external reboot functions
+#ENABLE_REBOOT_MODULE := 1
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 824bdc1..9d8c4e5 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -456,7 +456,7 @@
/* Write the reboot reason */
writel(reboot_reason, restart_reason_addr);
- if(reboot_reason == FASTBOOT_MODE)
+ if(reboot_reason == FASTBOOT_MODE || reboot_reason == DLOAD)
reset_type = PON_PSHOLD_WARM_RESET;
else
reset_type = PON_PSHOLD_HARD_RESET;
@@ -578,3 +578,15 @@
{
return DDR_CFG_DLY_VAL;
}
+
+int set_download_mode(enum dload_mode mode)
+{
+ if (platform_is_msm8994())
+ dload_util_write_cookie(mode == NORMAL_DLOAD ?
+ DLOAD_MODE_ADDR : EMERGENCY_DLOAD_MODE_ADDR, mode);
+ else
+ dload_util_write_cookie(mode == NORMAL_DLOAD ?
+ DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode);
+
+ return 0;
+}
diff --git a/target/msm8996/rules.mk b/target/msm8996/rules.mk
index d9349f7..2205f60 100644
--- a/target/msm8996/rules.mk
+++ b/target/msm8996/rules.mk
@@ -5,14 +5,13 @@
PLATFORM := msm8996
-MEMBASE := 0x90B00000 # SDRAM
+MEMBASE := 0x91000000 # SDRAM
MEMSIZE := 0x00400000 # 4MB
BASE_ADDR := 0x0000000
-SCRATCH_ADDR := 0x91100000
-SCRATCH_SIZE := 750
-KERNEL_SIZE := 512
+SCRATCH_ADDR := 0x91600000
+SCRATCH_SIZE := 746
# LPAE supports only 32 virtual address, L1 pt size is 4
L1_PT_SZ := 4
L2_PT_SZ := 3
@@ -36,7 +35,6 @@
MEMBASE=$(MEMBASE) \
BASE_ADDR=$(BASE_ADDR) \
TAGS_ADDR=$(TAGS_ADDR) \
- KERNEL_SIZE=$(KERNEL_SIZE) \
RAMDISK_ADDR=$(RAMDISK_ADDR) \
SCRATCH_ADDR=$(SCRATCH_ADDR) \
SCRATCH_SIZE=$(SCRATCH_SIZE) \
diff --git a/target/msmtitanium/init.c b/target/msmtitanium/init.c
new file mode 100644
index 0000000..5f76517
--- /dev/null
+++ b/target/msmtitanium/init.c
@@ -0,0 +1,252 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <platform/gpio.h>
+#include <dev/keys.h>
+#include <spmi_v2.h>
+#include <pm8x41.h>
+#include <board.h>
+#include <baseband.h>
+#include <hsusb.h>
+#include <scm.h>
+#include <platform/gpio.h>
+#include <platform/gpio.h>
+#include <platform/irqs.h>
+#include <platform/clock.h>
+#include <crypto5_wrapper.h>
+#include <partition_parser.h>
+#include <stdlib.h>
+
+#if LONG_PRESS_POWER_ON
+#include <shutdown_detect.h>
+#endif
+
+#define PMIC_ARB_CHANNEL_NUM 0
+#define PMIC_ARB_OWNER_ID 0
+#define TLMM_VOL_UP_BTN_GPIO 85
+
+#define FASTBOOT_MODE 0x77665500
+#define PON_SOFT_RB_SPARE 0x88F
+
+static uint32_t mmc_sdc_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE };
+
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+ uart_dm_init(1, 0, BLSP1_UART1_BASE);
+#endif
+}
+
+void target_mmc_caps(struct mmc_host *host)
+{
+ host->caps.ddr_mode = 0;
+ host->caps.hs200_mode = 0;
+ host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
+ host->caps.hs_clk_rate = MMC_CLK_50MHZ;
+}
+
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ uint8_t status = 0;
+
+ gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE);
+
+ /* Wait for the gpio config to take effect - debounce time */
+ thread_sleep(10);
+
+ /* Get status of GPIO */
+ status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
+
+ /* Active high signal. */
+ return status;
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ /* Volume down button tied in with PMIC RESIN. */
+ return pm8x41_resin_status();
+}
+
+static void target_keystatus()
+{
+ keys_init();
+
+ if(target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if(target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
+}
+
+/* Configure PMIC and Drop PS_HOLD for shutdown */
+void shutdown_device()
+{
+ dprintf(CRITICAL, "Going down for shutdown.\n");
+
+ /* Configure PMIC for shutdown */
+ pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "shutdown failed\n");
+
+ ASSERT(0);
+}
+
+
+void target_init(void)
+{
+ uint32_t base_addr;
+ uint8_t slot;
+
+ dprintf(INFO, "target_init()\n");
+
+ spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
+
+ target_keystatus();
+
+ /* Trying Slot 1*/
+ slot = 1;
+ base_addr = mmc_sdc_base[slot - 1];
+ if (mmc_boot_main(slot, base_addr)) {
+ /* Trying Slot 2 next */
+ slot = 2;
+ base_addr = mmc_sdc_base[slot - 1];
+ if (mmc_boot_main(slot, base_addr)) {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+ }
+#if LONG_PRESS_POWER_ON
+ shutdown_detect();
+#endif
+}
+
+void target_serialno(unsigned char *buf)
+{
+ uint32_t serialno;
+ if (target_is_emmc_boot()) {
+ serialno = mmc_get_psn();
+ snprintf((char *)buf, 13, "%x", serialno);
+ }
+}
+
+unsigned board_machtype(void)
+{
+}
+
+int set_download_mode(enum dload_mode mode)
+{
+ int ret = 0;
+ ret = scm_dload_mode(mode);
+
+ pm8x41_clear_pmic_watchdog();
+
+ return ret;
+}
+
+int emmc_recovery_init(void)
+{
+ return _emmc_recovery_init();
+}
+
+unsigned target_pause_for_battery_charge(void)
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+ uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /* In case of fastboot reboot,adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG) || (pon_reason & CBLPWR_N)))
+ return 1;
+ else
+ return 0;
+}
+
+/* UTMI MUX configuration to connect PHY to SNPS controller:
+ * Configure primary HS phy mux to use UTMI interface
+ * (connected to usb30 controller).
+ */
+static void tcsr_hs_phy_mux_configure(void)
+{
+ uint32_t reg;
+
+ reg = readl(USB2_PHY_SEL);
+
+ writel(reg | 0x1, USB2_PHY_SEL);
+}
+
+/* configure hs phy mux if using dwc controller */
+void target_usb_phy_mux_configure(void)
+{
+ if(!strcmp(target_usb_controller(), "dwc"))
+ {
+ tcsr_hs_phy_mux_configure();
+ }
+}
+
+/* Initialize target specific USB handlers */
+target_usb_iface_t* target_usb30_init()
+{
+ target_usb_iface_t *t_usb_iface;
+
+ t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
+ ASSERT(t_usb_iface);
+
+ t_usb_iface->mux_config = target_usb_phy_mux_configure;
+ //t_usb_iface->clock_init = clock_usb30_init;
+
+ return t_usb_iface;
+}
+
+/* identify the usb controller to be used for the target */
+const char * target_usb_controller()
+{
+ return "dwc";
+}
diff --git a/target/msmtitanium/meminfo.c b/target/msmtitanium/meminfo.c
new file mode 100644
index 0000000..b2f46df
--- /dev/null
+++ b/target/msmtitanium/meminfo.c
@@ -0,0 +1,85 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+ ram_partition ptn_entry;
+ unsigned int index;
+ int ret = 0;
+ uint32_t len = 0;
+
+ /* Make sure RAM partition table is initialized */
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Calculating the size of the mem_info_ptr */
+ for (index = 0 ; index < len; index++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, index);
+
+ if((ptn_entry.category == SDRAM) &&
+ (ptn_entry.type == SYS_MEMORY))
+ {
+
+ /* Pass along all other usable memory regions to Linux */
+ ret = dev_tree_add_mem_info(fdt,
+ memory_node_offset,
+ ptn_entry.start,
+ ptn_entry.size);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n");
+ goto target_dev_tree_mem_err;
+ }
+ }
+ }
+target_dev_tree_mem_err:
+
+ return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+ return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+ return (512 * 1024 * 1024);
+}
diff --git a/target/msmtitanium/rules.mk b/target/msmtitanium/rules.mk
new file mode 100644
index 0000000..b338bea
--- /dev/null
+++ b/target/msmtitanium/rules.mk
@@ -0,0 +1,29 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := msmtitanium
+
+MEMBASE := 0x8F600000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR := 0x80000000
+SCRATCH_ADDR := 0x90000000
+
+MODULES += \
+ dev/keys \
+ dev/vib \
+ lib/ptable \
+ dev/pmic/pm8x41 \
+ lib/libfdt
+
+DEFINES += \
+ MEMSIZE=$(MEMSIZE) \
+ MEMBASE=$(MEMBASE) \
+ BASE_ADDR=$(BASE_ADDR) \
+ SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+ $(LOCAL_DIR)/init.o \
+ $(LOCAL_DIR)/meminfo.o
diff --git a/target/msmtitanium/tools/makefile b/target/msmtitanium/tools/makefile
new file mode 100644
index 0000000..da48f0d
--- /dev/null
+++ b/target/msmtitanium/tools/makefile
@@ -0,0 +1,12 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTOUT_DIR := $(BUILDDIR)
+else
+APPSBOOTOUT_DIR := $(BOOTLOADER_OUT)/../..
+endif
+
+APPSBOOTHEADER: emmc_appsboot.mbn
+
+emmc_appsboot.mbn: $(OUTELF_STRIP)
+ $(hide) cp -f $(OUTELF_STRIP) $(APPSBOOTOUT_DIR)/emmc_appsboot.mbn