Merge "platform: msm_shared: Fix clock supply to card"
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index e7d7a0e..38ba3b4 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -37,9 +37,8 @@
static struct mdss_dsi_pll_config pll_data;
-static uint32_t calculate_bitclock(struct msm_panel_info *pinfo)
+static void calculate_bitclock(struct msm_panel_info *pinfo)
{
- uint32_t ret = NO_ERROR;
uint32_t h_period = 0, v_period = 0;
uint32_t width = pinfo->xres;
@@ -67,8 +66,6 @@
pll_data.byte_clock = pll_data.bit_clock >> 3;
pll_data.halfbit_clock = pll_data.bit_clock >> 1;
-
- return ret;
}
static uint32_t calculate_div1()
@@ -140,9 +137,38 @@
pll_data.posdiv3--; /* Register needs one value less */
}
-static uint32_t calculate_vco(uint8_t bpp, uint8_t num_of_lanes)
+static uint32_t calculate_dec_frac_start()
{
- uint32_t ret = NO_ERROR;
+ uint32_t refclk = 19200000;
+ uint32_t vco_rate = pll_data.vco_clock;
+ uint32_t tmp, mod;
+
+ vco_rate /= 2;
+ pll_data.dec_start = vco_rate / refclk;
+ tmp = vco_rate % refclk; /* module, fraction */
+ tmp /= 192;
+ tmp *= 1024;
+ tmp /= 100;
+ tmp *= 1024;
+ tmp /= 1000;
+ pll_data.frac_start = tmp;
+
+ vco_rate *= 2; /* restore */
+ tmp = vco_rate / refclk;/* div 1000 first */
+ mod = vco_rate % refclk;
+ tmp *= 127;
+ mod *= 127;
+ mod /= refclk;
+ tmp += mod;
+ tmp /= 10;
+ pll_data.lock_comp = tmp;
+
+ dprintf(SPEW, "%s: dec_start=%u dec_frac=%u lock_comp=%u\n", __func__,
+ pll_data.dec_start, pll_data.frac_start, pll_data.lock_comp);
+}
+
+static uint32_t calculate_vco_28nm(uint8_t bpp, uint8_t num_of_lanes)
+{
uint8_t counter = 0;
uint32_t temprate = 0;
@@ -172,7 +198,85 @@
/* calculate mnd and div3 for direct and indirect path */
calculate_div3(bpp, num_of_lanes);
- return ret;
+ return NO_ERROR;
+}
+
+static uint32_t calculate_vco_20nm(uint8_t bpp, uint8_t lanes)
+{
+ uint32_t vco, dsi_clk;
+ int mod, ndiv, hr_oclk2, hr_oclk3;
+ int m = 1;
+ int n = 1;
+ int bpp_m = 3; /* bpp = 3 */
+ int bpp_n = 1;
+
+ if (bpp == BITS_18) {
+ bpp_m = 9; /* bpp = 2.25 */
+ bpp_n = 4;
+
+ if (lanes == 2) {
+ m = 2;
+ n = 9;
+ } else if (lanes == 4) {
+ m = 4;
+ n = 9;
+ }
+ } else if (bpp == BITS_16) {
+ bpp_m = 2; /* bpp = 2 */
+ bpp_n = 1;
+ if (lanes == 3) {
+ m = 3;
+ n = 8;
+ }
+ }
+
+ hr_oclk2 = 4;
+
+ /* If bitclock is more than VCO min value */
+ if (pll_data.halfbit_clock >= HALF_VCO_MIN_CLOCK_20NM) {
+ /* Direct Mode */
+ vco = pll_data.halfbit_clock << 1;
+ /* support vco clock to max value only */
+ if (vco > VCO_MAX_CLOCK_20NM)
+ vco = VCO_MAX_CLOCK_20NM;
+
+ pll_data.directpath = 0x0;
+ pll_data.byte_clock = vco / 2 / hr_oclk2;
+ pll_data.lp_div_mux = 0x0;
+ ndiv = 1;
+ hr_oclk3 = hr_oclk2 * m / n * bpp_m / bpp_n / lanes;
+ } else {
+ /* Indirect Mode */
+ mod = VCO_MIN_CLOCK_20NM % (4 * pll_data.halfbit_clock );
+ ndiv = VCO_MIN_CLOCK_20NM / (4 * pll_data.halfbit_clock );
+ if (mod)
+ ndiv += 1;
+
+ vco = pll_data.halfbit_clock * 4 * ndiv;
+ pll_data.lp_div_mux = 0x1;
+ pll_data.directpath = 0x02; /* set bit 1 to enable for
+ indirect path */
+
+ pll_data.byte_clock = vco / 4 / hr_oclk2 / ndiv;
+ hr_oclk3 = hr_oclk2 * m / n * ndiv * 2 * bpp_m / bpp_n / lanes;
+ }
+
+ pll_data.vco_clock = vco;
+ dsi_clk = vco / 2 / hr_oclk3;
+ pll_data.ndiv = ndiv;
+ pll_data.hr_oclk2 = hr_oclk2 - 1; /* strat from 0 */
+ pll_data.hr_oclk3 = hr_oclk3 - 1; /* strat from 0 */
+
+ pll_data.pclk_m = m; /* M */
+ pll_data.pclk_n = ~(n - m); /* ~(N-M) */
+ pll_data.pclk_d = ~n; /* ~N */
+
+ dprintf(SPEW, "%s: oclk2=%d oclk3=%d ndiv=%d vco=%u dsi_clk=%u byte_clk=%u\n",
+ __func__, hr_oclk2, hr_oclk3, ndiv, vco, dsi_clk, pll_data.byte_clock);
+
+ calculate_dec_frac_start();
+
+ return NO_ERROR;
}
uint32_t calculate_clock_config(struct msm_panel_info *pinfo)
@@ -181,7 +285,10 @@
calculate_bitclock(pinfo);
- calculate_vco(pinfo->bpp, pinfo->mipi.num_of_lanes);
+ if (pinfo->mipi.mdss_dsi_phy_db->is_pll_20nm)
+ ret = calculate_vco_20nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
+ else
+ ret = calculate_vco_28nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
pinfo->mipi.dsi_pll_config = &pll_data;
diff --git a/dev/gcdb/display/gcdb_autopll.h b/dev/gcdb/display/gcdb_autopll.h
index 259abd6..ee0070d 100755
--- a/dev/gcdb/display/gcdb_autopll.h
+++ b/dev/gcdb/display/gcdb_autopll.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,6 +43,16 @@
#define HALFBIT_CLOCK3 44000000 /* VCO min clock div by 8 */
#define HALFBIT_CLOCK4 40000000 /* VCO min clock div by 9 */
+#define VCO_MIN_CLOCK_20NM 1000000000
+#define VCO_MAX_CLOCK_20NM 2000000000
+
+#define HALF_VCO_MIN_CLOCK_20NM (VCO_MIN_CLOCK_20NM >> 1)
+
+#define HALFBIT_CLOCK1_20NM 500000000 /* VCO min clock div by 2 */
+#define HALFBIT_CLOCK2_20NM 250000000 /* VCO min clock div by 4 */
+#define HALFBIT_CLOCK3_20NM 125000000 /* VCO min clock div by 8 */
+#define HALFBIT_CLOCK4_20NM 120000000 /* VCO min clock div by 9 */
+
#define BITS_24 24
#define BITS_18 18
#define BITS_16 16
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index da9ffa6..f41277f 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -159,7 +159,7 @@
return ret;
}
-bool gcdb_display_cmdline_arg(char *pbuf, uint16_t buf_size)
+bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size)
{
char *dsi_id = NULL;
char *panel_node = NULL;
@@ -171,28 +171,29 @@
int panel_mode = SPLIT_DISPLAY_FLAG | DUAL_PIPE_FLAG | DST_SPLIT_FLAG;
int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
- if (panelstruct.paneldata)
- {
+ if (!strcmp(panel_name, SIM_VIDEO_PANEL)) {
+ dsi_id = SIM_DSI_ID;
+ panel_mode = 0;
+ panel_node = SIM_VIDEO_PANEL_NODE;
+ } else if (!strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL)) {
+ dsi_id = SIM_DSI_ID;
+ panel_mode = 1;
+ panel_node = SIM_DUALDSI_VIDEO_PANEL_NODE;
+ slave_panel_node = SIM_DUALDSI_VIDEO_SLAVE_PANEL_NODE;
+ } else if (panelstruct.paneldata) {
dsi_id = panelstruct.paneldata->panel_controller;
panel_node = panelstruct.paneldata->panel_node_id;
panel_mode = panelstruct.paneldata->panel_operating_mode &
panel_mode;
slave_panel_node = panelstruct.paneldata->slave_panel_node_id;
- }
- else
- {
+ } else {
if (target_is_edp())
- {
default_str = "0:edp:";
- }
else
- {
default_str = "0:dsi:0:";
- }
arg_size = prefix_string_len + strlen(default_str);
- if (buf_size < arg_size)
- {
+ if (buf_size < arg_size) {
dprintf(CRITICAL, "display command line buffer is small\n");
return false;
}
@@ -227,13 +228,10 @@
if (panel_mode)
arg_size += DSI_1_STRING_LEN + slave_panel_node_len;
- if (buf_size < arg_size)
- {
+ if (buf_size < arg_size) {
dprintf(CRITICAL, "display command line buffer is small\n");
ret = false;
- }
- else
- {
+ } else {
strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
pbuf += prefix_string_len;
buf_size -= prefix_string_len;
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 5727067..23c2811 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -57,7 +57,7 @@
int target_ldo_ctrl(uint8_t enable);
int gcdb_display_init(const char *panel_name, uint32_t rev, void *base);
-bool gcdb_display_cmdline_arg(char *pbuf, uint16_t buf_size);
+bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size);
void gcdb_display_shutdown();
#endif /*_GCDB_DISPLAY_H_ */
diff --git a/dev/gcdb/display/include/display_resource.h b/dev/gcdb/display/include/display_resource.h
index 5caad1e..ce95769 100755
--- a/dev/gcdb/display/include/display_resource.h
+++ b/dev/gcdb/display/include/display_resource.h
@@ -43,6 +43,13 @@
#define LK_OVERRIDE_PANEL_LEN 2
#define NO_PANEL_CONFIG "none"
+#define SIM_VIDEO_PANEL "sim_video_panel"
+#define SIM_DUALDSI_VIDEO_PANEL "sim_dualdsi_video_panel"
+
+#define SIM_DSI_ID "dsi:0:"
+#define SIM_VIDEO_PANEL_NODE "qcom,mdss_dsi_sim_video"
+#define SIM_DUALDSI_VIDEO_PANEL_NODE "qcom,mdss_dsi_sim_video_0"
+#define SIM_DUALDSI_VIDEO_SLAVE_PANEL_NODE "qcom,mdss_dsi_sim_video_1"
/*---------------------------------------------------------------------------*/
/* Structure definition */
diff --git a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
index 666d63d..376c681 100644
--- a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
@@ -44,7 +44,7 @@
/* Panel configuration */
/*---------------------------------------------------------------------------*/
static struct panel_config sharp_wqxga_dualdsi_video_panel_data = {
- "qcom,mdss_dsi_sharp_wqxga_dualdsi_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ "qcom,mdss_dsi_sharp_wqxga_video_0", "dsi:0:", "qcom,mdss-dsi-panel",
10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 25, 1, 0,
"qcom,mdss_dsi_sharp_wqxga_video_1"
};
@@ -67,16 +67,16 @@
/* Panel on/off command information */
/*---------------------------------------------------------------------------*/
static char sharp_wqxga_dualdsi_video_on_cmd0[] = {
- 0x11, 0X00, 0x05, 0x80
+ 0x11, 0x00, 0x05, 0x80
};
static char sharp_wqxga_dualdsi_video_on_cmd1[] = {
- 0x29, 0x00, 0x5, 0x80
+ 0x29, 0x00, 0x05, 0x80
};
static struct mipi_dsi_cmd sharp_wqxga_dualdsi_video_on_command[] = {
- {0x4, sharp_wqxga_dualdsi_video_on_cmd0, 0xa0},
- {0x4, sharp_wqxga_dualdsi_video_on_cmd1, 0x02}
+ {0x4, sharp_wqxga_dualdsi_video_on_cmd0, 0x0a},
+ {0x4, sharp_wqxga_dualdsi_video_on_cmd1, 0x0a}
};
#define SHARP_WQXGA_DUALDSI_VIDEO_ON_COMMAND 2
@@ -90,6 +90,12 @@
0x10, 0x00, 0x05, 0x80
};
+static struct mipi_dsi_cmd sharp_wqxga_dualdsi_video_off_command[] = {
+ {0x4, sharp_wqxga_dualdsi_videooff_cmd0, 0x32},
+ {0x4, sharp_wqxga_dualdsi_videooff_cmd1, 0x78}
+};
+
+#define SHARP_WQXGA_DUALDSI_VIDEO_OFF_COMMAND 2
static struct command_state sharp_wqxga_dualdsi_video_state = {
0, 1
@@ -131,17 +137,16 @@
/* Panel reset sequence */
/*---------------------------------------------------------------------------*/
static struct panel_reset_sequence sharp_wqxga_dualdsi_video_reset_seq = {
- {1, 0, 1, }, {2, 5, 120, }, 2
+ {1, 0, 1, }, {10, 10, 120, }, 2
};
/*---------------------------------------------------------------------------*/
/* Backlight setting */
/*---------------------------------------------------------------------------*/
static struct backlight sharp_wqxga_dualdsi_video_backlight = {
- 1, 1, 4095, 100, 1, "PMIC_8941"
+ 1, 1, 4095, 100, 1, "PMIC_8941" /* BL_WLED */
};
#define SHARP_WQXGA_DUALDSI_VIDEO_SIGNATURE 0x210000
-
#endif /*_PANEL_SHARP_WQXGA_DUALDSI_VIDEO_H_*/
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index 72f4962..cd990f2 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -290,3 +290,183 @@
return;
}
+
+void mdp_gdsc_ctrl(uint8_t enable)
+{
+ uint32_t reg = 0;
+ reg = readl(MDP_GDSCR);
+ if (enable) {
+ if (!(reg & GDSC_POWER_ON_BIT)) {
+ reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK);
+ reg |= GDSC_EN_FEW_WAIT_256_MASK;
+ writel(reg, MDP_GDSCR);
+ while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)));
+ } else {
+ dprintf(INFO, "MDP GDSC already enabled\n");
+ }
+ } else {
+ reg |= BIT(0);
+ writel(reg, MDP_GDSCR);
+ while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT));
+ }
+}
+
+/* Configure MDP clock */
+void mdp_clock_enable(void)
+{
+ int ret;
+
+ /* Set MDP clock to 240MHz */
+ ret = clk_get_set_enable("mdp_ahb_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_mdp_clk_src", 240000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_vsync_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_mdp_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void mdp_clock_disable()
+{
+ clk_disable(clk_get("mdss_vsync_clk"));
+ clk_disable(clk_get("mdss_mdp_clk"));
+ clk_disable(clk_get("mdss_mdp_lut_clk"));
+ clk_disable(clk_get("mdss_mdp_clk_src"));
+ clk_disable(clk_get("mdp_ahb_clk"));
+
+}
+
+void mmss_bus_clock_enable(void)
+{
+ int ret;
+ /* Configure MMSSNOC AXI clock */
+ ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure S0 AXI clock */
+ ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure AXI clock */
+ ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void mmss_bus_clock_disable(void)
+{
+ /* Disable MDSS AXI clock */
+ clk_disable(clk_get("mdss_axi_clk"));
+
+ /* Disable MMSSNOC S0AXI clock */
+ clk_disable(clk_get("mmss_s0_axi_clk"));
+
+ /* Disable MMSSNOC AXI clock */
+ clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
+}
+
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+ uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
+{
+ int ret;
+
+ /* Configure Byte clock -autopll- This will not change because
+ byte clock does not need any divider*/
+ writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(0x1, DSI_BYTE0_CMD_RCGR);
+ writel(0x1, DSI_BYTE0_CBCR);
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ writel(0x1, DSI_PIXEL0_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ if (dual_dsi) {
+ /* Configure Byte 1 clock */
+ writel(0x100, DSI_BYTE1_CFG_RCGR);
+ writel(0x1, DSI_BYTE1_CMD_RCGR);
+ writel(0x1, DSI_BYTE1_CBCR);
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
+ writel(0x1, DSI_PIXEL1_CMD_RCGR);
+ writel(0x1, DSI_PIXEL1_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL1_M);
+ writel(pclk0_n, DSI_PIXEL1_N);
+ writel(pclk0_d, DSI_PIXEL1_D);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+ }
+}
+
+void mmss_dsi_clock_disable(uint32_t dual_dsi)
+{
+ /* Disable ESC clock */
+ clk_disable(clk_get("mdss_esc0_clk"));
+ writel(0x0, DSI_BYTE0_CBCR);
+ writel(0x0, DSI_PIXEL0_CBCR);
+
+ if (dual_dsi) {
+ /* Disable ESC clock */
+ clk_disable(clk_get("mdss_esc1_clk"));
+ writel(0x0, DSI_BYTE1_CBCR);
+ writel(0x0, DSI_PIXEL1_CBCR);
+ }
+}
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 3910502..aade4bd 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -215,8 +215,104 @@
#define SMEM_TARG_INFO_ADDR 0xFE805FF0
-/* Display */
-#define EDP_BASE 0xFD990000
+/* MDSS */
+#define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000
+#define MIPI_DSI_BASE (0xFD998000)
+#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
+#define MIPI_DSI1_BASE (0xFD9A0000)
+#define DSI0_PHY_BASE (0xFD998500)
+#define DSI1_PHY_BASE (0xFD9A0500)
+#define DSI0_PLL_BASE (0xFD998300)
+#define DSI1_PLL_BASE (0xFD9A0300)
+#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+
+#define MDP_BASE (0xfd900000)
+
+#define REG_MDP(off) (MDP_BASE + (off))
+#define MDP_HW_REV REG_MDP(0x1000)
+#define MDP_INTR_EN REG_MDP(0x1010)
+#define MDP_INTR_CLEAR REG_MDP(0x1018)
+#define MDP_HIST_INTR_EN REG_MDP(0x101C)
+
+#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
+#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
+#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
+#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
+
+#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
+#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
+
+#define MDP_CTL_0_BASE REG_MDP(0x2000)
+#define MDP_CTL_1_BASE REG_MDP(0x2200)
+
+#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
+#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
+#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
+
+/* can not find following two registers */
+#define MDP_REG_PPB0_CNTL REG_MDP(0x1420)
+#define MDP_REG_PPB0_CONFIG REG_MDP(0x1424)
+
+#define MDP_INTF_0_BASE REG_MDP(0x6b000)
+#define MDP_INTF_1_BASE REG_MDP(0x6b800)
+#define MDP_INTF_2_BASE REG_MDP(0x6c000)
+
+
+#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
+#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
+#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
+#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
+#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
+#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
+#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
+#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
+
+#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
+#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
+
+#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x13d8)
+#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x13dc)
+
+#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
+#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
+#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
+#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
+#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
+#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
+#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
+#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
+#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
+#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
+#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xc80B8)
+#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xc80BC)
+#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
+#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
+#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xc80C8)
+#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xc80CC)
+#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xc8070)
+#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xc8074)
+#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xc80A8)
+
+#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
+#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
+#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
+#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
+#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
+#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
+#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
+#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
+
+#define DMA_CMD_OFFSET 0x048
+#define DMA_CMD_LENGTH 0x04C
+
+#define INT_CTRL 0x110
+#define CMD_MODE_DMA_SW_TRIGGER 0x090
+
+#define EOT_PACKET_CTRL 0x0CC
+#define MISR_CMD_CTRL 0x0A0
+#define MISR_VIDEO_CTRL 0x0A4
+#define VIDEO_MODE_CTRL 0x010
+#define HS_TIMER_CTRL 0x0BC
#define SOFT_RESET 0x118
#define CLK_CTRL 0x11C
@@ -241,37 +337,4 @@
#define VIDEO_MODE_VSYNC 0x034
#define VIDEO_MODE_VSYNC_VPOS 0x038
-/* MDSS */
-#define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000
-#define MIPI_DSI_BASE 0xFD998000
-#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
-#define MIPI_DSI1_BASE 0xFD9A0000
-#define DSI0_PHY_BASE 0xFD998500
-#define DSI1_PHY_BASE 0xFD9A0500
-#define DSI0_PLL_BASE 0xFD998300
-#define DSI1_PLL_BASE 0xFD9A0300
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
-#define MDP_BASE (0xfd900000)
-#define REG_MDP(off) (MDP_BASE + (off))
-#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
-#define MDP_VP_0_VIG_1_BASE REG_MDP(0x1600)
-#define MDP_VP_0_RGB_0_BASE REG_MDP(0x2200)
-#define MDP_VP_0_RGB_1_BASE REG_MDP(0x2600)
-#define MDP_VP_0_DMA_0_BASE REG_MDP(0x3200)
-#define MDP_VP_0_DMA_1_BASE REG_MDP(0x3600)
-#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3A00)
-#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3E00)
-
-#define DMA_CMD_OFFSET 0x048
-#define DMA_CMD_LENGTH 0x04C
-
-#define INT_CTRL 0x110
-#define CMD_MODE_DMA_SW_TRIGGER 0x090
-
-#define EOT_PACKET_CTRL 0x0CC
-#define MISR_CMD_CTRL 0x0A0
-#define MISR_VIDEO_CTRL 0x0A4
-#define VIDEO_MODE_CTRL 0x010
-#define HS_TIMER_CTRL 0x0BC
-
#endif
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 386b628..774c8b6 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -93,14 +93,20 @@
ASSERT(model);
strlcpy(model, prop, len);
} else {
- model[0] = '\0';
+ dprintf(INFO, "model does not exist in device tree\n");
}
/* Find the board-id prop from DTB , if board-id is present then
* the DTB is version 2 */
board_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,board-id", &len_board_id);
- if (board_prop)
+ if (board_prop && len_board_id > 0)
{
+ if (len_board_id % BOARD_ID_SIZE)
+ {
+ dprintf(CRITICAL, "qcom,board-id in device tree is (%d) not a multiple of (%d)\n",
+ len_board_id, BOARD_ID_SIZE);
+ return false;
+ }
dtb_ver = DEV_TREE_VERSION_V2;
min_plat_id_len = PLAT_ID_SIZE;
}
@@ -140,7 +146,7 @@
board_dt_data.platform_variant_id = board_platform_id();
dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u 0x%x)\n",
- *model ? model : "unknown",
+ model ? model : "unknown",
cur_dt_entry.platform_id, cur_dt_entry.variant_id, cur_dt_entry.soc_rev);
if (platform_dt_match(&cur_dt_entry, &board_dt_data, 0) == 1)
@@ -200,94 +206,123 @@
/* We need to merge board & platform data into dt entry structure */
num_entries = msm_data_count * board_data_count;
- dt_entry_v2 = (struct dt_entry*) malloc(sizeof(struct dt_entry) * num_entries);
- ASSERT(dt_entry_v2);
- /* If we have '<X>; <Y>; <Z>' as platform data & '<A>; <B>; <C>' as board data.
- * Then dt entry should look like
- * <X ,A >;<X, B>;<X, C>;
- * <Y ,A >;<Y, B>;<Y, C>;
- * <Z ,A >;<Z, B>;<Z, C>;
- */
- i = 0;
- k = 0;
- for (i = 0; i < msm_data_count; i++)
- {
- for (j = 0; j < board_data_count; j++)
+ if (((uint64_t)msm_data_count * (uint64_t)board_data_count) == msm_data_count * board_data_count) {
+ dt_entry_v2 = (struct dt_entry*) malloc(sizeof(struct dt_entry) * num_entries);
+ ASSERT(dt_entry_v2);
+
+ /* If we have '<X>; <Y>; <Z>' as platform data & '<A>; <B>; <C>' as board data.
+ * Then dt entry should look like
+ * <X ,A >;<X, B>;<X, C>;
+ * <Y ,A >;<Y, B>;<Y, C>;
+ * <Z ,A >;<Z, B>;<Z, C>;
+ */
+ i = 0;
+ k = 0;
+ for (i = 0; i < msm_data_count; i++)
{
- dt_entry_v2[k].platform_id = platform_data[i].platform_id;
- dt_entry_v2[k].soc_rev = platform_data[i].soc_rev;
- dt_entry_v2[k].variant_id = board_data[j].variant_id;
- dt_entry_v2[k].board_hw_subtype = board_data[j].platform_subtype;
- k++;
+ for (j = 0; j < board_data_count; j++)
+ {
+ dt_entry_v2[k].platform_id = platform_data[i].platform_id;
+ dt_entry_v2[k].soc_rev = platform_data[i].soc_rev;
+ dt_entry_v2[k].variant_id = board_data[j].variant_id;
+ dt_entry_v2[k].board_hw_subtype = board_data[j].platform_subtype;
+ k++;
+ }
}
- }
- /* Now find the matching entry in the merged list */
- if (board_hardware_id() == HW_PLATFORM_QRD)
- {
- board_dt_data.target_variant_id = board_target_id();
- board_dt_data.platform_variant_id = board_platform_id();
- }
- else
- {
- board_dt_data.target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
- board_dt_data.platform_variant_id = board_platform_id();
- }
-
- for (i=0 ;i < num_entries; i++)
- {
- dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u %u 0x%x)\n",
- *model ? model : "unknown",
- dt_entry_v2[i].platform_id, dt_entry_v2[i].variant_id, dt_entry_v2[i].board_hw_subtype, dt_entry_v2[i].soc_rev);
-
- if (platform_dt_match(&dt_entry_v2[i], &board_dt_data, 0xff) == 1)
+ /* Now find the matching entry in the merged list */
+ if (board_hardware_id() == HW_PLATFORM_QRD)
{
- dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u %u 0x%x> != <%u %u %u 0x%x>\n",
- dt_entry_v2[i].platform_id,
- dt_entry_v2[i].variant_id,
- dt_entry_v2[i].soc_rev,
- dt_entry_v2[i].board_hw_subtype,
- board_platform_id(),
- board_hardware_id(),
- board_hardware_subtype(),
- board_soc_version());
- continue;
+ board_dt_data.target_variant_id = board_target_id();
+ board_dt_data.platform_variant_id = board_platform_id();
}
else
{
- /* If found a match, return the cur_dt_entry */
- found = 1;
- cur_dt_entry = dt_entry_v2[i];
- break;
+ board_dt_data.target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
+ board_dt_data.platform_variant_id = board_platform_id();
+ }
+
+ for (i=0 ;i < num_entries; i++)
+ {
+ dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u %u 0x%x)\n",
+ *model ? model : "unknown",
+ dt_entry_v2[i].platform_id, dt_entry_v2[i].variant_id, dt_entry_v2[i].board_hw_subtype, dt_entry_v2[i].soc_rev);
+
+ if (platform_dt_match(&dt_entry_v2[i], &board_dt_data, 0xff) == 1)
+ {
+ dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u %u 0x%x> != <%u %u %u 0x%x>\n",
+ dt_entry_v2[i].platform_id,
+ dt_entry_v2[i].variant_id,
+ dt_entry_v2[i].soc_rev,
+ dt_entry_v2[i].board_hw_subtype,
+ board_platform_id(),
+ board_hardware_id(),
+ board_hardware_subtype(),
+ board_soc_version());
+ continue;
+ }
+ else
+ {
+ /* If found a match, return the cur_dt_entry */
+ found = 1;
+ cur_dt_entry = dt_entry_v2[i];
+ break;
+ }
}
}
+ else
+ dprintf(CRITICAL, "Device tree got corrupted\n");
}
- if (!found)
+ if (dtb_ver == DEV_TREE_VERSION_V1)
{
- soc_rev = INVALID_SOC_REV_ID;
- goto end;
- }
- else
- soc_rev = cur_dt_entry.soc_rev;
+ if (!found)
+ soc_rev = INVALID_SOC_REV_ID;
+ else
+ {
+ soc_rev = cur_dt_entry.soc_rev;
- dprintf(INFO, "Device tree's msm_id matches the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
- cur_dt_entry.platform_id,
- cur_dt_entry.variant_id,
- cur_dt_entry.board_hw_subtype,
- cur_dt_entry.soc_rev,
- board_platform_id(),
- board_hardware_id(),
- board_hardware_subtype(),
- board_soc_version());
+ dprintf(INFO, "Device tree's msm_id matches the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
+ cur_dt_entry.platform_id,
+ cur_dt_entry.variant_id,
+ cur_dt_entry.board_hw_subtype,
+ cur_dt_entry.soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_hardware_subtype(),
+ board_soc_version());
+ }
+ return soc_rev;
+ }
+ else if (dtb_ver == DEV_TREE_VERSION_V2)
+ {
+ if (!found)
+ {
+ soc_rev = INVALID_SOC_REV_ID;
+ goto end;
+ }
+ else
+ soc_rev = cur_dt_entry.soc_rev;
+
+ dprintf(INFO, "Device tree's msm_id matches the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
+ cur_dt_entry.platform_id,
+ cur_dt_entry.variant_id,
+ cur_dt_entry.board_hw_subtype,
+ cur_dt_entry.soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_hardware_subtype(),
+ board_soc_version());
+ }
end:
free(board_data);
free(platform_data);
free(dt_entry_v2);
- free(model);
-
+ if(model) {
+ free(model);
+ }
return soc_rev;
}
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 1f5b902..ac389ee 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -78,6 +78,7 @@
#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */
#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */
#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */
+#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */
#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 000e2b1..2a8e192 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -165,6 +165,7 @@
char bistCtrl[MAX_BIST_CONFIG];
char laneCfg[MAX_LANE_CONFIG];
enum dsi_reg_mode regulator_mode;
+ int is_pll_20nm;
};
typedef struct mdss_dsi_pll_config {
@@ -181,6 +182,15 @@
uint8_t pclk_m;
uint8_t pclk_n;
uint8_t pclk_d;
+
+ /* pll 20nm */
+ uint32_t dec_start;
+ uint32_t frac_start;
+ uint32_t lock_comp;
+ uint8_t hr_oclk2;
+ uint8_t hr_oclk3;
+ uint8_t lp_div_mux;
+ uint8_t ndiv;
};
struct mipi_dsi_cmd {
@@ -219,6 +229,8 @@
int mdss_dsi_config(struct msm_fb_panel_data *panel);
int mdss_dsi_phy_init(struct mipi_dsi_panel_config *,
uint32_t ctl_base, uint32_t phy_base);
+void mdss_dsi_phy_contention_detection(struct mipi_dsi_panel_config *,
+ uint32_t phy_base);
int mdss_dsi_video_mode_config(uint16_t disp_width,
uint16_t disp_height,
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 1c2bb08..7ac614e 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -684,6 +684,8 @@
goto error;
}
+ mdss_dsi_phy_contention_detection(&mipi_pinfo, DSI0_PHY_BASE);
+
if (panel->pre_init_func) {
ret = panel->pre_init_func();
if (ret) {
@@ -802,13 +804,12 @@
mdelay(10);
writel(0x0001, DSI_SOFT_RESET);
writel(0x0000, DSI_SOFT_RESET);
- writel(0x1115501, DSI_INT_CTRL);
writel(0, DSI_CTRL);
}
- writel(0x1115501, DSI_INT_CTRL);
+ writel(0x1115501, MIPI_DSI0_BASE + INT_CTRL);
if (pinfo->mipi.broadcast)
- writel(0x1115501, DSI_INT_CTRL + 0x600);
+ writel(0x1115501, MIPI_DSI1_BASE + INT_CTRL);
return NO_ERROR;
}
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
new file mode 100644
index 0000000..754eb18
--- /dev/null
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -0,0 +1,276 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <debug.h>
+#include <reg.h>
+#include <err.h>
+#include <smem.h>
+#include <mipi_dsi.h>
+#include <platform/iomap.h>
+
+#define LPFR_LUT_SIZE 10
+
+#define VCO_REF_CLOCK_RATE 19200000
+
+#define FRAC_DIVIDER 10000
+
+#define MMSS_DSI_PHY_PLL_SYS_CLK_CTRL 0x0000
+#define MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN 0x0004
+#define MMSS_DSI_PHY_PLL_CMN_MODE 0x0008
+#define MMSS_DSI_PHY_PLL_IE_TRIM 0x000C
+#define MMSS_DSI_PHY_PLL_IP_TRIM 0x0010
+#define MMSS_DSI_PHY_PLL_PLL_CNTRL 0x0014
+#define MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL 0x0018
+#define MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL 0x001C
+#define MMSS_DSI_PHY_PLL_PLL_PHSEL_DC 0x0020
+#define MMSS_DSI_PHY_PLL_PLL_IP_SETI 0x0024
+#define MMSS_DSI_PHY_PLL_CORE_CLK_IN_SYNC_SEL 0x0028
+#define MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN 0x002C
+
+#define MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN 0x0030
+#define MMSS_DSI_PHY_PLL_PLL_CP_SETI 0x0034
+#define MMSS_DSI_PHY_PLL_PLL_IP_SETP 0x0038
+#define MMSS_DSI_PHY_PLL_PLL_CP_SETP 0x003C
+#define MMSS_DSI_PHY_PLL_ATB_SEL1 0x0040
+#define MMSS_DSI_PHY_PLL_ATB_SEL2 0x0044
+#define MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND 0x0048
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL 0x004C
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL2 0x0050
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL3 0x0054
+#define MMSS_DSI_PHY_PLL_RESETSM_PLL_CAL_COUNT1 0x0058
+#define MMSS_DSI_PHY_PLL_RESETSM_PLL_CAL_COUNT2 0x005C
+#define MMSS_DSI_PHY_PLL_DIV_REF1 0x0060
+#define MMSS_DSI_PHY_PLL_DIV_REF2 0x0064
+#define MMSS_DSI_PHY_PLL_KVCO_COUNT1 0x0068
+#define MMSS_DSI_PHY_PLL_KVCO_COUNT2 0x006C
+#define MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL 0x0070
+#define MMSS_DSI_PHY_PLL_KVCO_CODE 0x0074
+#define MMSS_DSI_PHY_PLL_VREF_CFG1 0x0078
+#define MMSS_DSI_PHY_PLL_VREF_CFG2 0x007C
+#define MMSS_DSI_PHY_PLL_VREF_CFG3 0x0080
+#define MMSS_DSI_PHY_PLL_VREF_CFG4 0x0084
+#define MMSS_DSI_PHY_PLL_VREF_CFG5 0x0088
+#define MMSS_DSI_PHY_PLL_VREF_CFG6 0x008C
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP1 0x0090
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP2 0x0094
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP3 0x0098
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN 0x009C
+
+#define MMSS_DSI_PHY_PLL_BGTC 0x00A0
+#define MMSS_DSI_PHY_PLL_PLL_TEST_UPDN 0x00A4
+#define MMSS_DSI_PHY_PLL_PLL_VCO_TUNE 0x00A8
+#define MMSS_DSI_PHY_PLL_DEC_START1 0x00AC
+#define MMSS_DSI_PHY_PLL_PLL_AMP_OS 0x00B0
+#define MMSS_DSI_PHY_PLL_SSC_EN_CENTER 0x00B4
+#define MMSS_DSI_PHY_PLL_SSC_ADJ_PER1 0x00B8
+#define MMSS_DSI_PHY_PLL_SSC_ADJ_PER2 0x00BC
+#define MMSS_DSI_PHY_PLL_SSC_PER1 0x00C0
+#define MMSS_DSI_PHY_PLL_SSC_PER2 0x00C4
+#define MMSS_DSI_PHY_PLL_SSC_STEP_SIZE1 0x00C8
+#define MMSS_DSI_PHY_PLL_SSC_STEP_SIZE2 0x00CC
+#define MMSS_DSI_PHY_PLL_RES_CODE_UP 0x00D0
+#define MMSS_DSI_PHY_PLL_RES_CODE_DN 0x00D4
+#define MMSS_DSI_PHY_PLL_RES_CODE_UP_OFFSET 0x00D8
+#define MMSS_DSI_PHY_PLL_RES_CODE_DN_OFFSET 0x00DC
+#define MMSS_DSI_PHY_PLL_RES_CODE_START_SEG1 0x00E0
+#define MMSS_DSI_PHY_PLL_RES_CODE_START_SEG2 0x00E4
+#define MMSS_DSI_PHY_PLL_RES_CODE_CAL_CSR 0x00E8
+#define MMSS_DSI_PHY_PLL_RES_CODE 0x00EC
+#define MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL 0x00F0
+#define MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL2 0x00F4
+#define MMSS_DSI_PHY_PLL_RES_TRIM_EN_VCOCALDONE 0x00F8
+#define MMSS_DSI_PHY_PLL_FAUX_EN 0x00FC
+
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START1 0x0100
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START2 0x0104
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START3 0x0108
+#define MMSS_DSI_PHY_PLL_DEC_START2 0x010C
+#define MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN 0x0110
+#define MMSS_DSI_PHY_PLL_PLL_CRCTRL 0x0114
+#define MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL 0x013C
+#define MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL 0x0140
+#define MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER 0x0144
+#define MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER 0x0148
+#define MMSS_DSI_PHY_PLL_PLL_VCO_HIGH 0x014C
+#define MMSS_DSI_PHY_PLL_RESET_SM 0x0150
+
+uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base)
+{
+ uint32_t cnt, status;
+
+ udelay(1000);
+
+ /* check pll lock first */
+ for (cnt = 0; cnt < 5; cnt++) {
+ status = readl(pll_base + MMSS_DSI_PHY_PLL_RESET_SM);
+ dprintf(SPEW, "%s: pll_base=%x cnt=%d status=%x\n",
+ __func__, pll_base, cnt, status);
+ status &= 0x20; /* bit 5 */
+ if (status)
+ break;
+ udelay(5000);
+ }
+
+ if (!status)
+ goto pll_done;
+
+ /* check pll ready */
+ for (cnt = 0; cnt < 5; cnt++) {
+ status = readl(pll_base + MMSS_DSI_PHY_PLL_RESET_SM);
+ dprintf(SPEW, "%s: pll_base=%x cnt=%d status=%x\n",
+ __func__, pll_base, cnt, status);
+ status &= 0x40; /* bit 6 */
+ if (status)
+ break;
+ udelay(5000);
+ }
+
+pll_done:
+ return status;
+}
+
+uint32_t mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base)
+{
+ writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG1);
+ writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG2);
+ writel(0x15, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL);
+
+ writel(0x20, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL);
+ writel(0x07, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL2);
+ writel(0x02, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+}
+
+static void pll_20nm_phy_kvco_config(uint32_t pll_base)
+{
+
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_DIV_REF1);
+ writel(0x01, pll_base + MMSS_DSI_PHY_PLL_DIV_REF2);
+ writel(0x8a, pll_base + MMSS_DSI_PHY_PLL_KVCO_COUNT1);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CODE);
+}
+
+static void pll_20nm_phy_loop_bw_config(uint32_t pll_base)
+{
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_IP_SETI);
+ writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_PLL_CP_SETI);
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_IP_SETP);
+ writel(0x1f, pll_base + MMSS_DSI_PHY_PLL_PLL_CP_SETP);
+ writel(0x77, pll_base + MMSS_DSI_PHY_PLL_PLL_CRCTRL);
+}
+
+static void pll_20nm_phy_config(uint32_t pll_base)
+{
+ writel(0x40, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CMN_MODE);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IE_TRIM);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IP_TRIM);
+ writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL);
+ writel(0x0e, pll_base + MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_DC);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CORE_CLK_IN_SYNC_SEL);
+ writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN);
+ writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL1);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL2);
+ writel(0x4b, pll_base + MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND);
+ udelay(1000);
+
+ pll_20nm_phy_kvco_config(pll_base);
+
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG1);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG2);
+ writel(0x10, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG3);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG4);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_BGTC);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_TEST_UPDN);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCO_TUNE);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_AMP_OS);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_SSC_EN_CENTER);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_UP);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_DN);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_CAL_CSR);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_EN_VCOCALDONE);
+ writel(0x0c, pll_base + MMSS_DSI_PHY_PLL_FAUX_EN);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN);
+
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL);
+ udelay(1000);
+
+ pll_20nm_phy_loop_bw_config(pll_base);
+}
+
+int32_t mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd)
+{
+ uint32_t data;
+
+ mdss_dsi_phy_sw_reset(ctl_base);
+ pll_20nm_phy_config(pll_base);
+
+ /* set up divider */
+ data = readl(pll_base + MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
+ data |= 0x080; /* bit 7 */
+ data |= (pd->lp_div_mux << 5);
+ data |= pd->ndiv;
+
+ writel(data, pll_base + MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
+
+ writel(pd->hr_oclk2, pll_base + MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER);
+ writel(pd->hr_oclk3, pll_base + MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER);
+
+ writel(((pd->frac_start & 0x7f) | 0x80),
+ pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START1);
+ writel((((pd->frac_start >> 7) & 0x7f) | 0x80),
+ pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START2);
+ writel((((pd->frac_start >> 14) & 0x3f) | 0x40),
+ pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START3);
+
+ writel(((pd->dec_start & 0x7f) | 0x80),
+ pll_base + MMSS_DSI_PHY_PLL_DEC_START1);
+ writel((((pd->dec_start & 0x80) >> 7) | 0x02),
+ pll_base + MMSS_DSI_PHY_PLL_DEC_START2);
+
+ writel((pd->lock_comp & 0xff),
+ pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP1);
+
+ writel(((pd->lock_comp >> 8) & 0xff),
+ pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP2);
+
+ writel(((pd->lock_comp >> 16) & 0xff),
+ pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP3);
+
+ /*
+ * Make sure that PLL vco configuration is complete
+ * before controlling the state machine.
+ */
+ udelay(1000);
+ dmb();
+}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 1170bb6..cd2d217 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -36,6 +36,23 @@
#define MIPI_DSI1_BASE MIPI_DSI_BASE
#endif
+#define MMSS_DSI_CLKOUT_TIMING_CTRL 0x0c4
+#define MMSS_DSI_PHY_TIMING_CTRL_0 0x0140
+#define MMSS_DSI_PHY_CTRL_0 0x0170
+#define MMSS_DSI_PHY_CTRL_1 0x0174
+#define MMSS_DSI_PHY_CTRL_2 0x0178
+#define MMSS_DSI_PHY_STRENGTH_CTRL_0 0x0184
+#define MMSS_DSI_PHY_STRENGTH_CTRL_1 0x0188
+#define MMSS_DSI_PHY_BIST_CTRL_0 0x01b4
+#define MMSS_DSI_PHY_GLBL_TEST_CTRL 0x01d4
+#define MMSS_DSI_PHY_LDO_CTRL 0x01dc
+
+#define TOTAL_TIMING_CTRL_CONFIG 12
+#define TOTAL_BIST_CTRL_CONFIG 6
+/* 4 data lanes and 1 clock lanes */
+#define TOTAL_LANE_COUNT 5
+#define CONFIG_REG_FOR_EACH_LANE 9
+
static void mipi_dsi_calibration(void)
{
uint32_t i = 0;
@@ -274,7 +291,7 @@
return 0;
}
-int mdss_dsi_phy_init(struct mipi_dsi_panel_config *pinfo,
+static int mdss_dsi_phy_28nm_init(struct mipi_dsi_panel_config *pinfo,
uint32_t ctl_base, uint32_t phy_base)
{
struct mdss_dsi_phy_ctrl *pd;
@@ -310,8 +327,6 @@
/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
writel(0x5f, phy_base + 0x0170);
- /* Strength ctrl 1 */
- writel(pd->strength[1], phy_base + 0x0188);
dmb();
/* 4 lanes + clk lane configuration */
/* lane config n * (0 - 4) & DataPath setup */
@@ -349,3 +364,96 @@
dmb();
}
+
+void mdss_dsi_phy_contention_detection(
+ struct mipi_dsi_panel_config *pinfo,
+ uint32_t phy_base)
+{
+ struct mdss_dsi_phy_ctrl *pd;
+
+ if (mdp_get_revision() == MDP_REV_304)
+ return;
+
+ pd = (pinfo->mdss_dsi_phy_config);
+ writel(pd->strength[1], phy_base + 0x0188);
+ dmb();
+}
+
+static int mdss_dsi_phy_20nm_init(struct mipi_dsi_panel_config *pinfo,
+ uint32_t ctl_base, uint32_t phy_base)
+{
+ struct mdss_dsi_phy_ctrl *pd = pinfo->mdss_dsi_phy_config;
+ uint32_t i, off = 0, ln, offset;
+
+ /* Strength ctrl 0 */
+ writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0);
+
+ if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE)
+ pd->regulator[0] = 0x2; /* LDO mode */
+ mdss_dsi_phy_regulator_init(pd);
+
+ if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE)
+ writel(0x25, phy_base + MMSS_DSI_PHY_LDO_CTRL); /* LDO mode */
+ else
+ writel(0x00, phy_base + MMSS_DSI_PHY_LDO_CTRL); /* DCDC mode */
+
+ off = MMSS_DSI_PHY_TIMING_CTRL_0;
+ for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) {
+ writel(pd->timing[i], phy_base + off);
+ dmb();
+ }
+
+ /* Currently the Phy settings for the DSI 0 is done in clk prepare*/
+ if (phy_base == DSI1_PHY_BASE) {
+ writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1);
+ writel(0x05, phy_base + MMSS_DSI_PHY_CTRL_0);
+ dmb();
+
+ writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0);
+ dmb();
+
+ /* BITCLK_HS_SEL should be set to 0 for left */
+ writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL);
+
+ writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_2);
+ writel(0x02, phy_base + MMSS_DSI_PHY_CTRL_2);
+ writel(0x03, phy_base + MMSS_DSI_PHY_CTRL_2);
+ dmb();
+ }
+
+ writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
+ dmb();
+
+ for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) {
+ off = (ln * 0x40);
+ for (i = 0; i < CONFIG_REG_FOR_EACH_LANE; i++, off += 4) {
+ offset = i + (ln * CONFIG_REG_FOR_EACH_LANE);
+ writel(pd->laneCfg[offset], phy_base + off);
+ dmb();
+ }
+ }
+
+ dmb();
+
+ off = MMSS_DSI_PHY_BIST_CTRL_0;
+ for (i = 0; i < TOTAL_BIST_CTRL_CONFIG; i++, off +=4) {
+ writel(pd->bistCtrl[i], phy_base + off);
+ }
+ dmb();
+
+ writel(0x41b, ctl_base + MMSS_DSI_CLKOUT_TIMING_CTRL);
+ dmb();
+}
+
+int mdss_dsi_phy_init (struct mipi_dsi_panel_config *pinfo,
+ uint32_t ctl_base, uint32_t phy_base)
+{
+ int ret;
+
+ if (pinfo->mdss_dsi_phy_config->is_pll_20nm)
+ ret = mdss_dsi_phy_20nm_init(pinfo, ctl_base, phy_base);
+ else
+ ret = mdss_dsi_phy_28nm_init(pinfo, ctl_base, phy_base);
+
+ return ret;
+}
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index fa49ff0..f5f6dce 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -404,6 +404,7 @@
endif
ifeq ($(PLATFORM),msm8994)
+DEFINES += DISPLAY_TYPE_MDSS=1
OBJS += $(LOCAL_DIR)/qgic.o \
$(LOCAL_DIR)/qtimer.o \
$(LOCAL_DIR)/qtimer_mmap.o \
@@ -431,7 +432,13 @@
$(LOCAL_DIR)/crypto_hash.o \
$(LOCAL_DIR)/crypto5_eng.o \
$(LOCAL_DIR)/crypto5_wrapper.o \
- $(LOCAL_DIR)/qusb2_phy.o
+ $(LOCAL_DIR)/qusb2_phy.o \
+ $(LOCAL_DIR)/mdp5.o \
+ $(LOCAL_DIR)/display.o \
+ $(LOCAL_DIR)/mipi_dsi.o \
+ $(LOCAL_DIR)/mipi_dsi_phy.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll_20nm.o
endif
ifeq ($(PLATFORM),ferrum)
diff --git a/platform/msmzirc/include/platform/iomap.h b/platform/msmzirc/include/platform/iomap.h
index a401803..f8e9cf3 100644
--- a/platform/msmzirc/include/platform/iomap.h
+++ b/platform/msmzirc/include/platform/iomap.h
@@ -171,6 +171,11 @@
#define QUSB2_PHY_BASE 0x00079000
#define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4)
#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00041028)
+#define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4)
+#define QUSB2PHY_PORT_TUNE1 (QUSB2_PHY_BASE + 0x00000080)
+#define QUSB2PHY_PORT_TUNE2 (QUSB2_PHY_BASE + 0x00000084)
+#define QUSB2PHY_PORT_TUNE3 (QUSB2_PHY_BASE + 0x00000088)
+#define QUSB2PHY_PORT_TUNE4 (QUSB2_PHY_BASE + 0x0000008C)
/* SS QMP (Qulacomm Multi Protocol) */
#define QMP_PHY_BASE 0x78000
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index 3aa2379..1dd3a66 100755
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -382,7 +382,7 @@
buf_size -= LK_OVERRIDE_PANEL_LEN;
strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
} else {
- ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+ ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
return ret;
@@ -394,20 +394,20 @@
panel_name += strspn(panel_name, " ");
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+ || (!strcmp(panel_name, SIM_VIDEO_PANEL))
+ || (!strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL))) {
+ dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
+ panel_name);
return;
- }
-
- if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+ } else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
dprintf(INFO, "%s: HDMI is primary\n", __func__);
return;
}
ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR);
- if (ret) {
+ if (ret)
msm_display_off();
- }
}
void target_display_shutdown(void)
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index d21fb94..355d8c9 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -389,7 +389,7 @@
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(pbuf, buf_size);
+ return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
void target_display_init(const char *panel_name)
@@ -398,8 +398,10 @@
uint32_t ret = 0;
uint32_t fb_addr = MIPI_FB_ADDR;
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+ || (!strcmp(panel_name, SIM_VIDEO_PANEL))) {
+ dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
+ panel_name);
return;
}
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index cb9f3ce..66dbbdd 100755
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -164,7 +164,7 @@
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(pbuf, buf_size);
+ return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
void target_display_init(const char *panel_name)
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index 44c3db3..ba16ac1 100755
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -363,7 +363,7 @@
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(pbuf, buf_size);
+ return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
void target_display_init(const char *panel_name)
@@ -371,8 +371,10 @@
uint32_t panel_loop = 0;
uint32_t ret = 0;
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+ || (!strcmp(panel_name, SIM_VIDEO_PANEL))) {
+ dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
+ panel_name);
return;
}
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 7d985a3..1c236b6 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -382,7 +382,7 @@
buf_size -= LK_OVERRIDE_PANEL_LEN;
strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
} else {
- ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+ ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
}
return ret;
@@ -399,16 +399,16 @@
panel_name += strspn(panel_name, " ");
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+ || (!strcmp(panel_name, SIM_VIDEO_PANEL))
+ || (!strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL))) {
+ dprintf(INFO, "Selected panel: %s\nSkip panel configuration",
+ panel_name);
return;
- }
-
- if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+ } else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
dprintf(INFO, "%s: HDMI is primary\n", __func__);
return;
}
-
switch (hw_id) {
case HW_PLATFORM_LIQUID:
edp_panel_init(&(panel.panel_info));
diff --git a/target/msm8994/include/target/display.h b/target/msm8994/include/target/display.h
new file mode 100644
index 0000000..70e5d76
--- /dev/null
+++ b/target/msm8994/include/target/display.h
@@ -0,0 +1,112 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_DISPLAY_H
+#define _TARGET_DISPLAY_H
+
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
+
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 78, 3, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = { /* lcd_reg_en */
+ "pm8994_gpios", 14, 3, 1, 0, 1
+};
+
+static struct gpio_pin bkl_gpio = { /* lcd_bklt_reg_en */
+ "pmi8994_gpios", 2, 3, 1, 0, 1
+};
+
+static struct gpio_pin pwm_gpio = { /* pmi_mpp01, lpg = 0 */
+ "pmi8994_mpps", 1, 0, 1, 0, 1
+};
+/*---------------------------------------------------------------------------*/
+/* LDO configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+ { "vdd", 14, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+ { "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+ { "vdda", 2, 1, 1250000, 100000, 100, 0, 0, 0, 0},
+ { "vcca", 28, 1, 1000000, 10000, 100, 0, 0, 0, 0},
+};
+
+#define TOTAL_LDO_DEFINED 3
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0x77, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x00, 0x00, 0xb1, 0xff, 0x00, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x03, 0x05, 0x03, 0x00, 0x20, 0x07, 0x01
+};
+
+static const char panel_lane_config[] = {
+0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x88,
+0x02, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x01, 0x88,
+0x02, 0x00, 0x00, 0x40, 0x20, 0x00, 0x00, 0x01, 0x88,
+0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x88,
+0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x88
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x5f, 0x00, 0x00, 0x10
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+#define DISPLAY_CMDLINE_PREFIX " mdss_mdp.panel="
+
+#define MIPI_FB_ADDR 0x03400000
+
+#define MIPI_HSYNC_PULSE_WIDTH 16
+#define MIPI_HSYNC_BACK_PORCH_DCLK 32
+#define MIPI_HSYNC_FRONT_PORCH_DCLK 76
+
+#define MIPI_VSYNC_PULSE_WIDTH 2
+#define MIPI_VSYNC_BACK_PORCH_LINES 2
+#define MIPI_VSYNC_FRONT_PORCH_LINES 4
+
+#define PWM_BL_LPG_CHAN_ID 0
+
+#endif
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index cfd665f..4a3a5c2 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -298,6 +298,22 @@
/* This is filled from board.c */
}
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+ switch(board_hardware_id())
+ {
+ case HW_PLATFORM_SURF:
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_FLUID:
+ dprintf(SPEW, "Target_cont_splash=1\n");
+ return 1;
+ default:
+ dprintf(SPEW, "Target_cont_splash=0\n");
+ return 0;
+ }
+}
+
/* Detect the modem type */
void target_baseband_detect(struct board_data *board)
{
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
new file mode 100644
index 0000000..15049a8
--- /dev/null
+++ b/target/msm8994/oem_panel.c
@@ -0,0 +1,223 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+
+#include "include/panel.h"
+#include "panel_display.h"
+
+/*---------------------------------------------------------------------------*/
+/* GCDB Panel Database */
+/*---------------------------------------------------------------------------*/
+#include "include/panel_sharp_wqxga_dualdsi_video.h"
+#include "include/panel_jdi_qhd_dualdsi_video.h"
+#include "include/panel_jdi_qhd_dualdsi_cmd.h"
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+enum {
+SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
+JDI_QHD_DUALDSI_VIDEO_PANEL,
+JDI_QHD_DUALDSI_CMD_PANEL,
+UNKNOWN_PANEL
+};
+
+/*
+ * The list of panels that are supported on this target.
+ * Any panel in this list can be selected using fastboot oem command.
+ */
+static struct panel_list supp_panels[] = {
+ {"sharp_wqxga_dualdsi_video", SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
+ {"jdi_qhd_dualdsi_video", JDI_QHD_DUALDSI_VIDEO_PANEL},
+ {"jdi_qhd_dualdsi_cmd", JDI_QHD_DUALDSI_CMD_PANEL},
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ /* OEM can keep there panel specific on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+int oem_panel_on()
+{
+ /* OEM can keep there panel specific on instructions in this
+ function */
+ if (panel_id == JDI_QHD_DUALDSI_CMD_PANEL) {
+ /* needs extra delay to avoid unexpected artifacts */
+ mdelay(JDI_QHD_DUALDSI_CMD_PANEL_ON_DELAY);
+
+ }
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /* OEM can keep there panel specific off instructions in this
+ function */
+ return NO_ERROR;
+}
+
+static bool init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ int pan_type;
+
+ phy_db->is_pll_20nm = 1;
+
+ switch (panel_id) {
+ case SHARP_WQXGA_DUALDSI_VIDEO_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ panelstruct->paneldata = &sharp_wqxga_dualdsi_video_panel_data;
+ panelstruct->paneldata->panel_operating_mode = 11;
+ panelstruct->paneldata->panel_with_enable_gpio = 0;
+ panelstruct->panelres = &sharp_wqxga_dualdsi_video_panel_res;
+ panelstruct->color = &sharp_wqxga_dualdsi_video_color;
+ panelstruct->videopanel = &sharp_wqxga_dualdsi_video_video_panel;
+ panelstruct->commandpanel = &sharp_wqxga_dualdsi_video_command_panel;
+ panelstruct->state = &sharp_wqxga_dualdsi_video_state;
+ panelstruct->laneconfig = &sharp_wqxga_dualdsi_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &sharp_wqxga_dualdsi_video_timing_info;
+ panelstruct->panelresetseq
+ = &sharp_wqxga_dualdsi_video_reset_seq;
+ panelstruct->backlightinfo = &sharp_wqxga_dualdsi_video_backlight;
+ pinfo->mipi.panel_cmds
+ = sharp_wqxga_dualdsi_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = SHARP_WQXGA_DUALDSI_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ sharp_wqxga_dualdsi_video_timings, TIMING_SIZE);
+ break;
+ case JDI_QHD_DUALDSI_VIDEO_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ panelstruct->paneldata = &jdi_qhd_dualdsi_video_panel_data;
+ panelstruct->panelres = &jdi_qhd_dualdsi_video_panel_res;
+ panelstruct->color = &jdi_qhd_dualdsi_video_color;
+ panelstruct->videopanel = &jdi_qhd_dualdsi_video_video_panel;
+ panelstruct->commandpanel = &jdi_qhd_dualdsi_video_command_panel;
+ panelstruct->state = &jdi_qhd_dualdsi_video_state;
+ panelstruct->laneconfig = &jdi_qhd_dualdsi_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_qhd_dualdsi_video_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_qhd_dualdsi_video_reset_seq;
+
+ /* force backlight to WLED */
+ panelstruct->backlightinfo = &jdi_qhd_dualdsi_video_backlight;
+ jdi_qhd_dualdsi_video_backlight.bl_interface_type = BL_WLED;
+
+ pinfo->mipi.panel_cmds
+ = jdi_qhd_dualdsi_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = JDI_QHD_DUALDSI_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_qhd_dualdsi_video_timings, TIMING_SIZE);
+ break;
+ case JDI_QHD_DUALDSI_CMD_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ panelstruct->paneldata = &jdi_qhd_dualdsi_cmd_panel_data;
+ panelstruct->panelres = &jdi_qhd_dualdsi_cmd_panel_res;
+ panelstruct->color = &jdi_qhd_dualdsi_cmd_color;
+ panelstruct->videopanel = &jdi_qhd_dualdsi_cmd_video_panel;
+ panelstruct->commandpanel = &jdi_qhd_dualdsi_cmd_command_panel;
+ panelstruct->state = &jdi_qhd_dualdsi_cmd_state;
+ panelstruct->laneconfig = &jdi_qhd_dualdsi_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_qhd_dualdsi_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_qhd_dualdsi_cmd_reset_seq;
+
+ /* force backlight to WLED */
+ jdi_qhd_dualdsi_cmd_backlight.bl_interface_type = BL_WLED;
+ panelstruct->backlightinfo = &jdi_qhd_dualdsi_cmd_backlight;
+
+ pinfo->mipi.panel_cmds
+ = jdi_qhd_dualdsi_cmd_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = JDI_QHD_DUALDSI_CMD_ON_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_qhd_dualdsi_cmd_timings, TIMING_SIZE);
+ break;
+ default:
+ case UNKNOWN_PANEL:
+ pan_type = PANEL_TYPE_UNKNOWN;
+ break;
+ }
+ return pan_type;
+}
+
+bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ int32_t panel_override_id;
+
+ if (panel_name) {
+ panel_override_id = panel_name_to_id(supp_panels,
+ ARRAY_SIZE(supp_panels), panel_name);
+
+ if (panel_override_id < 0) {
+ dprintf(CRITICAL, "Not able to search the panel:%s\n",
+ panel_name + strspn(panel_name, " "));
+ } else if (panel_override_id < UNKNOWN_PANEL) {
+ /* panel override using fastboot oem command */
+ panel_id = panel_override_id;
+
+ dprintf(INFO, "OEM panel override:%s\n",
+ panel_name + strspn(panel_name, " "));
+ goto panel_init;
+ }
+ }
+
+ switch (hw_id) {
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_FLUID:
+ case HW_PLATFORM_SURF:
+ panel_id = SHARP_WQXGA_DUALDSI_VIDEO_PANEL;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n"
+ , hw_id);
+ return PANEL_TYPE_UNKNOWN;
+ }
+
+panel_init:
+ return init_panel_data(panelstruct, pinfo, phy_db);
+}
diff --git a/target/msm8994/rules.mk b/target/msm8994/rules.mk
index e098b17..509c91a 100644
--- a/target/msm8994/rules.mk
+++ b/target/msm8994/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8994
@@ -11,7 +12,7 @@
SCRATCH_ADDR := 0x10000000
-DEFINES += DISPLAY_SPLASH_SCREEN=0
+DEFINES += DISPLAY_SPLASH_SCREEN=1
DEFINES += DISPLAY_TYPE_MIPI=1
DEFINES += DISPLAY_TYPE_DSI6G=1
@@ -20,6 +21,7 @@
dev/pmic/pm8x41 \
dev/qpnp_wled \
lib/ptable \
+ dev/gcdb/display \
lib/libfdt
DEFINES += \
@@ -35,3 +37,5 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
new file mode 100644
index 0000000..57dfe20
--- /dev/null
+++ b/target/msm8994/target_display.c
@@ -0,0 +1,315 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <smem.h>
+#include <err.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <pm8x41.h>
+#include <pm8x41_wled.h>
+#include <qpnp_wled.h>
+#include <board.h>
+#include <mdp5.h>
+#include <scm.h>
+#include <endian.h>
+#include <platform/gpio.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+#include <target/display.h>
+#include "include/panel.h"
+#include "include/display_resource.h"
+
+#define HFPLL_LDO_ID 12
+
+#define GPIO_STATE_LOW 0
+#define GPIO_STATE_HIGH 2
+#define RESET_GPIO_SEQ_LEN 3
+
+#define PWM_DUTY_US 13
+#define PWM_PERIOD_US 27
+#define PMIC_WLED_SLAVE_ID 3
+#define PMIC_MPP_SLAVE_ID 2
+
+static void dsi_pll_20nm_phy_init( uint32_t pll_base, int off)
+{
+ mdss_dsi_pll_20nm_sw_reset_st_machine(pll_base);
+
+ dmb();
+
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
+ writel(0x80, pll_base + off + 0x0174);
+
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
+ writel(0x00, pll_base + off + 0x0174);
+ udelay(5000);
+ /* Strength ctrl 0 */
+ writel(0x77, pll_base + off + 0x0184);
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
+ writel(0x7f, pll_base + off + 0x0170);
+
+ /* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */
+ writel(0x00, pll_base + off + 0x01d4);
+
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_2 */
+ writel(0x00, pll_base + off + 0x0178);
+}
+
+static uint32_t dsi_pll_20nm_enable_seq(uint32_t pll_base)
+{
+ uint32_t pll_locked;
+
+ /*
+ * PLL power up sequence.
+ * Add necessary delays recommeded by hardware.
+ */
+ writel(0x0D, pll_base + 0x9c); /* MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN */
+ writel(0x07, pll_base + 0x14); /* MMSS_DSI_PHY_PLL_PLL_CNTRL */
+ writel(0x00, pll_base + 0x2c); /* MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN */
+ udelay(500);
+
+ dsi_pll_20nm_phy_init(pll_base, 0x200); /* Ctrl 0 */
+ dmb();
+
+ pll_locked = mdss_dsi_pll_20nm_lock_status(pll_base);
+ if (!pll_locked)
+ dprintf(INFO, "%s: DSI PLL lock failed\n", __func__);
+ else
+ dprintf(INFO, "%s: DSI PLL lock Success\n", __func__);
+
+ return pll_locked;
+}
+
+static int msm8994_wled_backlight_ctrl(uint8_t enable)
+{
+ uint8_t slave_id = 3;
+
+ if (enable) {
+ pm8x41_wled_config_slave_id(slave_id);
+ qpnp_wled_enable_backlight(enable);
+ }
+ qpnp_ibb_enable(enable);
+ return NO_ERROR;
+}
+
+static int msm8994_pwm_backlight_ctrl(uint8_t enable)
+{
+ dprintf(INFO, "%s: NOt implemented\n", __func__);
+ return NO_ERROR;
+}
+
+void lcd_reg_en(void)
+{
+ struct pm8x41_gpio gpio = {
+ .direction = PM_GPIO_DIR_OUT,
+ .function = PM_GPIO_FUNC_HIGH,
+ .vin_sel = 2, /* VIN_2 */
+ .output_buffer = PM_GPIO_OUT_CMOS,
+ .out_strength = PM_GPIO_OUT_DRIVE_MED,
+ };
+
+ pm8x41_gpio_config(14, &gpio);
+ pm8x41_gpio_set(14, 1);
+}
+
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
+{
+ uint32_t ret = NO_ERROR;
+ struct pm8x41_mpp mpp;
+ int rc;
+
+ if (!bl) {
+ dprintf(CRITICAL, "backlight structure is not available\n");
+ return ERR_INVALID_ARGS;
+ }
+
+ switch (bl->bl_interface_type) {
+ case BL_WLED:
+ /* Enable MPP4 */
+ pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID);
+ mpp.base = PM8x41_MMP4_BASE;
+ mpp.vin = MPP_VIN2;
+ if (enable) {
+ pm_pwm_enable(false);
+ rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
+ if (rc < 0) {
+ mpp.mode = MPP_HIGH;
+ } else {
+ mpp.mode = MPP_DTEST1;
+ pm_pwm_enable(true);
+ }
+ pm8x41_config_output_mpp(&mpp);
+ pm8x41_enable_mpp(&mpp, MPP_ENABLE);
+ } else {
+ pm_pwm_enable(false);
+ pm8x41_enable_mpp(&mpp, MPP_DISABLE);
+ }
+ /* Need delay before power on regulators */
+ mdelay(20);
+ /* Enable WLED backlight control */
+ ret = msm8994_wled_backlight_ctrl(enable);
+ break;
+ case BL_PWM:
+ ret = msm8994_pwm_backlight_ctrl(enable);
+ break;
+ default:
+ dprintf(CRITICAL, "backlight type:%d not supported\n",
+ bl->bl_interface_type);
+ return ERR_NOT_SUPPORTED;
+ }
+
+ return ret;
+}
+
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ uint32_t ret;
+ struct mdss_dsi_pll_config *pll_data;
+ uint32_t dual_dsi = pinfo->mipi.dual_dsi;
+
+ pll_data = pinfo->mipi.dsi_pll_config;
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mmss_bus_clock_enable();
+ mdp_clock_enable();
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(0);
+ return ret;
+ }
+ mdss_dsi_auto_pll_20nm_config(DSI0_PLL_BASE,
+ MIPI_DSI0_BASE, pll_data);
+ dsi_pll_20nm_enable_seq(DSI0_PLL_BASE);
+ mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
+ pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
+ } else if(!target_cont_splash_screen()) {
+ /* Disable clocks if continuous splash off */
+ mmss_dsi_clock_disable(dual_dsi);
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return NO_ERROR;
+}
+
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
+{
+ uint32_t i = 0;
+
+ if (enable) {
+ gpio_tlmm_config(reset_gpio.pin_id, 0,
+ reset_gpio.pin_direction, reset_gpio.pin_pull,
+ reset_gpio.pin_strength, reset_gpio.pin_state);
+ /* reset */
+ for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
+ if (resetseq->pin_state[i] == GPIO_STATE_LOW)
+ gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
+ else
+ gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
+ mdelay(resetseq->sleep[i]);
+ }
+ } else {
+ gpio_set(reset_gpio.pin_id, 0);
+ }
+
+ return NO_ERROR;
+}
+
+int target_ldo_ctrl(uint8_t enable)
+{
+ if (enable) {
+ regulator_enable(); /* L2, L12, L14, and L28 */
+ mdelay(10);
+ qpnp_ibb_enable(true); /* +5V and -5V */
+ mdelay(50);
+ } else {
+ regulator_disable();
+ }
+
+ return NO_ERROR;
+}
+
+int target_display_pre_on()
+{
+ writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0);
+ writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1);
+ writel(0xC0000CCD, MDP_CLK_CTRL0);
+ writel(0xD0000CCC, MDP_CLK_CTRL1);
+ writel(0x00CCCCCC, MDP_CLK_CTRL2);
+ writel(0x000000CC, MDP_CLK_CTRL6);
+ writel(0x0CCCC0C0, MDP_CLK_CTRL3);
+ writel(0xCCCCC0C0, MDP_CLK_CTRL4);
+ writel(0xCCCCC0C0, MDP_CLK_CTRL5);
+ writel(0x00CCC000, MDP_CLK_CTRL7);
+
+ writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF0);
+ writel(0x08000808, VBIF_VBIF_IN_RD_LIM_CONF1);
+ writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF2);
+ writel(0x00000808, VBIF_VBIF_IN_RD_LIM_CONF3);
+ writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF0);
+ writel(0x00100000, VBIF_VBIF_IN_WR_LIM_CONF1);
+ writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF2);
+ writel(0x00000000, VBIF_VBIF_IN_WR_LIM_CONF3);
+ writel(0x00013fff, VBIF_VBIF_ABIT_SHORT);
+ writel(0x000000A4, VBIF_VBIF_ABIT_SHORT_CONF);
+ writel(0x00003FFF, VBIF_VBIF_GATE_OFF_WRREQ_EN);
+ writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
+
+ return NO_ERROR;
+}
+
+bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
+{
+ int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
+ bool ret = true;
+
+ ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
+
+ return ret;
+}
+
+void target_display_init(const char *panel_name)
+{
+ if (gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR))
+ msm_display_off();
+}
+
+void target_display_shutdown(void)
+{
+ gcdb_display_shutdown();
+}