Merge "platform: msm8996: Enable write back cache"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 1876c6e..fe1218b 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -141,7 +141,7 @@
/* make 4096 as default size to ensure EFS,EXT4's erasing */
#define DEFAULT_ERASE_SIZE 4096
-#define MAX_PANEL_BUF_SIZE 128
+#define MAX_PANEL_BUF_SIZE 196
#define DISPLAY_DEFAULT_PREFIX "mdss_mdp"
#define BOOT_DEV_MAX_LEN 64
@@ -1854,6 +1854,7 @@
info->is_unlocked = 1;
info->is_tampered = 0;
info->charger_screen_enabled = 0;
+ info->verity_mode = 1; //enforcing by default
write_device_info(info);
}
memcpy(dev, info, sizeof(device_info));
@@ -1964,6 +1965,9 @@
void cmd_boot(const char *arg, void *data, unsigned sz)
{
+#ifdef MDTP_SUPPORT
+ static bool is_mdtp_activated = 0;
+#endif /* MDTP_SUPPORT */
unsigned kernel_actual;
unsigned ramdisk_actual;
uint32_t image_actual;
@@ -2037,18 +2041,14 @@
else
{
/* fastboot boot is not allowed when MDTP is activated */
-
mdtp_ext_partition_verification_t ext_partition;
- ext_partition.partition = boot_into_recovery ? MDTP_PARTITION_RECOVERY : MDTP_PARTITION_BOOT;
- ext_partition.integrity_state = MDTP_PARTITION_STATE_UNSET;
- ext_partition.page_size = page_size;
- ext_partition.image_addr = (uint32_t)data;
- ext_partition.image_size = image_actual - sig_actual;
- ext_partition.sig_avail = TRUE;
- mdtp_fwlock_verify_lock(&ext_partition);
+
+ if (!is_mdtp_activated) {
+ ext_partition.partition = MDTP_PARTITION_NONE;
+ mdtp_fwlock_verify_lock(&ext_partition);
+ }
}
- bool is_mdtp_activated = 0;
mdtp_activated(&is_mdtp_activated);
if(is_mdtp_activated){
dprintf(CRITICAL, "fastboot boot command is not available.\n");
diff --git a/app/aboot/mdtp.c b/app/aboot/mdtp.c
index 8ed312b..01f907a 100644
--- a/app/aboot/mdtp.c
+++ b/app/aboot/mdtp.c
@@ -570,38 +570,40 @@
}
else
{
- for(i=0; i<MAX_PARTITIONS; i++)
+ if (ext_partition->partition != MDTP_PARTITION_NONE)
{
- if(dip->partition_cfg[i].lock_enabled && dip->partition_cfg[i].size)
+ for(i=0; i<MAX_PARTITIONS; i++)
{
- total_num_blocks = ((dip->partition_cfg[i].size - 1) / MDTP_FWLOCK_BLOCK_SIZE);
- if (validate_partition_params(dip->partition_cfg[i].size,
- dip->partition_cfg[i].hash_mode,
- dip->partition_cfg[i].verify_ratio))
+ if(dip->partition_cfg[i].lock_enabled && dip->partition_cfg[i].size)
{
- dprintf(CRITICAL, "mdtp: verify_all_partitions: Wrong partition parameters\n");
- verify_failure = TRUE;
- break;
- }
+ total_num_blocks = ((dip->partition_cfg[i].size - 1) / MDTP_FWLOCK_BLOCK_SIZE);
+ if (validate_partition_params(dip->partition_cfg[i].size,
+ dip->partition_cfg[i].hash_mode,
+ dip->partition_cfg[i].verify_ratio))
+ {
+ dprintf(CRITICAL, "mdtp: verify_all_partitions: Wrong partition parameters\n");
+ verify_failure = TRUE;
+ break;
+ }
- verify_failure |= (verify_partition(dip->partition_cfg[i].name,
- dip->partition_cfg[i].size,
- dip->partition_cfg[i].hash_mode,
- (dip->partition_cfg[i].verify_ratio * total_num_blocks) / 100,
- dip->partition_cfg[i].hash_table,
- dip->partition_cfg[i].force_verify_block) != 0);
+ verify_failure |= (verify_partition(dip->partition_cfg[i].name,
+ dip->partition_cfg[i].size,
+ dip->partition_cfg[i].hash_mode,
+ (dip->partition_cfg[i].verify_ratio * total_num_blocks) / 100,
+ dip->partition_cfg[i].hash_table,
+ dip->partition_cfg[i].force_verify_block) != 0);
+ }
+ }
+
+ ext_partition_verify_failure = verify_ext_partition(ext_partition);
+
+ if (verify_failure || ext_partition_verify_failure)
+ {
+ dprintf(CRITICAL, "mdtp: verify_all_partitions: Failed partition verification\n");
+ return;
}
}
-
- ext_partition_verify_failure = verify_ext_partition(ext_partition);
-
- if (verify_failure || ext_partition_verify_failure)
- {
- dprintf(CRITICAL, "mdtp: verify_all_partitions: Failed partition verification\n");
- return;
- }
is_mdtp_activated = 1;
-
}
*verify_result = VERIFY_OK;
@@ -728,7 +730,7 @@
/* Disallow CIPHER_DIP SCM call from this point, unless we are in recovery */
/* The recovery image will disallow CIPHER_DIP SCM call by itself. */
- if (ext_partition->partition != MDTP_PARTITION_RECOVERY)
+ if (ext_partition->partition == MDTP_PARTITION_BOOT)
{
mdtp_tzbsp_disallow_cipher_DIP();
}
@@ -752,7 +754,6 @@
static int mdtp_tzbsp_dec_verify_DIP(DIP_t *enc_dip, DIP_t *dec_dip, uint32_t *verified)
{
unsigned char hash[HASH_LEN];
- unsigned char buf[HASH_LEN], digest[HASH_LEN];
SHA256_CTX sha256_ctx;
int ret;
@@ -763,9 +764,6 @@
arch_clean_invalidate_cache_range((addr_t)enc_dip, sizeof(DIP_t));
arch_invalidate_cache_range((addr_t)dec_dip, sizeof(DIP_t));
- /* workaround: Dummy call to hash_find prevents a boot loop when using the CE from TZ */
- hash_find(buf, HASH_LEN, digest, CRYPTO_AUTH_ALG_SHA1);
-
ret = mdtp_cipher_dip_cmd((uint8_t*)enc_dip, sizeof(DIP_t),
(uint8_t*)dec_dip, sizeof(DIP_t),
DIP_DECRYPT);
@@ -799,7 +797,6 @@
/* Encrypt a given DIP and calculate its integrity information */
static int mdtp_tzbsp_enc_hash_DIP(DIP_t *dec_dip, DIP_t *enc_dip)
{
- unsigned char buf[HASH_LEN], digest[HASH_LEN];
SHA256_CTX sha256_ctx;
int ret;
@@ -813,9 +810,6 @@
arch_clean_invalidate_cache_range((addr_t)dec_dip, sizeof(DIP_t));
arch_invalidate_cache_range((addr_t)enc_dip, sizeof(DIP_t));
- /* workaround: Dummy call to hash_find prevents a boot loop when using the CE from TZ */
- hash_find(buf, HASH_LEN, digest, CRYPTO_AUTH_ALG_SHA1);
-
ret = mdtp_cipher_dip_cmd((uint8_t*)dec_dip, sizeof(DIP_t),
(uint8_t*)enc_dip, sizeof(DIP_t),
DIP_ENCRYPT);
diff --git a/app/aboot/mdtp.h b/app/aboot/mdtp.h
index c29dcc2..03e3b7c 100644
--- a/app/aboot/mdtp.h
+++ b/app/aboot/mdtp.h
@@ -113,6 +113,7 @@
typedef enum {
MDTP_PARTITION_BOOT = 0,
MDTP_PARTITION_RECOVERY,
+ MDTP_PARTITION_NONE,
MDTP_PARTITION_NUM,
} mdtp_ext_partition_t;
diff --git a/arch/arm/include/arch/arm/mmu.h b/arch/arm/include/arch/arm/mmu.h
index 12bcd23..43a474e 100644
--- a/arch/arm/include/arch/arm/mmu.h
+++ b/arch/arm/include/arch/arm/mmu.h
@@ -88,6 +88,7 @@
#define MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_NO_ALLOCATE ATTR_INDEX(5)
#define MMU_MEMORY_AP_READ_WRITE (1 << 6) /* Read/Write at any priveledge */
+#define MMU_MEMORY_AP_READ_ONLY (0x3 << 6) /* Read only priveledge */
#define MMU_MEMORY_XN (1ULL << 54)
#define MMU_MEMORY_PXN (1ULL << 53)
diff --git a/dev/gcdb/display/gcdb_display_param.c b/dev/gcdb/display/gcdb_display_param.c
index 91ce12b..7bc472f 100644
--- a/dev/gcdb/display/gcdb_display_param.c
+++ b/dev/gcdb/display/gcdb_display_param.c
@@ -214,6 +214,10 @@
else if (strstr((char *) panel_name, "#sim"))
oem_data.sim_mode = SIM_MODE;
+ /* disable cont splash when booting in simulator mode */
+ if (oem_data.sim_mode)
+ oem_data.cont_splash = false;
+
}
static bool mdss_dsi_set_panel_node(char *panel_name, char **dsi_id,
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 383d231..998246f 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -40,6 +40,12 @@
#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
#define RESTART_REASON_ADDR2 (MSM_SHARED_IMEM_BASE2 + 0x65C)
+#define DLOAD_MODE_ADDR (MSM_SHARED_IMEM_BASE + 0x0)
+#define EMERGENCY_DLOAD_MODE_ADDR (MSM_SHARED_IMEM_BASE + 0xFE0)
+#define DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE2 + 0x0)
+#define EMERGENCY_DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE2 + 0xFE0)
+
+
#define BS_INFO_OFFSET (0x6B0)
#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
#define BS_INFO_ADDR2 (MSM_SHARED_IMEM_BASE2 + BS_INFO_OFFSET)
diff --git a/platform/msm8996/include/platform/iomap.h b/platform/msm8996/include/platform/iomap.h
index 758182e..2ae1d17 100644
--- a/platform/msm8996/include/platform/iomap.h
+++ b/platform/msm8996/include/platform/iomap.h
@@ -191,7 +191,7 @@
* as device memory, define the start address
* and size in MB
*/
-#define RPMB_SND_RCV_BUF 0x90F00000
+#define RPMB_SND_RCV_BUF 0x91400000
#define RPMB_SND_RCV_BUF_SZ 0x2
#define TCSR_BOOT_MISC_DETECT 0x007B3000
diff --git a/platform/msm8996/platform.c b/platform/msm8996/platform.c
index 6ec83d7..090e81c 100644
--- a/platform/msm8996/platform.c
+++ b/platform/msm8996/platform.c
@@ -57,6 +57,10 @@
#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+/* downlaod mode memory - cacheable, write through */
+#define DLOAD_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_ONLY | MMU_MEMORY_XN)
+
static uint64_t ddr_start;
static mmu_section_t default_mmu_section_table[] =
@@ -77,10 +81,12 @@
};
+/* Map the ddr for download mode, this region belongs to non-hlos images and pil */
static mmu_section_t dload_mmu_section_table[] =
{
-/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
- { 0x85800000, 0x85800000, MMU_L2_NS_SECTION_MAPPING, 178, COMMON_MEMORY},
+/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
+ { 0x85800000, 0x85800000, MMU_L2_NS_SECTION_MAPPING, 8, DLOAD_MEMORY},
+ { 0x86200000, 0x86200000, MMU_L2_NS_SECTION_MAPPING, 174, DLOAD_MEMORY},
};
void platform_early_init(void)
@@ -119,14 +125,23 @@
int table_sz = ARRAY_SIZE(default_mmu_section_table);
mmu_section_t kernel_mmu_section_table;
uint64_t ddr_size = smem_get_ddr_size();
+ uint32_t kernel_size = 0;
if (ddr_size == MEM_4GB)
{
ddr_start = 0x80000000;
+ /* As per the memory map when DDR is 4GB first 88 MB is hlos memory
+ * use this for loading the kernel
+ */
+ kernel_size = 88;
}
else if (ddr_size == MEM_3GB)
{
ddr_start = 0x20000000;
+ /* As per memory map wheh DDR is 3GB the first 512 MB is assigned to hlos
+ * use this region for loading kernel
+ */
+ kernel_size = 512;
}
else
{
@@ -137,8 +152,8 @@
kernel_mmu_section_table.paddress = ddr_start;
kernel_mmu_section_table.vaddress = ddr_start;
kernel_mmu_section_table.type = MMU_L2_NS_SECTION_MAPPING;
- kernel_mmu_section_table.size = KERNEL_SIZE;
- kernel_mmu_section_table.flags = COMMON_MEMORY;
+ kernel_mmu_section_table.size = kernel_size;
+ kernel_mmu_section_table.flags = SCRATCH_MEMORY;
/* Map kernel entry */
arm_mmu_map_entry(&kernel_mmu_section_table);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 59c0125..baa1b37 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -484,7 +484,8 @@
$(LOCAL_DIR)/mipi_dsi_autopll.o \
$(LOCAL_DIR)/mipi_dsi_autopll_20nm.o \
$(LOCAL_DIR)/mdss_hdmi.o \
- $(LOCAL_DIR)/hdmi_pll_20nm.o
+ $(LOCAL_DIR)/hdmi_pll_20nm.o \
+ $(LOCAL_DIR)/dload_util.o
endif
ifeq ($(PLATFORM),msm8909)
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index f2d0feb..e3b513f 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -513,7 +513,7 @@
/* Write the reboot reason */
writel(reboot_reason, restart_reason_addr);
- if(reboot_reason == FASTBOOT_MODE)
+ if(reboot_reason == FASTBOOT_MODE || reboot_reason == DLOAD)
reset_type = PON_PSHOLD_WARM_RESET;
else
reset_type = PON_PSHOLD_HARD_RESET;
@@ -635,3 +635,15 @@
{
return DDR_CFG_DLY_VAL;
}
+
+int set_download_mode(enum dload_mode mode)
+{
+ if (platform_is_msm8994())
+ dload_util_write_cookie(mode == NORMAL_DLOAD ?
+ DLOAD_MODE_ADDR : EMERGENCY_DLOAD_MODE_ADDR, mode);
+ else
+ dload_util_write_cookie(mode == NORMAL_DLOAD ?
+ DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode);
+
+ return 0;
+}
diff --git a/target/msm8996/rules.mk b/target/msm8996/rules.mk
index d9349f7..2205f60 100644
--- a/target/msm8996/rules.mk
+++ b/target/msm8996/rules.mk
@@ -5,14 +5,13 @@
PLATFORM := msm8996
-MEMBASE := 0x90B00000 # SDRAM
+MEMBASE := 0x91000000 # SDRAM
MEMSIZE := 0x00400000 # 4MB
BASE_ADDR := 0x0000000
-SCRATCH_ADDR := 0x91100000
-SCRATCH_SIZE := 750
-KERNEL_SIZE := 512
+SCRATCH_ADDR := 0x91600000
+SCRATCH_SIZE := 746
# LPAE supports only 32 virtual address, L1 pt size is 4
L1_PT_SZ := 4
L2_PT_SZ := 3
@@ -36,7 +35,6 @@
MEMBASE=$(MEMBASE) \
BASE_ADDR=$(BASE_ADDR) \
TAGS_ADDR=$(TAGS_ADDR) \
- KERNEL_SIZE=$(KERNEL_SIZE) \
RAMDISK_ADDR=$(RAMDISK_ADDR) \
SCRATCH_ADDR=$(SCRATCH_ADDR) \
SCRATCH_SIZE=$(SCRATCH_SIZE) \