Merge "target: Update target backlight control API"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 71c6128..a8a7e66 100755
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -1454,7 +1454,7 @@
check_aboot_addr_range_overlap(hdr->ramdisk_addr, ramdisk_actual))
{
dprintf(CRITICAL, "kernel/ramdisk addresses overlap with aboot addresses.\n");
- return -1;
+ return;
}
/* sz should have atleast raw boot image */
@@ -1472,7 +1472,7 @@
if (check_aboot_addr_range_overlap(hdr->tags_addr, MAX_TAGS_SIZE))
{
dprintf(CRITICAL, "Tags addresses overlap with aboot addresses.\n");
- return -1;
+ return;
}
#endif
@@ -1502,7 +1502,7 @@
if (check_aboot_addr_range_overlap(hdr->tags_addr, MAX_TAGS_SIZE))
{
dprintf(CRITICAL, "Tags addresses overlap with aboot addresses.\n");
- return -1;
+ return;
}
#endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_wled.h b/dev/pmic/pm8x41/include/pm8x41_wled.h
index 92632ca..8ad7370 100644
--- a/dev/pmic/pm8x41/include/pm8x41_wled.h
+++ b/dev/pmic/pm8x41/include/pm8x41_wled.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -32,7 +32,7 @@
#define PM_WLED_BASE 0x0D800
#define PM_WLED_CTNL_REG(n) (PM_WLED_BASE + n)
-#define PM_WLED_LED_CTNL_REG(n) (PM_WLED_BASE + 0x60 + (n-1)*10)
+#define PM_WLED_LED_CTNL_REG(n) (PM_WLED_BASE + 0x60 + (n-1)*0x10)
#define PM_WLED_LED1_BRIGHTNESS_LSB PM_WLED_CTNL_REG(0x40)
#define PM_WLED_LED1_BRIGHTNESS_MSB PM_WLED_CTNL_REG(0x41)
diff --git a/platform/init.c b/platform/init.c
index a809501..5001373 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -101,3 +101,7 @@
{
return 0;
}
+
+__WEAK void clock_config_cdc(uint8_t slot)
+{
+}
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index e66208c..da1b024 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -128,6 +128,10 @@
{
ret = clk_get_set_enable(clk_name, 400000, 1);
}
+ else if(freq == MMC_CLK_25MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 25000000, 1);
+ }
else if(freq == MMC_CLK_50MHZ)
{
ret = clk_get_set_enable(clk_name, 50000000, 1);
@@ -136,10 +140,18 @@
{
ret = clk_get_set_enable(clk_name, 100000000, 1);
}
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
+ }
else if(freq == MMC_CLK_200MHZ)
{
ret = clk_get_set_enable(clk_name, 200000000, 1);
}
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
else
{
dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
@@ -159,6 +171,29 @@
#endif
}
+/* Configure clocks needed for CDCLP533 circuit */
+void clock_config_cdc(uint32_t interface)
+{
+ int ret = 0;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_sleep_clk", interface);
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_ff_clk", interface);
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
+ ASSERT(0);
+ }
+}
+
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 42a436f..dcb0ba8 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -150,6 +150,9 @@
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
+/* GPLL4 */
+#define GPLL4_STATUS (CLK_CTL_BASE + 0x1DDC)
+
/* SDCC */
#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
@@ -161,6 +164,10 @@
#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+/* SDCC clocks for CDC calibration*/
+#define SDCC1_CDCCAL_SLEEP_CBCR (CLK_CTL_BASE + 0x04E4)
+#define SDCC1_CDCCAL_FF_CBCR (CLK_CTL_BASE + 0x04E8)
+
/* SDCC2 */
#define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */
#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */
diff --git a/platform/msm8974/msm8974-clock.c b/platform/msm8974/msm8974-clock.c
index 68000d5..e2209c2 100644
--- a/platform/msm8974/msm8974-clock.c
+++ b/platform/msm8974/msm8974-clock.c
@@ -39,6 +39,7 @@
/* Mux source select values */
#define cxo_source_val 0
#define gpll0_source_val 1
+#define gpll4_source_val 5
#define cxo_mm_source_val 0
#define mmpll0_mm_source_val 1
#define mmpll1_mm_source_val 2
@@ -115,8 +116,41 @@
},
};
+static struct pll_vote_clk gpll4_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(4),
+ .status_reg = (void *) GPLL4_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 768000000,
+ .dbg_name = "gpll4_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
/* SDCC Clocks */
-static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+/* This table is for sdc1 apps clk only for MSM8974 PRO AC */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_ac[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F(192000000, gpll4, 4, 0, 0),
+ F(384000000, gpll4, 2, 0, 0),
+ F_END
+};
+
+/* This table is for
+ * sdc[1-4] for all MSM8974 excluding MSM8974PROAC
+ * sdc[2-4] for MSM8974PRO AC
+ */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] =
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
@@ -137,7 +171,7 @@
.d_reg = (uint32_t *) SDCC1_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
@@ -168,6 +202,28 @@
},
};
+static struct branch_clk gcc_sdcc1_cdccal_sleep_clk =
+{
+ .cbcr_reg = SDCC1_CDCCAL_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_cdccal_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_cdccal_ff_clk =
+{
+ .cbcr_reg = SDCC1_CDCCAL_FF_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_cdccal_ff_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct rcg_clk sdcc2_apps_clk_src =
{
.cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
@@ -177,7 +233,7 @@
.d_reg = (uint32_t *) SDCC2_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
@@ -761,6 +817,9 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+ CLK_LOOKUP("gcc_sdcc1_cdccal_sleep_clk", gcc_sdcc1_cdccal_sleep_clk.c),
+ CLK_LOOKUP("gcc_sdcc1_cdccal_ff_clk", gcc_sdcc1_cdccal_ff_clk.c),
+
CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
@@ -804,8 +863,14 @@
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
};
+void msm8974_ac_clock_override()
+{
+ sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_ac;
+}
void platform_clock_init(void)
{
+ if (platform_is_8974ac())
+ msm8974_ac_clock_override();
clk_init(msm_clocks_8974, ARRAY_SIZE(msm_clocks_8974));
}
diff --git a/platform/msm8974/platform.c b/platform/msm8974/platform.c
index be35f84..460317c 100644
--- a/platform/msm8974/platform.c
+++ b/platform/msm8974/platform.c
@@ -87,6 +87,81 @@
return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
}
+/* Check for 8974 chip */
+int platform_is_8974()
+{
+ uint32_t platform = board_platform_id();
+ int ret = 0;
+
+ switch(platform)
+ {
+ case APQ8074:
+ case MSM8274:
+ case MSM8674:
+ case MSM8974:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
+/* Check for 8974 PRO chip */
+int platform_is_8974Pro()
+{
+ uint32_t platform = board_platform_id();
+ int ret = 0;
+
+ switch(platform)
+ {
+ case MSM8974AC:
+ case MSM8674AC:
+ case MSM8274AC:
+ case APQ8074AC:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
+/* Check for 8974PRO AC chip */
+int platform_is_8974ac()
+{
+ uint32_t platform = board_platform_id();
+ int ret = 0;
+
+ switch(platform)
+ {
+ case APQ8074AA:
+ case APQ8074AB:
+ case APQ8074AC:
+
+ case MSM8274AA:
+ case MSM8274AB:
+ case MSM8274AC:
+
+ case MSM8674AA:
+ case MSM8674AB:
+ case MSM8674AC:
+
+ case MSM8974AA:
+ case MSM8974AB:
+ case MSM8974AC:
+
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
addr_t get_bs_info_addr()
{
uint32_t soc_ver = board_soc_version();
diff --git a/platform/msm_shared/clock_lib2.c b/platform/msm_shared/clock_lib2.c
index 218b585..6f778b1 100644
--- a/platform/msm_shared/clock_lib2.c
+++ b/platform/msm_shared/clock_lib2.c
@@ -129,7 +129,14 @@
return rc;
/* First enable the source clock for this freq. */
- clk_enable(nf->src_clk);
+ rc = clk_enable(nf->src_clk);
+
+ if(rc)
+ {
+ dprintf(CRITICAL, "clock_lib2_rcg_set_rate: failed to enable clk %s ret %d\n",
+ nf->src_clk->dbg_name, rc);
+ ASSERT(0);
+ }
/* Perform clock-specific frequency switch operations. */
ASSERT(rclk->set_rate);
diff --git a/platform/msm_shared/include/clock-local.h b/platform/msm_shared/include/clock-local.h
index a9f1151..7a7d9fd 100644
--- a/platform/msm_shared/include/clock-local.h
+++ b/platform/msm_shared/include/clock-local.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -130,7 +130,7 @@
struct bank_masks *const bank_masks;
void (*set_rate)(struct rcg_clk *, struct clk_freq_tbl *);
- struct clk_freq_tbl *const freq_tbl;
+ struct clk_freq_tbl *freq_tbl;
struct clk_freq_tbl *current_freq;
struct clk *depends;
diff --git a/platform/msm_shared/include/clock_lib2.h b/platform/msm_shared/include/clock_lib2.h
index 7998a89..e808c87 100644
--- a/platform/msm_shared/include/clock_lib2.h
+++ b/platform/msm_shared/include/clock_lib2.h
@@ -156,7 +156,7 @@
void (*set_rate)(struct rcg_clk *, struct clk_freq_tbl *);
/* freq table */
- struct clk_freq_tbl *const freq_tbl;
+ struct clk_freq_tbl *freq_tbl;
struct clk_freq_tbl *current_freq;
struct clk c;
diff --git a/platform/msm_shared/include/gpio.h b/platform/msm_shared/include/gpio.h
index 2a95eda..56b9c82 100644
--- a/platform/msm_shared/include/gpio.h
+++ b/platform/msm_shared/include/gpio.h
@@ -34,12 +34,19 @@
/* Current values for tlmm pins */
enum {
- TLMM_CUR_VAL_16MA = 0x7,
- TLMM_CUR_VAL_10MA = 0x4,
+ TLMM_CUR_VAL_2MA = 0x0,
+ TLMM_CUR_VAL_4MA,
+ TLMM_CUR_VAL_6MA,
+ TLMM_CUR_VAL_8MA,
+ TLMM_CUR_VAL_10MA,
+ TLMM_CUR_VAL_12MA,
+ TLMM_CUR_VAL_14MA,
+ TLMM_CUR_VAL_16MA,
} tlmm_drive_config;
enum {
TLMM_PULL_UP = 0x3,
+ TLMM_PULL_DOWN = 0x1,
TLMM_NO_PULL = 0x0,
} tlmm_pull_values;
@@ -51,6 +58,7 @@
SDC1_DATA_PULL_CTL_OFF = 9,
SDC1_CMD_PULL_CTL_OFF = 11,
SDC1_CLK_PULL_CTL_OFF = 13,
+ SDC1_RCLK_PULL_CTL_OFF = 15,
} tlmm_drv_ctrl;
/* Input for the tlmm config function */
diff --git a/platform/msm_shared/include/mmc.h b/platform/msm_shared/include/mmc.h
index abdd31f..33ad2bf 100644
--- a/platform/msm_shared/include/mmc.h
+++ b/platform/msm_shared/include/mmc.h
@@ -397,6 +397,7 @@
/* EXT_CSD */
#define MMC_BOOT_ACCESS_WRITE 0x3
+#define MMC_BOOT_SET_BIT 0x1
#define MMC_BOOT_EXT_USER_WP 171
#define MMC_BOOT_EXT_ERASE_GROUP_DEF 175
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index b6a2ca6..1eb9745 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -49,6 +49,7 @@
#define CMD16_SET_BLOCKLEN 16
#define CMD17_READ_SINGLE_BLOCK 17
#define CMD18_READ_MULTIPLE_BLOCK 18
+#define CMD21_SEND_TUNING_BLOCK 21
#define CMD23_SET_BLOCK_COUNT 23
#define CMD24_WRITE_SINGLE_BLOCK 24
#define CMD25_WRITE_MULTIPLE_BLOCK 25
@@ -101,10 +102,12 @@
/* Values for ext csd fields */
#define MMC_HS_TIMING 0x1
#define MMC_HS200_TIMING 0x2
+#define MMC_HS400_TIMING 0x3
#define MMC_ACCESS_WRITE 0x3
#define MMC_SET_BIT 0x1
#define MMC_HS_DDR_MODE (BIT(2) | BIT(3))
#define MMC_HS_HS200_MODE (BIT(4) | BIT(5))
+#define MMC_HS_HS400_MODE (BIT(6) | BIT(7))
#define MMC_SEC_COUNT4_SHIFT 24
#define MMC_SEC_COUNT3_SHIFT 16
#define MMC_SEC_COUNT2_SHIFT 8
@@ -140,6 +143,8 @@
#define MMC_CLK_50MHZ 49152000
#define MMC_CLK_96MHZ 96000000
#define MMC_CLK_200MHZ 200000000
+#define MMC_CLK_192MHZ 192000000
+#define MMC_CLK_400MHZ 400000000
#define MMC_ADDR_OUT_OF_RANGE(resp) ((resp >> 31) & 0x01)
@@ -181,6 +186,8 @@
#define ACMD51_READ_CARD_SCR 51
#define CMD55_APP_CMD 55
+#define MMC_SAVE_TIMING(host, TIMING) host->timing = TIMING
+
/* Can be used to unpack array of upto 32 bits data */
#define UNPACK_BITS(array, start, len, size_of) \
({ \
diff --git a/platform/msm_shared/include/sdhci.h b/platform/msm_shared/include/sdhci.h
index 976b5e3..b7061dd 100644
--- a/platform/msm_shared/include/sdhci.h
+++ b/platform/msm_shared/include/sdhci.h
@@ -47,6 +47,7 @@
uint8_t sdr_support; /* Single Data rate */
uint8_t ddr_support; /* Dual Data rate */
uint8_t sdr50_support; /* UHS mode, with 100 MHZ clock */
+ uint8_t sdr104_support; /* UHS mode, with 200 MHZ clock */
};
/*
@@ -54,10 +55,13 @@
* controller parameters
*/
struct sdhci_host {
- uint32_t base; /* Base address for the host */
- uint32_t cur_clk_rate; /* Running clock rate */
- event_t* sdhc_event; /* Event for power control irqs */
- struct host_caps caps; /* Host capabilities */
+ uint32_t base; /* Base address for the host */
+ uint32_t cur_clk_rate; /* Running clock rate */
+ uint32_t timing; /* current timing for the host */
+ bool tuning_in_progress; /* Tuning is being executed */
+ event_t* sdhc_event; /* Event for power control irqs */
+ struct host_caps caps; /* Host capabilities */
+ struct sdhci_msm_data *msm_host; /* MSM specific host info */
};
/*
@@ -123,6 +127,7 @@
#define REG_READ32(host, a) readl(host->base + a)
#define REG_WRITE32(host, v, a) writel(v, (host->base + a))
+#define REG_RMW32(host, a, s, w, v) RMWREG32((host->base + a), s, w, v)
#define REG_READ16(host, a) readhw(host->base + a)
#define REG_WRITE16(host, v, a) writehw(v, (host->base + a))
@@ -269,7 +274,7 @@
#define SDHCI_SWITCH_CMD 6
#define SDHCI_CMD_TIMEOUT 0xF
#define SDHCI_MAX_CMD_RETRY 10000
-#define SDHCI_MAX_TRANS_RETRY 100000
+#define SDHCI_MAX_TRANS_RETRY 10000
#define SDHCI_PREP_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
@@ -309,15 +314,30 @@
#define SDHCI_CLK_50MHZ 50000000
#define SDHCI_CLK_100MHZ 100000000
#define SDHCI_CLK_200MHZ 200000000
+#define SDHCI_CLK_400MHZ 400000000
+
+/* UHS macros */
+#define SDHCI_UHS_MODE_MASK 0x0007
/* DDR mode related macros */
-#define SDHCI_DDR_MODE_EN 0x0004
-#define SDHCI_DDR_MODE_MASK BIT(2)
+#define SDHCI_DDR50_MODE_EN 0x0004
+#define SDHCI_DDR50_MODE_MASK BIT(2)
/* HS200/SDR50 mode related macros */
+#define SDHCI_SDR25_MODE_EN 0x0001
+#define SDHCI_SDR12_MODE_EN 0x0000
#define SDHCI_SDR50_MODE_MASK BIT(0)
#define SDHCI_SDR50_MODE_EN 0x0002
+#define SDHCI_SDR104_MODE_MASK BIT(1)
+#define SDHCI_SDR104_MODE_EN 0x0003
+
+#define SDHCI_SDR104_MODE 0x3
+#define SDHCI_SDR50_MODE 0x2
+#define SDHCI_DDR50_MODE 0x4
+#define SDHCI_SDR25_MODE 0x1
+#define SDHCI_SDR12_MODE 0x0
+
/*
* APIs and macros exposed for mmc/sd drivers
*/
@@ -338,8 +358,8 @@
uint8_t sdhci_set_bus_width(struct sdhci_host *, uint16_t);
/* API: Clock supply for the controller */
uint32_t sdhci_clk_supply(struct sdhci_host *, uint32_t);
-/* API: Enable DDR mode */
-void sdhci_set_ddr_mode(struct sdhci_host *);
-/* API: To enable SDR mode */
-void sdhci_set_sdr_mode(struct sdhci_host *);
+/* API: To enable SDR/DDR mode */
+void sdhci_set_uhs_mode(struct sdhci_host *, uint32_t);
+/* API: Soft reset for the controller */
+void sdhci_reset(struct sdhci_host *host, uint8_t mask);
#endif
diff --git a/platform/msm_shared/include/sdhci_msm.h b/platform/msm_shared/include/sdhci_msm.h
index 1d77823..93a8457 100644
--- a/platform/msm_shared/include/sdhci_msm.h
+++ b/platform/msm_shared/include/sdhci_msm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -31,13 +31,84 @@
#include <kernel/event.h>
+#define SDHCI_HC_START_BIT 0x0
+#define SDHCI_HC_WIDTH 0x1
+
+#define SDCC_MCI_POWER 0x0
+#define CORE_SW_RST_START 0x7
+#define CORE_SW_RST_WIDTH 0x1
+
+/* DLL & CDC registers
+ * DLL: Delay Line
+ * CDC: Calibrated Delay Circuit
+ */
+#define SDCC_DLL_CONFIG_REG 0x100
+#define SDCC_VENDOR_SPECIFIC_FUNC 0x10C
+#define SDCC_REG_DLL_STATUS 0x108
+#define SDCC_CDC_DDR200_CFG 0x184
+#define SDCC_VENDOR_SPEC_CSR_CDC_CFG 0x178
+#define SDCC_CSR_CDC_CTRL_CFG0 0x130
+#define SDCC_CSR_CDC_CTRL_CFG1 0x134
+#define SDCC_CSR_CDC_CAL_TIMER_CFG0 0x138
+#define SDCC_CSR_CDC_CAL_TIMER_CFG1 0x13C
+#define SDCC_CSR_CDC_REFCOUNT_CFG 0x140
+#define SDCC_CSR_CDC_COARSE_CAL_CFG 0x144
+#define SDCC_CSR_CDC_DELAY_CFG 0x150
+#define SDCC_CDC_OFFSET_CFG 0x14C
+#define SDCC_CDC_SLAVE_DDA_CFG 0x160
+#define SDCC_CSR_CDC_STATUS0 0x164
+
+/* DLL & CDC helper macros */
+#define SDCC_DLL_PWR_SAVE_EN BIT(1)
+#define SDCC_DLL_LOCK_STAT BIT(7)
+#define SDCC_DLL_EN BIT(16)
+#define SDCC_DLL_CDR_EN BIT(17)
+#define SDCC_DLL_CLK_OUT_EN BIT(18)
+#define SDCC_DLL_CDR_EXT_EN BIT(19)
+#define SDCC_DLL_PDN_EN BIT(29)
+#define SDCC_DLL_RESET_EN BIT(30)
+#define SDCC_DLL_CONFIG_MCLK_START 0x18
+#define SDCC_DLL_CONFIG_MCLK_WIDTH 0x3
+#define SDCC_DLL_GRAY_CODE_START 0x14
+#define SDCC_DLL_GRAY_CODE_WIDTH 0x4
+#define CMD_DAT_TRACK_SEL BIT(0)
+#define CDC_T4_DLY_SEL BIT(0)
+#define CDC_SWITCH_BYPASS_OFF BIT(0)
+#define CDC_SWITCH_RC_EN BIT(1)
+#define START_CDC_TRAFFIC BIT(6)
+#define FW_CLK_SW_RST_DIS BIT(13)
+#define CDC_SW_TRIGGER_FULL_CALIB BIT(16)
+#define CDC_HW_AUTO_CAL_EN BIT(17)
+#define CDC_TIMER_EN BIT(16)
+#define CSR_CDC_ERROR_MASK 0x7000000
+
+/* SDCC macros for HS400 */
+#define SDCC_HC_MCLK_SEL_HS400 0x3
+#define SDCC_HC_MCLK_HS400_START 0x8
+#define SDCC_HC_MCLK_HS400_WIDTH 0x2
+#define SDCC_HC_MCLK_SEL_IN_HS400 0x6
+#define SDCC_HC_MCLK_SEL_IN_DFLT 0x2
+#define SDCC_HC_MCLK_SEL_IN_UHS 0x4
+#define SDCC_HC_MCLK_SEL_IN_START 0x13
+#define SDCC_HC_MCLK_SEL_IN_WIDTH 0x3
+#define SDCC_HC_MCLK_SEL_IN_EN 0x1
+#define SDCC_HC_MCLK_SEL_IN_EN_START 0x12
+#define SDCC_HC_MCLK_SEL_IN_EN_WIDTH 0x1
+
+#define MAX_PHASES 16
+
struct sdhci_msm_data
{
uint32_t pwrctl_base;
uint32_t pwr_irq;
+ uint8_t tuning_done;
+ uint8_t calibration_done;
+ uint8_t saved_phase;
+ uint8_t slot;
event_t* sdhc_event;
};
-void sdhci_msm_init(struct sdhci_msm_data *data);
-
+void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *data);
+uint32_t sdhci_msm_execute_tuning(struct sdhci_host *host, uint32_t bus_width);
+void sdhci_mode_disable(struct sdhci_host *host);
#endif
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index 25d619c..f62d407 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -2554,7 +2554,7 @@
sizeof(struct mmc_boot_command));
/* Disabling PERM_WP for USER AREA (CMD6) */
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_SET_BIT,
MMC_BOOT_EXT_USER_WP,
MMC_BOOT_US_PERM_WP_DIS);
@@ -2601,8 +2601,7 @@
}
/* Setting POWER_ON_WP for USER AREA (CMD6) */
-
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_SET_BIT,
MMC_BOOT_EXT_USER_WP,
MMC_BOOT_US_PWR_WP_EN);
@@ -2685,13 +2684,29 @@
unsigned int rc = MMC_BOOT_E_SUCCESS;
/* Checking whether group write protection feature is available */
- if (mmc_card.csd.wp_grp_enable) {
+ if (mmc_card.csd.wp_grp_enable)
+ {
rc = mmc_boot_get_wp_status(&mmc_card, sector);
+ if (rc != MMC_BOOT_E_SUCCESS)
+ {
+ dprintf(CRITICAL, "Failure in getting wp_status (%u):%s:%u\n", rc, __FILE__, __LINE__);
+ return rc;
+ }
rc = mmc_boot_set_clr_power_on_wp_user(&mmc_card, sector, size,
set_clear_wp);
+ if (rc != MMC_BOOT_E_SUCCESS)
+ {
+ dprintf(CRITICAL, "Failure in setting power on wp user (%u):%s:%u\n", rc, __FILE__, __LINE__);
+ return rc;
+ }
rc = mmc_boot_get_wp_status(&mmc_card, sector);
- return rc;
- } else
+ if (rc != MMC_BOOT_E_SUCCESS)
+ {
+ dprintf(CRITICAL, "Failure in getting wp_status (%u)%s:%u\n", rc, __FILE__, __LINE__);
+ return rc;
+ }
+ }
+ else
return MMC_BOOT_E_FAILURE;
}
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index de3db2b..c3ecaac 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -768,9 +768,23 @@
/*
- * Function: mmc card supports ddr mode
+ * Function: mmc card supports hs400 mode
* Arg : None
- * Return : 1 if DDR mode is supported, 0 otherwise
+ * Return : 1 if hs400 mode is supported, 0 otherwise
+ * Flow : Check the ext csd attributes of the card
+ */
+static uint8_t mmc_card_supports_hs400_mode(struct mmc_card *card)
+{
+ if (card->ext_csd[MMC_DEVICE_TYPE] & MMC_HS_HS400_MODE)
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ * Function: mmc card supports hs200 mode
+ * Arg : None
+ * Return : 1 if HS200 mode is supported, 0 otherwise
* Flow : Check the ext csd attributes of the card
*/
static uint8_t mmc_card_supports_hs200_mode(struct mmc_card *card)
@@ -824,8 +838,25 @@
return mmc_ret;
}
- /* Enable hs200 mode in controller */
- sdhci_set_sdr_mode(host);
+ /* Enable SDR104 mode in controller */
+ sdhci_set_uhs_mode(host, SDHCI_SDR104_MODE);
+
+ /* Run the clock @ 400 Mhz */
+ if (mmc_card_supports_hs400_mode(card))
+ {
+ clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, MMC_HS400_TIMING);
+ }
+ else
+ {
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, MMC_HS200_TIMING);
+ }
+
+ /* Execute Tuning for hs200 mode */
+ if ((mmc_ret = sdhci_msm_execute_tuning(host, width)))
+ dprintf(CRITICAL, "Tuning for hs200 failed\n");
return mmc_ret;
}
@@ -849,7 +880,11 @@
return mmc_ret;
}
- sdhci_set_ddr_mode(host);
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, SDHCI_DDR50_MODE);
+
+ /* Set the DDR mode in controller */
+ sdhci_set_uhs_mode(host, SDHCI_DDR50_MODE);
return 0;
}
@@ -875,10 +910,98 @@
return mmc_ret;
}
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, SDHCI_SDR25_MODE);
+
+ /* Set the SDR25 mode in controller */
+ sdhci_set_uhs_mode(host, SDHCI_SDR25_MODE);
+
return 0;
}
/*
+ * Function : Enable HS400 mode
+ * Arg : Host, card structure and bus width
+ * Return : 0 on Success, 1 on Failure
+ * Flow :
+ * - Set the bus width to 8 bit DDR
+ * - Set the HS_TIMING on ext_csd 185 for the card
+ */
+uint32_t mmc_set_hs400_mode(struct sdhci_host *host,
+ struct mmc_card *card, uint32_t width)
+{
+ uint32_t mmc_ret = 0;
+
+ /*
+ * Emmc 5.0 spec does not allow changing to hs400 mode directly
+ * Need to follow the sequence to change to hs400 mode
+ * 1. Enable HS200 mode, perform tuning
+ * 2. Change to high speed mode
+ * 3. Enable DDR mode
+ * 4. Enable HS400 mode & execute tuning
+ */
+
+ /* HS400 mode is supported only in DDR 8-bit */
+ if (width != DATA_BUS_WIDTH_8BIT)
+ {
+ dprintf(CRITICAL, "Bus width is not 8-bit, cannot switch to hs400: %u\n", width);
+ return 1;
+ }
+
+ /* 1.Enable HS200 mode */
+ mmc_ret = mmc_set_hs200_mode(host, card, width);
+
+ if (mmc_ret)
+ {
+ dprintf(CRITICAL, "Failure Setting HS200 mode %s\t%d\n",__func__, __LINE__);
+ return mmc_ret;
+ }
+
+ /* 2. Enable High speed mode */
+ /* This is needed to set the clock to a low value &
+ * so that we can switch to hs_timing --> 0x1 */
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, SDHCI_SDR12_MODE);
+ sdhci_set_uhs_mode(host, SDHCI_SDR12_MODE);
+
+ /* 3. Set HS_TIMING to 0x1 */
+ mmc_ret = mmc_set_hs_interface(host, card);
+ if (mmc_ret)
+ {
+ dprintf(CRITICAL, "Error adjusting interface speed!:%s\t%d\n", __func__, __LINE__);
+ return mmc_ret;
+ }
+
+ /*4. Enable DDR mode */
+ mmc_ret = mmc_set_ddr_mode(host, card);
+ if (mmc_ret)
+ {
+ dprintf(CRITICAL, "Failure setting DDR mode:%s\t%d\n", __func__, __LINE__);
+ return mmc_ret;
+ }
+
+ /*5. Set hs400 timing */
+ mmc_ret = mmc_switch_cmd(host, card, MMC_ACCESS_WRITE, MMC_EXT_MMC_HS_TIMING, MMC_HS400_TIMING);
+
+ if (mmc_ret)
+ {
+ dprintf(CRITICAL, "Switch cmd returned failure %s\t%d\n",__func__, __LINE__);
+ return mmc_ret;
+ }
+
+ /* 6. Enable SDR104 mode in controller */
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, MMC_HS400_TIMING);
+ sdhci_set_uhs_mode(host, SDHCI_SDR104_MODE);
+
+ /* 7. Execute Tuning for hs400 mode */
+ if ((mmc_ret = sdhci_msm_execute_tuning(host, width)))
+ dprintf(CRITICAL, "Tuning for hs400 failed\n");
+
+ return mmc_ret;
+}
+
+/*
* Function: mmc_host_init
* Arg : mmc device structure
* Return : 0 on success, 1 on Failure
@@ -891,7 +1014,7 @@
struct sdhci_host *host;
struct mmc_config_data *cfg;
- struct sdhci_msm_data data;
+ struct sdhci_msm_data *data;
event_t sdhc_event;
@@ -903,9 +1026,15 @@
host->base = cfg->sdhc_base;
host->sdhc_event = &sdhc_event;
- data.sdhc_event = &sdhc_event;
- data.pwrctl_base = cfg->pwrctl_base;
- data.pwr_irq = cfg->pwr_irq;
+ data = (struct sdhci_msm_data *) malloc(sizeof(struct sdhci_msm_data));
+ ASSERT(data);
+
+ data->sdhc_event = &sdhc_event;
+ data->pwrctl_base = cfg->pwrctl_base;
+ data->pwr_irq = cfg->pwr_irq;
+ data->slot = cfg->slot;
+
+ host->msm_host = data;
/* Initialize any clocks needed for SDC controller */
clock_init_mmc(cfg->slot);
@@ -915,7 +1044,7 @@
/*
* MSM specific sdhc init
*/
- sdhci_msm_init(&data);
+ sdhci_msm_init(host, data);
/*
* Initialize the controller, read the host capabilities
@@ -1261,6 +1390,9 @@
if (sdhci_send_command(host, &cmd))
return 1;
+ /* Set the SDR25 mode in controller*/
+ sdhci_set_uhs_mode(host, SDHCI_SDR25_MODE);
+
return 0;
}
@@ -1330,9 +1462,6 @@
}
}
- /* Set the sdcc clock to 50 MHZ */
- sdhci_clk_supply(host, SDHCI_CLK_50MHZ);
-
/* Now get the extended CSD for the card */
if (MMC_CARD_MMC(card))
{
@@ -1391,11 +1520,23 @@
}
/* Enable high speed mode in the follwing order:
+ * 1. HS400 mode if supported by host & card
* 1. HS200 mode if supported by host & card
* 2. DDR mode host, if supported by host & card
* 3. Use normal speed mode with supported bus width
*/
- if (mmc_card_supports_hs200_mode(card) && host->caps.sdr50_support) {
+ if (mmc_card_supports_hs400_mode(card) && host->caps.sdr104_support)
+ {
+ mmc_return = mmc_set_hs400_mode(host, card, bus_width);
+ if (mmc_return)
+ {
+ dprintf(CRITICAL, "Failure to set HS400 mode for Card(RCA:%x)\n",
+ card->rca);
+ return mmc_return;
+ }
+ }
+ else if (mmc_card_supports_hs200_mode(card) && host->caps.sdr104_support)
+ {
mmc_return = mmc_set_hs200_mode(host, card, bus_width);
if (mmc_return) {
@@ -1537,6 +1678,7 @@
{
uint32_t mmc_ret = 0;
struct mmc_command cmd;
+ struct mmc_card *card = &dev->card;
memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
@@ -1553,8 +1695,19 @@
cmd.resp_type = SDHCI_CMD_RESP_R1;
cmd.trans_mode = SDHCI_MMC_READ;
cmd.data_present = 0x1;
- /* Use CMD23 If card supports cMD23 */
- cmd.cmd23_support = dev->card.scr.cmd23_support;
+
+ /* Use CMD23 If card supports CMD23:
+ * For SD card use the value read from SCR register
+ * For emmc by default use CMD23.
+ * Also as per SDCC spec always use CMD23 to stop
+ * multiblock read/write if UHS (Ultra High Speed) is
+ * enabled
+ */
+ if (MMC_CARD_SD(card))
+ cmd.cmd23_support = dev->card.scr.cmd23_support;
+ else
+ cmd.cmd23_support = 0x1;
+
cmd.data.data_ptr = dest;
cmd.data.num_blocks = num_blocks;
@@ -1596,6 +1749,7 @@
{
uint32_t mmc_ret = 0;
struct mmc_command cmd;
+ struct mmc_card *card = &dev->card;
memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
@@ -1612,8 +1766,19 @@
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
cmd.trans_mode = SDHCI_MMC_WRITE;
- /* Use CMD23 If card supports cMD23 */
- cmd.cmd23_support = dev->card.scr.cmd23_support;
+
+ /* Use CMD23 If card supports CMD23:
+ * For SD card use the value read from SCR register
+ * For emmc by default use CMD23.
+ * Also as per SDCC spec always use CMD23 to stop
+ * multiblock read/write if UHS (Ultra High Speed) is
+ * enabled
+ */
+ if (MMC_CARD_SD(card))
+ cmd.cmd23_support = dev->card.scr.cmd23_support;
+ else
+ cmd.cmd23_support = 0x1;
+
cmd.data_present = 0x1;
cmd.data.data_ptr = src;
cmd.data.num_blocks = num_blocks;
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 4399c60..6fba466 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -45,7 +45,7 @@
* Return : None
* Flow: : Reset the host controller
*/
-static void sdhci_reset(struct sdhci_host *host, uint8_t mask)
+void sdhci_reset(struct sdhci_host *host, uint8_t mask)
{
uint32_t reg;
uint32_t timeout = SDHCI_RESET_MAX_TIMEOUT;
@@ -102,12 +102,7 @@
uint32_t freq = 0;
uint16_t clk_val = 0;
- if (clk > host->caps.base_clk_rate) {
- dprintf(CRITICAL, "Error: Requested clk freq is more than supported\n");
- return 1;
- }
-
- if (clk == host->caps.base_clk_rate)
+ if (clk >= host->caps.base_clk_rate)
goto clk_ctrl;
/* As per the sd spec div should be a multiplier of 2 */
@@ -141,7 +136,7 @@
clk_val |= SDHCI_CLK_EN;
REG_WRITE16(host, clk_val, SDHCI_CLK_CTRL_REG);
- host->cur_clk_rate = freq;
+ host->cur_clk_rate = clk;
return 0;
}
@@ -212,58 +207,23 @@
}
+
/*
* Function: sdhci set SDR mode
- * Arg : Host structure
+ * Arg : Host structure, UHS mode
* Return : None
* Flow: : 1. Disable the clock
- * 2. Enable sdr mode
+ * 2. Enable UHS mode
* 3. Enable the clock
* Details : SDR50/SDR104 mode is nothing but HS200
* mode SDCC spec refers to it as SDR mode
* & emmc spec refers as HS200 mode.
*/
-void sdhci_set_sdr_mode(struct sdhci_host *host)
+void sdhci_set_uhs_mode(struct sdhci_host *host, uint32_t mode)
{
uint16_t clk;
uint16_t ctrl = 0;
-
- /* Disable the clock */
- clk = REG_READ16(host, SDHCI_CLK_CTRL_REG);
- clk &= ~SDHCI_CLK_EN;
- REG_WRITE16(host, clk, SDHCI_CLK_CTRL_REG);
-
- /* Enable SDR50 mode:
- * Right now we support only SDR50 mode which runs at
- * 100 MHZ sdcc clock, we dont need tuning with SDR50
- * mode
- */
- ctrl = REG_READ16(host, SDHCI_HOST_CTRL2_REG);
-
- /* Enable SDR50/SDR104 mode based on the controller
- * capabilities.
- */
- if (host->caps.sdr50_support)
- ctrl |= SDHCI_SDR50_MODE_EN;
-
- REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG);
-
- /* Run the clock back */
- sdhci_clk_supply(host, SDHCI_CLK_100MHZ);
-}
-
-/*
- * Function: sdhci set ddr mode
- * Arg : Host structure
- * Return : None
- * Flow: : 1. Disable the clock
- * 2. Enable DDR mode
- * 3. Enable the clock
- */
-void sdhci_set_ddr_mode(struct sdhci_host *host)
-{
- uint16_t clk;
- uint16_t ctrl = 0;
+ uint32_t clk_val = 0;
/* Disable the clock */
clk = REG_READ16(host, SDHCI_CLK_CTRL_REG);
@@ -271,13 +231,48 @@
REG_WRITE16(host, clk, SDHCI_CLK_CTRL_REG);
ctrl = REG_READ16(host, SDHCI_HOST_CTRL2_REG);
- ctrl |= SDHCI_DDR_MODE_EN;
- /* Enalbe DDR mode */
+ ctrl &= ~SDHCI_UHS_MODE_MASK;
+
+ /* Enable SDR50/SDR104/DDR50 mode */
+ switch (mode)
+ {
+ case SDHCI_SDR104_MODE:
+ ctrl |= SDHCI_SDR104_MODE_EN;
+ clk_val = SDHCI_CLK_200MHZ;
+ break;
+ case SDHCI_SDR50_MODE:
+ ctrl |= SDHCI_SDR50_MODE_EN;
+ clk_val = SDHCI_CLK_100MHZ;
+ break;
+ case SDHCI_DDR50_MODE:
+ ctrl |= SDHCI_DDR50_MODE_EN;
+ clk_val = SDHCI_CLK_50MHZ;
+ break;
+ case SDHCI_SDR25_MODE:
+ ctrl |= SDHCI_SDR25_MODE_EN;
+ clk_val = SDHCI_CLK_50MHZ;
+ break;
+ case SDHCI_SDR12_MODE_EN:
+ ctrl |= SDHCI_SDR12_MODE_EN;
+ clk_val = SDHCI_CLK_25MHZ;
+ break;
+ default:
+ dprintf(CRITICAL, "Error: Invalid UHS mode: %x\n", mode);
+ ASSERT(0);
+ };
+
REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG);
+ /*
+ * SDHC spec does not have matching UHS mode
+ * So we use Vendor specific registers to enable
+ * HS400 mode
+ */
+ sdhci_msm_set_mci_clk(host);
+
/* Run the clock back */
- sdhci_clk_supply(host, host->cur_clk_rate);
+ sdhci_clk_supply(host, clk_val);
}
/*
@@ -388,6 +383,7 @@
uint32_t retry = 0;
uint32_t int_status;
uint32_t trans_complete = 0;
+ uint32_t err_status;
do {
int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG);
@@ -444,6 +440,20 @@
break;
}
+ /*
+ * If we are in tuning then we need to wait until Data timeout , Data end
+ * or Data CRC error
+ */
+ if (host->tuning_in_progress)
+ {
+ err_status = REG_READ16(host, SDHCI_ERR_INT_STS_REG);
+ if ((err_status & SDHCI_DAT_TIMEOUT_MASK) || (err_status & SDHCI_DAT_CRC_MASK))
+ {
+ sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
+ return 0;
+ }
+ }
+
retry++;
udelay(1000);
if (retry == SDHCI_MAX_TRANS_RETRY) {
@@ -790,10 +800,6 @@
{
uint32_t caps[2];
- /*
- * Reset the controller
- */
- sdhci_reset(host, SDHCI_SOFT_RESET);
/* Read the capabilities register & store the info */
caps[0] = REG_READ32(host, SDHCI_CAPS_REG1);
@@ -822,11 +828,14 @@
host->caps.voltage = SDHCI_VOL_1_8;
/* DDR mode support */
- host->caps.ddr_support = (caps[1] & SDHCI_DDR_MODE_MASK) ? 1 : 0;
+ host->caps.ddr_support = (caps[1] & SDHCI_DDR50_MODE_MASK) ? 1 : 0;
/* SDR50 mode support */
host->caps.sdr50_support = (caps[1] & SDHCI_SDR50_MODE_MASK) ? 1 : 0;
+ /* SDR104 mode support */
+ host->caps.sdr104_support = (caps[1] & SDHCI_SDR104_MODE_MASK) ? 1 : 0;
+
/* Set bus power on */
sdhci_set_bus_power_on(host);
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index 1b6c8b0..8677dbe 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -30,14 +30,38 @@
#include <platform/irqs.h>
#include <platform/interrupts.h>
#include <platform/timer.h>
+#include <sys/types.h>
#include <target.h>
#include <string.h>
#include <stdlib.h>
#include <bits.h>
#include <debug.h>
+#include <mmc.h>
#include <sdhci.h>
#include <sdhci_msm.h>
+/* Known data stored in the card & read during tuning
+ * process. 64 bytes for 4bit bus width & 128 bytes
+ * of data for 8 bit bus width.
+ * These values are derived from HPG
+ */
+static const uint32_t tuning_block_64[] = {
+ 0x00FF0FFF, 0xCCC3CCFF, 0xFFCC3CC3, 0xEFFEFFFE,
+ 0xDDFFDFFF, 0xFBFFFBFF, 0xFF7FFFBF, 0xEFBDF777,
+ 0xF0FFF0FF, 0x3CCCFC0F, 0xCFCC33CC, 0xEEFFEFFF,
+ 0xFDFFFDFF, 0xFFBFFFDF, 0xFFF7FFBB, 0xDE7B7FF7
+};
+
+static const uint32_t tuning_block_128[] = {
+ 0xFF00FFFF, 0x0000FFFF, 0xCCCCFFFF, 0xCCCC33CC,
+ 0xCC3333CC, 0xFFFFCCCC, 0xFFFFEEFF, 0xFFEEEEFF,
+ 0xFFDDFFFF, 0xDDDDFFFF, 0xBBFFFFFF, 0xBBFFFFFF,
+ 0xFFFFFFBB, 0xFFFFFF77, 0x77FF7777, 0xFFEEDDBB,
+ 0x00FFFFFF, 0x00FFFFFF, 0xCCFFFF00, 0xCC33CCCC,
+ 0x3333CCCC, 0xFFCCCCCC, 0xFFEEFFFF, 0xEEEEFFFF,
+ 0xDDFFFFFF, 0xDDFFFFFF, 0xFFFFFFDD, 0xFFFFFFBB,
+ 0xFFFFBBBB, 0xFFFF77FF, 0xFF7777FF, 0xEEDDBB77
+};
/*
* Function: sdhci int handler
@@ -113,12 +137,26 @@
* Return : None
* Flow: : Enable sdhci mode & do msm specific init
*/
-void sdhci_msm_init(struct sdhci_msm_data *config)
+void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *config)
{
+ /* Disable HC mode */
+ RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, 0);
+
+ /* Core power reset */
+ RMWREG32((config->pwrctl_base + SDCC_MCI_POWER), CORE_SW_RST_START, CORE_SW_RST_WIDTH, 1);
+
+ /* Wait for the core power reset to complete*/
+ mdelay(1);
+
/* Enable sdhc mode */
writel(SDHCI_HC_MODE_EN, (config->pwrctl_base + SDCC_MCI_HC_MODE));
/*
+ * Reset the controller
+ */
+ sdhci_reset(host, SDHCI_SOFT_RESET);
+
+ /*
* CORE_SW_RST may trigger power irq if previous status of PWRCTL
* was either BUS_ON or IO_HIGH. So before we enable the power irq
* interrupt in GIC (by registering the interrupt handler), we need to
@@ -136,4 +174,462 @@
/* Enable pwr control interrupt */
writel(SDCC_HC_PWR_CTRL_INT, (config->pwrctl_base + SDCC_HC_PWRCTL_MASK_REG));
+
+ config->tuning_done = false;
+ config->calibration_done = false;
+ host->tuning_in_progress = false;
}
+
+/*
+ * Function: sdhci msm set mci clk
+ * Arg : Host structure
+ * Return : None
+ * Flow: : Set HC_SELECT & HC_SELECT_EN for hs400
+ */
+void sdhci_msm_set_mci_clk(struct sdhci_host *host)
+{
+ struct sdhci_msm_data *msm_host;
+
+ msm_host = host->msm_host;
+
+ if (host->timing == MMC_HS400_TIMING)
+ {
+ /*
+ * If the current tuning mode is HS400 then we should set the MCLK to run
+ * the clock @ MCLK/2. Also set HS400 mode in SELECT_IN of vendor specific
+ * register
+ */
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_HS400_START, SDCC_HC_MCLK_HS400_WIDTH, SDCC_HC_MCLK_SEL_HS400);
+
+ /* Enable HS400 mode from HC_SELECT_IN bit of VENDOR_SPEC register
+ * As the SDCC spec does not have matching mode for HS400
+ */
+ if (msm_host->tuning_done && !msm_host->calibration_done)
+ {
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_START, SDCC_HC_MCLK_SEL_IN_WIDTH, SDCC_HC_MCLK_SEL_IN_HS400);
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_EN_START, SDCC_HC_MCLK_SEL_IN_EN_WIDTH, SDCC_HC_MCLK_SEL_IN_EN);
+ }
+ }
+ else
+ {
+ /*
+ * Set 0x0 mode in SELECT_IN of vendor specific register so that the
+ * host control2 register settings from sdhc spec are used for
+ * speed mode
+ */
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_START, SDCC_HC_MCLK_SEL_IN_WIDTH, 0x0);
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_EN_START, SDCC_HC_MCLK_SEL_IN_EN_WIDTH, 0x0);
+ }
+}
+
+/*
+ * Set the value based on sdcc clock frequency
+ */
+static void msm_set_dll_freq(struct sdhci_host *host)
+{
+ uint32_t reg_val = 0;
+
+ /* Set clock freq value based on clock range */
+ if (host->cur_clk_rate <= 112000000)
+ reg_val = 0x0;
+ else if (host->cur_clk_rate <= 125000000)
+ reg_val = 0x1;
+ else if (host->cur_clk_rate <= 137000000)
+ reg_val = 0x2;
+ else if (host->cur_clk_rate <= 150000000)
+ reg_val = 0x3;
+ else if (host->cur_clk_rate <= 162000000)
+ reg_val = 0x4;
+ else if (host->cur_clk_rate <= 175000000)
+ reg_val = 0x5;
+ else if (host->cur_clk_rate <= 187000000)
+ reg_val = 0x6;
+ else if (host->cur_clk_rate <= 200000000)
+ reg_val = 0x7;
+
+ REG_RMW32(host, SDCC_DLL_CONFIG_REG, SDCC_DLL_CONFIG_MCLK_START, SDCC_DLL_CONFIG_MCLK_WIDTH, reg_val);
+}
+
+/* Initialize DLL (Programmable Delay Line) */
+static void sdhci_msm_init_dll(struct sdhci_host *host)
+{
+ uint32_t pwr_save = 0;
+
+ pwr_save = REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & SDCC_DLL_PWR_SAVE_EN;
+
+ /* PWR SAVE to 0 */
+ if (pwr_save)
+ REG_WRITE32(host, (REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & ~SDCC_DLL_PWR_SAVE_EN), SDCC_VENDOR_SPECIFIC_FUNC);
+ /* Set DLL_RST to 1 */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_RESET_EN), SDCC_DLL_CONFIG_REG);
+ /* Set DLL_PDN to 1 */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_PDN_EN), SDCC_DLL_CONFIG_REG);
+
+ /* Set frequency field in DLL_CONFIG */
+ msm_set_dll_freq(host);
+
+ /* Write 0 to DLL_RST */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_RESET_EN), SDCC_DLL_CONFIG_REG);
+ /* Write 0 to DLL_PDN */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_PDN_EN), SDCC_DLL_CONFIG_REG);
+ /* Write 1 to DLL_EN */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_EN), SDCC_DLL_CONFIG_REG);
+ /* Write 1 to CLK_OUT_EN */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_CLK_OUT_EN), SDCC_DLL_CONFIG_REG);
+ /* Wait for DLL_LOCK in DLL_STATUS register */
+ while(!((REG_READ32(host, SDCC_REG_DLL_STATUS)) & SDCC_DLL_LOCK_STAT));
+ /* Set the powersave back on */
+ if (pwr_save)
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_PWR_SAVE_EN), SDCC_VENDOR_SPECIFIC_FUNC);
+}
+
+/* Configure DLL with delay value based on 'phase' */
+static void sdhci_msm_config_dll(struct sdhci_host *host, uint32_t phase)
+{
+ uint32_t core_cfg = 0;
+ /* Gray code values from SWI */
+ uint32_t gray_code [] = { 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, 0xC, 0xD, 0xF, 0xE, 0xA, 0xB, 0x9, 0x8 };
+
+ /* set CDR_EN & CLK_OUT_EN to 0 and
+ * CDR_EXT_EN & DLL_EN to 1*/
+ core_cfg = REG_READ32(host, SDCC_DLL_CONFIG_REG);
+ core_cfg &= ~(SDCC_DLL_CDR_EN | SDCC_DLL_CLK_OUT_EN);
+ core_cfg |= (SDCC_DLL_CDR_EXT_EN | SDCC_DLL_EN);
+ REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG);
+
+ /* Wait until CLK_OUT_EN is 0 */
+ while(REG_READ32(host, SDCC_DLL_CONFIG_REG) & SDCC_DLL_CLK_OUT_EN);
+
+ REG_RMW32(host, SDCC_DLL_CONFIG_REG, SDCC_DLL_GRAY_CODE_START, SDCC_DLL_GRAY_CODE_WIDTH, gray_code[phase]);
+
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_CLK_OUT_EN), SDCC_DLL_CONFIG_REG);
+
+ /* Wait until CLK_OUT_EN is 1 */
+ while(!(REG_READ32(host, SDCC_DLL_CONFIG_REG) & SDCC_DLL_CLK_OUT_EN));
+
+ core_cfg = REG_READ32(host, SDCC_DLL_CONFIG_REG);
+
+ core_cfg |= SDCC_DLL_CDR_EN;
+ core_cfg &= ~SDCC_DLL_CDR_EXT_EN;
+
+ REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG);
+
+ return;
+}
+
+/*
+ * Find the right tuning delay, this function finds the largest
+ * consecutive sequence of phases & then selects the 3/4 th of
+ * the range which has max entries
+ * For eg: If we get the following sequence in phase_table[]
+ * (A) phase_table[] = 0x1, 0x2, 0x3, 0x4 , 0x5
+ * (B) phase_table[] = 0xA, 0xB, 0xC
+ * In the above case the (A) has maximum consecutive entries with '5' entries
+ * So delay would be phase_table[(0x5 * 3) / 4] = 0x3
+ */
+static int sdhci_msm_find_appropriate_phase(struct sdhci_host *host,
+ uint32_t *phase_table,
+ uint32_t total_phases)
+{
+ int sub_phases[MAX_PHASES][MAX_PHASES]={{0}};
+ int phases_per_row[MAX_PHASES] = {0};
+ uint32_t i,j;
+ int selected_phase = 0;
+ uint32_t row_index = 0;
+ uint32_t col_index = 0;
+ uint32_t phase_15_row_idx = 0;
+ uint32_t phases_0_row_idx = 0;
+ uint32_t max_phases_3_4_idx = 0;
+ uint32_t max_phases = 0;
+ uint32_t max_phases_row = 0;
+ bool found_loop = false;
+
+ if (!phase_table[0] && phase_table[total_phases - 1] == (MAX_PHASES - 1))
+ found_loop = true;
+
+ for (i = 0; i < total_phases; i++)
+ {
+ /* Break the phase table entries into different sub arrays based
+ * on the consecutive entries. Each row will have one sub array
+ * of consecutive entries.
+ * for eg: phase_table [] = { 0x0, 0x1, 0x2, 0xA, 0xB}
+ * sub_phases [0][] = { 0x0, 0x1, 0x2}
+ * sub_phases [1][] = { 0xA, 0xB}
+ */
+ sub_phases[row_index][col_index] = phase_table[i];
+ phases_per_row[row_index]++;
+ col_index++;
+
+ /* If we are at the last phase no need to check further */
+ if ((i + 1) == total_phases)
+ break;
+
+ /* If phase_table does not have consecutive entries, move to next entry */
+ if (phase_table[i]+1 != phase_table[i+1])
+ {
+ row_index++;
+ col_index = 0;
+ }
+ }
+
+ if (found_loop && total_phases < MAX_PHASES)
+ {
+ /* For consecutive entries we need to consider loops.
+ * If the phase_table contains 0x0 & 0xF then we have
+ * a loop, the number after 0xF in the sequence would be
+ * 0x0.
+ * for eg:
+ * phase_table = { 0x0, 0x1, 0x2, 0xD, 0xE, 0xF }
+ * then
+ * sub_phase [0][] = { 0x0, 0x1, 0x2 }
+ * sub_phase [1][] = { 0xD, 0xE, 0xF }
+ * Since we have a loop here, we need to merge the sub arrays as:
+ * sub_phase [1][] = { 0xD, 0xE, 0xF, 0x0, 0x1, 0x2 }
+ */
+
+ /* The entry 0xF will always be in the last row
+ * and entry 0x0 will always be in the first row
+ */
+ phase_15_row_idx = row_index;
+ j = 0;
+ for (i = phases_per_row[phase_15_row_idx] ; i < MAX_PHASES ; i++)
+ {
+ sub_phases[phase_15_row_idx][i] = sub_phases[phases_0_row_idx][j];
+ if (++j >= phases_per_row[phases_0_row_idx])
+ break;
+ }
+
+ /* Update the number of entries for the sub_phase after the merger */
+ phases_per_row[phase_15_row_idx] = phases_per_row[phase_15_row_idx] + phases_per_row[phases_0_row_idx];
+ phases_per_row[phases_0_row_idx] = 0;
+ }
+
+ for (i = 0 ; i <= row_index; i++)
+ {
+ if (phases_per_row[i] > max_phases)
+ {
+ max_phases = phases_per_row[i];
+ max_phases_row = i;
+ }
+ }
+
+ max_phases_3_4_idx = (max_phases * 3) / 4;
+ if (max_phases_3_4_idx)
+ max_phases_3_4_idx--;
+
+ selected_phase = sub_phases[max_phases_row][max_phases_3_4_idx];
+
+ return selected_phase;
+}
+
+static uint32_t sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
+{
+ uint32_t timeout;
+ uint32_t cdc_err;
+
+ /* Reset & Initialize the DLL block */
+ sdhci_msm_init_dll(host);
+
+ /* Write the save phase */
+ sdhci_msm_config_dll(host, host->msm_host->saved_phase);
+
+ /* Configure the clocks needed for CDC */
+ clock_config_cdc(host->msm_host->slot);
+
+ /* Set the FF_CLK_SW_RST_DIS to 1 */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_MCI_HC_MODE) | FW_CLK_SW_RST_DIS), SDCC_MCI_HC_MODE);
+
+ /* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | CMD_DAT_TRACK_SEL), SDCC_DLL_CONFIG_REG);
+
+ /* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) & ~CDC_T4_DLY_SEL), SDCC_CDC_DDR200_CFG);
+
+ /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) & ~START_CDC_TRAFFIC), SDCC_CDC_DDR200_CFG);
+
+ /* Write 0 to CDC_SWITCH_BYPASS_OFF field in CSR_CDC_GEN_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_VENDOR_SPEC_CSR_CDC_CFG) & ~CDC_SWITCH_BYPASS_OFF), SDCC_VENDOR_SPEC_CSR_CDC_CFG);
+
+ /* Write 1 to CDC_SWITCH_RC_EN field in CSR_CDC_GEN_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_VENDOR_SPEC_CSR_CDC_CFG) | CDC_SWITCH_RC_EN), SDCC_VENDOR_SPEC_CSR_CDC_CFG);
+
+ /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) & ~START_CDC_TRAFFIC), SDCC_CDC_DDR200_CFG);
+
+ /* Perform CDCLP533 initialization sequence
+ * SDCC_CSR_CDC_CTRL_CFG0 --> 0x11800EC
+ * SDCC_CSR_CDC_CTRL_CFG1 --> 0x3011111
+ * SDCC_CSR_CDC_CAL_TIMER_CFG0 --> 0x1201000
+ * SDCC_CSR_CDC_CAL_TIMER_CFG1 --> 0x4
+ * SDCC_CSR_CDC_REFCOUNT_CFG --> 0xCB732020
+ * SDCC_CSR_CDC_COARSE_CAL_CFG --> 0xB19
+ * SDCC_CSR_CDC_DELAY_CFG --> 0x3AC
+ * SDCC_CDC_OFFSET_CFG --> 0x0
+ * SDCC_CDC_SLAVE_DDA_CFG --> 0x16334
+ */
+
+ REG_WRITE32(host, 0x11800EC, SDCC_CSR_CDC_CTRL_CFG0);
+ REG_WRITE32(host, 0x3011111, SDCC_CSR_CDC_CTRL_CFG1);
+ REG_WRITE32(host, 0x1201000, SDCC_CSR_CDC_CAL_TIMER_CFG0);
+ REG_WRITE32(host, 0x4, SDCC_CSR_CDC_CAL_TIMER_CFG1);
+ REG_WRITE32(host, 0xCB732020, SDCC_CSR_CDC_REFCOUNT_CFG);
+ REG_WRITE32(host, 0xB19, SDCC_CSR_CDC_COARSE_CAL_CFG);
+ REG_WRITE32(host, 0x3AC, SDCC_CSR_CDC_DELAY_CFG);
+ REG_WRITE32(host, 0x0, SDCC_CDC_OFFSET_CFG);
+ REG_WRITE32(host, 0x16334, SDCC_CDC_SLAVE_DDA_CFG);
+
+ /* Write 1 to SW_TRIGGER_FULL_CALIB */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CSR_CDC_CTRL_CFG0) | CDC_SW_TRIGGER_FULL_CALIB), SDCC_CSR_CDC_CTRL_CFG0);
+
+ /* Write 0 to SW_TRIGGER_FULL_CALIB */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CSR_CDC_CTRL_CFG0) & ~CDC_SW_TRIGGER_FULL_CALIB), SDCC_CSR_CDC_CTRL_CFG0);
+
+ /* Write 1 to HW_AUTO_CAL_EN */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CSR_CDC_CTRL_CFG0) | CDC_HW_AUTO_CAL_EN), SDCC_CSR_CDC_CTRL_CFG0);
+
+ /* Write 1 to TIMER_ENA */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CSR_CDC_CAL_TIMER_CFG0) | CDC_TIMER_EN), SDCC_CSR_CDC_CAL_TIMER_CFG0);
+
+ /* Wait for CALIBRATION_DONE in CDC_STATUS */
+ timeout = 50;
+ while (!(REG_READ32(host, SDCC_CSR_CDC_STATUS0) & BIT(0)))
+ {
+ timeout--;
+ mdelay(1);
+ if (!timeout)
+ {
+ dprintf(CRITICAL, "Error: Calibration done in CDC status not set\n");
+ return 1;
+ }
+ }
+
+ cdc_err = REG_READ32(host, SDCC_CSR_CDC_STATUS0) & CSR_CDC_ERROR_MASK;
+ if (cdc_err)
+ {
+ dprintf(CRITICAL, "CDC error set during calibration: %x\n", cdc_err);
+ return 1;
+ }
+ /* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) | START_CDC_TRAFFIC), SDCC_CDC_DDR200_CFG);
+
+ return 0;
+}
+
+/*
+ * Function: sdhci msm execute tuning
+ * Arg : Host structure & bus width
+ * Return : 0 on Success, 1 on Failure
+ * Flow: : Execute Tuning sequence for HS200
+ */
+uint32_t sdhci_msm_execute_tuning(struct sdhci_host *host, uint32_t bus_width)
+{
+ uint32_t *tuning_block;
+ uint32_t *tuning_data;
+ uint32_t tuned_phases[MAX_PHASES] = {{0}};
+ uint32_t size;
+ uint32_t phase = 0;
+ uint32_t tuned_phase_cnt = 0;
+ int ret = 0;
+ struct sdhci_msm_data *msm_host;
+
+ msm_host = host->msm_host;
+
+ /* In Tuning mode */
+ host->tuning_in_progress = true;
+
+ /* Calibration for CDCLP533 needed for HS400 mode */
+ if (msm_host->tuning_done && !msm_host->calibration_done && host->timing == MMC_HS400_TIMING)
+ {
+ ret = sdhci_msm_cdclp533_calibration(host);
+ if (!ret)
+ msm_host->calibration_done = true;
+ goto out;
+ }
+
+ if (bus_width == DATA_BUS_WIDTH_8BIT)
+ {
+ tuning_block = tuning_block_128;
+ size = sizeof(tuning_block_128);
+ }
+ else
+ {
+ tuning_block = tuning_block_64;
+ size = sizeof(tuning_block_64);
+ }
+
+ tuning_data = (uint32_t *) memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
+
+ ASSERT(tuning_data);
+
+ /* Reset & Initialize the DLL block */
+ sdhci_msm_init_dll(host);
+
+ while (phase < MAX_PHASES)
+ {
+ struct mmc_command cmd = {0};
+
+ /* configure dll to set phase delay */
+ sdhci_msm_config_dll(host, phase);
+
+ cmd.cmd_index = CMD21_SEND_TUNING_BLOCK;
+ cmd.argument = 0x0;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R1;
+ cmd.trans_mode = SDHCI_MMC_READ;
+ cmd.data_present = 0x1;
+ cmd.data.data_ptr = tuning_data;
+ cmd.data.blk_sz = size;
+ cmd.data.num_blocks = 0x1;
+
+ /* send command */
+ if (!sdhci_send_command(host, &cmd) && !memcmp(tuning_data, tuning_block, size))
+ tuned_phases[tuned_phase_cnt++] = phase;
+
+ phase++;
+ }
+
+ /* Find the appropriate tuned phase */
+ if (tuned_phase_cnt)
+ {
+ ret = sdhci_msm_find_appropriate_phase(host, tuned_phases, tuned_phase_cnt);
+
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed in selecting the tuning phase\n");
+ ret = 1;
+ goto free;
+ }
+
+ phase = (uint32_t) ret;
+ ret = 0;
+
+ sdhci_msm_config_dll(host, phase);
+
+ /* Save the tuned phase */
+ host->msm_host->saved_phase = phase;
+ }
+ else
+ {
+ dprintf(CRITICAL, "Failed to get tuned phase\n");
+ ret = 1;
+ }
+
+free:
+ free(tuning_data);
+out:
+ /* Tuning done */
+ host->tuning_in_progress = false;
+ host->msm_host->tuning_done = true;
+ return ret;
+}
+
+/*
+ * API to disable HC mode
+ */
+void sdhci_mode_disable(struct sdhci_host *host)
+{
+ /* Disable HC mode */
+ RMWREG32((host->msm_host->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, 0);
+}
+
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 4067a8c..1a1c444 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -501,9 +501,9 @@
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
- { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
};
/* Pull configs for sdc pins */
diff --git a/target/msm8226/oem_panel.c b/target/msm8226/oem_panel.c
index 9f3127b..a0fcc41 100755
--- a/target/msm8226/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -72,6 +72,7 @@
HW_PLATFORM_SUBTYPE_SKUF = 2,
HW_PLATFORM_SUBTYPE_1080P = 2,
HW_PLATFORM_SUBTYPE_SKUAB = 3,
+ HW_PLATFORM_SUBTYPE_1080P_EXT_BUCK = 3,
HW_PLATFORM_SUBTYPE_SKUG = 5,
};
@@ -349,11 +350,11 @@
break;
case HW_PLATFORM_MTP:
case HW_PLATFORM_SURF:
- if (hw_subtype == HW_PLATFORM_SUBTYPE_1080P) {
+ if ((hw_subtype == HW_PLATFORM_SUBTYPE_1080P) ||
+ (hw_subtype == HW_PLATFORM_SUBTYPE_1080P_EXT_BUCK))
panel_id = JDI_1080P_VIDEO_PANEL;
- } else {
+ else
panel_id = nt35590_panel_id;
- }
break;
default:
dprintf(CRITICAL, "Display not enabled for %d HW type\n"
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index 1ee89bf..2e6c151 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -239,10 +239,19 @@
config.bus_width = DATA_BUS_WIDTH_8BIT;
};
- config.max_clk_rate = MMC_CLK_200MHZ;
-
/* Trying Slot 1*/
config.slot = 1;
+ /*
+ * For 8974 AC platform the software clock
+ * plan recommends to use the following frequencies:
+ * 200 MHz --> 192 MHZ
+ * 400 MHZ --> 384 MHZ
+ * only for emmc slot
+ */
+ if (platform_is_8974ac())
+ config.max_clk_rate = MMC_CLK_192MHZ;
+ else
+ config.max_clk_rate = MMC_CLK_200MHZ;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
@@ -250,6 +259,7 @@
if (!(dev = mmc_init(&config))) {
/* Trying Slot 2 next */
config.slot = 2;
+ config.max_clk_rate = MMC_CLK_200MHZ;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
@@ -685,6 +695,9 @@
#ifdef SSD_ENABLE
clock_ce_disable(SSD_CE_INSTANCE_1);
#endif
+
+ /* Disable HC mode before jumping to kernel */
+ sdhci_mode_disable(&dev->host);
}
void shutdown_device()
@@ -745,9 +758,20 @@
{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
};
+ struct tlmm_cfgs sdc1_rclk_cfg[] =
+ {
+ { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK },
+ };
+
/* Set the drive strength & pull control values */
tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+
+ /* RCLK is supported only with 8974 pro, set rclk to pull down
+ * only for 8974 pro targets
+ */
+ if (!platform_is_8974())
+ tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
}
int emmc_recovery_init(void)