platform: msm_shared: Use DSI PLL1 base defined in mipi structure
Derived platforms can have different base offsets. Use the PLL1
base offset from updated mipi structure.
Change-Id: Iead4f257801705a6dc98c58c23142fe084ad487e
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 3e537c9..12995ff 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -252,8 +252,8 @@
int rdbk_len);
int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base,
struct mdss_dsi_pll_config *pd);
-void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
- struct mdss_dsi_pll_config *pd);
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t pll_1_base,
+ uint32_t ctl_base, struct mdss_dsi_pll_config *pd);
void mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base);
uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base);
void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t pll_base);
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
index 780b56e..6a323be 100644
--- a/platform/msm_shared/mipi_dsi_autopll_20nm.c
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -278,8 +278,8 @@
dmb();
}
-void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
- struct mdss_dsi_pll_config *pd)
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base,uint32_t pll_1_base,
+ uint32_t ctl_base, struct mdss_dsi_pll_config *pd)
{
mdss_dsi_pll_20nm_phy_config(pll_base);
@@ -290,7 +290,7 @@
*/
if (ctl_base == MIPI_DSI0_BASE) {
dprintf(SPEW, "Calling disable function for PHY PLL 1 \n");
- mdss_dsi_pll_20nm_disable(DSI1_PLL_BASE);
+ mdss_dsi_pll_20nm_disable(pll_1_base);
}
mdss_dsi_pll_20nm_config_vco_rate(pll_base, pd);
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 8d7863f..8eba8e0 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -286,6 +286,7 @@
return ret;
}
mdss_dsi_auto_pll_20nm_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.pll_1_base,
pinfo->mipi.ctl_base,
pll_data);
dsi_pll_20nm_enable_seq(pinfo->mipi.pll_0_base);