msm_shared/mmc: cleanup mmc clock
Moved platform specific code to platform files.
Change-Id: Id12247e6ab7619de86715f0241f56ba8f24ff1ec
diff --git a/platform/msm7k/acpuclock.c b/platform/msm7k/acpuclock.c
old mode 100755
new mode 100644
index 25c7ceb..695f18e
--- a/platform/msm7k/acpuclock.c
+++ b/platform/msm7k/acpuclock.c
@@ -10,7 +10,7 @@
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
+ * the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -20,7 +20,7 @@
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
@@ -31,6 +31,8 @@
#include <kernel/thread.h>
#include <platform/iomap.h>
#include <reg.h>
+#include <debug.h>
+#include <mmc.h>
#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
@@ -104,6 +106,23 @@
DIV_4 << 1 | 0,
};
+/* enum for SDC CLK IDs */
+enum
+{
+ SDC1_CLK = 19,
+ SDC1_PCLK = 20,
+ SDC2_CLK = 21,
+ SDC2_PCLK = 22,
+ SDC3_CLK = 23,
+ SDC3_PCLK = 24,
+ SDC4_CLK = 25,
+ SDC4_PCLK = 26
+};
+
+/* Zero'th entry is dummy */
+static uint8_t sdc_clk[] = {0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
+static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
+
void mdelay(unsigned msecs);
@@ -151,3 +170,39 @@
#endif
}
}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ uint32_t reg = 0;
+
+ if( mmc_clock_set_rate(sdc_clk[interface], freq) < 0 )
+ {
+ dprintf(CRITICAL, "Failure setting clock rate for MCLK - "
+ "clk_rate: %d\n!", freq);
+ ASSERT(0);
+ }
+
+ /* enable clock */
+ if( mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0 )
+ {
+ dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
+ ASSERT(0);
+ }
+
+ reg |= MMC_BOOT_MCI_CLK_ENABLE;
+ reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+ reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
+ writel( reg, MMC_BOOT_MCI_CLK );
+}
+
+/* Intialize MMC clock */
+void clock_init_mmc(uint32_t interface)
+{
+ if( mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0 )
+ {
+ dprintf(CRITICAL, "Failure enabling PCLK!\n");
+ ASSERT(0);
+ }
+}
+
diff --git a/platform/msm7x27a/acpuclock.c b/platform/msm7x27a/acpuclock.c
old mode 100755
new mode 100644
index c203813..4d923e6
--- a/platform/msm7x27a/acpuclock.c
+++ b/platform/msm7x27a/acpuclock.c
@@ -32,6 +32,8 @@
#include <platform/iomap.h>
#include <reg.h>
#include <smem.h>
+#include <debug.h>
+#include <mmc.h>
#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
#define BIT(x) (1 << (x))
@@ -123,6 +125,23 @@
0x000000FF /* Mask to read src1 */
};
+/* enum for SDC CLK IDs */
+enum
+{
+ SDC1_CLK = 19,
+ SDC1_PCLK = 20,
+ SDC2_CLK = 21,
+ SDC2_PCLK = 22,
+ SDC3_CLK = 23,
+ SDC3_PCLK = 24,
+ SDC4_CLK = 25,
+ SDC4_PCLK = 26
+};
+
+/* Zero'th entry is dummy */
+static uint8_t sdc_clk[] = {0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
+static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
+
void mdelay(unsigned msecs);
unsigned board_msm_id(void);
@@ -252,3 +271,39 @@
/* USB local clock control not enabled; use proc comm */
usb_clock_init();
}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ uint32_t reg = 0;
+
+ if( mmc_clock_set_rate(sdc_clk[interface], freq) < 0 )
+ {
+ dprintf(CRITICAL, "Failure setting clock rate for MCLK - "
+ "clk_rate: %d\n!", freq);
+ ASSERT(0);
+ }
+
+ /* enable clock */
+ if( mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0 )
+ {
+ dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
+ ASSERT(0);
+ }
+
+ reg |= MMC_BOOT_MCI_CLK_ENABLE;
+ reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+ reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
+ writel( reg, MMC_BOOT_MCI_CLK );
+}
+
+/* Intialize MMC clock */
+void clock_init_mmc(uint32_t interface)
+{
+ if( mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0 )
+ {
+ dprintf(CRITICAL, "Failure enabling PCLK!\n");
+ ASSERT(0);
+ }
+}
+
diff --git a/platform/msm7x30/acpuclock.c b/platform/msm7x30/acpuclock.c
index 2a42297..c6aae9c 100644
--- a/platform/msm7x30/acpuclock.c
+++ b/platform/msm7x30/acpuclock.c
@@ -30,6 +30,8 @@
#include <kernel/thread.h>
#include <platform/iomap.h>
#include <reg.h>
+#include <debug.h>
+#include <mmc.h>
#define ACPU_806MHZ 42
#define ACPU_1024MHZ 53
@@ -49,6 +51,24 @@
/* mv = (750mV + (raw * 25mV)) * (2 - VREF_SEL) */
#define VDD_RAW(mv) (((MV(mv) / V_STEP) - 30) | VREG_DATA)
+
+/* enum for SDC CLK IDs */
+enum
+{
+ SDC1_CLK = 19,
+ SDC1_PCLK = 20,
+ SDC2_CLK = 21,
+ SDC2_PCLK = 22,
+ SDC3_CLK = 23,
+ SDC3_PCLK = 24,
+ SDC4_CLK = 25,
+ SDC4_PCLK = 26
+};
+
+/* Zero'th entry is dummy */
+static uint8_t sdc_clk[] = {0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
+static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
+
void spm_init(void)
{
writel(0x05, MSM_SAW_BASE + 0x10); /* MSM_SPM_REG_SAW_CFG */
@@ -309,3 +329,39 @@
val = val | readl(SH2_GLBL_CLK_ENA_SC);
writel(val, SH2_GLBL_CLK_ENA_SC);
}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ uint32_t reg = 0;
+
+ if( mmc_clock_set_rate(sdc_clk[interface], freq) < 0 )
+ {
+ dprintf(CRITICAL, "Failure setting clock rate for MCLK - "
+ "clk_rate: %d\n!", freq);
+ ASSERT(0);
+ }
+
+ /* enable clock */
+ if( mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0 )
+ {
+ dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
+ ASSERT(0);
+ }
+
+ reg |= MMC_BOOT_MCI_CLK_ENABLE;
+ reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+ reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
+ writel( reg, MMC_BOOT_MCI_CLK );
+}
+
+/* Intialize MMC clock */
+void clock_init_mmc(uint32_t interface)
+{
+ if( mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0 )
+ {
+ dprintf(CRITICAL, "Failure enabling PCLK!\n");
+ ASSERT(0);
+ }
+}
+
diff --git a/platform/msm8960/acpuclock.c b/platform/msm8960/acpuclock.c
index 6d65504..404bee2 100644
--- a/platform/msm8960/acpuclock.c
+++ b/platform/msm8960/acpuclock.c
@@ -32,6 +32,7 @@
#include <platform/clock.h>
#include <uart_dm.h>
#include <gsbi.h>
+#include <mmc.h>
/* Set rate and enable the clock */
void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr)
@@ -184,7 +185,8 @@
while (!readl(MM_PLL1_STATUS_REG));
}
-void config_mdp_lut_clk(void){
+void config_mdp_lut_clk(void)
+{
/* Force on*/
writel(MDP_LUT_VAL, MDP_LUT_CC_REG);
}
@@ -204,7 +206,8 @@
}
/* Initialize all clocks needed by Display */
-void mmss_clock_init(void){
+void mmss_clock_init(void)
+{
/* Configure Pixel clock */
config_mmss_clk(PIXEL_NS_VAL, PIXEL_MD_VAL, PIXEL_CC_VAL, PIXEL_NS_REG, PIXEL_MD_REG, PIXEL_CC_REG);
@@ -217,3 +220,40 @@
/* Configure ESC clock */
config_mmss_clk(ESC_NS_VAL, 0x0, ESC_CC_VAL, ESC_NS_REG, 0x0, ESC_CC_REG);
}
+
+/* Intialize MMC clock */
+void clock_init_mmc(uint32_t interface)
+{
+ /* Nothing to be done. */
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ uint32_t reg = 0;
+
+ switch(freq)
+ {
+ case MMC_CLK_400KHZ:
+ clock_config(SDC_CLK_NS_400KHZ,
+ SDC_CLK_MD_400KHZ,
+ SDC_NS(interface),
+ SDC_MD(interface));
+ break;
+ case MMC_CLK_48MHZ:
+ case MMC_CLK_50MHZ: /* Max supported is 48MHZ */
+ clock_config(SDC_CLK_NS_48MHZ,
+ SDC_CLK_MD_48MHZ,
+ SDC_NS(interface),
+ SDC_MD(interface));
+ break;
+ default:
+ ASSERT(0);
+
+ }
+
+ reg |= MMC_BOOT_MCI_CLK_ENABLE;
+ reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+ reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
+ writel( reg, MMC_BOOT_MCI_CLK );
+}
diff --git a/platform/msm8960/include/platform/clock.h b/platform/msm8960/include/platform/clock.h
index 39b9856..f254f36 100644
--- a/platform/msm8960/include/platform/clock.h
+++ b/platform/msm8960/include/platform/clock.h
@@ -45,6 +45,13 @@
#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
+/* NS/MD value for MMC */
+#define SDC_CLK_NS_400KHZ 0x00440040
+#define SDC_CLK_MD_400KHZ 0x00010043
+
+#define SDC_CLK_NS_48MHZ 0x00FE005B
+#define SDC_CLK_MD_48MHZ 0x000100FD
+
void hsusb_clock_init(void);
void clock_config_uart_dm(uint8_t id);
void clock_config_i2c(uint8_t id, uint32_t freq);
diff --git a/platform/msm8960/mmc_init.c b/platform/msm8960/mmc_init.c
deleted file mode 100644
index 811861a..0000000
--- a/platform/msm8960/mmc_init.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of Code Aurora Forum, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <debug.h>
-#include <reg.h>
-#include <platform/iomap.h>
-#include "mmc.h"
-
-#define MSM_BOOT_SDC_NS_VAL_400KHZ 0x00440040
-#define MSM_BOOT_SDC_MD_VAL_400KHZ 0x00010043
-
-#define MSM_BOOT_SDC_NS_VAL_48MHZ 0x00FE005B
-#define MSM_BOOT_SDC_MD_VAL_48MHZ 0x000100FD
-
-void clock_set_enable (unsigned char slot, unsigned int mclk)
-{
-
- if (mclk == MMC_CLK_400KHZ)
- {
- clock_config(MSM_BOOT_SDC_NS_VAL_400KHZ,
- MSM_BOOT_SDC_MD_VAL_400KHZ,
- SDC_NS(slot),
- SDC_MD(slot));
- mdelay(10);
- }
- else if (mclk == MMC_CLK_48MHZ)
- {
- clock_config(MSM_BOOT_SDC_NS_VAL_48MHZ,
- MSM_BOOT_SDC_MD_VAL_48MHZ,
- SDC_NS(slot),
- SDC_MD(slot));
- mdelay(10);
- }
- else
- {
- ASSERT(0);
- }
-}
-
diff --git a/platform/msm8960/rules.mk b/platform/msm8960/rules.mk
index acfd810..7804f60 100644
--- a/platform/msm8960/rules.mk
+++ b/platform/msm8960/rules.mk
@@ -20,7 +20,6 @@
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/interrupts.o \
$(LOCAL_DIR)/acpuclock.o \
- $(LOCAL_DIR)/mmc_init.o \
$(LOCAL_DIR)/gpio.o \
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/platform/msm8x60/acpuclock.c b/platform/msm8x60/acpuclock.c
index a2158fb..0577bb8 100644
--- a/platform/msm8x60/acpuclock.c
+++ b/platform/msm8x60/acpuclock.c
@@ -35,6 +35,7 @@
#include <platform/scm-io.h>
#include <uart_dm.h>
#include <gsbi.h>
+#include <mmc.h>
/* Read, modify, then write-back a register. */
static void rmwreg(uint32_t val, uint32_t reg, uint32_t mask)
@@ -330,3 +331,39 @@
writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
}
+/* Intialize MMC clock */
+void clock_init_mmc(uint32_t interface)
+{
+ /* Nothing to be done. */
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ uint32_t reg = 0;
+
+ switch(freq)
+ {
+ case MMC_CLK_400KHZ:
+ clock_config(SDC_CLK_NS_400KHZ,
+ SDC_CLK_MD_400KHZ,
+ SDC_NS(interface),
+ SDC_MD(interface));
+ break;
+ case MMC_CLK_48MHZ:
+ case MMC_CLK_50MHZ: /* Max supported is 48MHZ */
+ clock_config(SDC_CLK_NS_48MHZ,
+ SDC_CLK_MD_48MHZ,
+ SDC_NS(interface),
+ SDC_MD(interface));
+ break;
+ default:
+ ASSERT(0);
+
+ }
+
+ reg |= MMC_BOOT_MCI_CLK_ENABLE;
+ reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+ reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
+ writel( reg, MMC_BOOT_MCI_CLK );
+}
diff --git a/platform/msm8x60/include/platform/clock.h b/platform/msm8x60/include/platform/clock.h
index 1dab781..7f8f818 100644
--- a/platform/msm8x60/include/platform/clock.h
+++ b/platform/msm8x60/include/platform/clock.h
@@ -98,6 +98,13 @@
#define I2C_CLK_MD_24MHz 0x000100FB
#define I2C_CLK_NS_24MHz 0x00FC005B
+/* NS/MD value for MMC */
+#define SDC_CLK_NS_400KHZ 0x0010005B
+#define SDC_CLK_MD_400KHZ 0x0001000F
+
+#define SDC_CLK_NS_48MHZ 0x00FE005B
+#define SDC_CLK_MD_48MHZ 0x000100FD
+
enum clk_sources {
PLL_0 = 0,
PLL_1,
diff --git a/platform/msm8x60/include/platform/iomap.h b/platform/msm8x60/include/platform/iomap.h
index 39fa22b..714c5c8 100755
--- a/platform/msm8x60/include/platform/iomap.h
+++ b/platform/msm8x60/include/platform/iomap.h
@@ -105,6 +105,8 @@
#define CLK_CTL_BASE 0x00900000
+#define SDC_MD(n) (CLK_CTL_BASE + 0x2828 + (32 * ((n) - 1)))
+#define SDC_NS(n) (CLK_CTL_BASE + 0x282C + (32 * ((n) - 1)))
#define USB_HS1_HCLK_CTL (CLK_CTL_BASE + 0x2900)
#define USB_HS1_XCVR_FS_CLK_MD (CLK_CTL_BASE + 0x2908)
#define USB_HS1_XCVR_FS_CLK_NS (CLK_CTL_BASE + 0x290C)
diff --git a/platform/msm8x60/mmc_init.c b/platform/msm8x60/mmc_init.c
deleted file mode 100755
index 56cff45..0000000
--- a/platform/msm8x60/mmc_init.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of Code Aurora Forum, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <string.h>
-#include <stdlib.h>
-#include <debug.h>
-#include <reg.h>
-#include "mmc.h"
-
-#define CLK_CTL_BASE 0x00900000
-
-#define SDC_NS(n) (CLK_CTL_BASE + 0x282C + 32*((n) - 1))
-
-#define SDC_MD(n) (CLK_CTL_BASE + 0x2828 + 32*((n) - 1))
-
-static void mmc_set_clk(unsigned slot, unsigned ns, unsigned md)
-{
- unsigned int val;
- unsigned char sdc_id = slot;
- /*Clock Init*/
- // 1. Set bit 7 in the NS registers
- val = 1 << 7;
- writel(val, SDC_NS(sdc_id));
-
- //2. Program MD registers
- writel(md, SDC_MD(sdc_id));
-
- //3. Program NS resgister OR'd with Bit 7
- val = 1 << 7;
- val |= ns;
- writel(val, SDC_NS(sdc_id));
-
- //4. Clear bit 7 of NS register
- val = 1 << 7;
- val = ~val;
- val = val & readl(SDC_NS(sdc_id));
- writel(val, SDC_NS(sdc_id));
-
- //5. For MD != NA set bit 8 of NS register
- val = 1 << 8;
- val = val | readl(SDC_NS(sdc_id));
- writel(val, SDC_NS(sdc_id));
-
- //6. Set bit 11 in NS register
- val = 1 << 11;
- val = val | readl(SDC_NS(sdc_id));
- writel(val, SDC_NS(sdc_id));
-
- //7. Set bit 9 in NS register
- val = 1 << 9;
- val = val | readl(SDC_NS(sdc_id));
- writel(val, SDC_NS(sdc_id));
-}
-
-
-void clock_set_enable (unsigned slot, unsigned int mclk)
-{
- if (mclk == MMC_CLK_400KHZ)
- {
- mmc_set_clk(slot, 0x0010005B, 0x0001000F);
- }
- else if (mclk == MMC_CLK_20MHZ)
- {
- mmc_set_clk(slot, 0x00ED0043, 0x000100EC);
- }
- else if (mclk == MMC_CLK_48MHZ)
- {
- mmc_set_clk(slot, 0x00FE005B, 0x000100FD);
- }
-}
diff --git a/platform/msm8x60/rules.mk b/platform/msm8x60/rules.mk
index 19d571e..2aa1d55 100644
--- a/platform/msm8x60/rules.mk
+++ b/platform/msm8x60/rules.mk
@@ -24,7 +24,6 @@
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/interrupts.o \
$(LOCAL_DIR)/acpuclock.o \
- $(LOCAL_DIR)/mmc_init.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/panel.o \
$(LOCAL_DIR)/pmic.o \
diff --git a/platform/msm_shared/include/mmc.h b/platform/msm_shared/include/mmc.h
index 4fb893e..305ba9c 100644
--- a/platform/msm_shared/include/mmc.h
+++ b/platform/msm_shared/include/mmc.h
@@ -504,10 +504,8 @@
struct mmc_boot_host
{
unsigned int mclk_rate;
- unsigned int pclk_rate;
unsigned int ocr;
unsigned int cmd_retry;
- unsigned int clk_enabled;
};
@@ -601,16 +599,6 @@
#define MMC_BOOT_MCI_HFIFO_COUNT ( MMC_BOOT_MCI_FIFO_DEPTH / 2 )
#define MMC_BOOT_MCI_FIFO_SIZE ( MMC_BOOT_MCI_FIFO_DEPTH * 4 )
-/*Need to put at proper place*/
-#define SDC1_CLK 19 /* Secure Digital Card clocks */
-#define SDC1_PCLK 20
-#define SDC2_CLK 21
-#define SDC2_PCLK 22
-#define SDC3_CLK 23
-#define SDC3_PCLK 24
-#define SDC4_CLK 25
-#define SDC4_PCLK 26
-
#define MAX_PARTITIONS 64
#define MMC_BOOT_CHECK_PATTERN 0xAA /* 10101010b */
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index c19d9de..f54e183 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -78,11 +78,6 @@
unsigned int ext3_count = 0;
unsigned int vfat_count = 0;
-#if !(defined(PLATFORM_MSM8X60) || defined(PLATFORM_MSM8960))
-static unsigned mmc_sdc_clk[] = { SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
-static unsigned mmc_sdc_pclk[] = { SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
-#endif
-
unsigned char mmc_slot = 0;
unsigned int mmc_boot_mci_base = 0;
@@ -108,7 +103,6 @@
unsigned int data_len,
unsigned int command, unsigned int addr,
unsigned int *out);
-void clock_set_enable(unsigned slot, unsigned int mclk);
unsigned int SWAP_ENDIAN(unsigned int val)
{
@@ -118,92 +112,6 @@
(val >> 24);
}
-/*
- * Function to enable and set master and peripheral clock for
- * MMC card.
- */
-static unsigned int mmc_boot_enable_clock( struct mmc_boot_host* host,
- unsigned int mclk)
-{
- unsigned int mmc_clk = 0;
-
-#if !(defined(PLATFORM_MSM8X60) || defined(PLATFORM_MSM8960))
- int mmc_signed_ret = 0;
- unsigned SDC_CLK = mmc_sdc_clk[mmc_slot - 1];
- unsigned SDC_PCLK = mmc_sdc_pclk[mmc_slot - 1];
-
- if( host == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- if( !host->clk_enabled )
- {
- /* set clock */
- if( mmc_clock_enable_disable(SDC_PCLK, MMC_CLK_ENABLE) < 0 )
- {
- dprintf(CRITICAL, "Failure enabling PCLK!\n");
- goto error_pclk;
- }
-
- if( mmc_clock_enable_disable(SDC_CLK, MMC_CLK_ENABLE) < 0 )
- {
- dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
- goto error;
- }
- host->clk_enabled = 1;
- }
- if( host->mclk_rate != mclk )
- {
- if( mmc_clock_set_rate(SDC_CLK, mclk) < 0 )
- {
- dprintf(CRITICAL, "Failure setting clock rate for MCLK - clk_rate: %d\n!", mclk );
- goto error_mclk;
- }
-
- if( ( mmc_signed_ret = mmc_clock_get_rate(SDC_CLK) ) < 0 )
- {
- dprintf(CRITICAL, "Failure getting clock rate for MCLK - clk_rate: %d\n!", host->mclk_rate );
- goto error_mclk;
- }
-
- host->mclk_rate = (unsigned int)mmc_signed_ret;
- }
-
- if( ( mmc_signed_ret = mmc_clock_get_rate(SDC_PCLK) ) < 0 )
- {
- dprintf(CRITICAL, "Failure getting clock rate for PCLK - clk_rate: %d\n!", host->pclk_rate );
- goto error_pclk;
- }
-
- host->pclk_rate = ( unsigned int )mmc_signed_ret;
- dprintf(SPEW, "Clock rate - mclk: %dHz pclk: %dHz\n", host->mclk_rate, host->pclk_rate );
-#else
- clock_set_enable(mmc_slot, mclk);
- host->mclk_rate = mclk;
- host->pclk_rate = mclk;
- host->clk_enabled = 1;
-#endif
-
- //enable mci clock
- mmc_clk |= MMC_BOOT_MCI_CLK_ENABLE;
- //enable flow control
- mmc_clk |= MMC_BOOT_MCI_CLK_ENA_FLOW;
- //latch data and command using feedback clock
- mmc_clk |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
- writel( mmc_clk, MMC_BOOT_MCI_CLK );
- return MMC_BOOT_E_SUCCESS;
-
-#if !(defined(PLATFORM_MSM8X60) || defined(PLATFORM_MSM8960))
-error_pclk:
- mmc_clock_enable_disable(SDC_PCLK, MMC_CLK_DISABLE);
-error_mclk:
- mmc_clock_enable_disable(SDC_CLK, MMC_CLK_DISABLE);
-error:
- return MMC_BOOT_E_CLK_ENABLE_FAIL;
-#endif
-}
-
/* Sets a timeout for read operation.
*/
@@ -1619,15 +1527,10 @@
}while( MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE );
-#if defined(PLATFORM_MSM8X60) || defined(PLATFORM_MSM8960)
- mmc_ret = mmc_boot_enable_clock( host, MMC_CLK_48MHZ);
-#else
- mmc_ret = mmc_boot_enable_clock( host, MMC_CLK_50MHZ);
-#endif
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return MMC_BOOT_E_CLK_ENABLE_FAIL;
- }
+ clock_config_mmc(mmc_slot, MMC_CLK_50MHZ);
+
+ host->mclk_rate = MMC_CLK_50MHZ;
+
return MMC_BOOT_E_SUCCESS;
}
@@ -1819,15 +1722,14 @@
host->ocr = MMC_BOOT_OCR_27_36 | MMC_BOOT_OCR_SEC_MODE;
host->cmd_retry = MMC_BOOT_MAX_COMMAND_RETRY;
- host->clk_enabled = 0;
- /* clock frequency should be less than 400KHz in identification mode */
- mmc_ret = mmc_boot_enable_clock( host, MMC_CLK_400KHZ);
+ /* Initialize any clocks needed for SDC controller */
+ clock_init_mmc(mmc_slot);
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return MMC_BOOT_E_CLK_ENABLE_FAIL;
- }
+ /* Setup initial freq to 400KHz */
+ clock_config_mmc(mmc_slot, MMC_CLK_400KHZ);
+
+ host->mclk_rate = MMC_CLK_400KHZ;
/* set power mode*/
/* give some time to reach minimum voltate */
@@ -2178,15 +2080,9 @@
mdelay(1);
-#if defined(PLATFORM_MSM8X60) || defined(PLATFORM_MSM8960)
- mmc_ret = mmc_boot_enable_clock( host, MMC_CLK_48MHZ);
-#else
- mmc_ret = mmc_boot_enable_clock( host, MMC_CLK_50MHZ);
-#endif
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return MMC_BOOT_E_CLK_ENABLE_FAIL;
- }
+ clock_config_mmc(mmc_slot, MMC_CLK_50MHZ);
+
+ host->mclk_rate = MMC_CLK_50MHZ;
return MMC_BOOT_E_SUCCESS;
}