Merge "platform: mipi: Disable DSI1 interrupts"
diff --git a/dev/gcdb/display/oem_panel.c b/dev/gcdb/display/oem_panel.c
index bacea0f..c630fee 100755
--- a/dev/gcdb/display/oem_panel.c
+++ b/dev/gcdb/display/oem_panel.c
@@ -194,8 +194,13 @@
return false;
}
break;
- case MSM8226:
+ case MSM8826:
case MSM8626:
+ case MSM8226:
+ case MSM8926:
+ case MSM8126:
+ case MSM8326:
+ case APQ8026:
switch (hw_id) {
case HW_PLATFORM_QRD:
case HW_PLATFORM_MTP:
@@ -208,6 +213,10 @@
return false;
}
break;
+ default:
+ dprintf(CRITICAL, "GCDB:Display: Platform id:%d not supported\n"
+ , platformid);
+ return false;
}
init_panel_data(panelstruct, pinfo, phy_db);
diff --git a/dev/panel/msm/mipi_truly_video_wvga.c b/dev/panel/msm/mipi_truly_video_wvga.c
index 4e6f416..8a19af8 100644
--- a/dev/panel/msm/mipi_truly_video_wvga.c
+++ b/dev/panel/msm/mipi_truly_video_wvga.c
@@ -74,7 +74,7 @@
};
static char disp_on6[12] = {
0x07, 0x00, 0x29, 0xC0,
- 0xC2, 0x10, 0x06, 0x06,
+ 0xC2, 0x00, 0x06, 0x06,
0x01, 0x03, 0x00, 0xFF
};
static char disp_on7[32] = {
@@ -129,7 +129,7 @@
};
static char disp_on14[8] = {
0x03, 0x00, 0x29, 0xC0,
- 0xDE, 0x01, 0x41, 0xFF
+ 0xDE, 0x01, 0x51, 0xFF
};
static char disp_on15[4] = {
0xE6, 0x51, 0x23, 0x80
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 45f3bc7..731528c 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -70,6 +70,7 @@
/*Target power on reasons*/
+#define HARD_RST 1
#define DC_CHG 8
#define USB_CHG 16
#define PON1 32
diff --git a/platform/msm_shared/bam.c b/platform/msm_shared/bam.c
index bd7a595..25bf9d0 100644
--- a/platform/msm_shared/bam.c
+++ b/platform/msm_shared/bam.c
@@ -223,6 +223,9 @@
/* Initialize FIFO offset for the first read */
bam->pipe[pipe_num].fifo.offset = BAM_DESC_SIZE;
+ writel(P_ENABLE | readl(BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base)),
+ BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base));
+
/* Everything is set.
* Flag pipe init done.
*/
@@ -243,9 +246,9 @@
/* Pipe event threshold register is not relevant in sys modes */
/* Enable pipe in system mode and set the direction */
- writel(P_SYS_MODE_MASK | P_ENABLE |
- (bam->pipe[pipe_num].trans_type << P_DIRECTION_SHIFT),
- BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base));
+ writel(P_SYS_MODE_MASK | bam->pipe[pipe_num].lock_grp << P_LOCK_GRP_SHIFT |
+ (bam->pipe[pipe_num].trans_type << P_DIRECTION_SHIFT),
+ BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base));
/* Mark the pipe FIFO as uninitialized. */
bam->pipe[pipe_num].initialized = 0;
diff --git a/platform/msm_shared/crypto5_eng.c b/platform/msm_shared/crypto5_eng.c
index 669d6ac..ed5c8ad 100644
--- a/platform/msm_shared/crypto5_eng.c
+++ b/platform/msm_shared/crypto5_eng.c
@@ -256,6 +256,7 @@
dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].trans_type = BAM2SYS;
dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.size = params->read_fifo_size;
dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.head = crypto_allocate_fifo(params->read_fifo_size);
+ dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].lock_grp = params->pipes.read_pipe_grp;
/* Set Write pipe params. */
dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].pipe_num = params->pipes.write_pipe;
@@ -263,6 +264,7 @@
dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].trans_type = SYS2BAM;
dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.size = params->write_fifo_size;
dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.head = crypto_allocate_fifo(params->write_fifo_size);
+ dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].lock_grp = params->pipes.write_pipe_grp;
dev->bam.threshold = CRYPTO_MAX_THRESHOLD;
diff --git a/platform/msm_shared/include/bam.h b/platform/msm_shared/include/bam.h
index 099b1b6..ae673ab 100644
--- a/platform/msm_shared/include/bam.h
+++ b/platform/msm_shared/include/bam.h
@@ -81,6 +81,7 @@
#define P_SYS_MODE_MASK (1 << 5)
/* 1: Producer mode 0: Consumer mode */
#define P_DIRECTION_SHIFT 3
+#define P_LOCK_GRP_SHIFT 16
#define P_ENABLE (1 << 1)
#define BAM_P_RSTn(n, x) (0x00001000 + 0x4 + 0x1000 * (n) + (x))
@@ -198,6 +199,7 @@
uint8_t spi_num;
uint8_t int_mode;
uint8_t initialized;
+ uint8_t lock_grp;
};
/* Structure to define a BAM instance being used
diff --git a/platform/msm_shared/include/crypto5_eng.h b/platform/msm_shared/include/crypto5_eng.h
index 958fa1a..872f46e 100644
--- a/platform/msm_shared/include/crypto5_eng.h
+++ b/platform/msm_shared/include/crypto5_eng.h
@@ -103,6 +103,8 @@
{
uint8_t read_pipe;
uint8_t write_pipe;
+ uint8_t read_pipe_grp;
+ uint8_t write_pipe_grp;
};
struct output_dump
diff --git a/platform/msm_shared/include/qpic_nand.h b/platform/msm_shared/include/qpic_nand.h
index abc2bb9..0676301 100644
--- a/platform/msm_shared/include/qpic_nand.h
+++ b/platform/msm_shared/include/qpic_nand.h
@@ -325,6 +325,9 @@
unsigned read_pipe;
unsigned write_pipe;
unsigned cmd_pipe;
+ uint8_t read_pipe_grp;
+ uint8_t write_pipe_grp;
+ uint8_t cmd_pipe_grp;
};
/* Structure to define the initial nand config */
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index e6bac4e..5616956 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -255,8 +255,13 @@
}
/* 6 enable seq for 8226 target */
- else if (platformid == MSM8226 ||
- platformid == MSM8626) {
+ else if (platformid == MSM8826 ||
+ platformid == MSM8626 ||
+ platformid == MSM8226 ||
+ platformid == MSM8926 ||
+ platformid == MSM8126 ||
+ platformid == MSM8326 ||
+ platformid == APQ8026) {
if (dsi_pll_enable_seq_m()) {
} else if (dsi_pll_enable_seq_d()) {
} else if (dsi_pll_enable_seq_d()) {
@@ -267,7 +272,7 @@
dprintf(CRITICAL, "Not able to enable the pll\n");
}
} else {
- dprintf(CRITICAL, "Target not supported\n");
+ dprintf(CRITICAL, "Target not supported in auto PLL\n");
}
}
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index 6a386ce..16a498b 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -259,6 +259,7 @@
bam.pipe[DATA_PRODUCER_PIPE_INDEX].trans_type = BAM2SYS;
bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.size = QPIC_BAM_DATA_FIFO_SIZE;
bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.head = data_desc_fifo;
+ bam.pipe[DATA_PRODUCER_PIPE_INDEX].lock_grp = config->pipes.read_pipe_grp;
/* Set Write pipe params. */
bam.pipe[DATA_CONSUMER_PIPE_INDEX].pipe_num = config->pipes.write_pipe;
@@ -266,6 +267,7 @@
bam.pipe[DATA_CONSUMER_PIPE_INDEX].trans_type = SYS2BAM;
bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.size = QPIC_BAM_DATA_FIFO_SIZE;
bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.head = data_desc_fifo;
+ bam.pipe[DATA_CONSUMER_PIPE_INDEX].lock_grp = config->pipes.write_pipe_grp;
/* Set Cmd pipe params. */
bam.pipe[CMD_PIPE_INDEX].pipe_num = config->pipes.cmd_pipe;
@@ -273,6 +275,7 @@
bam.pipe[CMD_PIPE_INDEX].trans_type = BAM2SYS;
bam.pipe[CMD_PIPE_INDEX].fifo.size = QPIC_BAM_CMD_FIFO_SIZE;
bam.pipe[CMD_PIPE_INDEX].fifo.head = cmd_desc_fifo;
+ bam.pipe[CMD_PIPE_INDEX].lock_grp = config->pipes.cmd_pipe_grp;
/* Programs the threshold for BAM transfer
* When this threshold is reached, BAM signals the peripheral via the pipe_bytes_available
diff --git a/target/mdm9625/init.c b/target/mdm9625/init.c
index ab9fd90..77f7331 100644
--- a/target/mdm9625/init.c
+++ b/target/mdm9625/init.c
@@ -54,6 +54,11 @@
#define DATA_PRODUCER_PIPE 1
#define CMD_PIPE 2
+/* NANDc BAM pipe groups */
+#define DATA_PRODUCER_PIPE_GRP 0
+#define DATA_CONSUMER_PIPE_GRP 0
+#define CMD_PIPE_GRP 1
+
/* NANDc EE */
#define QPIC_NAND_EE 0
@@ -122,6 +127,10 @@
config.pipes.write_pipe = DATA_CONSUMER_PIPE;
config.pipes.cmd_pipe = CMD_PIPE;
+ config.pipes.read_pipe_grp = DATA_PRODUCER_PIPE_GRP;
+ config.pipes.write_pipe_grp = DATA_CONSUMER_PIPE_GRP;
+ config.pipes.cmd_pipe_grp = CMD_PIPE_GRP;
+
config.bam_base = MSM_NAND_BAM_BASE;
config.nand_base = MSM_NAND_BASE;
config.ee = QPIC_NAND_EE;
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 4b3b618..d8c7031 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -55,6 +55,8 @@
#define CRYPTO_ENGINE_FIFO_SIZE 64
#define CRYPTO_ENGINE_READ_PIPE 3
#define CRYPTO_ENGINE_WRITE_PIPE 2
+#define CRYPTO_READ_PIPE_LOCK_GRP 0
+#define CRYPTO_WRITE_PIPE_LOCK_GRP 0
#define CRYPTO_ENGINE_CMD_ARRAY_SIZE 20
#define TLMM_VOL_UP_BTN_GPIO 106
@@ -122,9 +124,11 @@
ce_params.bam_base = MSM_CE1_BAM_BASE;
/* Set up BAM config. */
- ce_params.bam_ee = CRYPTO_ENGINE_EE;
- ce_params.pipes.read_pipe = CRYPTO_ENGINE_READ_PIPE;
- ce_params.pipes.write_pipe = CRYPTO_ENGINE_WRITE_PIPE;
+ ce_params.bam_ee = CRYPTO_ENGINE_EE;
+ ce_params.pipes.read_pipe = CRYPTO_ENGINE_READ_PIPE;
+ ce_params.pipes.write_pipe = CRYPTO_ENGINE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CRYPTO_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CRYPTO_WRITE_PIPE_LOCK_GRP;
/* Assign buffer sizes. */
ce_params.num_ce = CRYPTO_ENGINE_CMD_ARRAY_SIZE;
@@ -350,9 +354,18 @@
{
uint8_t pon_reason = pm8x41_get_pon_reason();
uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
- if (is_cold_boot && ((pon_reason == USB_CHG) || (pon_reason == DC_CHG)))
- return 1;
- return 0;
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /*In case of fastboot reboot or adb reboot we do not want go into
+ * charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot && (!(pon_reason & HARD_RST)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ return 1;
+ else
+ return 0;
}
unsigned target_baseband()
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index 11a9967..7ef2d36 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -70,6 +70,8 @@
#define CE_FIFO_SIZE 64
#define CE_READ_PIPE 3
#define CE_WRITE_PIPE 2
+#define CE_READ_PIPE_LOCK_GRP 0
+#define CE_WRITE_PIPE_LOCK_GRP 0
#define CE_ARRAY_SIZE 20
#ifdef SSD_ENABLE
@@ -174,9 +176,11 @@
ce_params.bam_base = MSM_CE2_BAM_BASE;
/* Set up BAM config. */
- ce_params.bam_ee = CE_EE;
- ce_params.pipes.read_pipe = CE_READ_PIPE;
- ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.bam_ee = CE_EE;
+ ce_params.pipes.read_pipe = CE_READ_PIPE;
+ ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
/* Assign buffer sizes. */
ce_params.num_ce = CE_ARRAY_SIZE;