Merge "target: mdm9625: fix size calculation for available memory"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 7d42713..d50be73 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -77,7 +77,6 @@
#define EXPAND(NAME) #NAME
#define TARGET(NAME) EXPAND(NAME)
-#define DEFAULT_CMDLINE "mem=100M console=null";
#ifdef MEMBASE
#define EMMC_BOOT_IMG_HEADER_ADDR (0xFF000+(MEMBASE))
@@ -132,6 +131,29 @@
extern int fastboot_trigger(void);
#endif
+static void update_ker_tags_rdisk_addr(struct boot_img_hdr *hdr)
+{
+ /* overwrite the destination of specified for the project */
+ /*
+ * Update the value to sane values only when the boot image
+ * header does not have sane values, this is added to make sure
+ * that we always use values from boot.img header and use the
+ * force values when boot image header has default values.
+ */
+#ifdef ABOOT_FORCE_KERNEL_ADDR
+ if (hdr->kernel_addr == ABOOT_DEFAULT_KERNEL_ADDR)
+ hdr->kernel_addr = ABOOT_FORCE_KERNEL_ADDR;
+#endif
+#ifdef ABOOT_FORCE_RAMDISK_ADDR
+ if (hdr->ramdisk_addr == ABOOT_DEFAULT_RAMDISK_ADDR)
+ hdr->ramdisk_addr = ABOOT_FORCE_RAMDISK_ADDR;
+#endif
+#ifdef ABOOT_FORCE_TAGS_ADDR
+ if (hdr->tags_addr == ABOOT_DEFAULT_TAGS_ADDR)
+ hdr->tags_addr = ABOOT_FORCE_TAGS_ADDR;
+#endif
+}
+
static void ptentry_to_tag(unsigned **ptr, struct ptentry *ptn)
{
struct atag_ptbl_entry atag_ptn;
@@ -463,7 +485,6 @@
struct boot_img_hdr *uhdr;
unsigned offset = 0;
unsigned long long ptn = 0;
- const char *cmdline;
int index = INVALID_PTN;
unsigned char *image_addr = 0;
@@ -517,6 +538,13 @@
page_mask = page_size - 1;
}
+ /*
+ * Update the kernel/ramdisk/tags address if the boot image header
+ * has default values, these default values come from mkbootimg when
+ * the boot image is flashed using fastboot flash:raw
+ */
+ update_ker_tags_rdisk_addr(hdr);
+
/* Get virtual addresses since the hdr saves physical addresses. */
hdr->kernel_addr = VA((addr_t)(hdr->kernel_addr));
hdr->ramdisk_addr = VA((addr_t)(hdr->ramdisk_addr));
@@ -723,14 +751,8 @@
unified_boot:
- if(hdr->cmdline[0]) {
- cmdline = (char*) hdr->cmdline;
- } else {
- cmdline = DEFAULT_CMDLINE;
- }
-
boot_linux((void *)hdr->kernel_addr, (void *)hdr->tags_addr,
- (const char *)cmdline, board_machtype(),
+ (const char *)hdr->cmdline, board_machtype(),
(void *)hdr->ramdisk_addr, hdr->ramdisk_size);
return 0;
@@ -742,7 +764,6 @@
struct ptentry *ptn;
struct ptable *ptable;
unsigned offset = 0;
- const char *cmdline;
unsigned char *image_addr = 0;
unsigned kernel_actual;
@@ -804,6 +825,13 @@
return -1;
}
+ /*
+ * Update the kernel/ramdisk/tags address if the boot image header
+ * has default values, these default values come from mkbootimg when
+ * the boot image is flashed using fastboot flash:raw
+ */
+ update_ker_tags_rdisk_addr(hdr);
+
/* Get virtual addresses since the hdr saves physical addresses. */
hdr->kernel_addr = VA(hdr->kernel_addr);
hdr->ramdisk_addr = VA(hdr->ramdisk_addr);
@@ -952,17 +980,10 @@
}
continue_boot:
- if(hdr->cmdline[0]) {
- cmdline = (char*) hdr->cmdline;
- } else {
- cmdline = DEFAULT_CMDLINE;
- }
- dprintf(INFO, "cmdline = '%s'\n", cmdline);
-
/* TODO: create/pass atags to kernel */
boot_linux((void *)hdr->kernel_addr, (void *)hdr->tags_addr,
- (const char *)cmdline, board_machtype(),
+ (const char *)hdr->cmdline, board_machtype(),
(void *)hdr->ramdisk_addr, hdr->ramdisk_size);
return 0;
@@ -1224,16 +1245,12 @@
kernel_actual = ROUND_TO_PAGE(hdr->kernel_size, page_mask);
ramdisk_actual = ROUND_TO_PAGE(hdr->ramdisk_size, page_mask);
- /* overwrite the destination of specified for the project */
-#ifdef ABOOT_FORCE_KERNEL_ADDR
- hdr->kernel_addr = ABOOT_FORCE_KERNEL_ADDR;
-#endif
-#ifdef ABOOT_FORCE_RAMDISK_ADDR
- hdr->ramdisk_addr = ABOOT_FORCE_RAMDISK_ADDR;
-#endif
-#ifdef ABOOT_FORCE_TAGS_ADDR
- hdr->tags_addr = ABOOT_FORCE_TAGS_ADDR;
-#endif
+ /*
+ * Update the kernel/ramdisk/tags address if the boot image header
+ * has default values, these default values come from mkbootimg when
+ * the boot image is flashed using fastboot flash:raw
+ */
+ update_ker_tags_rdisk_addr(hdr);
/* Get virtual addresses since the hdr saves physical addresses. */
hdr->kernel_addr = VA(hdr->kernel_addr);
diff --git a/app/tests/i2c_test.c b/app/tests/i2c_test.c
index cfaa920..8d2c1e3 100644
--- a/app/tests/i2c_test.c
+++ b/app/tests/i2c_test.c
@@ -38,7 +38,7 @@
struct qup_i2c_dev *dev;
char ret[100] = {'\0'};
- dev = qup_blsp_i2c_init(BLSP_ID_2, QUP_ID_4, 100000, 24000000);
+ dev = qup_blsp_i2c_init(BLSP_ID_2, QUP_ID_4, 100000, 19200000);
if (!dev) {
dprintf(CRITICAL, "Failed initializing I2c\n");
diff --git a/platform/msm8610/acpuclock.c b/platform/msm8610/acpuclock.c
index 3656468..1d3fcfd 100644
--- a/platform/msm8610/acpuclock.c
+++ b/platform/msm8610/acpuclock.c
@@ -38,32 +38,137 @@
void hsusb_clock_init(void)
{
+ int ret;
+ struct clk *iclk, *cclk;
+
+ ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Wait for the clocks to be stable since we are disabling soon after. */
+ mdelay(1);
+
+ iclk = clk_get("usb_iface_clk");
+ cclk = clk_get("usb_core_clk");
+
+ clk_disable(iclk);
+ clk_disable(cclk);
+
+ /* Wait for the clock disable to complete. */
+ mdelay(1);
+
+ /* Start the block reset for usb */
+ writel(1, USB_HS_BCR);
+
+ /* Wait for reset to complete. */
+ mdelay(1);
+
+ /* Take usb block out of reset */
+ writel(0, USB_HS_BCR);
+
+ /* Wait for the block to be brought out of reset. */
+ mdelay(1);
+
+ ret = clk_enable(iclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_enable(cclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
}
void clock_init_mmc(uint32_t interface)
{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
- uint32_t reg;
+ int ret;
+ char clk_name[64];
- reg = 0;
- reg |= MMC_BOOT_MCI_CLK_ENABLE;
- reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
- reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
- writel(reg, MMC_BOOT_MCI_CLK);
+ snprintf(clk_name, 64, "sdc%u_core_clk", interface);
- /* Wait for the MMC_BOOT_MCI_CLK write to go through. */
- mmc_mclk_reg_wr_delay();
+ /* Disalbe MCI_CLK before changing the sdcc clock */
+ mmc_boot_mci_clk_disable();
- /* Wait 1 ms to provide the free running SD CLK to the card. */
- mdelay(1);
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Enable MCI CLK */
+ mmc_boot_mci_clk_enable();
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+
+ ret = clk_get_set_enable("uart2_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("uart2_core_clk", 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart2_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void clock_config_ce(uint8_t instance)
+{
}
diff --git a/platform/msm8610/include/platform/iomap.h b/platform/msm8610/include/platform/iomap.h
index 5170d29..1900894 100644
--- a/platform/msm8610/include/platform/iomap.h
+++ b/platform/msm8610/include/platform/iomap.h
@@ -34,7 +34,7 @@
#define SDRAM_START_ADDR 0x00000000
-#define MSM_SHARED_BASE 0x0FA00000
+#define MSM_SHARED_BASE 0x0D600000
#define APPS_SS_BASE 0xF9000000
@@ -82,4 +82,36 @@
#define MPM2_MPM_CTRL_BASE 0xFC4A1000
#define MPM2_MPM_PS_HOLD 0xFC4AB000
+/* GPLL */
+#define GPLL0_MODE CLK_CTL_BASE
+#define GPLL0_STATUS (CLK_CTL_BASE + 0x001C)
+#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
+
+/* SDCC */
+#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
+#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
+#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8)
+#define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC)
+#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */
+#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */
+#define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */
+#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
+#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+
+/* UART */
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
+#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
+#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
+#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
+#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714)
+#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718)
+#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C)
+
+/* USB */
+#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
+#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488)
+#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
+#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
+
#endif
diff --git a/platform/msm8610/msm8610-clock.c b/platform/msm8610/msm8610-clock.c
index 3073c51..4d13801 100644
--- a/platform/msm8610/msm8610-clock.c
+++ b/platform/msm8610/msm8610-clock.c
@@ -88,9 +88,199 @@
.disable = clock_lib2_vote_clk_disable,
};
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 600000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F(200000000, gpll0, 3, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 96, 15625),
+ F( 7372800, gpll0, 1, 192, 15625),
+ F(14745600, gpll0, 1, 384, 15625),
+ F(16000000, gpll0, 5, 2, 15),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 5, 1, 5),
+ F(32000000, gpll0, 1, 4, 75),
+ F(40000000, gpll0, 15, 0, 0),
+ F(46400000, gpll0, 1, 29, 375),
+ F(48000000, gpll0, 12.5, 0, 0),
+ F(51200000, gpll0, 1, 32, 375),
+ F(56000000, gpll0, 1, 7, 75),
+ F(58982400, gpll0, 1, 1536, 15625),
+ F(60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+ .parent = &blsp1_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(17),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+ F(75000000, gpll0, 8, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+ .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb_hs_system_clk",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
+ .parent = &usb_hs_system_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_system_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* Clock lookup table */
static struct clk_lookup msm_clocks_8610[] =
{
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+
+ CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+
+ CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
+ CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index c4a86af..d466f40 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -328,8 +328,11 @@
uint32_t reg = 0;
reg = readl(MDP_GDSCR);
if (enable) {
- if (reg & 0x1)
- writel((reg & ~0x1), MDP_GDSCR);
+ if (reg & 0x1) {
+ reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK);
+ reg |= GDSC_EN_FEW_WAIT_256_MASK;
+ writel(reg, MDP_GDSCR);
+ }
while(readl(MDP_GDSCR) & ((GDSC_POWER_ON_BIT) | (GDSC_POWER_ON_STATUS_BIT)));
} else
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index 6906ed2..0e11d4e 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -39,6 +39,8 @@
#define MDP_GDSCR REG_MM(0x2304)
#define GDSC_POWER_ON_BIT BIT(31)
#define GDSC_POWER_ON_STATUS_BIT BIT(29)
+#define GDSC_EN_FEW_WAIT_MASK (0x0F << 16)
+#define GDSC_EN_FEW_WAIT_256_MASK BIT(19)
#define MDP_CMD_RCGR REG_MM(0x2040)
#define MDP_CFG_RCGR REG_MM(0x2044)
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 02dc0a9..a033ac8 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -153,7 +153,7 @@
#define BLSP2_QUP5_I2C_APPS_CBCR (CLK_CTL_BASE + 0xB88)
#define BLSP_QUP_BASE(blsp_id, qup_id) ((blsp_id == 1) ? \
- (PERIPH_SS_BASE + 0x00023000 \
+ (PERIPH_SS_BASE + 0x00123000 \
+ (qup_id * 0x1000)) :\
(PERIPH_SS_BASE + 0x00163000 + \
(qup_id * 0x1000)))
diff --git a/platform/msm_shared/hsusb.c b/platform/msm_shared/hsusb.c
index 897c181..02a15db 100644
--- a/platform/msm_shared/hsusb.c
+++ b/platform/msm_shared/hsusb.c
@@ -667,7 +667,7 @@
hsusb_clock_init();
/* RESET */
- writel(0x00080000, USB_USBCMD);
+ writel(0x00080002, USB_USBCMD);
thread_sleep(20);
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index dd74b10..eea958e 100755
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -270,6 +270,7 @@
MSM8630AA = 143,
MSM8230AA = 144,
MSM8626 = 145,
+ MSM8610 = 147,
MDM9225 = 149,
MDM9225M = 150,
MDM9625M = 152,
@@ -281,6 +282,9 @@
MSM8226 = 158,
MSM8826 = 159,
APQ8030AA = 160,
+ MSM8110 = 161,
+ MSM8210 = 162,
+ MSM8810 = 163,
MSM8125 = 167,
MDM9310 = 171,
APQ8064AA = 172, /* aka V2 SLOW_PRIME */
diff --git a/project/msm8974.mk b/project/msm8974.mk
index ab53f9f..2cbec50 100644
--- a/project/msm8974.mk
+++ b/project/msm8974.mk
@@ -7,6 +7,7 @@
MODULES += app/aboot
DEBUG := 1
+EMMC_BOOT := 1
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
@@ -17,3 +18,16 @@
#Disable thumb mode
ENABLE_THUMB := false
+
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x00008000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x02000000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x01e00000
+
+# Right now we are assuming these are the only default values
+DEFINES += ABOOT_DEFAULT_KERNEL_ADDR=0x10008000
+DEFINES += ABOOT_DEFAULT_RAMDISK_ADDR=0x1100000
+DEFINES += ABOOT_DEFAULT_TAGS_ADDR=0x10000100
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index bad77d9..8d162a7 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -291,3 +291,8 @@
return 0;
}
+
+unsigned target_baseband()
+{
+ return board_baseband();
+}
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index f7dc13b..78efd75 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -33,12 +33,17 @@
#include <platform.h>
#include <uart_dm.h>
#include <mmc.h>
+#include <platform/gpio.h>
#include <spmi.h>
#include <board.h>
+#include <dev/keys.h>
+#include <pm8x41.h>
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
+#define TLMM_VOL_UP_BTN_GPIO 72
+
static uint32_t mmc_sdc_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE };
@@ -49,8 +54,36 @@
#endif
}
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ uint8_t status = 0;
+
+ gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE);
+
+ /* Get status of GPIO */
+ status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
+
+ /* Active low signal. */
+ return !status;
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ /* Volume down button tied in with PMIC RESIN. */
+ return pm8x41_resin_status();
+}
+
static void target_keystatus()
{
+ keys_init();
+
+ if(target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if(target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
}
void target_init(void)
@@ -62,6 +95,8 @@
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
+ target_keystatus();
+
/* Trying Slot 1*/
slot = 1;
base_addr = mmc_sdc_base[slot - 1];
@@ -80,6 +115,14 @@
}
}
+/* Do any target specific intialization needed before entering fastboot mode */
+void target_fastboot_init(void)
+{
+ /* Set the BOOT_DONE flag in PM8110 */
+ pm8x41_set_boot_done();
+}
+
unsigned board_machtype(void)
{
+ return 0;
}
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index c4dc69d..b21142f 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -279,6 +279,11 @@
};
}
+unsigned target_baseband()
+{
+ return board_baseband();
+}
+
void target_serialno(unsigned char *buf)
{
unsigned int serialno;