msm_shared: mdp: fix incorrect flush programming
If continuous splash is enabled, incorrect flush programming in lk
can have adverse effects when kernel boots up. Current flush programming
is writing BIT(16) which is for write-back interface and incorrect.
Fix this and add correct flush bit for DSPP1.
Change-Id: Ifb9c148cf9d7702f2289eb8d9e127e21773d22a2
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 50e1cd5..73294f5 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -515,8 +515,8 @@
int mdp_dsi_video_on(void)
{
int ret = NO_ERROR;
- writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(0x32090, MDP_CTL_1_BASE + CTL_FLUSH);
+ writel(0x22048, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(0x24090, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return ret;
}
@@ -553,8 +553,8 @@
int mdp_dma_on(void)
{
- writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(0x32090, MDP_CTL_1_BASE + CTL_FLUSH);
+ writel(0x22048, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(0x24090, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_CTL_0_BASE + CTL_START);
return NO_ERROR;
}
@@ -566,7 +566,7 @@
int mdp_edp_on(void)
{
- writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(0x22048, MDP_CTL_0_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return NO_ERROR;
}