Merge "target: msm8994: Add kvp data KEY_CURRENT for the regulators."
diff --git a/AndroidBoot.mk b/AndroidBoot.mk
index 089c4d8..06647a9 100644
--- a/AndroidBoot.mk
+++ b/AndroidBoot.mk
@@ -13,10 +13,23 @@
SIGNED_KERNEL := SIGNED_KERNEL=0
endif
+ifeq ($(BOOTLOADER_PLATFORM),)
+ BOOTLOADER_PLATFORM := $(TARGET_BOARD_PLATFORM)
+endif
+
+ifeq ($(PRODUCTS.$(INTERNAL_PRODUCT).PRODUCT_SUPPORTS_VERITY),true)
+ VERIFIED_BOOT := VERIFIED_BOOT=1
+else
+ VERIFIED_BOOT := VERIFEID_BOOT=0
+endif
+
+ifneq ($(TARGET_BUILD_VARIANT),user)
+ DEVICE_STATUS := DEFAULT_UNLOCK=true
+ USER_BUILD_VARIANT=true
+endif
+
ifeq ($(TARGET_BOARD_PLATFORM),msm8660)
BOOTLOADER_PLATFORM := msm8660_surf
-else
- BOOTLOADER_PLATFORM := $(TARGET_BOARD_PLATFORM)
endif
ABOOT_OUT := $(TARGET_OUT_INTERMEDIATES)/ABOOT_OBJ
@@ -29,7 +42,7 @@
# ELF binary for ABOOT
TARGET_ABOOT_ELF := $(PRODUCT_OUT)/aboot.elf
$(TARGET_ABOOT_ELF): ABOOT_CLEAN | $(ABOOT_OUT)
- $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(ABOOT_OUT) $(BOOTLOADER_PLATFORM) $(EMMC_BOOT) $(SIGNED_KERNEL)
+ $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(ABOOT_OUT) $(BOOTLOADER_PLATFORM) $(EMMC_BOOT) $(SIGNED_KERNEL) $(VERIFIED_BOOT) $(DEVICE_STATUS)
# NAND variant output
TARGET_NAND_BOOTLOADER := $(PRODUCT_OUT)/appsboot.mbn
@@ -57,8 +70,8 @@
$(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(NAND_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) $(SIGNED_KERNEL)
# Top level for eMMC variant targets
-$(TARGET_EMMC_BOOTLOADER): emmc_appsbootldr_clean | $(EMMC_BOOTLOADER_OUT)
- $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(EMMC_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) EMMC_BOOT=1 $(SIGNED_KERNEL)
+$(TARGET_EMMC_BOOTLOADER): emmc_appsbootldr_clean | $(EMMC_BOOTLOADER_OUT) $(INSTALLED_KEYSTOREIMAGE_TARGET)
+ $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(EMMC_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) EMMC_BOOT=1 $(SIGNED_KERNEL) $(VERIFIED_BOOT) $(DEVICE_STATUS)
# Keep build NAND & eMMC as default for targets still using TARGET_BOOTLOADER
TARGET_BOOTLOADER := $(PRODUCT_OUT)/EMMCBOOT.MBN
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index fcd0ee8..b51d450 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -2,7 +2,7 @@
* Copyright (c) 2009, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -40,6 +40,7 @@
#include <arch/ops.h>
#include <dev/flash.h>
+#include <dev/flash-ubi.h>
#include <lib/ptable.h>
#include <dev/keys.h>
#include <dev/fbcon.h>
@@ -71,6 +72,7 @@
#include "devinfo.h"
#include "board.h"
#include "scm.h"
+#include "mdtp.h"
extern bool target_use_signed_kernel(void);
extern void platform_uninit(void);
@@ -105,6 +107,10 @@
#define MAX_TAGS_SIZE 1024
+#define RECOVERY_HARD_RESET_MODE 0x01
+#define FASTBOOT_HARD_RESET_MODE 0x02
+#define RTC_HARD_RESET_MODE 0x03
+
#define RECOVERY_MODE 0x77665502
#define FASTBOOT_MODE 0x77665500
#define ALARM_BOOT 0x77665503
@@ -113,16 +119,14 @@
#define DEFAULT_ERASE_SIZE 4096
#define MAX_PANEL_BUF_SIZE 128
-#define UBI_MAGIC "UBI#"
#define DISPLAY_DEFAULT_PREFIX "mdss_mdp"
-#define UBI_MAGIC_SIZE 0x04
#define BOOT_DEV_MAX_LEN 64
#define IS_ARM64(ptr) (ptr->magic_64 == KERNEL64_HDR_MAGIC) ? true : false
#define ADD_OF(a, b) (UINT_MAX - b > a) ? (a + b) : UINT_MAX
-#if UFS_SUPPORT || USE_BOOTDEV_CMDLINE
+#if USE_BOOTDEV_CMDLINE
static const char *emmc_cmdline = " androidboot.bootdevice=";
#else
static const char *emmc_cmdline = " androidboot.emmc=true";
@@ -245,7 +249,7 @@
}
if (target_is_emmc_boot()) {
cmdline_len += strlen(emmc_cmdline);
-#if UFS_SUPPORT || USE_BOOTDEV_CMDLINE
+#if USE_BOOTDEV_CMDLINE
boot_dev_buf = (char *) malloc(sizeof(char) * BOOT_DEV_MAX_LEN);
ASSERT(boot_dev_buf);
platform_boot_dev_cmdline(boot_dev_buf);
@@ -360,7 +364,7 @@
if (have_cmdline) --dst;
have_cmdline = 1;
while ((*dst++ = *src++));
-#if UFS_SUPPORT || USE_BOOTDEV_CMDLINE
+#if USE_BOOTDEV_CMDLINE
src = boot_dev_buf;
if (have_cmdline) --dst;
while ((*dst++ = *src++));
@@ -493,7 +497,10 @@
if (boot_dev_buf)
free(boot_dev_buf);
- dprintf(INFO, "cmdline: %s\n", cmdline_final ? cmdline_final : "");
+ if (cmdline_final)
+ dprintf(INFO, "cmdline: %s\n", cmdline_final);
+ else
+ dprintf(INFO, "cmdline is NULL\n");
return cmdline_final;
}
@@ -618,7 +625,7 @@
#if VERIFIED_BOOT
/* Write protect the device info */
- if (mmc_write_protect("devinfo", 1))
+ if (target_build_variant_user() && mmc_write_protect("devinfo", 1))
{
dprintf(INFO, "Failed to write protect dev info\n");
ASSERT(0);
@@ -687,11 +694,14 @@
static void verify_signed_bootimg(uint32_t bootimg_addr, uint32_t bootimg_size)
{
int ret;
+
+#if !VERIFIED_BOOT
#if IMAGE_VERIF_ALGO_SHA1
uint32_t auth_algo = CRYPTO_AUTH_ALG_SHA1;
#else
uint32_t auth_algo = CRYPTO_AUTH_ALG_SHA256;
#endif
+#endif
/* Assume device is rooted at this time. */
device.is_tampered = 1;
@@ -890,6 +900,8 @@
return -1;
}
}
+ /* Set Lun for boot & recovery partitions */
+ mmc_set_lun(partition_get_lun(index));
if (mmc_read(ptn + offset, (uint32_t *) buf, page_size)) {
dprintf(CRITICAL, "ERROR: Cannot read boot image header\n");
@@ -1080,7 +1092,7 @@
imagesize_actual = (page_size + kernel_actual + ramdisk_actual);
#endif
- if (check_aboot_addr_range_overlap(image_addr, imagesize_actual))
+ if (check_aboot_addr_range_overlap((uint32_t) image_addr, imagesize_actual))
{
dprintf(CRITICAL, "Boot image buffer address overlaps with aboot addresses.\n");
return -1;
@@ -1103,7 +1115,7 @@
bs_set_timestamp(BS_KERNEL_LOAD_DONE);
#ifdef TZ_SAVE_KERNEL_HASH
- aboot_save_boot_hash_mmc(image_addr, imagesize_actual);
+ aboot_save_boot_hash_mmc((uint32_t) image_addr, imagesize_actual);
#endif /* TZ_SAVE_KERNEL_HASH */
/* Move kernel, ramdisk and device tree to correct address */
@@ -1434,7 +1446,9 @@
{
struct device_info *info = (void*) info_buf;
unsigned long long ptn = 0;
+#if !VERIFIED_BOOT
unsigned long long size;
+#endif
int index = INVALID_PTN;
uint32_t blocksize;
uint8_t lun = 0;
@@ -1454,7 +1468,9 @@
lun = partition_get_lun(index);
mmc_set_lun(lun);
+#if !VERIFIED_BOOT
size = partition_get_size(index);
+#endif
memcpy(info, dev, sizeof(device_info));
@@ -1475,7 +1491,9 @@
{
struct device_info *info = (void*) info_buf;
unsigned long long ptn = 0;
+#if !VERIFIED_BOOT
unsigned long long size;
+#endif
int index = INVALID_PTN;
uint32_t blocksize;
@@ -1493,7 +1511,9 @@
mmc_set_lun(partition_get_lun(index));
+#if !VERIFIED_BOOT
size = partition_get_size(index);
+#endif
blocksize = mmc_get_device_blocksize();
@@ -1700,6 +1720,12 @@
int ret = 0;
uint8_t dtb_copied = 0;
+#ifdef MDTP_SUPPORT
+ /* Go through Firmware Lock verification before continue with boot process */
+ mdtp_fwlock_verify_lock();
+ fbcon_clear();
+#endif /* MDTP_SUPPORT */
+
#if VERIFIED_BOOT
if(!device.is_unlocked)
{
@@ -2166,10 +2192,10 @@
void cmd_flash_mmc(const char *arg, void *data, unsigned sz)
{
sparse_header_t *sparse_header;
- /* 8 Byte Magic + 2048 Byte xml + Encrypted Data */
- unsigned int *magic_number = (unsigned int *) data;
#ifdef SSD_ENABLE
+ /* 8 Byte Magic + 2048 Byte xml + Encrypted Data */
+ unsigned int *magic_number = (unsigned int *) data;
int ret=0;
uint32 major_version=0;
uint32 minor_version=0;
@@ -2289,19 +2315,21 @@
|| !strcmp(ptn->name, "persist")
|| !strcmp(ptn->name, "recoveryfs")
|| !strcmp(ptn->name, "modem"))
- {
- if (memcmp((void *)data, UBI_MAGIC, UBI_MAGIC_SIZE))
- extra = 1;
- else
- extra = 0;
- }
+ extra = 1;
else
sz = ROUND_TO_PAGE(sz, page_mask);
dprintf(INFO, "writing %d bytes to '%s'\n", sz, ptn->name);
- if (flash_write(ptn, extra, data, sz)) {
- fastboot_fail("flash write failure");
- return;
+ if (!memcmp((void *)data, UBI_MAGIC, UBI_MAGIC_SIZE)) {
+ if (flash_ubi_img(ptn, data, sz)) {
+ fastboot_fail("flash write failure");
+ return;
+ }
+ } else {
+ if (flash_write(ptn, extra, data, sz)) {
+ fastboot_fail("flash write failure");
+ return;
+ }
}
dprintf(INFO, "partition '%s' updated\n", ptn->name);
fastboot_okay("");
@@ -2320,6 +2348,12 @@
fastboot_okay("");
fastboot_stop();
+#ifdef MDTP_SUPPORT
+ /* Go through Firmware Lock verification before continue with boot process */
+ mdtp_fwlock_verify_lock();
+ fbcon_clear();
+#endif /* MDTP_SUPPORT */
+
if (target_is_emmc_boot())
{
boot_linux_from_mmc();
@@ -2425,7 +2459,6 @@
fastboot_okay("");
}
-static struct fbimage logo_header = {{{0}, 0, 0, 0, {0}}, 0};
struct fbimage* splash_screen_flash();
int splash_screen_check_header(struct fbimage *logo)
@@ -2442,35 +2475,38 @@
struct ptentry *ptn;
struct ptable *ptable;
struct fbcon_config *fb_display = NULL;
- struct fbimage *logo = &logo_header;
+ struct fbimage *logo = NULL;
+ logo = (struct fbimage *) malloc(ROUNDUP(page_size, sizeof(struct fbimage)));
+ ASSERT(logo);
+
ptable = flash_get_ptable();
if (ptable == NULL) {
dprintf(CRITICAL, "ERROR: Partition table not found\n");
- return NULL;
+ goto err;
}
ptn = ptable_find(ptable, "splash");
if (ptn == NULL) {
dprintf(CRITICAL, "ERROR: splash Partition not found\n");
- return NULL;
+ goto err;
}
if (flash_read(ptn, 0,(unsigned int *) logo, sizeof(logo->header))) {
dprintf(CRITICAL, "ERROR: Cannot read boot image header\n");
- return NULL;
+ goto err;
}
if (splash_screen_check_header(logo)) {
dprintf(CRITICAL, "ERROR: Boot image header invalid\n");
- return NULL;
+ goto err;
}
fb_display = fbcon_display();
if (fb_display) {
if ((logo->header.width != fb_display->width) || (logo->header.height != fb_display->height)) {
dprintf(CRITICAL, "Logo config doesn't match with fb config. Fall back to default logo\n");
- return NULL;
+ goto err;
}
uint8_t *base = (uint8_t *) fb_display->base;
if (flash_read(ptn + sizeof(logo->header), 0,
@@ -2478,12 +2514,16 @@
((((logo->header.width * logo->header.height * fb_display->bpp/8) + 511) >> 9) << 9))) {
fbcon_clear();
dprintf(CRITICAL, "ERROR: Cannot read splash image from partition\n");
- return NULL;
+ goto err;
}
logo->image = base;
}
return logo;
+
+err:
+ free(logo);
+ return NULL;
}
struct fbimage* splash_screen_mmc()
@@ -2491,7 +2531,11 @@
int index = INVALID_PTN;
unsigned long long ptn = 0;
struct fbcon_config *fb_display = NULL;
- struct fbimage *logo = &logo_header;
+ struct fbimage *logo = NULL;
+ uint32_t blocksize;
+ uint32_t readsize;
+ uint32_t logosize;
+ uint32_t ptn_size;
index = partition_get_index("splash");
if (index == 0) {
@@ -2505,35 +2549,52 @@
return NULL;
}
- if (mmc_read(ptn, (uint32_t *) logo, sizeof(logo->header))) {
+ ptn_size = partition_get_size(index);
+ blocksize = mmc_get_device_blocksize();
+ logosize = ROUNDUP(sizeof(logo->header), blocksize);
+
+ logo = (struct fbimage *)memalign(CACHE_LINE, ROUNDUP(logosize, CACHE_LINE));
+ ASSERT(logo);
+
+ if (mmc_read(ptn, (uint32_t *) logo, logosize)) {
dprintf(CRITICAL, "ERROR: Cannot read splash image header\n");
- return NULL;
+ goto err;
}
if (splash_screen_check_header(logo)) {
dprintf(CRITICAL, "ERROR: Splash image header invalid\n");
- return NULL;
+ goto err;
}
fb_display = fbcon_display();
if (fb_display) {
if ((logo->header.width != fb_display->width) || (logo->header.height != fb_display->height)) {
dprintf(CRITICAL, "Logo config doesn't match with fb config. Fall back default logo\n");
- return NULL;
+ goto err;
}
uint8_t *base = (uint8_t *) fb_display->base;
- if (mmc_read(ptn + sizeof(logo->header),
- (uint32_t *)base,
- ((((logo->header.width * logo->header.height * fb_display->bpp/8) + 511) >> 9) << 9))) {
+ readsize = ROUNDUP((logo->header.width * logo->header.height * fb_display->bpp/8), blocksize);
+
+ if (readsize > ptn_size)
+ {
+ dprintf(CRITICAL, "@%d:Invalid logo header readsize:%u exceeds ptn_size:%u\n", __LINE__, readsize,ptn_size);
+ goto err;
+ }
+
+ if (mmc_read(ptn + logosize,(uint32_t *)base, readsize)) {
fbcon_clear();
dprintf(CRITICAL, "ERROR: Cannot read splash image from partition\n");
- return NULL;
+ goto err;
}
logo->image = base;
}
return logo;
+
+err:
+ free(logo);
+ return NULL;
}
@@ -2671,6 +2732,7 @@
void aboot_init(const struct app_descriptor *app)
{
unsigned reboot_mode = 0;
+ unsigned hard_reboot_mode = 0;
bool boot_into_fastboot = false;
/* Setup page size information for nv storage */
@@ -2738,11 +2800,15 @@
#endif
reboot_mode = check_reboot_mode();
- if (reboot_mode == RECOVERY_MODE) {
+ hard_reboot_mode = check_hard_reboot_mode();
+ if (reboot_mode == RECOVERY_MODE ||
+ hard_reboot_mode == RECOVERY_HARD_RESET_MODE) {
boot_into_recovery = 1;
- } else if(reboot_mode == FASTBOOT_MODE) {
+ } else if(reboot_mode == FASTBOOT_MODE ||
+ hard_reboot_mode == FASTBOOT_HARD_RESET_MODE) {
boot_into_fastboot = true;
- } else if(reboot_mode == ALARM_BOOT) {
+ } else if(reboot_mode == ALARM_BOOT ||
+ hard_reboot_mode == RTC_HARD_RESET_MODE) {
boot_reason_alarm = true;
}
@@ -2765,6 +2831,13 @@
#endif
}
}
+
+#ifdef MDTP_SUPPORT
+ /* Go through Firmware Lock verification before continue with boot process */
+ mdtp_fwlock_verify_lock();
+ fbcon_clear();
+#endif /* MDTP_SUPPORT */
+
boot_linux_from_mmc();
}
else
@@ -2815,7 +2888,7 @@
#endif
target_crypto_init_params();
- hash_find(image_addr, image_size, (unsigned char *)&digest, auth_algo);
+ hash_find((unsigned char *) image_addr, image_size, (unsigned char *)&digest, auth_algo);
save_kernel_hash_cmd(digest);
dprintf(INFO, "aboot_save_boot_hash_mmc: imagesize_actual size %d bytes.\n", (int) image_size);
diff --git a/app/aboot/mdtp.c b/app/aboot/mdtp.c
new file mode 100644
index 0000000..60b97b0
--- /dev/null
+++ b/app/aboot/mdtp.c
@@ -0,0 +1,545 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <dev/fbcon.h>
+#include <target.h>
+#include <mmc.h>
+#include <partition_parser.h>
+#include <platform.h>
+#include <crypto_hash.h>
+#include <malloc.h>
+#include <sha.h>
+#include <string.h>
+#include <rand.h>
+#include <stdlib.h>
+#include "scm.h"
+#include "mdtp.h"
+
+#define DIP_ENCRYPT 0
+#define DIP_DECRYPT 1
+
+static int mdtp_tzbsp_dec_verify_DIP(DIP_t *enc_dip, DIP_t *dec_dip, uint32_t *verified);
+static int mdtp_tzbsp_enc_hash_DIP(DIP_t *dec_dip, DIP_t *enc_dip);
+
+/********************************************************************************/
+
+/* Read the DIP from EMMC */
+static int read_DIP(DIP_t *dip)
+{
+ unsigned long long ptn = 0;
+ uint32_t actual_partition_size;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ int index = INVALID_PTN;
+
+ ASSERT(dip != NULL);
+
+ index = partition_get_index("dip");
+ ptn = partition_get_offset(index);
+
+ if(ptn == 0)
+ {
+ return -1;
+ }
+
+ actual_partition_size = ROUNDUP(sizeof(DIP_t), block_size);
+
+ if(mmc_read(ptn, (void *)dip, actual_partition_size))
+ {
+ dprintf(CRITICAL, "mdtp: read_DIP: ERROR, cannot read DIP info\n");
+ return -1;
+ }
+
+ dprintf(INFO, "mdtp: read_DIP: SUCCESS, read %d bytes\n", actual_partition_size);
+
+ return 0;
+}
+
+/* Store the DIP into the EMMC */
+static int write_DIP(DIP_t *dip)
+{
+ unsigned long long ptn = 0;
+ uint32_t partition_size;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ int index = INVALID_PTN;
+
+ ASSERT(dip != NULL);
+
+ index = partition_get_index("dip");
+ ptn = partition_get_offset(index);
+ if(ptn == 0)
+ {
+ return -1;
+ }
+
+ partition_size = partition_get_size(index);
+
+ if(partition_size < size)
+ {
+ dprintf(CRITICAL, "mdtp: write_DIP: ERROR, DIP partition too small\n");
+ return -1;
+ }
+
+ if(mmc_write(ptn, ROUNDUP(size, block_size), (void *)dip))
+ {
+ dprintf(CRITICAL, "mdtp: write_DIP: ERROR, cannot read DIP info\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Provision the DIP by storing the default DIP into the EMMC */
+static void provision_DIP()
+{
+ DIP_t *enc_dip;
+ DIP_t *dec_dip;
+ int ret;
+
+ enc_dip = malloc(sizeof(DIP_t));
+ if (enc_dip == NULL)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot allocate DIP\n");
+ return;
+ }
+
+ dec_dip = malloc(sizeof(DIP_t));
+ if (dec_dip == NULL)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot allocate DIP\n");
+ free(enc_dip);
+ return;
+ }
+
+ memset(dec_dip, 0, sizeof(DIP_t));
+
+ dec_dip->status = DIP_STATUS_DEACTIVATED;
+
+ ret = mdtp_tzbsp_enc_hash_DIP(dec_dip, enc_dip);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot cipher DIP\n");
+ goto out;
+ }
+
+ ret = write_DIP(enc_dip);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot write DIP\n");
+ goto out;
+ }
+
+ ret = mdtp_tzbsp_set_provisioned_fuse();
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot set DIP_PROVISIONED fuse\n\n");
+ goto out;
+ }
+
+out:
+ free(enc_dip);
+ free(dec_dip);
+}
+
+/* Validate a hash calculated on entire given partition */
+static int verify_partition_single_hash(char *name, uint32_t size, DIP_hash_table_entry_t *hash_table)
+{
+ unsigned char digest[32]={0};
+ unsigned long long ptn = 0;
+ int index = INVALID_PTN;
+ unsigned char *buf = (unsigned char *)target_get_scratch_address();
+ uint32_t block_size = mmc_get_device_blocksize();
+ uint32_t actual_partition_size = ROUNDUP(size, block_size);
+
+ dprintf(INFO, "mdtp: verify_partition_single_hash: %s, %u\n", name, size);
+
+ ASSERT(name != NULL);
+ ASSERT(hash_table != NULL);
+
+ index = partition_get_index(name);
+ ptn = partition_get_offset(index);
+
+ if(ptn == 0) {
+ dprintf(CRITICAL, "mdtp: verify_partition_single_hash: %s: partition was not found\n", name);
+ return -1;
+ }
+
+ if (mmc_read(ptn, (void *)buf, actual_partition_size))
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition__single_hash: %s: mmc_read() fail.\n", name);
+ return -1;
+ }
+
+ /* calculating the hash value using HW crypto */
+ target_crypto_init_params();
+ hash_find(buf, size, (unsigned char *)&digest, CRYPTO_AUTH_ALG_SHA256);
+
+ if (memcmp(&digest[0], &(hash_table->hash[0]), HASH_LEN))
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition_single_hash: %s: Failed partition hash verification\n", name);
+
+ return -1;
+ }
+
+ dprintf(INFO, "verify_partition_single_hash: %s: VERIFIED!\n", name);
+
+ return 0;
+}
+
+/* Validate a hash table calculated per block of a given partition */
+static int verify_partition_block_hash(char *name,
+ uint32_t size,
+ uint32_t total_num_blocks,
+ uint32_t verify_num_blocks,
+ DIP_hash_table_entry_t *hash_table,
+ uint8_t *force_verify_block)
+{
+ unsigned char digest[32]={0};
+ unsigned long long ptn = 0;
+ int index = INVALID_PTN;
+ unsigned char *buf = (unsigned char *)target_get_scratch_address();
+ uint32_t bytes_to_read;
+ uint32_t block_num = 0;
+
+ dprintf(INFO, "mdtp: verify_partition_block_hash: %s, %u\n", name, size);
+
+ ASSERT(name != NULL);
+ ASSERT(hash_table != NULL);
+
+ index = partition_get_index(name);
+ ptn = partition_get_offset(index);
+
+ if(ptn == 0) {
+ dprintf(CRITICAL, "mdtp: verify_partition_block_hash: %s: partition was not found\n", name);
+ return -1;
+ }
+
+ /* initiating parameters for hash calculation using HW crypto */
+ target_crypto_init_params();
+
+ while (MDTP_FWLOCK_BLOCK_SIZE * block_num < size)
+ {
+ if (*force_verify_block == 0)
+ {
+ /* Skip validation of this block with probability of verify_num_blocks / total_num_blocks */
+ if ((rand() % total_num_blocks) >= verify_num_blocks)
+ {
+ block_num++;
+ hash_table += 1;
+ force_verify_block += 1;
+ dprintf(CRITICAL, "mdtp: verify_partition_block_hash: %s: skipped verification of block %d\n", name, block_num);
+ continue;
+ }
+ }
+
+ if ((size - (MDTP_FWLOCK_BLOCK_SIZE * block_num) < MDTP_FWLOCK_BLOCK_SIZE))
+ {
+ bytes_to_read = size - (MDTP_FWLOCK_BLOCK_SIZE * block_num);
+ } else
+ {
+ bytes_to_read = MDTP_FWLOCK_BLOCK_SIZE;
+ }
+
+ if (mmc_read(ptn + (MDTP_FWLOCK_BLOCK_SIZE * block_num), (void *)buf, bytes_to_read))
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition_block_hash: %s: mmc_read() fail.\n", name);
+ return -1;
+ }
+
+ /* calculating the hash value using HW */
+ hash_find(buf, bytes_to_read, (unsigned char *)&digest, CRYPTO_AUTH_ALG_SHA256);
+
+ if (memcmp(&digest[0], &(hash_table->hash[0]), HASH_LEN))
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition_block_hash: %s: Failed partition hash[%d] verification\n", name, block_num);
+ return -1;
+ }
+
+ block_num++;
+ hash_table += 1;
+ force_verify_block += 1;
+ }
+
+ dprintf(INFO, "verify_partition_block_hash: %s: VERIFIED!\n", name);
+
+ return 0;
+}
+
+/* Verify a given partitinon */
+static int verify_partition(char *name,
+ uint32_t size,
+ mdtp_fwlock_mode_t hash_mode,
+ uint32_t total_num_blocks,
+ uint32_t verify_num_blocks,
+ DIP_hash_table_entry_t *hash_table,
+ uint8_t *force_verify_block)
+{
+
+ ASSERT(name != NULL);
+ ASSERT(hash_table != NULL);
+
+ if (hash_mode == MDTP_FWLOCK_MODE_SINGLE)
+ {
+ return verify_partition_single_hash(name, size, hash_table);
+ } else if (hash_mode == MDTP_FWLOCK_MODE_BLOCK || hash_mode == MDTP_FWLOCK_MODE_FILES)
+ {
+ return verify_partition_block_hash(name, size, total_num_blocks, verify_num_blocks, hash_table, force_verify_block);
+ }
+ else
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition: %s: Wrong DIP partition hash mode\n", name);
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Verify all protected partitinons according to the DIP */
+static int verify_all_partitions(DIP_t *dip, verify_result_t *verify_result)
+{
+ int i;
+ int verify_failure = 0;
+ uint32_t total_num_blocks;
+
+ ASSERT(dip != NULL);
+ ASSERT(verify_result != NULL);
+
+ *verify_result = VERIFY_FAILED;
+
+ if (dip->status == DIP_STATUS_DEACTIVATED)
+ {
+ *verify_result = VERIFY_SKIPPED;
+ return 0;
+ }
+ else if (dip->status == DIP_STATUS_ACTIVATED)
+ {
+ show_checking_msg();
+
+ for(i=0; i<MAX_PARTITIONS; i++)
+ {
+ if(dip->partition_cfg[i].lock_enabled && dip->partition_cfg[i].size)
+ {
+ total_num_blocks = ((dip->partition_cfg[i].size - 1) / MDTP_FWLOCK_BLOCK_SIZE);
+
+ verify_failure |= verify_partition(dip->partition_cfg[i].name,
+ dip->partition_cfg[i].size,
+ dip->partition_cfg[i].hash_mode,
+ total_num_blocks,
+ (dip->partition_cfg[i].verify_ratio * total_num_blocks) / 100,
+ dip->partition_cfg[i].hash_table,
+ dip->partition_cfg[i].force_verify_block);
+ }
+ }
+
+ if (verify_failure)
+ {
+ dprintf(CRITICAL, "mdtp: verify_all_partitions: Failed partition verification\n");
+ show_invalid_msg();
+ return -1;
+ }
+
+ }
+
+ *verify_result = VERIFY_OK;
+ show_OK_msg();
+ return 0;
+}
+
+/* Verify the DIP and all protected partitions */
+static void validate_DIP_and_firmware()
+{
+ int ret;
+ DIP_t *enc_dip;
+ DIP_t *dec_dip;
+ uint32_t verified = 0;
+ verify_result_t verify_result;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ enc_dip = malloc(ROUNDUP(sizeof(DIP_t), block_size));
+ if (enc_dip == NULL)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot allocate DIP\n");
+ return;
+ }
+
+ dec_dip = malloc(ROUNDUP(sizeof(DIP_t), block_size));
+ if (dec_dip == NULL)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot allocate DIP\n");
+ free(enc_dip);
+ return;
+ }
+
+ /* Read the DIP holding the MDTP Firmware Lock state from the DIP partition */
+ ret = read_DIP(enc_dip);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, cannot read DIP\n");
+ goto out;
+ }
+
+ /* Decrypt and verify the integrity of the DIP */
+ ret = mdtp_tzbsp_dec_verify_DIP(enc_dip, dec_dip, &verified);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, cannot verify DIP\n");
+ show_invalid_msg();
+ goto out;
+ }
+
+ /* In case DIP integrity verification fails, notify the user and halt */
+ if(!verified)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, corrupted DIP\n");
+ show_invalid_msg();
+ goto out;
+ }
+
+ /* Verify the integrity of the partitions which are protectedm, according to the content of the DIP */
+ ret = verify_all_partitions(dec_dip, &verify_result);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, cannot verify firmware\n");
+ goto out;
+ }
+
+ if (verify_result == VERIFY_OK)
+ {
+ dprintf(INFO, "mdtp: validate_DIP_and_firmware: Verify OK\n");
+ }
+ else if (verify_result == VERIFY_FAILED)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, corrupted firmware\n");
+ } else /* VERIFY_SKIPPED */
+ {
+ dprintf(INFO, "mdtp: validate_DIP_and_firmware: Verify skipped\n");
+ }
+
+out:
+ free(enc_dip);
+ free(dec_dip);
+
+ return;
+}
+
+/********************************************************************************/
+
+/** Entry point of the MDTP Firmware Lock: If needed, verify the DIP
+ * and all protected partitions **/
+
+int mdtp_fwlock_verify_lock()
+{
+ int ret;
+ bool enabled;
+
+ ret = mdtp_fuse_get_enabled(&enabled);
+ if(ret)
+ {
+ dprintf(CRITICAL, "mdtp: mdtp_fwlock_verify_lock: ERROR, cannot get enabled fuse\n");
+ return -1;
+ }
+
+ /* Continue with Firmware Lock verification only if enabled by eFuse */
+ if (enabled)
+ {
+ validate_DIP_and_firmware();
+ }
+
+ return 0;
+}
+
+/********************************************************************************/
+
+/* Decrypt a given DIP and verify its integrity */
+static int mdtp_tzbsp_dec_verify_DIP(DIP_t *enc_dip, DIP_t *dec_dip, uint32_t *verified)
+{
+ unsigned char *hash_p;
+ unsigned char hash[HASH_LEN];
+ SHA256_CTX sha256_ctx;
+ int ret;
+
+ ASSERT(enc_dip != NULL);
+ ASSERT(dec_dip != NULL);
+ ASSERT(verified != NULL);
+
+ ret = mdtp_cipher_dip_cmd((uint8_t*)enc_dip, sizeof(DIP_t),
+ (uint8_t*)dec_dip, sizeof(DIP_t),
+ DIP_DECRYPT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "mdtp: mdtp_tzbsp_dec_verify_DIP: ERROR, cannot cipher DIP\n");
+ *verified = 0;
+ return -1;
+ }
+
+ SHA256_Init(&sha256_ctx);
+ SHA256_Update(&sha256_ctx, dec_dip, sizeof(DIP_t) - HASH_LEN);
+ SHA256_Final(hash, &sha256_ctx);
+
+ hash_p = (unsigned char*)dec_dip + sizeof(DIP_t) - HASH_LEN;
+
+ if (memcmp(hash, hash_p, HASH_LEN))
+ {
+ *verified = 0;
+ }
+ else
+ {
+ *verified = 1;
+ }
+
+ return 0;
+}
+
+static int mdtp_tzbsp_enc_hash_DIP(DIP_t *dec_dip, DIP_t *enc_dip)
+{
+ unsigned char *hash_p;
+ SHA256_CTX sha256_ctx;
+ int ret;
+
+ ASSERT(dec_dip != NULL);
+ ASSERT(enc_dip != NULL);
+
+ hash_p = (unsigned char*)dec_dip + sizeof(DIP_t) - HASH_LEN;
+
+ SHA256_Init(&sha256_ctx);
+ SHA256_Update(&sha256_ctx, dec_dip, sizeof(DIP_t) - HASH_LEN);
+ SHA256_Final(hash_p, &sha256_ctx);
+
+ ret = mdtp_cipher_dip_cmd((uint8_t*)dec_dip, sizeof(DIP_t),
+ (uint8_t*)enc_dip, sizeof(DIP_t),
+ DIP_ENCRYPT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "mdtp: mdtp_tzbsp_enc_hash_DIP: ERROR, cannot cipher DIP\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/app/aboot/mdtp.h b/app/aboot/mdtp.h
new file mode 100644
index 0000000..9975899
--- /dev/null
+++ b/app/aboot/mdtp.h
@@ -0,0 +1,122 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __APP_MDTP_H
+#define __APP_MDTP_H
+
+#define TOKEN_LEN 16
+#define MAX_BLOCKS 512
+#define MAX_PARTITIONS 3
+#define MAX_PARTITION_NAME_LEN 100
+#define HASH_LEN 32
+#define MDTP_MAX_PIN_LEN 8
+#define DIP_PADDING 11
+
+#define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y)))
+#define MDTP_FWLOCK_BLOCK_SIZE (1024*1024*16)
+#define MDTP_FWLOCK_MAX_FILES (100)
+#define MDTP_FWLOCK_MAX_FILE_NAME_LEN (100)
+
+#pragma pack(push, mdtp, 1)
+
+typedef enum {
+ DIP_STATUS_DEACTIVATED = 0,
+ DIP_STATUS_ACTIVATED,
+ DIP_STATUS_SIZE = 0x7FFFFFFF
+} dip_status_t;
+
+typedef enum {
+ MDTP_FWLOCK_MODE_SINGLE = 0,
+ MDTP_FWLOCK_MODE_BLOCK,
+ MDTP_FWLOCK_MODE_FILES,
+ MDTP_FWLOCK_MODE_SIZE = 0x7FFFFFFF
+} mdtp_fwlock_mode_t;
+
+typedef struct DIP_hash_table_entry {
+ unsigned char hash[HASH_LEN]; /* Hash on block */
+} DIP_hash_table_entry_t;
+
+typedef struct DIP_partition_cfg {
+ uint32_t size; /* DIP size */
+ char name[MAX_PARTITION_NAME_LEN]; /* Partition name */
+ uint8_t lock_enabled; /* Image locked? */
+ mdtp_fwlock_mode_t hash_mode; /* Hash per IMAGE or BLOCK */
+ uint8_t force_verify_block[MAX_BLOCKS]; /* Verify only given block numbers. */
+ char files_to_protect[MDTP_FWLOCK_MAX_FILES][MDTP_FWLOCK_MAX_FILE_NAME_LEN]; /* Verify given files */
+ uint32_t verify_ratio; /* Statistically verify this ratio of blocks */
+ DIP_hash_table_entry_t hash_table[MAX_BLOCKS]; /* Hash table */
+} DIP_partition_cfg_t;
+
+typedef struct mdtp_pin {
+ char mdtp_pin[MDTP_MAX_PIN_LEN+1]; /* A null terminated PIN. */
+} mdtp_pin_t;
+
+/** MDTP configuration. */
+typedef struct mdtp_cfg {
+ uint8_t enable_local_pin_authentication;/* Allow local authentication using a PIN. */
+ mdtp_pin_t mdtp_pin; /* Null terminated PIN provided by the user for local deactivation.
+ PIN length should be from MDTP_MIN_PIN_LEN to MDTP_MAX_PIN_LEN digits. */
+} mdtp_cfg_t;
+
+typedef struct DIP {
+ /* Management area of the DIP */
+ uint32_t version; /* DIP version */
+ dip_status_t status; /* DIP activated/deactivated */
+ mdtp_cfg_t mdtp_cfg; /* MDTP configuration, such as PIN */
+
+ /* Firmware Lock area of the DIP */
+ DIP_partition_cfg_t partition_cfg[MAX_PARTITIONS]; /* Config for each partition */
+
+ /* Footer area of the DIP */
+ uint8_t padding[DIP_PADDING]; /* Pad to multiple of 16 bytes */
+ unsigned char hash[HASH_LEN]; /* DIP integrity */
+} DIP_t;
+
+#pragma pack(pop, mdtp)
+typedef enum {
+ VERIFY_SKIPPED = 0,
+ VERIFY_OK,
+ VERIFY_FAILED,
+} verify_result_t;
+
+/* Start Firmware Lock verification process */
+int mdtp_fwlock_verify_lock();
+
+/* Return whether the MDTP is currently enabled or disabled in HW */
+int mdtp_fuse_get_enabled(bool *enabled);
+
+/* Display the "Firmware Valid" screen */
+void show_OK_msg();
+
+/* Display the "Firmware Invalid" screen */
+void show_invalid_msg();
+
+/* Display the "Verifying Firmware" screen */
+void show_checking_msg();
+
+#endif
diff --git a/app/aboot/mdtp_fuse.c b/app/aboot/mdtp_fuse.c
new file mode 100644
index 0000000..c4abd19
--- /dev/null
+++ b/app/aboot/mdtp_fuse.c
@@ -0,0 +1,257 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <target.h>
+#include <mmc.h>
+#include <partition_parser.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "mdtp.h"
+#include "scm.h"
+
+#define MAX_EFUSES (8)
+#define EFUSE_END (MDTP_EFUSE_START + MAX_EFUSES - 1)
+#define MAX_METADATA_SIZE (0x1000)
+#define QFPROM_ADDR_SPACE_RAW (0)
+
+/********************************************************************************/
+
+typedef union
+{
+ struct {
+ uint8_t enable1 : 1;
+ uint8_t disable1 : 1;
+ uint8_t enable2 : 1;
+ uint8_t disable2 : 1;
+ uint8_t enable3 : 1;
+ uint8_t disable3 : 1;
+ uint8_t reserved1 : 1;
+ uint8_t reserved2 : 1;
+ } bitwise;
+ uint8_t mask;
+} mdtp_eFuses_t;
+
+typedef struct metadata {
+ mdtp_eFuses_t eFuses;
+} metadata_t;
+
+/********************************************************************************/
+
+/**
+ * Checks if we are in test mode according to relevant eFuses
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int is_test_mode(void)
+{
+ static int test_mode_set = 0;
+ static int test_mode = 0;
+ int ret = 0;
+ uint32_t status_low = 0;
+ uint32_t status_high = 0;
+
+#define SECBOOT_FUSE 0x01
+#define SHK_FUSE 0x02
+#define DEBUG_FUSE 0x04
+
+ /* Make sure we only read the test mode once */
+ if (test_mode_set)
+ return test_mode;
+
+ ret = scm_svc_get_secure_state(&status_low, &status_high);
+
+ if(ret == 0)
+ {
+ /* (SECBOOT_FUSE | SHK_FUSE | DEBUG_FUSE) implies that none of the fuses are blown */
+ if((status_low & (SECBOOT_FUSE | SHK_FUSE | DEBUG_FUSE)) == (SECBOOT_FUSE | SHK_FUSE | DEBUG_FUSE))
+ test_mode = 1;
+ }
+ else
+ {
+ dprintf(CRITICAL, "mdtp: is_test_mode: qsee_get_secure_state returned error: %d, status.value[0]: %d", ret, status_low);
+ test_mode = 0;
+ }
+
+ test_mode_set = 1;
+ dprintf(INFO, "mdtp: is_test_mode: test mode is set to %d", test_mode);
+
+ return test_mode;
+}
+
+/**
+ * Read the Firmware Lock Metadata from EMMC
+ *
+ * @param metadata - Read a metadata block holding eFuse emulation from MDTP partition.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int read_metadata(metadata_t *metadata)
+{
+ unsigned long long ptn = 0;
+ uint32_t actual_size;
+ char metadata_block[MAX_METADATA_SIZE];
+ int index = INVALID_PTN;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ ptn = partition_get_offset(index);
+
+ if(ptn == 0)
+ {
+ return -1;
+ }
+
+ if (sizeof(metadata_t) > MAX_METADATA_SIZE)
+ {
+ dprintf(CRITICAL, "mdtp: read_metadata: ERROR, meta data size %d too big\n", sizeof(metadata_t));
+ return -1;
+ }
+
+ actual_size = ROUNDUP(MAX_METADATA_SIZE, block_size);
+
+ if(mmc_read(ptn, (void *)metadata_block, actual_size))
+ {
+ dprintf(CRITICAL, "mdtp: read_metadata: ERROR, cannot read mdtp info\n");
+ return -1;
+ }
+
+ memcpy(metadata, metadata_block, sizeof(metadata_t));
+
+ dprintf(INFO, "mdtp: read_metadata: SUCCESS, read %d bytes\n", actual_size);
+
+ return 0;
+}
+
+/**
+ * read_QFPROM_fuse
+ *
+ * @param mask[out] - MDTP efuse value represented by a bitfield.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int read_QFPROM_fuse(uint8_t *mask)
+{
+ static const uint32_t row_address = MDTP_EFUSE_ADDRESS;
+ uint32_t addr_type = QFPROM_ADDR_SPACE_RAW;
+ uint32_t row_data[2] = {0};
+ uint32_t qfprom_api_status = 0;
+
+ /* Read the current row where the eFuse is located */
+ (void) qfprom_read_row_cmd(row_address, addr_type, row_data, &qfprom_api_status);
+ if (qfprom_api_status)
+ {
+ dprintf(CRITICAL, "mdtp: write_QFPROM_fuse: qsee_fuse_read failed. qfprom_api_status=%d", qfprom_api_status);
+ return -1;
+ }
+
+ /* Shift the read data to be reflected in mask */
+ *mask = (uint8_t)(row_data[0] >> MDTP_EFUSE_START);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * read_test_fuse
+ *
+ * @param mask[out] - MDTP efuse value represented by a bitfield.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int read_test_fuse(uint8_t *mask)
+{
+ int status = 0;
+ metadata_t metadata;
+
+ status = read_metadata(&metadata);
+ if (status) {
+ dprintf(CRITICAL, "mdtp: read_test_fuse: Failure getting metadata");
+ return -1;
+ }
+
+ *mask = metadata.eFuses.mask;
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * read_fuse
+ *
+ * @param mask[out] - MDTP efuse value represented by a bitfield.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int read_fuse(uint8_t *mask)
+{
+ if (is_test_mode())
+ return read_test_fuse(mask);
+ else
+ return read_QFPROM_fuse(mask);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * mdtp_fuse_get_enabled
+ *
+ * Read the Firmware Lock eFuses and return whether the Firmware
+ * Lock is currently enabled or disabled in HW.
+ *
+ * @param[out] enabled: 0 - enable, 1 - disable.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+int mdtp_fuse_get_enabled(bool *enabled)
+{
+ int status;
+ mdtp_eFuses_t eFuses;
+
+ status = read_fuse(&eFuses.mask);
+ if (status)
+ {
+ dprintf(CRITICAL, "mdtp: mdtp_fuse_get_enabled: Failure in reading fuse");
+ return -1;
+ }
+
+ if ((eFuses.bitwise.enable1 && !eFuses.bitwise.disable1) ||
+ (eFuses.bitwise.enable2 && !eFuses.bitwise.disable2) ||
+ (eFuses.bitwise.enable3 && !eFuses.bitwise.disable3))
+ {
+ *enabled = 1;
+ }
+ else
+ *enabled = 0;
+
+ return 0;
+}
+
diff --git a/app/aboot/mdtp_ui.c b/app/aboot/mdtp_ui.c
new file mode 100644
index 0000000..30d70d6
--- /dev/null
+++ b/app/aboot/mdtp_ui.c
@@ -0,0 +1,301 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <dev/fbcon.h>
+#include <target.h>
+#include <mmc.h>
+#include <partition_parser.h>
+#include <stdlib.h>
+#include "mdtp.h"
+
+#define MDTP_IMAGE_WIDTH 500
+#define MDTP_IMAGE_HEIGHT 800
+#define MDTP_UX_DELAY 1000
+#define MDTP_OK_OFFSET 0x0
+#define MDTP_CHECKING_OFFSET 0x200000
+#define MDTP_INVALID_OFFSET 0x400000
+#define MDTP_RECOVERED_OFFSET 0x600000
+
+extern uint32_t target_volume_down(void);
+extern void fbcon_putImage(struct fbimage *fbimg, bool flag);
+extern void mdelay(unsigned msecs);
+
+static struct fbimage mdtp_header;/* = {0};*/
+
+/********************************************************************************/
+
+/* Load the "Firmware Valid" image from EMMC */
+static struct fbimage* mdtp_images_mmc_OK()
+{
+ int index = INVALID_PTN;
+ unsigned long long ptn = 0;
+ struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &mdtp_header;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition table not found\n");
+ return NULL;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display)
+ {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ base += LOGO_IMG_OFFSET;
+
+ if (mmc_read(ptn, (void*)base, ROUNDUP(MDTP_IMAGE_WIDTH*MDTP_IMAGE_HEIGHT*3, block_size))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: mdtp image read failed\n");
+ return NULL;
+ }
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+/* Load the "Firmware Invalid" image from EMMC */
+static struct fbimage* mdtp_images_mmc_INVALID()
+{
+ int index = INVALID_PTN;
+ unsigned long long ptn = 0;
+ struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &mdtp_header;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition table not found\n");
+ return NULL;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display)
+ {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ base += LOGO_IMG_OFFSET;
+
+ if (mmc_read(ptn+MDTP_INVALID_OFFSET, (void*)base, ROUNDUP(MDTP_IMAGE_WIDTH*MDTP_IMAGE_HEIGHT*3, block_size))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: mdtp image read failed\n");
+ return NULL;
+ }
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+/* Load the "Verifying Firmware" image from EMMC */
+static struct fbimage* mdtp_images_mmc_CHECKING()
+{
+ int index = INVALID_PTN;
+ unsigned long long ptn = 0;
+ struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &mdtp_header;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition table not found\n");
+ return NULL;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display)
+ {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ base += LOGO_IMG_OFFSET;
+
+ if (mmc_read(ptn+MDTP_CHECKING_OFFSET, (void*)base, ROUNDUP(MDTP_IMAGE_WIDTH*MDTP_IMAGE_HEIGHT*3, block_size))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: mdtp image read failed\n");
+ return NULL;
+ }
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+/* Load the "Verifying Firmware" image from EMMC */
+static struct fbimage* mdtp_images_mmc_RECOVERED()
+{
+ int index = INVALID_PTN;
+ unsigned long long ptn = 0;
+ struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &mdtp_header;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition table not found\n");
+ return NULL;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display)
+ {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ base += LOGO_IMG_OFFSET;
+
+ if (mmc_read(ptn+MDTP_RECOVERED_OFFSET, (void*)base, ROUNDUP(MDTP_IMAGE_WIDTH*MDTP_IMAGE_HEIGHT*3, block_size))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: mdtp image read failed\n");
+ return NULL;
+ }
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+/* Show the "Firmware Valid" image */
+static void display_image_on_screen_OK()
+{
+ struct fbimage *fbimg;
+
+ fbcon_clear();
+ fbimg = mdtp_images_mmc_OK();
+ fbimg->header.width = MDTP_IMAGE_WIDTH;
+ fbimg->header.height = MDTP_IMAGE_HEIGHT;
+
+ dprintf(CRITICAL, "display_image_on_screen_OK\n");
+ fbcon_putImage(fbimg, true);
+}
+
+/* Show the "Firmware Invalid" image */
+static void display_image_on_screen_INVALID()
+{
+ struct fbimage *fbimg;
+
+ fbcon_clear();
+ fbimg = mdtp_images_mmc_INVALID();
+ fbimg->header.width = MDTP_IMAGE_WIDTH;
+ fbimg->header.height = MDTP_IMAGE_HEIGHT;
+
+ dprintf(CRITICAL, "display_image_on_screen_INVALID\n");
+ fbcon_putImage(fbimg, true);
+}
+
+/* Show the "Verifying Firmware" image */
+static void display_image_on_screen_CHECKING()
+{
+ struct fbimage *fbimg;
+
+ fbcon_clear();
+ fbimg = mdtp_images_mmc_CHECKING();
+ fbimg->header.width = MDTP_IMAGE_WIDTH;
+ fbimg->header.height = MDTP_IMAGE_HEIGHT;
+
+ dprintf(CRITICAL, "display_image_on_screen_CHECKING\n");
+ fbcon_putImage(fbimg, true);
+}
+
+/* Show the "Verifying Firmware" image */
+static void display_image_on_screen_RECOVERED()
+{
+ struct fbimage *fbimg;
+
+ fbcon_clear();
+ fbimg = mdtp_images_mmc_RECOVERED();
+ fbimg->header.width = MDTP_IMAGE_WIDTH;
+ fbimg->header.height = MDTP_IMAGE_HEIGHT;
+
+ dprintf(CRITICAL, "display_image_on_screen_RECOVERED\n");
+ fbcon_putImage(fbimg, true);
+}
+
+/* Display the "Firmware Valid" screen */
+void show_OK_msg()
+{
+ display_image_on_screen_OK();
+ mdelay(MDTP_UX_DELAY);
+
+ return;
+}
+
+/* Display the "Firmware Invalid" screen */
+void show_invalid_msg()
+{
+ display_image_on_screen_INVALID();
+
+ while (1)
+ {
+ if(target_volume_down())
+ {
+ display_image_on_screen_RECOVERED();
+ mdelay(MDTP_UX_DELAY);
+ break;
+ }
+ }
+
+ return;
+}
+
+/* Display the "Verifying Firmware" screen */
+void show_checking_msg()
+{
+ display_image_on_screen_CHECKING();
+ return;
+}
+
+/* Display the "Verifying Firmware" screen */
+void show_recovered_msg()
+{
+ display_image_on_screen_RECOVERED();
+ return;
+}
+
diff --git a/app/aboot/recovery.c b/app/aboot/recovery.c
index 0c55e9b..15797a1 100644
--- a/app/aboot/recovery.c
+++ b/app/aboot/recovery.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -418,6 +418,12 @@
size = mmc_get_device_blocksize();
index = partition_get_index((const char *) ptn_name);
+ if (index < 0)
+ {
+ dprintf(CRITICAL, "%s: Partition not found\n", ptn_name);
+ return -1;
+ }
+
ptn = partition_get_offset(index);
mmc_set_lun(partition_get_lun(index));
if(ptn == 0) {
diff --git a/app/aboot/rules.mk b/app/aboot/rules.mk
index 5342d7a..95a8865 100644
--- a/app/aboot/rules.mk
+++ b/app/aboot/rules.mk
@@ -9,3 +9,9 @@
$(LOCAL_DIR)/fastboot.o \
$(LOCAL_DIR)/recovery.o
+ifeq ($(ENABLE_MDTP_SUPPORT),1)
+OBJS += \
+ $(LOCAL_DIR)/mdtp.o \
+ $(LOCAL_DIR)/mdtp_ui.o \
+ $(LOCAL_DIR)/mdtp_fuse.o
+endif
diff --git a/arch/arm/arch.c b/arch/arm/arch.c
index dc171b4..6b5cf72 100644
--- a/arch/arm/arch.c
+++ b/arch/arm/arch.c
@@ -25,6 +25,7 @@
#include <arch/ops.h>
#include <arch/arm.h>
#include <arch/arm/mmu.h>
+#include <arch/defines.h>
#include <platform.h>
#if ARM_CPU_CORTEX_A8
@@ -59,6 +60,8 @@
val |= (3<<22)|(3<<20);
__asm__ volatile("mcr p15, 0, %0, c1, c0, 2" :: "r" (val));
+ isb();
+
/* set enable bit in fpexc */
__asm__ volatile("mrc p10, 7, %0, c8, c0, 0" : "=r" (val));
val |= (1<<30);
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S
index 22d9a2b..cfcbaa4 100644
--- a/arch/arm/cache-ops.S
+++ b/arch/arm/cache-ops.S
@@ -328,6 +328,7 @@
/* void arch_flush_invalidate_cache_range(addr_t start, size_t len); */
FUNCTION(arch_clean_invalidate_cache_range)
+ dsb
add r2, r0, r1 // Calculate the end address
bic r0,#(CACHE_LINE-1) // Align start with cache line
0:
diff --git a/arch/arm/include/arch/arm.h b/arch/arm/include/arch/arm.h
index a14bf9c..e056628 100644
--- a/arch/arm/include/arch/arm.h
+++ b/arch/arm/include/arch/arm.h
@@ -87,6 +87,8 @@
void arm_write_dacr(uint32_t val);
void arm_invalidate_tlb(void);
+void dump_fault_frame(struct arm_fault_frame *frame);
+
#if defined(__cplusplus)
}
#endif
diff --git a/arch/arm/ops.S b/arch/arm/ops.S
index 6daea96..4cfd180 100644
--- a/arch/arm/ops.S
+++ b/arch/arm/ops.S
@@ -42,7 +42,13 @@
/* int atomic_swap(int *ptr, int val); */
FUNCTION(atomic_swap)
- swp r0, r2, [r1]
+.L_loop_swap:
+ ldrex r12, [r0]
+ strex r2, r1, [r0]
+ cmp r2 , #0
+ bne .L_loop_swap
+
+ mov r0, r12
bx lr
/* int atomic_add(int *ptr, int val); */
diff --git a/dev/fbcon/fbcon.c b/dev/fbcon/fbcon.c
index a593a62..ce79a3e 100644
--- a/dev/fbcon/fbcon.c
+++ b/dev/fbcon/fbcon.c
@@ -2,7 +2,7 @@
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -35,6 +35,7 @@
#include <splash.h>
#include <platform.h>
#include <string.h>
+#include <arch/ops.h>
#include "font5x12.h"
@@ -233,6 +234,8 @@
}
fbcon_putImage(fbimg, flag);
+ if(flag)
+ free(fbimg);
}
void fbcon_putImage(struct fbimage *fbimg, bool flag)
@@ -242,9 +245,11 @@
unsigned total_y;
unsigned bytes_per_bpp;
unsigned image_base;
- unsigned width, pitch, height;
- unsigned char *logo_base;
- struct logo_img_header *header;
+ unsigned width = 0, pitch = 0, height = 0;
+#if DISPLAY_TYPE_MIPI
+ unsigned char *logo_base = NULL;
+#endif
+ struct logo_img_header *header = NULL;
if (!config) {
@@ -256,7 +261,6 @@
header = &fbimg->header;
width = pitch = header->width;
height = header->height;
- logo_base = (unsigned char *)fbimg->image;
}
total_x = config->width;
@@ -264,9 +268,12 @@
bytes_per_bpp = ((config->bpp) / 8);
#if DISPLAY_TYPE_MIPI
+ if(fbimg) {
+ logo_base = (unsigned char *)fbimg->image;
+ }
if (bytes_per_bpp == 3)
{
- if(flag) {
+ if(flag && header) {
if (header->width == config->width && header->height == config->height)
return;
else {
@@ -294,6 +301,8 @@
memcpy (config->base + ((image_base + (i * (config->width))) * bytes_per_bpp),
logo_base + (i * pitch * bytes_per_bpp), width * bytes_per_bpp);
}
+ /* Flush the contents to memory before giving the data to dma */
+ arch_clean_invalidate_cache_range((addr_t) config->base, (total_x * total_y * bytes_per_bpp));
}
fbcon_flush();
@@ -317,6 +326,8 @@
(header->height * bytes_per_bpp));
}
}
+ /* Flush the contents to memory before giving the data to dma */
+ arch_clean_invalidate_cache_range((addr_t) config->base, (total_x * total_y * bytes_per_bpp));
fbcon_flush();
#endif
}
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index cff176f..2794203 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -56,16 +56,20 @@
pinfo->lcdc.v_front_porch + pinfo->lcdc.v_pulse_width +
pinfo->lcdc.yres_pad;
- /* Pixel clock rate */
- pll_data.pixel_clock = h_period * v_period * pinfo->mipi.frame_rate;
-
- /* Store all bit clock form data */
+ /*
+ * If a bit clock rate is not specified, calculate it based
+ * on panel parameters
+ */
if (pinfo->mipi.bitclock == 0)
- pll_data.bit_clock = (pll_data.pixel_clock * pinfo->bpp) /
- pinfo->mipi.num_of_lanes;
+ pll_data.bit_clock = (h_period * v_period *
+ pinfo->mipi.frame_rate * pinfo->bpp) /
+ pinfo->mipi.num_of_lanes;
else
pll_data.bit_clock = pinfo->mipi.bitclock;
+ pll_data.pixel_clock = (pll_data.bit_clock * pinfo->mipi.num_of_lanes) /
+ pinfo->bpp;
+
pll_data.byte_clock = pll_data.bit_clock >> 3;
pll_data.halfbit_clock = pll_data.bit_clock >> 1;
@@ -97,7 +101,6 @@
static uint32_t calculate_div3(uint8_t bpp, uint8_t num_of_lanes)
{
- uint32_t ret = NO_ERROR;
pll_data.pclk_m = 0x1; /* M = 1, N= 1 */
pll_data.pclk_n = 0xFF; /* ~ (N-M) = 0xff */
pll_data.pclk_d = 0xFF; /* ~N = 0xFF */
@@ -138,13 +141,14 @@
}
pll_data.posdiv3--; /* Register needs one value less */
+ return NO_ERROR;
}
static uint32_t calculate_dec_frac_start()
{
uint32_t refclk = 19200000;
uint32_t vco_rate = pll_data.vco_clock;
- uint32_t tmp;
+ uint32_t tmp, mod;
vco_rate /= 2;
pll_data.dec_start = vco_rate / refclk;
@@ -157,21 +161,30 @@
pll_data.frac_start = tmp;
vco_rate *= 2; /* restore */
- tmp = vco_rate / (refclk / 1000);/* div 1000 first */
- tmp *= 1024;
- tmp /= 1000;
- tmp /= 10;
- pll_data.lock_comp = tmp - 1;
+ if (pll_data.en_vco_zero_phase) {
+ tmp = vco_rate / (refclk / 1000);/* div 1000 first */
+ tmp *= 1024;
+ tmp /= 1000;
+ tmp /= 10;
+ pll_data.lock_comp = tmp - 1;
+ } else {
+ tmp = vco_rate / refclk;
+ mod = vco_rate % refclk;
+ tmp *= 127;
+ mod *= 127;
+ mod /= refclk;
+ tmp += mod;
+ tmp /= 10;
+ pll_data.lock_comp = tmp;
+ }
dprintf(SPEW, "%s: dec_start=0x%x dec_frac=0x%x lock_comp=0x%x\n", __func__,
pll_data.dec_start, pll_data.frac_start, pll_data.lock_comp);
+ return NO_ERROR;
}
static uint32_t calculate_vco_28nm(uint8_t bpp, uint8_t num_of_lanes)
{
- uint8_t counter = 0;
- uint32_t temprate = 0;
-
/* If half bitclock is more than VCO min value */
if (pll_data.halfbit_clock > VCO_MIN_CLOCK) {
@@ -201,6 +214,24 @@
return NO_ERROR;
}
+#ifndef DISPLAY_EN_20NM_PLL_90_PHASE
+static void config_20nm_pll_vco_range(void)
+{
+ pll_data.vco_min = 300000000;
+ pll_data.vco_max = 1500000000;
+ pll_data.en_vco_zero_phase = 1;
+ dprintf(SPEW, "%s: Configured VCO for zero phase\n", __func__);
+}
+#else
+static void config_20nm_pll_vco_range(void)
+{
+ pll_data.vco_min = 1000000000;
+ pll_data.vco_max = 2000000000;
+ pll_data.en_vco_zero_phase = 0;
+ dprintf(SPEW, "%s: Configured VCO for 90 phase\n", __func__);
+}
+#endif
+
static uint32_t calculate_vco_20nm(uint8_t bpp, uint8_t lanes)
{
uint32_t vco, dsi_clk;
@@ -233,12 +264,12 @@
hr_oclk2 = 4;
/* If bitclock is more than VCO min value */
- if (pll_data.halfbit_clock >= HALF_VCO_MIN_CLOCK_20NM) {
+ if (pll_data.halfbit_clock >= ((pll_data.vco_min) >> 1)) {
/* Direct Mode */
vco = pll_data.halfbit_clock << 1;
/* support vco clock to max value only */
- if (vco > VCO_MAX_CLOCK_20NM)
- vco = VCO_MAX_CLOCK_20NM;
+ if (vco > (pll_data.vco_max))
+ vco = (pll_data.vco_max);
pll_data.directpath = 0x0;
pll_data.byte_clock = vco / 2 / hr_oclk2;
@@ -247,8 +278,8 @@
hr_oclk3 = hr_oclk2 * m / n * bpp_m / bpp_n / lanes;
} else {
/* Indirect Mode */
- mod = VCO_MIN_CLOCK_20NM % (4 * pll_data.halfbit_clock );
- ndiv = VCO_MIN_CLOCK_20NM / (4 * pll_data.halfbit_clock );
+ mod = (pll_data.vco_min) % (4 * pll_data.halfbit_clock );
+ ndiv = (pll_data.vco_min) / (4 * pll_data.halfbit_clock );
if (mod)
ndiv += 1;
@@ -286,6 +317,9 @@
calculate_bitclock(pinfo);
if (pinfo->mipi.mdss_dsi_phy_db->is_pll_20nm)
+ config_20nm_pll_vco_range();
+
+ if (pinfo->mipi.mdss_dsi_phy_db->is_pll_20nm)
ret = calculate_vco_20nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
else
ret = calculate_vco_28nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
diff --git a/dev/gcdb/display/gcdb_autopll.h b/dev/gcdb/display/gcdb_autopll.h
index b261a34..aca4463 100755
--- a/dev/gcdb/display/gcdb_autopll.h
+++ b/dev/gcdb/display/gcdb_autopll.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,11 +43,6 @@
#define HALFBIT_CLOCK3 44000000 /* VCO min clock div by 8 */
#define HALFBIT_CLOCK4 40000000 /* VCO min clock div by 9 */
-#define VCO_MIN_CLOCK_20NM 300000000
-#define VCO_MAX_CLOCK_20NM 1500000000
-
-#define HALF_VCO_MIN_CLOCK_20NM (VCO_MIN_CLOCK_20NM >> 1)
-
#define HALFBIT_CLOCK1_20NM 500000000 /* VCO min clock div by 2 */
#define HALFBIT_CLOCK2_20NM 250000000 /* VCO min clock div by 4 */
#define HALFBIT_CLOCK3_20NM 125000000 /* VCO min clock div by 8 */
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 2066e4d..4a49b1b 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -30,13 +30,16 @@
#include <debug.h>
#include <err.h>
#include <smem.h>
+#include <clock.h>
#include <msm_panel.h>
#include <string.h>
#include <stdlib.h>
#include <board.h>
#include <mdp5.h>
+#include <qtimer.h>
#include <platform/gpio.h>
#include <mipi_dsi.h>
+#include <partition_parser.h>
#include "include/display_resource.h"
#include "include/panel.h"
@@ -80,12 +83,10 @@
uint32_t ret = NO_ERROR;
ret = calculate_clock_config(pinfo);
- if (ret) {
- dprintf(CRITICAL, "Clock calculation failed \n");
- /* should it stop here ? check with display team */
- }
-
- ret = target_panel_clock(enable, pinfo);
+ if (ret)
+ dprintf(CRITICAL, "Clock calculation failed\n");
+ else
+ ret = target_panel_clock(enable, pinfo);
return ret;
}
@@ -149,6 +150,172 @@
return ret;
}
+static int mdss_dsi_dfps_get_pll_codes_cal(struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ uint32_t fps_bak;
+ uint32_t i;
+
+ fps_bak = pinfo->mipi.frame_rate;
+
+ for (i = 0; i < pinfo->dfps.panel_dfps.frame_rate_cnt; i++) {
+ int err;
+ pinfo->mipi.frame_rate = pinfo->dfps.panel_dfps.frame_rate[i];
+
+ err = mdss_dsi_panel_clock(1, pinfo);
+ if (!err) {
+ pinfo->dfps.codes_dfps[i].is_valid = 1;
+ pinfo->dfps.codes_dfps[i].frame_rate =
+ pinfo->mipi.frame_rate;
+ pinfo->dfps.codes_dfps[i].frame_rate =
+ pinfo->mipi.frame_rate;
+ pinfo->dfps.codes_dfps[i].clk_rate =
+ pinfo->mipi.dsi_pll_config->vco_clock;
+ pinfo->dfps.codes_dfps[i].pll_codes =
+ pinfo->mipi.pll_codes;
+
+ mdss_dsi_panel_clock(0, pinfo);
+ } else {
+ ret = err;
+ pinfo->dfps.codes_dfps[i].is_valid = 0;
+ dprintf(CRITICAL, "frame_rate=%d failed!\n",
+ pinfo->mipi.frame_rate);
+ }
+ }
+
+ pinfo->mipi.frame_rate = fps_bak;
+
+ return ret;
+}
+
+static int mdss_dsi_dfps_get_stored_pll_codes(struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ int index;
+ unsigned long long ptn;
+ uint32_t blocksize;
+ struct dfps_info *dfps;
+
+ index = partition_get_index("splash");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition table not found\n");
+ ret = ERROR;
+ goto splash_err;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition invalid offset\n");
+ ret = ERROR;
+ goto splash_err;
+ }
+
+ mmc_set_lun(partition_get_lun(index));
+
+ blocksize = mmc_get_device_blocksize();
+ if (blocksize == 0) {
+ dprintf(CRITICAL, "ERROR:splash Partition invalid blocksize\n");
+ ret = ERROR;
+ goto splash_err;
+ }
+
+ dfps = (struct dfps_info *)memalign(CACHE_LINE, ROUNDUP(PAGE_SIZE,
+ CACHE_LINE));
+ if (!dfps) {
+ dprintf(CRITICAL, "ERROR:splash Partition invalid memory\n");
+ ret = ERROR;
+ goto splash_err;
+ }
+
+ if (mmc_read(ptn, (uint32_t *) dfps, blocksize)) {
+ dprintf(CRITICAL, "mmc read splash failure%d\n", PAGE_SIZE);
+ ret = ERROR;
+ free(dfps);
+ goto splash_err;
+ }
+
+ dprintf(SPEW, "enable=%d cnt=%d\n", dfps->panel_dfps.enabled,
+ dfps->panel_dfps.frame_rate_cnt);
+
+ if (!dfps->panel_dfps.enabled || dfps->panel_dfps.frame_rate_cnt >
+ DFPS_MAX_FRAME_RATE) {
+ ret = ERROR;
+ free(dfps);
+ goto splash_err;
+ }
+
+ pinfo->dfps = *dfps;
+ free(dfps);
+
+splash_err:
+ return ret;
+}
+
+static int mdss_dsi_dfps_store_pll_codes(struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ int index;
+ unsigned long long ptn;
+
+ index = partition_get_index("splash");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition table not found\n");
+ ret = ERROR;
+ goto store_err;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition invalid offset\n");
+ ret = ERROR;
+ goto store_err;
+ }
+
+ mmc_set_lun(partition_get_lun(index));
+
+ ret = mmc_write(ptn, sizeof(uint32_t), &pinfo->dfps);
+ if (ret)
+ dprintf(CRITICAL, "mmc write failed!\n");
+
+store_err:
+ return ret;
+}
+
+static int mdss_dsi_mipi_dfps_config(struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+
+ if (!pinfo)
+ return ERROR;
+
+ if (!pinfo->dfps.panel_dfps.enabled)
+ goto dfps_done;
+
+ if (!mdss_dsi_dfps_get_stored_pll_codes(pinfo)) {
+ dprintf(SPEW, "Found stored PLL codes!\n");
+ goto dfps_cal_done;
+ }
+
+ ret = mdss_dsi_dfps_get_pll_codes_cal(pinfo);
+ if (ret) {
+ dprintf(CRITICAL, "Cannot cal pll codes!\n");
+ goto dfps_done;
+ } else {
+ dprintf(SPEW, "Calibrate all pll codes!\n");
+ }
+
+ ret = mdss_dsi_dfps_store_pll_codes(pinfo);
+ if (ret)
+ dprintf(CRITICAL, "Cannot store pll codes!\n");
+
+dfps_cal_done:
+ if (pinfo->dfps.dfps_fb_base)
+ memcpy(pinfo->dfps.dfps_fb_base, &pinfo->dfps,
+ sizeof(struct dfps_info));
+dfps_done:
+ return ret;
+}
+
static int mdss_dsi_bl_enable(uint8_t enable)
{
int ret = NO_ERROR;
@@ -199,6 +366,7 @@
char *default_str;
int panel_mode = SPLIT_DISPLAY_FLAG | DUAL_PIPE_FLAG | DST_SPLIT_FLAG;
int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
+ char *sctl_string;
panel_name += strspn(panel_name, " ");
@@ -254,7 +422,12 @@
arg_size = prefix_string_len + dsi_id_len + panel_node_len +
LK_OVERRIDE_PANEL_LEN + 1;
- arg_size += DSI_1_STRING_LEN + slave_panel_node_len;
+ if (!strcmp(panelstruct.paneldata->panel_destination, "DISPLAY_2"))
+ sctl_string = DSI_0_STRING;
+ else
+ sctl_string = DSI_1_STRING;
+
+ arg_size += strlen(sctl_string) + slave_panel_node_len;
if (buf_size < arg_size) {
dprintf(CRITICAL, "display command line buffer is small\n");
@@ -277,12 +450,11 @@
pbuf += panel_node_len;
buf_size -= panel_node_len;
- strlcpy(pbuf, DSI_1_STRING, buf_size);
- pbuf += DSI_1_STRING_LEN;
- buf_size -= DSI_1_STRING_LEN;
+ strlcpy(pbuf, sctl_string, buf_size);
+ pbuf += strlen(sctl_string);
+ buf_size -= strlen(sctl_string);
strlcpy(pbuf, slave_panel_node, buf_size);
}
-end:
return ret;
}
@@ -386,9 +558,20 @@
panel.panel_info.mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
panel.pll_clk_func = mdss_dsi_panel_clock;
+ panel.dfps_func = mdss_dsi_mipi_dfps_config;
panel.power_func = mdss_dsi_panel_power;
panel.pre_init_func = mdss_dsi_panel_pre_init;
panel.bl_func = mdss_dsi_bl_enable;
+ /*
+ * If dfps enabled, reserve fb memory to store pll
+ * codes and pass pll codes values to kernel.
+ */
+ if (panel.panel_info.dfps.panel_dfps.enabled) {
+ panel.panel_info.dfps.dfps_fb_base = base;
+ base += DFPS_PLL_CODES_SIZE;
+ dprintf(SPEW, "fb_base=0x%p!\n", base);
+ }
+
panel.fb.base = base;
panel.fb.width = panel.panel_info.xres;
panel.fb.height = panel.panel_info.yres;
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 3b112e3..95e11d4 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -35,6 +35,7 @@
/*---------------------------------------------------------------------------*/
#include <debug.h>
#include "include/display_resource.h"
+#include "panel_display.h"
#define TIMING_SIZE 48
#define REGULATOR_SIZE 28
@@ -43,9 +44,6 @@
#define BIST_SIZE 6
#define LANE_SIZE 45
-#define DSI_1_STRING ":1:"
-#define DSI_1_STRING_LEN 3
-
/*---------------------------------------------------------------------------*/
/* API */
/*---------------------------------------------------------------------------*/
@@ -57,7 +55,22 @@
int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo);
int gcdb_display_init(const char *panel_name, uint32_t rev, void *base);
-bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size);
+int gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size);
void gcdb_display_shutdown();
+int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo, struct mdss_dsi_phy_ctrl *phy_db);
+
+static inline void set_panel_cmd_string(const char *panel_name,
+ char *cont_splash)
+{
+ char *ch = NULL;
+ ch = strchr((char *) panel_name, ':');
+ if (ch) {
+ *cont_splash = *(ch + 1);
+ *ch = '\0';
+ } else {
+ *cont_splash = '\0';
+ }
+}
#endif /*_GCDB_DISPLAY_H_ */
diff --git a/dev/gcdb/display/include/display_resource.h b/dev/gcdb/display/include/display_resource.h
index ca392ff..6250427 100755
--- a/dev/gcdb/display/include/display_resource.h
+++ b/dev/gcdb/display/include/display_resource.h
@@ -42,6 +42,11 @@
#define LK_OVERRIDE_PANEL "1:"
#define LK_OVERRIDE_PANEL_LEN 2
+#define DSI_0_STRING ":0:"
+#define DSI_0_STRING_LEN 3
+#define DSI_1_STRING ":1:"
+#define DSI_1_STRING_LEN 3
+
#define NO_PANEL_CONFIG "none"
#define SIM_VIDEO_PANEL "sim_video_panel"
#define SIM_DUALDSI_VIDEO_PANEL "sim_dualdsi_video_panel"
@@ -61,7 +66,7 @@
/*---------------------------------------------------------------------------*/
/*GPIO pin structure to define reset pin, enable pin, te pin, etc. */
-typedef struct gpio_pin{
+struct gpio_pin{
char *pin_source;
uint32_t pin_id;
@@ -72,7 +77,7 @@
};
/*LDO entry structure for different LDO entries. */
-typedef struct ldo_entry{
+struct ldo_entry{
char *ldo_name;
uint32_t ldo_id;
uint32_t ldo_type;
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index c21383e..913bafb 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -39,7 +39,7 @@
#define TOTAL_RESET_GPIO_CTRL 5
/*---------------------------------------------------------------------------*/
-/* panel type
+/* panel type */
/*---------------------------------------------------------------------------*/
enum {
PANEL_TYPE_UNKNOWN,
@@ -53,7 +53,7 @@
/*---------------------------------------------------------------------------*/
/*Panel Configuration */
-typedef struct panel_config{
+struct panel_config{
char *panel_node_id;
char *panel_controller;
@@ -62,6 +62,7 @@
uint16_t panel_type;
char *panel_destination;
uint32_t panel_orientation;
+ /* panel_clockrate is deprecated in favor of panel_bitclock_freq */
uint32_t panel_clockrate;
uint16_t panel_framerate;
uint16_t panel_channelid;
@@ -78,7 +79,7 @@
char *slave_panel_node_id;
};
-typedef struct panel_resolution{
+struct panel_resolution{
uint16_t panel_width;
uint16_t panel_height;
@@ -100,7 +101,7 @@
uint16_t invert_hsync_polarity;
};
-typedef struct color_info{
+struct color_info{
uint8_t color_format;
uint8_t color_order;
uint8_t underflow_color;
@@ -109,12 +110,12 @@
uint8_t pixel_alignment;
};
-typedef struct command_state {
+struct command_state {
uint8_t oncommand_state;
uint8_t offcommand_state;
};
-typedef struct videopanel_info {
+struct videopanel_info {
uint8_t hsync_pulse;
uint8_t hfp_power_mode;
uint8_t hbp_power_mode;
@@ -126,7 +127,7 @@
uint32_t bllp_eof_power;
};
-typedef struct commandpanel_info {
+struct commandpanel_info {
uint8_t techeck_enable;
uint8_t tepin_select;
uint8_t teusing_tepin;
@@ -141,16 +142,17 @@
uint32_t cmdmode_idletime;
};
-typedef struct lane_configuration {
+struct lane_configuration {
uint8_t dsi_lanes;
uint8_t dsi_lanemap;
uint8_t lane0_state;
uint8_t lane1_state;
uint8_t lane2_state;
uint8_t lane3_state;
+ uint8_t force_clk_lane_hs;
};
-typedef struct panel_timing {
+struct panel_timing {
uint8_t dsi_mdp_trigger;
uint8_t dsi_dma_trigger;
uint8_t tclk_post;
@@ -163,13 +165,13 @@
BL_DCS,
};
-typedef struct panel_reset_sequence {
+struct panel_reset_sequence {
uint8_t pin_state[TOTAL_RESET_GPIO_CTRL];
uint32_t sleep[TOTAL_RESET_GPIO_CTRL];
uint8_t pin_direction;
};
-typedef struct backlight {
+struct backlight {
uint16_t bl_interface_type;
uint16_t bl_min_level;
uint16_t bl_max_level;
@@ -178,7 +180,7 @@
char *bl_pmic_model;
};
-typedef struct fb_compression {
+struct fb_compression {
uint32_t enabled;
uint32_t comp_ratio;
uint32_t comp_mode;
@@ -196,6 +198,10 @@
uint32_t lossy_mode_thd;
uint32_t lossy_rgb_thd;
uint32_t lossy_mode_idx;
+
+ uint32_t slice_height;
+ uint32_t pred_mode;
+ uint32_t max_pred_err;
};
#endif /*_PANEL_H_ */
diff --git a/dev/gcdb/display/include/panel_generic_720p_cmd.h b/dev/gcdb/display/include/panel_generic_720p_cmd.h
index 8320407..8e9ccd4 100644
--- a/dev/gcdb/display/include/panel_generic_720p_cmd.h
+++ b/dev/gcdb/display/include/panel_generic_720p_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -151,7 +151,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration generic_720p_cmd_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_hx8279a_wsvga_video.h b/dev/gcdb/display/include/panel_hx8279a_wsvga_video.h
new file mode 100644
index 0000000..b465b78
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8279a_wsvga_video.h
@@ -0,0 +1,1146 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_HX8279A_WSVGA_VIDEO_H_
+#define _PANEL_HX8279A_WSVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config hx8279a_wsvga_video_panel_data = {
+ "qcom,mdss_dsi_hx8279a_wsvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8279a_wsvga_video_panel_res = {
+ 600, 1024, 20, 36, 24, 0, 2, 5, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8279a_wsvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char hx8279a_wsvga_video_on_cmd0[] = {
+ 0xB0, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd1[] = {
+ 0xBA, 0xA4, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd2[] = {
+ 0xBD, 0x71, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd3[] = {
+ 0xBE, 0x22, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd4[] = {
+ 0xBF, 0x19, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd5[] = {
+ 0xC5, 0x05, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd6[] = {
+ 0xC6, 0x02, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd7[] = {
+ 0xC7, 0x05, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd8[] = {
+ 0xC8, 0x03, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd9[] = {
+ 0xC9, 0x18, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd10[] = {
+ 0xB0, 0x01, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd11[] = {
+ 0xB1, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd12[] = {
+ 0xB2, 0x2c, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd13[] = {
+ 0xB3, 0x5c, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd14[] = {
+ 0xB4, 0xac, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd15[] = {
+ 0xB5, 0xdc, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd16[] = {
+ 0xB6, 0x5c, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd17[] = {
+ 0xB7, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd18[] = {
+ 0xB8, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd19[] = {
+ 0xB9, 0x0C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd20[] = {
+ 0xBA, 0x3C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd21[] = {
+ 0xBB, 0x6C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd22[] = {
+ 0xBC, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd23[] = {
+ 0xBD, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd24[] = {
+ 0xBE, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd25[] = {
+ 0xBF, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd26[] = {
+ 0xC0, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd27[] = {
+ 0xC1, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd28[] = {
+ 0xC2, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd29[] = {
+ 0xC3, 0x15, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd30[] = {
+ 0xC4, 0xAA, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd31[] = {
+ 0xC5, 0xAF, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd32[] = {
+ 0xC6, 0x03, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd33[] = {
+ 0xC7, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd34[] = {
+ 0xC8, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd35[] = {
+ 0xC9, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd36[] = {
+ 0xCA, 0xAC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd37[] = {
+ 0xCB, 0xDC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd38[] = {
+ 0xCC, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd39[] = {
+ 0xCD, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd40[] = {
+ 0xCE, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd41[] = {
+ 0xCF, 0x0C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd42[] = {
+ 0xD0, 0x3C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd43[] = {
+ 0xD1, 0x6C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd44[] = {
+ 0xD2, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd45[] = {
+ 0xD3, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd46[] = {
+ 0xD4, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd47[] = {
+ 0xD5, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd48[] = {
+ 0xD6, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd49[] = {
+ 0xD7, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd50[] = {
+ 0xD8, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd51[] = {
+ 0xD9, 0x15, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd52[] = {
+ 0xDA, 0xAA, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd53[] = {
+ 0xDB, 0xAF, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd54[] = {
+ 0xDC, 0x03, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd55[] = {
+ 0xDD, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd56[] = {
+ 0xDE, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd57[] = {
+ 0xDF, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd58[] = {
+ 0xE0, 0xAC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd59[] = {
+ 0xE1, 0xDC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd60[] = {
+ 0xE2, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd61[] = {
+ 0xE3, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd62[] = {
+ 0xE4, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd63[] = {
+ 0xE5, 0x0C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd64[] = {
+ 0xE6, 0x3C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd65[] = {
+ 0xE7, 0x6C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd66[] = {
+ 0xE8, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd67[] = {
+ 0xE9, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd68[] = {
+ 0xEA, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd69[] = {
+ 0xEB, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd70[] = {
+ 0xEC, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd71[] = {
+ 0xED, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd72[] = {
+ 0xEE, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd73[] = {
+ 0xEF, 0x15, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd74[] = {
+ 0xF0, 0xAA, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd75[] = {
+ 0xF1, 0xAF, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd76[] = {
+ 0xF2, 0x03, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd77[] = {
+ 0xB0, 0x02, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd78[] = {
+ 0xB1, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd79[] = {
+ 0xB2, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd80[] = {
+ 0xB3, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd81[] = {
+ 0xB4, 0xAC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd82[] = {
+ 0xB5, 0xDC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd83[] = {
+ 0xB6, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd84[] = {
+ 0xB7, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd85[] = {
+ 0xB8, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd86[] = {
+ 0xB9, 0x0C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd87[] = {
+ 0xBA, 0x3C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd88[] = {
+ 0xBB, 0x6C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd89[] = {
+ 0xBC, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd90[] = {
+ 0xBD, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd91[] = {
+ 0xBE, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd92[] = {
+ 0xBF, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd93[] = {
+ 0xC0, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd94[] = {
+ 0xC1, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd95[] = {
+ 0xC2, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd96[] = {
+ 0xC3, 0x15, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd97[] = {
+ 0xC4, 0xAA, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd98[] = {
+ 0xC5, 0xAF, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd99[] = {
+ 0xC6, 0x03, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd100[] = {
+ 0xC7, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd101[] = {
+ 0xC8, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd102[] = {
+ 0xC9, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd103[] = {
+ 0xCA, 0xAC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd104[] = {
+ 0xCB, 0xDC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd105[] = {
+ 0xCC, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd106[] = {
+ 0xCD, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd107[] = {
+ 0xCE, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd108[] = {
+ 0xCF, 0x0C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd109[] = {
+ 0xD0, 0x3C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd110[] = {
+ 0xD1, 0x6C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd111[] = {
+ 0xD2, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd112[] = {
+ 0xD3, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd113[] = {
+ 0xD4, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd114[] = {
+ 0xD5, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd115[] = {
+ 0xD6, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd116[] = {
+ 0xD7, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd117[] = {
+ 0xD8, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd118[] = {
+ 0xD9, 0x15, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd119[] = {
+ 0xDA, 0xAA, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd120[] = {
+ 0xDB, 0xAF, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd121[] = {
+ 0xDC, 0x03, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd122[] = {
+ 0xDD, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd123[] = {
+ 0xDE, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd124[] = {
+ 0xDF, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd125[] = {
+ 0xE0, 0xAC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd126[] = {
+ 0xE1, 0xDC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd127[] = {
+ 0xE2, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd128[] = {
+ 0xE3, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd129[] = {
+ 0xE4, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd130[] = {
+ 0xE5, 0x0C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd131[] = {
+ 0xE6, 0x3C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd132[] = {
+ 0xE7, 0x6C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd133[] = {
+ 0xE8, 0x9C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd134[] = {
+ 0xE9, 0xCC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd135[] = {
+ 0xEA, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd136[] = {
+ 0xEB, 0x2C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd137[] = {
+ 0xEC, 0x5C, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd138[] = {
+ 0xED, 0xFC, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd139[] = {
+ 0xEE, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd140[] = {
+ 0xEF, 0x15, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd141[] = {
+ 0xF0, 0xAA, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd142[] = {
+ 0xF1, 0xAF, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd143[] = {
+ 0xF2, 0x03, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd144[] = {
+ 0xB0, 0x03, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd145[] = {
+ 0xC0, 0x40, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd146[] = {
+ 0xC1, 0x10, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd147[] = {
+ 0xC4, 0x2F, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd148[] = {
+ 0xC5, 0x9E, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd149[] = {
+ 0xC8, 0x41, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd150[] = {
+ 0xC9, 0x61, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd151[] = {
+ 0xCA, 0x01, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd152[] = {
+ 0xCB, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd153[] = {
+ 0xDC, 0x01, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd154[] = {
+ 0xDD, 0x07, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd155[] = {
+ 0xDE, 0x05, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd156[] = {
+ 0xDF, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd157[] = {
+ 0xE0, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd158[] = {
+ 0xE1, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd159[] = {
+ 0xE2, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd160[] = {
+ 0xE3, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd161[] = {
+ 0xE4, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd162[] = {
+ 0xE5, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd163[] = {
+ 0xE6, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd164[] = {
+ 0xE7, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd165[] = {
+ 0xE8, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd166[] = {
+ 0xE9, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd167[] = {
+ 0xEA, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd168[] = {
+ 0xEB, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd169[] = {
+ 0xEC, 0x02, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd170[] = {
+ 0xED, 0x08, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd171[] = {
+ 0xEE, 0x06, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd172[] = {
+ 0xEF, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd173[] = {
+ 0xF0, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd174[] = {
+ 0xF1, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd175[] = {
+ 0xF2, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd176[] = {
+ 0xF3, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd177[] = {
+ 0xF4, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd178[] = {
+ 0xF5, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd179[] = {
+ 0xF6, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd180[] = {
+ 0xF7, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd181[] = {
+ 0xF8, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd182[] = {
+ 0xF9, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd183[] = {
+ 0xFA, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd184[] = {
+ 0xFB, 0x00, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd185[] = {
+ 0xB0, 0x05, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd186[] = {
+ 0xB3, 0x52, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd187[] = {
+ 0xB0, 0x06, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd188[] = {
+ 0xB8, 0xA5, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd189[] = {
+ 0xC0, 0xA5, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd190[] = {
+ 0xC7, 0x1F, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd191[] = {
+ 0xCE, 0x4F, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd192[] = {
+ 0xB8, 0x5A, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd193[] = {
+ 0xC0, 0x5A, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd194[] = {
+ 0xB0, 0x03, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd195[] = {
+ 0xB2, 0xA5, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd196[] = {
+ 0xB3, 0x04, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd197[] = {
+ 0xB0, 0x0F, 0x15, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd198[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char hx8279a_wsvga_video_on_cmd199[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8279a_wsvga_video_on_command[] = {
+ {0x4, hx8279a_wsvga_video_on_cmd0, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd1, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd2, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd3, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd4, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd5, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd6, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd7, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd8, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd9, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd10, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd11, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd12, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd13, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd14, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd15, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd16, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd17, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd18, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd19, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd20, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd21, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd22, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd23, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd24, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd25, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd26, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd27, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd28, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd29, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd30, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd31, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd32, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd33, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd34, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd35, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd36, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd37, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd38, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd39, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd40, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd41, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd42, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd43, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd44, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd45, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd46, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd47, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd48, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd49, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd50, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd51, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd52, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd53, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd54, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd55, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd56, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd57, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd58, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd59, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd60, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd61, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd62, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd63, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd64, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd65, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd66, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd67, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd68, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd69, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd70, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd71, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd72, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd73, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd74, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd75, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd76, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd77, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd78, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd79, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd80, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd81, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd82, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd83, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd84, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd85, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd86, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd87, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd88, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd89, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd90, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd91, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd92, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd93, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd94, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd95, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd96, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd97, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd98, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd99, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd100, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd101, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd102, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd103, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd104, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd105, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd106, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd107, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd108, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd109, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd110, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd111, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd112, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd113, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd114, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd115, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd116, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd117, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd118, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd119, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd120, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd121, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd122, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd123, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd124, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd125, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd126, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd127, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd128, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd129, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd130, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd131, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd132, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd133, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd134, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd135, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd136, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd137, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd138, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd139, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd140, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd141, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd142, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd143, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd144, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd145, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd146, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd147, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd148, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd149, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd150, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd151, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd152, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd153, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd154, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd155, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd156, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd157, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd158, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd159, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd160, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd161, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd162, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd163, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd164, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd165, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd166, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd167, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd168, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd169, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd170, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd171, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd172, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd173, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd174, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd175, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd176, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd177, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd178, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd179, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd180, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd181, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd182, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd183, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd184, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd185, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd186, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd187, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd188, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd189, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd190, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd191, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd192, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd193, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd194, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd195, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd196, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd197, 0x00},
+ {0x4, hx8279a_wsvga_video_on_cmd198, 0xc8},
+ {0x4, hx8279a_wsvga_video_on_cmd199, 0x23}
+};
+
+#define HX8279A_WSVGA_VIDEO_ON_COMMAND 200
+
+
+static char hx8279a_wsvga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char hx8279a_wsvga_videooff_cmd1[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xC3, 0x40, 0x00, 0x20,
+};
+
+static char hx8279a_wsvga_videooff_cmd2[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8279a_wsvga_video_off_command[] = {
+ {0x4, hx8279a_wsvga_videooff_cmd0, 0x32},
+ {0x8, hx8279a_wsvga_videooff_cmd1, 0x00},
+ {0x4, hx8279a_wsvga_videooff_cmd2, 0x96}
+};
+
+#define HX8279A_WSVGA_VIDEO_OFF_COMMAND 3
+
+
+static struct command_state hx8279a_wsvga_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info hx8279a_wsvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info hx8279a_wsvga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 0, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration hx8279a_wsvga_video_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t hx8279a_wsvga_video_timings[] = {
+ 0x39, 0x10, 0x0A, 0x00, 0x30, 0x32, 0x0E, 0x14, 0x0D, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing hx8279a_wsvga_video_timing_info = {
+ 0, 4, 0x1E, 0x38
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence hx8279a_wsvga_video_reset_seq = {
+ {1, 0, 1, }, {1, 50, 100, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight hx8279a_wsvga_video_backlight = {
+ 0, 1, 255, 2, 0, "PMIC_8941"
+};
+
+#endif /*_PANEL_HX8279A_WSVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_hx8379a_fwvga_skua_video.h b/dev/gcdb/display/include/panel_hx8379a_fwvga_skua_video.h
index f4b5ff5..160a2a2 100644
--- a/dev/gcdb/display/include/panel_hx8379a_fwvga_skua_video.h
+++ b/dev/gcdb/display/include/panel_hx8379a_fwvga_skua_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -208,7 +208,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8379a_fwvga_skua_video_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
index b11b9b4..7b43162 100755
--- a/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -206,7 +206,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8379a_fwvga_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h
new file mode 100755
index 0000000..e96f540
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h
@@ -0,0 +1,148 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_HX8379A_TRULY_FWVGA_VIDEO_H_
+#define _PANEL_HX8379A_TRULY_FWVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config hx8379a_truly_fwvga_video_panel_data = {
+ "qcom,mdss_dsi_hx8379a_truly_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ""
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8379a_truly_fwvga_video_panel_res = {
+ 480, 854, 100, 94, 40, 0, 6, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8379a_truly_fwvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char hx8379a_truly_fwvga_video_on_cmd0[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char hx8379a_truly_fwvga_video_on_cmd1[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379a_truly_fwvga_video_on_command[] = {
+ {0x4, hx8379a_truly_fwvga_video_on_cmd0, 0x96},
+ {0x4, hx8379a_truly_fwvga_video_on_cmd1, 0x78},
+};
+
+#define HX8379A_TRULY_FWVGA_VIDEO_ON_COMMAND 2
+
+static char hx8379a_truly_fwvga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char hx8379a_truly_fwvga_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379a_truly_fwvga_video_off_command[] = {
+ {0x4, hx8379a_truly_fwvga_videooff_cmd0, 0x32},
+ {0x4, hx8379a_truly_fwvga_videooff_cmd1, 0x78}
+};
+
+#define HX8379A_TRULY_FWVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state hx8379a_truly_fwvga_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info hx8379a_truly_fwvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info hx8379a_truly_fwvga_video_video_panel = {
+ 0, 0, 0, 0, 1, 1, DSI_NON_BURST_SYNCH_EVENT, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration hx8379a_truly_fwvga_video_lane_config = {
+ 2, 0, 1, 1, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t hx8379a_truly_fwvga_video_timings[] = {
+ 0x8B, 0x1f, 0x14, 0x00, 0x45, 0x4A, 0x19, 0x23, 0x23, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing hx8379a_truly_fwvga_video_timing_info = {
+ 0, 4, 0x04, 0x1d
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence hx8379a_truly_fwvga_video_reset_seq = {
+ {1, 0, 1, }, {20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight hx8379a_truly_fwvga_video_backlight = {
+ BL_PWM, 1, 255, 0, 2, 0
+};
+
+#endif /*_PANEL_HX8379A_TRULY_FWVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_hx8379a_wvga_video.h b/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
index ff6133d..12db690 100644
--- a/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
+++ b/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -243,7 +243,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8379a_wvga_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h
new file mode 100644
index 0000000..d261148
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h
@@ -0,0 +1,259 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are
+* met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above
+* copyright notice, this list of conditions and the following
+* disclaimer in the documentation and/or other materials provided
+* with the distribution.
+* * Neither the name of The Linux Foundation nor the names of its
+* contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _PANEL_HX8379C_FWVGA_VIDEO_H_
+#define _PANEL_HX8379C_FWVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config hx8379c_fwvga_video_panel_data = {
+ "qcom,mdss_dsi_hx8379c_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 1, 7000, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8379c_fwvga_video_panel_res = {
+ 480, 854, 60, 60, 60, 0, 6, 6, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8379c_fwvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char hx8379c_fwvga_video_on_cmd0[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB9, 0xFF, 0x83, 0x79,
+};
+
+static char hx8379c_fwvga_video_on_cmd1[] = {
+ 0x11, 0x00, 0x39, 0xC0,
+ 0xB1, 0x44, 0x1C, 0x1C,
+ 0x31, 0x31, 0x50, 0xD0,
+ 0xEE, 0x54, 0x80, 0x38,
+ 0x38, 0xF8, 0x32, 0x22,
+ 0x22, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd2[] = {
+ 0x0A, 0x00, 0x39, 0xC0,
+ 0xB2, 0x80, 0xFE, 0x0B,
+ 0x04, 0x00, 0x50, 0x11,
+ 0x42, 0x1D, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd3[] = {
+ 0x0B, 0x00, 0x39, 0xC0,
+ 0xB4, 0x69, 0x6A, 0x69,
+ 0x6A, 0x69, 0x6A, 0x22,
+ 0x70, 0x23, 0x70, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd4[] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0xC7, 0x00, 0x00, 0x00,
+ 0xC0, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd5[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xCC, 0x02, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd6[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xD2, 0x77, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd7[] = {
+ 0x1E, 0x00, 0x39, 0xC0,
+ 0xD3, 0x00, 0x07, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x32, 0x10, 0x03, 0x00,
+ 0x03, 0x03, 0x60, 0x03,
+ 0x60, 0x00, 0x08, 0x00,
+ 0x08, 0x45, 0x44, 0x08,
+ 0x08, 0x37, 0x08, 0x08,
+ 0x37, 0x09, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd8[] = {
+ 0x23, 0x00, 0x39, 0xC0,
+ 0xD5, 0x18, 0x18, 0x19,
+ 0x19, 0x18, 0x18, 0x20,
+ 0x21, 0x24, 0x25, 0x18,
+ 0x18, 0x18, 0x18, 0x00,
+ 0x01, 0x04, 0x05, 0x02,
+ 0x03, 0x06, 0x07, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x00, 0x00, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd9[] = {
+ 0x21, 0x00, 0x39, 0xC0,
+ 0xD6, 0x18, 0x18, 0x18,
+ 0x18, 0x19, 0x19, 0x25,
+ 0x24, 0x21, 0x20, 0x18,
+ 0x18, 0x18, 0x18, 0x05,
+ 0x04, 0x01, 0x00, 0x03,
+ 0x02, 0x07, 0x06, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd10[] = {
+ 0x2B, 0x00, 0x39, 0xC0,
+ 0xE0, 0x00, 0x04, 0x0B,
+ 0x2F, 0x39, 0x3F, 0x21,
+ 0x46, 0x07, 0x0A, 0x0C,
+ 0x17, 0x0F, 0x13, 0x16,
+ 0x14, 0x15, 0x07, 0x11,
+ 0x13, 0x30, 0x00, 0x04,
+ 0x0B, 0x2F, 0x3A, 0x3F,
+ 0x21, 0x46, 0x07, 0x0A,
+ 0x0C, 0x17, 0x0F, 0x14,
+ 0x16, 0x14, 0x15, 0x07,
+ 0x11, 0x13, 0x16, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd11[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xB6, 0x4E, 0x4E, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd12[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char hx8379c_fwvga_video_on_cmd13[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379c_fwvga_video_on_command[] = {
+ {0x8, hx8379c_fwvga_video_on_cmd0, 0x00},
+ {0x18, hx8379c_fwvga_video_on_cmd1, 0x00},
+ {0x10, hx8379c_fwvga_video_on_cmd2, 0x00},
+ {0x10, hx8379c_fwvga_video_on_cmd3, 0x00},
+ {0xc, hx8379c_fwvga_video_on_cmd4, 0x00},
+ {0x8, hx8379c_fwvga_video_on_cmd5, 0x00},
+ {0x8, hx8379c_fwvga_video_on_cmd6, 0x00},
+ {0x24, hx8379c_fwvga_video_on_cmd7, 0x00},
+ {0x28, hx8379c_fwvga_video_on_cmd8, 0x00},
+ {0x28, hx8379c_fwvga_video_on_cmd9, 0x00},
+ {0x30, hx8379c_fwvga_video_on_cmd10, 0x00},
+ {0x8, hx8379c_fwvga_video_on_cmd11, 0x00},
+ {0x4, hx8379c_fwvga_video_on_cmd12, 0x78},
+ {0x4, hx8379c_fwvga_video_on_cmd13, 0x14}
+};
+
+#define HX8379C_FWVGA_VIDEO_ON_COMMAND 14
+
+
+static char hx8379c_fwvga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char hx8379c_fwvga_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379c_fwvga_video_off_command[] = {
+ {0x4, hx8379c_fwvga_videooff_cmd0, 0x32},
+ {0x4, hx8379c_fwvga_videooff_cmd1, 0x78}
+};
+
+#define HX8379C_FWVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state hx8379c_fwvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info hx8379c_fwvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info hx8379c_fwvga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration hx8379c_fwvga_video_lane_config = {
+ 2, 0, 1, 1, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t hx8379c_fwvga_video_timings[] = {
+ 0x7B, 0x21, 0x1A, 0x00, 0x31, 0x2D, 0x1E, 0x23, 0x2B, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing hx8379c_fwvga_video_timing_info = {
+ 0, 4, 0x20, 0x2c
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence hx8379c_fwvga_video_reset_seq = {
+ {1, 0, 1, }, {20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight hx8379c_fwvga_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define HX8379C_FWVGA_VIDEO_SIGNATURE 0xFFFF
+
+#endif /*_PANEL_HX8379A_FWVGA_SKUA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_hx8389b_qhd_video.h b/dev/gcdb/display/include/panel_hx8389b_qhd_video.h
index 577918d..db6bfa0 100755
--- a/dev/gcdb/display/include/panel_hx8389b_qhd_video.h
+++ b/dev/gcdb/display/include/panel_hx8389b_qhd_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -255,7 +255,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8389b_qhd_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8394a_720p_video.h b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
index 2bf8c69..32bb066 100644
--- a/dev/gcdb/display/include/panel_hx8394a_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -242,7 +242,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8394a_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_hx8394d_720p_video.h b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
index 3db296d..3ab32f8 100644
--- a/dev/gcdb/display/include/panel_hx8394d_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -248,7 +248,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8394d_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_hx8394d_qhd_video.h b/dev/gcdb/display/include/panel_hx8394d_qhd_video.h
new file mode 100644
index 0000000..c04fccb
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8394d_qhd_video.h
@@ -0,0 +1,285 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_HX8394D_QHD_VIDEO_H_
+
+#define _PANEL_HX8394D_QHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config hx8394d_qhd_video_panel_data = {
+ "qcom,mdss_dsi_hx8394d_qhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8394d_qhd_video_panel_res = {
+ 540, 960, 52, 100, 24, 0, 8, 20, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8394d_qhd_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char hx8394d_qhd_video_on_cmd0[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xb9, 0xff, 0x83, 0x94,
+};
+
+
+static char hx8394d_qhd_video_on_cmd1[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xba, 0x33, 0x83, 0xFF,
+};
+
+static char hx8394d_qhd_video_on_cmd2[] = {
+ 0x10, 0x00, 0x39, 0xC0,
+ 0xb1, 0x6c, 0x12, 0x12,
+ 0x37, 0x04, 0x11, 0xf1,
+ 0x80, 0xec, 0x94, 0x23,
+ 0x80, 0xc0, 0xd2, 0x18,
+};
+
+
+static char hx8394d_qhd_video_on_cmd3[] = {
+ 0x0c, 0x00, 0x39, 0xC0,
+ 0xb2, 0x00, 0x64, 0x0e,
+ 0x0d, 0x32, 0x23, 0x08,
+ 0x08, 0x1c, 0x4d, 0x00,
+};
+
+
+static char hx8394d_qhd_video_on_cmd4[] = {
+ 0x0d, 0x00, 0x39, 0xC0,
+ 0xb4, 0x00, 0xff, 0x03,
+ 0x50, 0x03, 0x50, 0x03,
+ 0x50, 0x01, 0x6a, 0x01,
+ 0x6a, 0xFF, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd5[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xbc, 0x07, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd6[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xbf, 0x41, 0x0e, 0x01,
+};
+
+
+static char hx8394d_qhd_video_on_cmd7[] = {
+ 0x1f, 0x00, 0x39, 0xC0,
+ 0xd3, 0x00, 0x07, 0x00,
+ 0x00, 0x00, 0x10, 0x00,
+ 0x32, 0x10, 0x05, 0x00,
+ 0x00, 0x32, 0x10, 0x00,
+ 0x00, 0x00, 0x32, 0x10,
+ 0x00, 0x00, 0x00, 0x36,
+ 0x03, 0x09, 0x09, 0x37,
+ 0x00, 0x00, 0x37, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd8[] = {
+ 0x2d, 0x00, 0x39, 0xC0,
+ 0xd5, 0x02, 0x03, 0x00,
+ 0x01, 0x06, 0x07, 0x04,
+ 0x05, 0x20, 0x21, 0x22,
+ 0x23, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x24,
+ 0x25, 0x18, 0x18, 0x19,
+ 0x19, 0xFF, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd9[] = {
+ 0x2d, 0x00, 0x39, 0xC0,
+ 0xd6, 0x05, 0x04, 0x07,
+ 0x06, 0x01, 0x00, 0x03,
+ 0x02, 0x23, 0x22, 0x21,
+ 0x20, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x58,
+ 0x58, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x25,
+ 0x24, 0x19, 0x19, 0x18,
+ 0x18, 0xFF, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd10[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xcc, 0x09, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd11[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xc0, 0x30, 0x14, 0xFF,
+};
+
+static char hx8394d_qhd_video_on_cmd12[] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0xc7, 0x00, 0xc0, 0x40,
+ 0xc0, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8394d_qhd_video_on_cmd13[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xb6, 0x43, 0x43, 0xFF,
+};
+
+static char hx8394d_qhd_video_on_cmd14[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char hx8394d_qhd_video_on_cmd15[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8394d_qhd_video_on_command[] = {
+ { 0x8 , hx8394d_qhd_video_on_cmd0, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd1, 0x00},
+ { 0x14 , hx8394d_qhd_video_on_cmd2, 0x00},
+ { 0x10 , hx8394d_qhd_video_on_cmd3, 0x00},
+ { 0x14 , hx8394d_qhd_video_on_cmd4, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd5, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd6, 0x00},
+ { 0x24 , hx8394d_qhd_video_on_cmd7, 0x00},
+ { 0x34 , hx8394d_qhd_video_on_cmd8, 0x00},
+ { 0x34 , hx8394d_qhd_video_on_cmd9, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd10, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd11, 0x00},
+ { 0xc , hx8394d_qhd_video_on_cmd12, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd13, 0x00},
+ { 0x4 , hx8394d_qhd_video_on_cmd14, 0xc8},
+ { 0x4 , hx8394d_qhd_video_on_cmd15, 0x0a}
+};
+#define HX8394D_QHD_VIDEO_ON_COMMAND 16
+
+static char hx8394d_qhd_video_off_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char hx8394d_qhd_video_off_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8394d_qhd_video_off_command[] = {
+ {0x4, hx8394d_qhd_video_off_cmd0, 0x32},
+ {0x4, hx8394d_qhd_video_off_cmd1, 0x78}
+};
+
+#define HX8394D_QHD_VIDEO_OFF_COMMAND 2
+
+static struct command_state hx8394d_qhd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info hx8394d_qhd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info hx8394d_qhd_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration hx8394d_qhd_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t hx8394d_qhd_video_timings[] = {
+ 0x79, 0x1a, 0x12, 0x00, 0x3e, 0x42, 0x16, 0x1e, 0x15, 0x03, 0x04, 0x00
+};
+
+static struct mipi_dsi_cmd hx8394d_qhd_video_rotation[] = {
+
+};
+#define HX8394D_QHD_VIDEO_ROTATION 0
+
+
+static struct panel_timing hx8394d_qhd_video_timing_info = {
+ 0, 4, 0x04, 0x1b
+};
+
+static struct panel_reset_sequence hx8394d_qhd_video_panel_reset_seq = {
+{
+ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight hx8394d_qhd_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define HX8394D_QHD_VIDEO_SIGNATURE 0xFFFF
+
+#endif /*_HX8394D_QHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_ili9806e_fwvga_video.h b/dev/gcdb/display/include/panel_ili9806e_fwvga_video.h
new file mode 100644
index 0000000..c4941c5
--- /dev/null
+++ b/dev/gcdb/display/include/panel_ili9806e_fwvga_video.h
@@ -0,0 +1,814 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are
+* met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above
+* copyright notice, this list of conditions and the following
+* disclaimer in the documentation and/or other materials provided
+* with the distribution.
+* * Neither the name of The Linux Foundation nor the names of its
+* contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_ILI9806E_FWVGA_VIDEO_H_
+#define _PANEL_ILI9806E_FWVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config ili9806e_fwvga_video_panel_data = {
+ "qcom,mdss_dsi_ili9806e_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution ili9806e_fwvga_video_panel_res = {
+ 480, 854, 54, 100, 36, 0, 8, 20, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info ili9806e_fwvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char ili9806e_fwvga_video_on_cmd0[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xFF, 0xFF, 0x98, 0x06,
+ 0x04, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd1[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x08, 0x10, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd2[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x21, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd3[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x30, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd4[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x31, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd5[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x40, 0x16, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd6[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x41, 0x33, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd7[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x42, 0x03, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd8[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x43, 0x89, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd9[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x44, 0x06, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd10[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x50, 0x80, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd11[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x51, 0x80, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd12[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x52, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd13[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x53, 0x43, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd14[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x60, 0x07, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd15[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x61, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd16[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x62, 0x07, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd17[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x63, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd18[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA0, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd19[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA1, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd20[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA2, 0x0A, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd21[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA3, 0x10, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd22[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA4, 0x0B, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd23[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA5, 0x1C, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd24[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA6, 0x0B, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd25[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA7, 0x09, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd26[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA8, 0x05, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd27[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xA9, 0x0B, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd28[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xAA, 0x07, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd29[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xAB, 0x06, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd30[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xAC, 0x0E, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd31[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xAD, 0x29, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd32[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xAE, 0x25, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd33[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xAF, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd34[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC0, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd35[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC1, 0x02, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd36[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC2, 0x07, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd37[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC3, 0x0C, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd38[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC4, 0x06, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd39[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC5, 0x18, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd40[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC6, 0x0B, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd41[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC7, 0x0A, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd42[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC8, 0x02, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd43[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC9, 0x06, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd44[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xCA, 0x03, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd45[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xCB, 0x03, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd46[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xCC, 0x0B, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd47[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xCD, 0x2A, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd48[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xCE, 0x25, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd49[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xCF, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd50[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xFF, 0xFF, 0x98, 0x06,
+ 0x04, 0x06, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd51[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x00, 0x20, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd52[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x01, 0x0A, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd53[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x02, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd54[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x03, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd55[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x04, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd56[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x05, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd57[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x06, 0x98, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd58[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x07, 0x06, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd59[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x08, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd60[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x09, 0x80, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd61[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x0A, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd62[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x0B, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd63[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x0C, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd64[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x0D, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd65[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x0E, 0x05, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd66[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x0F, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd67[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x10, 0xF0, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd68[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x11, 0xF4, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd69[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x12, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd70[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x13, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd71[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x14, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd72[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x15, 0xC0, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd73[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x16, 0x08, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd74[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x17, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd75[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x18, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd76[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x19, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd77[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x1A, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd78[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x1B, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd79[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x1C, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd80[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x1D, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd81[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x20, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd82[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x21, 0x23, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd83[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x22, 0x45, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd84[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x23, 0x67, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd85[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x24, 0x01, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd86[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x25, 0x23, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd87[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x26, 0x45, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd88[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x27, 0x67, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd89[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x30, 0x11, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd90[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x31, 0x11, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd91[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x32, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd92[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x33, 0xEE, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd93[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x34, 0xFF, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd94[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x35, 0xBB, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd95[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x36, 0xAA, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd96[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x37, 0xDD, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd97[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x38, 0xCC, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd98[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x39, 0x66, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd99[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x3A, 0x77, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd100[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x3B, 0x22, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd101[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x3C, 0x22, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd102[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x3D, 0x22, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd103[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x3E, 0x22, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd104[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x3F, 0x22, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd105[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x40, 0x22, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd106[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xFF, 0xFF, 0x98, 0x06,
+ 0x04, 0x07, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd107[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x17, 0x22, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd108[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x02, 0x77, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd109[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xFF, 0xFF, 0x98, 0x06,
+ 0x04, 0x00, 0xFF, 0xFF,
+};
+
+static char ili9806e_fwvga_video_on_cmd110[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char ili9806e_fwvga_video_on_cmd111[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd ili9806e_fwvga_video_on_command[] = {
+ {0xc, ili9806e_fwvga_video_on_cmd0, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd1, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd2, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd3, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd4, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd5, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd6, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd7, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd8, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd9, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd10, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd11, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd12, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd13, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd14, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd15, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd16, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd17, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd18, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd19, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd20, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd21, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd22, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd23, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd24, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd25, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd26, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd27, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd28, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd29, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd30, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd31, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd32, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd33, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd34, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd35, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd36, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd37, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd38, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd39, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd40, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd41, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd42, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd43, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd44, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd45, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd46, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd47, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd48, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd49, 0x00},
+ {0xc, ili9806e_fwvga_video_on_cmd50, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd51, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd52, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd53, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd54, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd55, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd56, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd57, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd58, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd59, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd60, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd61, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd62, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd63, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd64, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd65, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd66, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd67, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd68, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd69, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd70, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd71, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd72, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd73, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd74, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd75, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd76, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd77, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd78, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd79, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd80, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd81, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd82, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd83, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd84, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd85, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd86, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd87, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd88, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd89, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd90, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd91, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd92, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd93, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd94, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd95, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd96, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd97, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd98, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd99, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd100, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd101, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd102, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd103, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd104, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd105, 0x00},
+ {0xc, ili9806e_fwvga_video_on_cmd106, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd107, 0x00},
+ {0x8, ili9806e_fwvga_video_on_cmd108, 0x00},
+ {0xc, ili9806e_fwvga_video_on_cmd109, 0x00},
+ {0x4, ili9806e_fwvga_video_on_cmd110, 0x96},
+ {0x4, ili9806e_fwvga_video_on_cmd111, 0x78}
+};
+
+#define ILI9806E_FWVGA_VIDEO_ON_COMMAND 112
+
+
+static char ili9806e_fwvga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char ili9806e_fwvga_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd ili9806e_fwvga_video_off_command[] = {
+ {0x4, ili9806e_fwvga_videooff_cmd0, 0x32},
+ {0x4, ili9806e_fwvga_videooff_cmd1, 0x78}
+};
+
+#define ILI9806E_FWVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state ili9806e_fwvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info ili9806e_fwvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info ili9806e_fwvga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration ili9806e_fwvga_video_lane_config = {
+ 2, 0, 1, 1, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t ili9806e_fwvga_video_timings[] = {
+ 0x7D, 0x24, 0x19, 0x00, 0x34, 0x31, 0x1D, 0x26, 0x2A, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing ili9806e_fwvga_video_timing_info = {
+ 0, 4, 0x1F, 0x2C
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence ili9806e_fwvga_video_reset_seq = {
+ {1, 0, 1, }, {20, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight ili9806e_fwvga_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define ILI9806E_FWVGA_VIDEO_SIGNATURE 0xFFFF
+#endif /*_PANEL_ILI9806E_FWVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_innolux_720p_video.h b/dev/gcdb/display/include/panel_innolux_720p_video.h
index 8bd4680..ca50810 100644
--- a/dev/gcdb/display/include/panel_innolux_720p_video.h
+++ b/dev/gcdb/display/include/panel_innolux_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -948,7 +948,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration innolux_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_jdi_1080p_video.h b/dev/gcdb/display/include/panel_jdi_1080p_video.h
index bcee0c1..add8e55 100755
--- a/dev/gcdb/display/include/panel_jdi_1080p_video.h
+++ b/dev/gcdb/display/include/panel_jdi_1080p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -47,7 +47,7 @@
static struct panel_config jdi_1080p_video_panel_data = {
"qcom,mdss_dsi_jdi_1080p_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, ""
};
/*---------------------------------------------------------------------------*/
@@ -90,11 +90,11 @@
static struct mipi_dsi_cmd jdi_1080p_video_on_command[] = {
-{ 0x4 , jdi_1080p_video_on_cmd0},
-{ 0x4 , jdi_1080p_video_on_cmd1},
-{ 0x4 , jdi_1080p_video_on_cmd2},
-{ 0x4 , jdi_1080p_video_on_cmd3},
-{ 0x4 , jdi_1080p_video_on_cmd4}
+{ 0x4 , jdi_1080p_video_on_cmd0, 0x0},
+{ 0x4 , jdi_1080p_video_on_cmd1, 0x0},
+{ 0x4 , jdi_1080p_video_on_cmd2, 0x0},
+{ 0x4 , jdi_1080p_video_on_cmd3, 0x0},
+{ 0x4 , jdi_1080p_video_on_cmd4, 0x0}
};
#define JDI_1080P_VIDEO_ON_COMMAND 5
@@ -110,8 +110,8 @@
static struct mipi_dsi_cmd jdi_1080p_video_off_command[] = {
-{ 0x4 , jdi_1080p_videooff_cmd0},
-{ 0x4 , jdi_1080p_videooff_cmd1}
+{ 0x4 , jdi_1080p_videooff_cmd0, 0},
+{ 0x4 , jdi_1080p_videooff_cmd1, 0}
};
#define JDI_1080P_VIDEO_OFF_COMMAND 2
@@ -141,7 +141,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_1080p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
@@ -152,14 +152,6 @@
0xe7, 0x36, 0x24, 0x00, 0x66, 0x6a, 0x2a, 0x3a, 0x2d, 0x03, 0x04, 0x00
};
-
-
-static struct mipi_dsi_cmd jdi_1080p_video_rotation[] = {
-
-};
-#define JDI_1080P_VIDEO_ROTATION 0
-
-
static struct panel_timing jdi_1080p_video_timing_info = {
0x0, 0x04, 0x04, 0x1b
};
diff --git a/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h b/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h
index 5f5e5d3..8cfee8e 100644
--- a/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -82,14 +82,31 @@
0x29, 0x00, 0x05, 0x80
};
+static char jdi_4k_dualdsi_video_on_cmd_ip_0[] = {
+ 0xb0, 0x04, 0x23, 0x80
+};
+
+static char jdi_4k_dualdsi_video_on_cmd_ip_1[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xED, 0x80, 0x00, 0x34,
+ 0x5B, 0x04, 0xB0, 0xFF
+};
+
+static char jdi_4k_dualdsi_video_on_cmd_ip_2[] = {
+ 0xb0, 0x03, 0x23, 0x80
+};
+
static struct mipi_dsi_cmd jdi_4k_dualdsi_video_on_command[] = {
{0x4, jdi_4k_dualdsi_video_on_cmd0, 0x78},
{0x4, jdi_4k_dualdsi_video_on_cmd1, 0x78},
{0x4, jdi_4k_dualdsi_video_on_cmd2, 0x78},
+ {0x4, jdi_4k_dualdsi_video_on_cmd_ip_0, 0x50},
+ {0xC, jdi_4k_dualdsi_video_on_cmd_ip_1, 0x0a},
+ {0x4, jdi_4k_dualdsi_video_on_cmd_ip_2, 0x50},
{0x4, jdi_4k_dualdsi_video_on_cmd3, 0x78}
};
-#define JDI_4K_DUALDSI_VIDEO_ON_COMMAND 4
+#define JDI_4K_DUALDSI_VIDEO_ON_COMMAND 7
static char jdi_4k_dualdsi_videooff_cmd0[] = {
@@ -130,7 +147,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_4k_dualdsi_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
@@ -159,7 +176,7 @@
};
static struct fb_compression jdi_4k_dualdsi_video_fbc = {
- 1, 2, 1, 1, 2, 1, 1, 1, 1200, 5, 91, 0x200, 192, 4, 3
+ 1, 2, 1, 1, 2, 1, 1, 1, 1200, 5, 91, 0x200, 192, 4, 3, 0, 0, 0
};
#endif /*_PANEL_JDI_4K_DUALDSI_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_jdi_a216_fhd_video.h b/dev/gcdb/display/include/panel_jdi_a216_fhd_video.h
new file mode 100755
index 0000000..6f09f38
--- /dev/null
+++ b/dev/gcdb/display/include/panel_jdi_a216_fhd_video.h
@@ -0,0 +1,165 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_JDI_A216_FHD_VIDEO_H_
+#define _PANEL_JDI_A216_FHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config jdi_a216_fhd_video_panel_data = {
+ "qcom,mdss_dsi_jdi_a216_fhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution jdi_a216_fhd_video_panel_res = {
+ 1080, 1920, 32, 20, 12, 0, 4, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info jdi_a216_fhd_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char jdi_a216_fhd_video_on_cmd0[] = {
+ 0x51, 0xFF, 0x15, 0x80
+};
+
+static char jdi_a216_fhd_video_on_cmd1[] = {
+ 0x53, 0x0C, 0x15, 0x80
+};
+
+static char jdi_a216_fhd_video_on_cmd2[] = {
+ 0x55, 0x00, 0x15, 0x80
+};
+
+static char jdi_a216_fhd_video_on_cmd3[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static char jdi_a216_fhd_video_on_cmd4[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_a216_fhd_video_on_command[] = {
+ {0x4, jdi_a216_fhd_video_on_cmd0, 0x0a},
+ {0x4, jdi_a216_fhd_video_on_cmd1, 0x0a},
+ {0x4, jdi_a216_fhd_video_on_cmd2, 0x0a},
+ {0x4, jdi_a216_fhd_video_on_cmd3, 0x28},
+ {0x4, jdi_a216_fhd_video_on_cmd4, 0xc8},
+};
+
+#define JDI_A216_FHD_VIDEO_ON_COMMAND 5
+
+
+static char jdi_a216_fhd_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char jdi_a216_fhd_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_a216_fhd_video_off_command[] = {
+ {0x4, jdi_a216_fhd_videooff_cmd0, 0x32},
+ {0x4, jdi_a216_fhd_videooff_cmd1, 0x78}
+};
+
+#define JDI_A216_FHD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state jdi_a216_fhd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info jdi_a216_fhd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info jdi_a216_fhd_video_video_panel = {
+ 0, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration jdi_a216_fhd_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t jdi_a216_fhd_video_timings[] = {
+ 0xce, 0x2e, 0x1e, 0x00, 0x5a, 0x5c, 0x24, 0x30, 0x24, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing jdi_a216_fhd_video_timing_info = {
+ 0x0, 0x04, 0x0a, 0x2c
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence jdi_a216_fhd_video_reset_seq = {
+ {1, 0, 1, }, {20, 200, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight jdi_a216_fhd_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#endif /*_PANEL_JDI_A216_FHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_jdi_fhd_video.h b/dev/gcdb/display/include/panel_jdi_fhd_video.h
index 95522dd..9405223 100644
--- a/dev/gcdb/display/include/panel_jdi_fhd_video.h
+++ b/dev/gcdb/display/include/panel_jdi_fhd_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,7 +45,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config jdi_fhd_video_panel_data = {
"qcom,mdss_dsi_jdi_fhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0
};
/*---------------------------------------------------------------------------*/
@@ -118,11 +118,11 @@
};
static char jdi_fhd_video_on_cmd13[] = {
- 0x11, 0xFF, 0x05, 0x80
+ 0x11, 0x00, 0x05, 0x80
};
static char jdi_fhd_video_on_cmd14[] = {
- 0x29, 0xFF, 0x05, 0x80
+ 0x29, 0x00, 0x05, 0x80
};
static struct mipi_dsi_cmd jdi_fhd_video_on_command[] = {
@@ -184,7 +184,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_fhd_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h
index 31b18f5..a0686d3 100644
--- a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h
+++ b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -185,7 +185,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_qhd_dualdsi_cmd_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h
index bd5ae6d..79acd3f 100644
--- a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -196,7 +196,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_qhd_dualdsi_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35521_720p_video.h b/dev/gcdb/display/include/panel_nt35521_720p_video.h
index c5f9069..810fb6a 100644
--- a/dev/gcdb/display/include/panel_nt35521_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35521_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -1443,7 +1443,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35521_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_nt35521_wxga_video.h b/dev/gcdb/display/include/panel_nt35521_wxga_video.h
index bdac711..2195176 100644
--- a/dev/gcdb/display/include/panel_nt35521_wxga_video.h
+++ b/dev/gcdb/display/include/panel_nt35521_wxga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -1002,7 +1002,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35521_wxga_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
index 72f5a18..6894e96 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -2900,7 +2900,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35590_720p_cmd_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_video.h b/dev/gcdb/display/include/panel_nt35590_720p_video.h
index b935482..b812ef0 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -2913,7 +2913,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35590_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_nt35590_qvga_cmd.h b/dev/gcdb/display/include/panel_nt35590_qvga_cmd.h
index 2a8b91f..a6854f8 100644
--- a/dev/gcdb/display/include/panel_nt35590_qvga_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35590_qvga_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -2907,7 +2907,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35590_qvga_cmd_lane_config = {
- 1, 0, 1, 0, 0, 0
+ 1, 0, 1, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
index 2cd3d07..b514c96 100644
--- a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
+++ b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -2988,7 +2988,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35596_1080p_skuk_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 1
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35596_1080p_video.h b/dev/gcdb/display/include/panel_nt35596_1080p_video.h
index 0c32667..57f6b4c 100644
--- a/dev/gcdb/display/include/panel_nt35596_1080p_video.h
+++ b/dev/gcdb/display/include/panel_nt35596_1080p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -3236,7 +3236,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35596_1080p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h b/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
new file mode 100644
index 0000000..6e957be
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
@@ -0,0 +1,261 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_NT35597_WQXGA_CMD_H_
+#define _PANEL_NT35597_WQXGA_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config nt35597_wqxga_cmd_panel_data = {
+ "qcom,dsi_nt35597_wqxga_cmd", /* panel_node_id */
+ "dsi:0:", /* panel_controller */
+ "qcom,mdss-dsi-panel", /* panel_compatible */
+ 11, /* panel_interface */
+ 1, /* panel_type */
+ "DISPLAY_1", /* panel_destination */
+ 0, /* panel_orientation */
+ 0, /* panel_clockrate */
+ 60, /* panel_framerate */
+ 0, /* panel_channelid */
+ 0, /* dsi_virtualchannel_id */
+ 0, /* panel_broadcast_mode */
+ 0, /* panel_lp11_init */
+ 0, /* panel_init_delay */
+ 0, /* dsi_stream */
+ 0, /* interleave_mode */
+ 0, /* panel_bitclock_freq */
+ 0, /* panel_operating_mode */
+ 0, /* panel_with_enable_gpio */
+ 0, /* mode_gpio_state */
+ 0, /* slave_panel_node_id */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35597_wqxga_cmd_panel_res = {
+ 1440, /* panel_width */
+ 2560, /* panel_height */
+ 152, /* hfront_porch */
+ 160, /* hback_porch */
+ 12, /* hpulse_width */
+ 0, /* hsync_skew */
+ 10, /* vfront_porch */
+ 9, /* vback_porch */
+ 1, /* vpulse_width */
+ 0, /* hleft_border */
+ 0, /* hright_border */
+ 0, /* vtop_border */
+ 0, /* vbottom_border */
+ 0, /* hactive_res */
+ 0, /* uint16_t vactive_res */
+ 0, /* invert_data_polarity */
+ 0, /* invert_vsync_polarity */
+ 0, /* invert_hsync_polarity */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35597_wqxga_cmd_color = {
+ 24, /* color_format */
+ 0, /* color_order */
+ 0xff, /* underflow_color */
+ 0, /* border_color */
+ 0, /* pixel_packing */
+ 0, /* pixel_alignment */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char nt35597_wqxga_cmd_on_cmd0[] = {
+ 0xff, 0x10, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_cmd_on_cmd1[] = {
+ 0xbb, 0x10, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_cmd_on_cmd2[] = {
+ 0x06, 0x00, 0x39, 0x80,
+ 0x3b, 0x03, 0x09, 0x0a,
+ 0x98, 0xa0,
+};
+
+static char nt35597_wqxga_cmd_on_cmd3[] = {
+ 0xe5, 0x00, 0x15, 0x80
+};
+
+static char nt35597_wqxga_cmd_on_cmd4[] = {
+ 0xc0, 0x01, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_cmd_on_cmd5[] = {
+ 0xfb, 0x01, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_cmd_on_cmd6[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_cmd_on_cmd7[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_cmd_on_command[] = {
+ {0x4, nt35597_wqxga_cmd_on_cmd0, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd1, 0x00},
+ {0xA, nt35597_wqxga_cmd_on_cmd2, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd3, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd4, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd5, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd6, 0x78},
+ {0x4, nt35597_wqxga_cmd_on_cmd7, 0x78}
+};
+
+#define NT35597_WQXGA_CMD_ON_COMMAND 8
+
+
+static char nt35597_wqxga_cmdoff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_cmdoff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_cmd_off_command[] = {
+ {0x4, nt35597_wqxga_cmdoff_cmd0, 0x02},
+ {0x4, nt35597_wqxga_cmdoff_cmd1, 0x78}
+};
+
+#define NT35597_WQXGA_CMD_OFF_COMMAND 2
+
+
+static struct command_state nt35597_wqxga_cmd_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info nt35597_wqxga_cmd_command_panel = {
+ //1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0
+ 0, /* techeck_enable*/
+ 0, /* tepin_select */
+ 0, /* teusing_tepin */
+ 0, /* autorefresh_enable */
+ 0, /* autorefresh_framenumdiv */
+ 0x2c, /* tevsync_rdptr_irqline */
+ 0, /* tevsync_continue_lines */
+ 0, /* tevsync_startline_divisor */
+ 0, /* tepercent_variance */
+ 0, /* tedcs_command */
+ 0, /* disable_eotafter_hsxfer */
+ 0, /* cmdmode_idletime */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info nt35597_wqxga_cmd_video_panel = {
+ 0, /* hsync_pulse */
+ 0, /* hfp_power_mode */
+ 0, /* hbp_power_mode */
+ 0, /* hsa_power_mode */
+ 1, /* bllp_eof_power_mode */
+ 1, /* bllp_power_mode */
+ 1, /* traffic_mode */
+ 0, /* dma_delayafter_vsync */
+ 0x9, /* bllp_eof_power */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration nt35597_wqxga_cmd_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t nt35597_wqxga_cmd_timings[] = {
+ 0xC4, 0x2E, 0x20, 0x00, 0x5C, 0x5E, 0x24, 0x32, 0x24, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing nt35597_wqxga_cmd_timing_info = {
+ 0x00, /* dsi_mdp_trigger */
+ 0x04, /* dsi_dma_trigger */
+ 0x03, /* tclk_post */
+ 0x25 /* tclk_pre */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence nt35597_wqxga_cmd_reset_seq = {
+ {1, 0, 1, }, {10, 10, 10, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight nt35597_wqxga_cmd_backlight = {
+ 0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+static struct fb_compression nt35597_wqxga_cmd_fbc = {
+ 1, /* enabled */
+ 3, /* comp_ratio */
+ 1, /* comp_mode */
+ 1, /* qerr_enable */
+ 2, /* cd_bias */
+ 1, /* pat_enable */
+ 1, /* vlc_enable */
+ 1, /* bflc_enable */
+ 900, /* line_x_budget */
+ 5, /* block_x_budget */
+ 59, /* block_budget */
+ 0x200, /* lossless_mode_thd */
+ 192, /* lossy_mode_thd */
+ 4, /* lossy_rgb_thd */
+ 3, /* lossy_mode_idx */
+ 4, /* slice_height */
+ 1, /* pred_mode */
+ 2, /* max_pred_err */
+};
+
+#endif /*_PANEL_NT35597_WQXGA_CMD_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_video.h b/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
new file mode 100644
index 0000000..d2f34d8
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
@@ -0,0 +1,249 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_NT35597_WQXGA_VIDEO_H_
+#define _PANEL_NT35597_WQXGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config nt35597_wqxga_video_panel_data = {
+ "qcom,dsi_nt35597_wqxga_video", /* panel_node_id */
+ "dsi:0:", /* panel_controller */
+ "qcom,mdss-dsi-panel", /* panel_compatible */
+ 10, /* panel_interface */
+ 0, /* panel_type */
+ "DISPLAY_1", /* panel_destination */
+ 0, /* panel_orientation */
+ 0, /* panel_clockrate */
+ 60, /* panel_framerate */
+ 0, /* panel_channelid */
+ 0, /* dsi_virtualchannel_id */
+ 0, /* panel_broadcast_mode */
+ 0, /* panel_lp11_init */
+ 0, /* panel_init_delay */
+ 0, /* dsi_stream */
+ 0, /* interleave_mode */
+ 0, /* panel_bitclock_freq */
+ 0, /* panel_operating_mode */
+ 0, /* panel_with_enable_gpio */
+ 0, /* mode_gpio_state */
+ 0, /* slave_panel_node_id */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35597_wqxga_video_panel_res = {
+ 1440, /* panel_width */
+ 2560, /* panel_height */
+ 152, /* hfront_porch */
+ 160, /* hback_porch */
+ 12, /* hpulse_width */
+ 0, /* hsync_skew */
+ 10, /* vfront_porch */
+ 9, /* vback_porch */
+ 1, /* vpulse_width */
+ 0, /* hleft_border */
+ 0, /* hright_border */
+ 0, /* vtop_border */
+ 0, /* vbottom_border */
+ 0, /* hactive_res */
+ 0, /* uint16_t vactive_res */
+ 0, /* invert_data_polarity */
+ 0, /* invert_vsync_polarity */
+ 0, /* invert_hsync_polarity */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35597_wqxga_video_color = {
+ 24, /* color_format */
+ 0, /* color_order */
+ 0xff, /* underflow_color */
+ 0, /* border_color */
+ 0, /* pixel_packing */
+ 0, /* pixel_alignment */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char nt35597_wqxga_video_on_cmd0[] = {
+ 0xff, 0x10, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_video_on_cmd1[] = {
+ 0xbb, 0x03, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_video_on_cmd2[] = {
+ 0x06, 0x00, 0x39, 0x80,
+ 0x3b, 0x03, 0x09, 0x0a,
+ 0x98, 0xa0,
+};
+
+static char nt35597_wqxga_video_on_cmd3[] = {
+ 0xe5, 0x00, 0x15, 0x80
+};
+
+static char nt35597_wqxga_video_on_cmd4[] = {
+ 0xc0, 0x01, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_video_on_cmd5[] = {
+ 0xfb, 0x01, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_video_on_cmd6[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_video_on_cmd7[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_video_on_command[] = {
+ {0x4, nt35597_wqxga_video_on_cmd0, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd1, 0x00},
+ {0xA, nt35597_wqxga_video_on_cmd2, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd3, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd4, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd5, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd6, 0x78},
+ {0x4, nt35597_wqxga_video_on_cmd7, 0x78}
+};
+
+#define NT35597_WQXGA_VIDEO_ON_COMMAND 8
+
+
+static char nt35597_wqxga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_video_off_command[] = {
+ {0x4, nt35597_wqxga_videooff_cmd0, 0x02},
+ {0x4, nt35597_wqxga_videooff_cmd1, 0x78}
+};
+
+#define NT35597_WQXGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state nt35597_wqxga_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info nt35597_wqxga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info nt35597_wqxga_video_video_panel = {
+ 0, /* hsync_pulse */
+ 0, /* hfp_power_mode */
+ 0, /* hbp_power_mode */
+ 0, /* hsa_power_mode */
+ 1, /* bllp_eof_power_mode */
+ 1, /* bllp_power_mode */
+ 1, /* traffic_mode */
+ 0, /* dma_delayafter_vsync */
+ 0x9, /* bllp_eof_power */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration nt35597_wqxga_video_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t nt35597_wqxga_video_timings[] = {
+ 0xC4, 0x2E, 0x20, 0x00, 0x5C, 0x5E, 0x24, 0x32, 0x24, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing nt35597_wqxga_video_timing_info = {
+ 0x00, /* dsi_mdp_trigger */
+ 0x04, /* dsi_dma_trigger */
+ 0x03, /* tclk_post */
+ 0x25 /* tclk_pre */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence nt35597_wqxga_video_reset_seq = {
+ {1, 0, 1, }, {10, 10, 10, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight nt35597_wqxga_video_backlight = {
+ 0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+static struct fb_compression nt35597_wqxga_video_fbc = {
+ 1, /* enabled */
+ 3, /* comp_ratio */
+ 1, /* comp_mode */
+ 1, /* qerr_enable */
+ 2, /* cd_bias */
+ 1, /* pat_enable */
+ 1, /* vlc_enable */
+ 1, /* bflc_enable */
+ 900, /* line_x_budget */
+ 5, /* block_x_budget */
+ 59, /* block_budget */
+ 0x200, /* lossless_mode_thd */
+ 192, /* lossy_mode_thd */
+ 4, /* lossy_rgb_thd */
+ 3, /* lossy_mode_idx */
+ 4, /* slice_height */
+ 1, /* pred_mode */
+ 2, /* max_pred_err */
+};
+
+#endif /*_PANEL_nt35597_wqxga_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_otm1283a_720p_video.h b/dev/gcdb/display/include/panel_otm1283a_720p_video.h
index ec44928..a7b6c96 100755
--- a/dev/gcdb/display/include/panel_otm1283a_720p_video.h
+++ b/dev/gcdb/display/include/panel_otm1283a_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -930,7 +930,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration otm1283a_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h b/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
index 7fa9098..caaf38a 100755
--- a/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -652,7 +652,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration otm8018b_fwvga_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
diff --git a/dev/gcdb/display/include/panel_otm8019a_fwvga_video.h b/dev/gcdb/display/include/panel_otm8019a_fwvga_video.h
index 235057e..c88fbc3 100755
--- a/dev/gcdb/display/include/panel_otm8019a_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_otm8019a_fwvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -786,7 +786,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration otm8019a_fwvga_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_r61318_hd_video.h b/dev/gcdb/display/include/panel_r61318_hd_video.h
new file mode 100644
index 0000000..72c27c2
--- /dev/null
+++ b/dev/gcdb/display/include/panel_r61318_hd_video.h
@@ -0,0 +1,296 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_R61318_HD_VIDEO_H_
+#define _PANEL_R61318_HD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config r61318_hd_video_panel_data = {
+ "qcom,mdss_dsi_r61318_hd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution r61318_hd_video_panel_res = {
+ 720, 1280, 40, 30, 12, 0, 18, 9, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info r61318_hd_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char r61318_hd_video_on_cmd0[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd1[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB3, 0x00, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd2[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB6, 0x32, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd3[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x36, 0x0A, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd4[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xC0, 0x20, 0xB2, 0x0D,
+ 0x10, 0x02, 0x80, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd5[] = {
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xC1, 0x35, 0x85, 0x85,
+ 0x85, 0x10, 0x10, 0x33,
+
+};
+
+static char r61318_hd_video_on_cmd6[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xC3, 0x20, 0x0F, 0x00,
+
+};
+
+static char r61318_hd_video_on_cmd7[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xC4, 0xBC, 0xD2, 0x00,
+
+};
+
+static char r61318_hd_video_on_cmd8[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xC5, 0x06, 0x03, 0x1D,
+
+};
+
+static char r61318_hd_video_on_cmd9[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC6, 0x21, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd10[] = {
+ 0x1D, 0x00, 0x29, 0xC0,
+ 0xC8, 0x60, 0x0E, 0x08,
+ 0x62, 0x90, 0x52, 0x95,
+ 0x54, 0x49, 0x29, 0x84,
+ 0x90, 0xA2, 0x4A, 0x29,
+ 0x45, 0x15, 0x42, 0x48,
+ 0xA9, 0xA4, 0xA4, 0xAA,
+ 0x85, 0x0c, 0x11, 0xc0,
+ 0x31, 0xFF, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd11[] = {
+ 0x1F, 0x00, 0x29, 0xC0,
+ 0xCA, 0x02, 0x0A, 0x0F,
+ 0x15, 0x1B, 0x20, 0x23,
+ 0x1F, 0x24, 0x24, 0x21,
+ 0x1A, 0x15, 0x0F, 0x01,
+ 0x02, 0x0A, 0x0F, 0x15,
+ 0x1B, 0x20, 0x23, 0x1F,
+ 0x24, 0x24, 0x21, 0x1A,
+ 0x15, 0x0F, 0x01, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd12[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCD, 0x00, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd13[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE5, 0x02, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd14[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xD0, 0x05, 0x89, 0x1A,
+};
+
+static char r61318_hd_video_on_cmd15[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xD1, 0x03, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd16[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD2, 0x81, 0x1F, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd17[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xD4, 0x50, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd18[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD5, 0x34, 0x34, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd19[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x53, 0x24, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd20[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x51, 0xff, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd21[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char r61318_hd_video_on_cmd22[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd r61318_hd_video_on_command[] = {
+ {0x8, r61318_hd_video_on_cmd0, 0x00},
+ {0x8, r61318_hd_video_on_cmd1, 0x00},
+ {0x8, r61318_hd_video_on_cmd2, 0x00},
+ {0x8, r61318_hd_video_on_cmd3, 0x00},
+ {0xc, r61318_hd_video_on_cmd4, 0x00},
+ {0xc, r61318_hd_video_on_cmd5, 0x00},
+ {0x8, r61318_hd_video_on_cmd6, 0x00},
+ {0x8, r61318_hd_video_on_cmd7, 0x00},
+ {0x8, r61318_hd_video_on_cmd8, 0x00},
+ {0x8, r61318_hd_video_on_cmd9, 0x00},
+ {0x24, r61318_hd_video_on_cmd10, 0x00},
+ {0x24, r61318_hd_video_on_cmd11, 0x00},
+ {0x8, r61318_hd_video_on_cmd12, 0x00},
+ {0x8, r61318_hd_video_on_cmd13, 0x00},
+ {0x8, r61318_hd_video_on_cmd14, 0x00},
+ {0x8, r61318_hd_video_on_cmd15, 0x00},
+ {0x8, r61318_hd_video_on_cmd16, 0x00},
+ {0x8, r61318_hd_video_on_cmd17, 0x00},
+ {0x8, r61318_hd_video_on_cmd18, 0x00},
+ {0x8, r61318_hd_video_on_cmd19, 0x00},
+ {0x8, r61318_hd_video_on_cmd20, 0x00},
+ {0x4, r61318_hd_video_on_cmd21, 0x78},
+ {0x4, r61318_hd_video_on_cmd22, 0x32}
+};
+
+#define R61318_HD_VIDEO_ON_COMMAND 23
+
+
+static char r61318_hd_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char r61318_hd_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd r61318_hd_video_off_command[] = {
+ {0x4, r61318_hd_videooff_cmd0, 0x32},
+ {0x4, r61318_hd_videooff_cmd1, 0x78}
+};
+
+#define R61318_HD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state r61318_hd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info r61318_hd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info r61318_hd_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration r61318_hd_video_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t r61318_hd_video_timings[] = {
+ 0xab, 0x1c, 0x14, 0x00, 0x2a, 0x27, 0x18, 0x1e, 0x21, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing r61318_hd_video_timing_info = {
+ 0, 4, 0x20, 0x2e
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence r61318_hd_video_reset_seq = {
+ {1, 0, 1, }, {20, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight r61318_hd_video_backlight = {
+ 2, 1, 255, 0, 2, "bl_ctrl_dcs"
+};
+
+#endif /*_PANEL_R61318_HD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_r63417_1080p_video.h b/dev/gcdb/display/include/panel_r63417_1080p_video.h
new file mode 100644
index 0000000..dad028a
--- /dev/null
+++ b/dev/gcdb/display/include/panel_r63417_1080p_video.h
@@ -0,0 +1,313 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_R63417_1080P_VIDEO_H_
+#define _PANEL_R63417_1080P_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config r63417_1080p_video_panel_data = {
+ "qcom,mdss_dsi_r63417_1080p_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution r63417_1080p_video_panel_res = {
+ 1080, 1920, 100, 12, 60, 0, 25, 6, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info r63417_1080p_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char r63417_1080p_video_on_cmd0[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x11, 0x00, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd1[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB0, 0x04, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd2[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB3, 0x14, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd3[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB6, 0x3A, 0xC3, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd4[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC0, 0x00, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd5[] = {
+ 0x23, 0x00, 0x29, 0xC0,
+ 0xC1, 0xC4, 0x60, 0x10,
+ 0xEB, 0xFF, 0x6F, 0xCE,
+ 0xFF, 0xFF, 0x17, 0x12,
+ 0x58, 0x73, 0xAE, 0x31,
+ 0x20, 0xC6, 0xFF, 0xFF,
+ 0x1F, 0xF3, 0xFF, 0x5F,
+ 0x10, 0x10, 0x10, 0x10,
+ 0x00, 0x62, 0x01, 0x22,
+ 0x22, 0x00, 0x01, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd6[] = {
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xC2, 0x31, 0xF7, 0x80,
+ 0x08, 0x08, 0x00, 0x00,
+};
+
+static char r63417_1080p_video_on_cmd7[] = {
+ 0x17, 0x00, 0x29, 0xC0,
+ 0xC4, 0x70, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x06, 0x05,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x06, 0x05, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd8[] = {
+ 0x29, 0x00, 0x29, 0xC0,
+ 0xC6, 0xC8, 0x01, 0x69,
+ 0x01, 0x69, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x0B, 0x17,
+ 0x09, 0xC8, 0x08, 0x67,
+ 0x08, 0x67, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x16, 0x18,
+ 0x08, 0xFF, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd9[] = {
+ 0x0A, 0x00, 0x29, 0xC0,
+ 0xCB, 0x31, 0xFC, 0x3F,
+ 0x8C, 0x00, 0x00, 0x00,
+ 0x00, 0xC0, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd10[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCC, 0x0B, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd11[] = {
+ 0x0B, 0x00, 0x29, 0xC0,
+ 0xD0, 0x22, 0x82, 0xBB,
+ 0x19, 0x99, 0x4C, 0x19,
+ 0x19, 0x0C, 0x00, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd12[] = {
+ 0x1a, 0x00, 0x29, 0xC0,
+ 0xD3, 0x1B, 0x33, 0xBB,
+ 0xBB, 0xB3, 0x33, 0x33,
+ 0x33, 0x01, 0x01, 0x00,
+ 0xA0, 0xD8, 0xA0, 0x0D,
+ 0x55, 0x55, 0x33, 0x3B,
+ 0x37, 0x72, 0x07, 0x3D,
+ 0xBF, 0x44, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd13[] = {
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xD5, 0x06, 0x00, 0x00,
+ 0x01, 0x67, 0x01, 0x67,
+};
+
+static char r63417_1080p_video_on_cmd14[] = {
+ 0x1f, 0x00, 0x29, 0xC0,
+ 0xC7, 0x0C, 0x1B, 0x22,
+ 0x2B, 0x37, 0x43, 0x4C,
+ 0x5B, 0x3F, 0x47, 0x52,
+ 0x5F, 0x67, 0x6B, 0x6E,
+ 0x0C, 0x1B, 0x22, 0x2B,
+ 0x37, 0x43, 0x4C, 0x5B,
+ 0x3F, 0x47, 0x52, 0x5F,
+ 0x67, 0x6B, 0x6E, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd15[] = {
+ 0x14, 0x00, 0x29, 0xC0,
+ 0xC8, 0x01, 0x00, 0x00,
+ 0x03, 0xFB, 0xFB, 0xEF,
+ 0x00, 0x00, 0x03, 0xFB,
+ 0xFB, 0xEF, 0x00, 0x00,
+ 0x03, 0xFB, 0xFB, 0xEF,
+};
+
+static char r63417_1080p_video_on_cmd16[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x51, 0xFF, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd17[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x53, 0x2C, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd18[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x55, 0x03, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd19[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x35, 0x00, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd20[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x29, 0x00, 0xFF, 0xFF,
+};
+
+static struct mipi_dsi_cmd r63417_1080p_video_on_command[] = {
+ {0x8, r63417_1080p_video_on_cmd0, 0x78},
+ {0x8, r63417_1080p_video_on_cmd1, 0x00},
+ {0xc, r63417_1080p_video_on_cmd2, 0x00},
+ {0x8, r63417_1080p_video_on_cmd3, 0x00},
+ {0x8, r63417_1080p_video_on_cmd4, 0x00},
+ {0x28, r63417_1080p_video_on_cmd5, 0x00},
+ {0xc, r63417_1080p_video_on_cmd6, 0x00},
+ {0x1c, r63417_1080p_video_on_cmd7, 0x00},
+ {0x30, r63417_1080p_video_on_cmd8, 0x00},
+ {0x10, r63417_1080p_video_on_cmd9, 0x00},
+ {0x8, r63417_1080p_video_on_cmd10, 0x00},
+ {0x10, r63417_1080p_video_on_cmd11, 0x00},
+ {0x20, r63417_1080p_video_on_cmd12, 0x00},
+ {0xc, r63417_1080p_video_on_cmd13, 0x00},
+ {0x24, r63417_1080p_video_on_cmd14, 0x00},
+ {0x18, r63417_1080p_video_on_cmd15, 0x00},
+ {0x8, r63417_1080p_video_on_cmd16, 0x00},
+ {0x8, r63417_1080p_video_on_cmd17, 0x00},
+ {0x8, r63417_1080p_video_on_cmd18, 0x00},
+ {0x8, r63417_1080p_video_on_cmd19, 0x00},
+ {0x8, r63417_1080p_video_on_cmd20, 0x64}
+};
+
+#define R63417_1080P_VIDEO_ON_COMMAND 21
+
+
+static char r63417_1080p_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char r63417_1080p_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd r63417_1080p_video_off_command[] = {
+ {0x4, r63417_1080p_videooff_cmd0, 0x32},
+ {0x4, r63417_1080p_videooff_cmd1, 0x78}
+};
+
+#define R63417_1080P_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state r63417_1080p_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info r63417_1080p_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info r63417_1080p_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration r63417_1080p_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t r63417_1080p_video_timings[] = {
+ 0xAE, 0x44, 0x37, 0x00, 0x5D, 0x55, 0x39, 0x46, 0x5B, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing r63417_1080p_video_timing_info = {
+ 0, 4, 0x1e, 0x34
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence r63417_1080p_video_reset_seq = {
+ {1, 0, 1, }, {20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight r63417_1080p_video_backlight = {
+ 1, 1, 255, 0, 2, "bl_ctrl_dcs"
+};
+
+#endif /*_PANEL_R63417_1080P_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_samsung_wxga_video.h b/dev/gcdb/display/include/panel_samsung_wxga_video.h
new file mode 100644
index 0000000..e01b562
--- /dev/null
+++ b/dev/gcdb/display/include/panel_samsung_wxga_video.h
@@ -0,0 +1,227 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_SAMSUNG_WXGA_VIDEO_H_
+#define _PANEL_SAMSUNG_WXGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config samsung_wxga_video_panel_data = {
+ "qcom,mdss_dsi_samsung_wxga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution samsung_wxga_video_panel_res = {
+ 800, 1280, 16, 140, 14, 0, 8, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info samsung_wxga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char samsung_wxga_video_on_cmd0[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xF0, 0x5A, 0x5A, 0xFF,
+};
+
+static char samsung_wxga_video_on_cmd1[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xF1, 0x5A, 0x5A, 0xFF,
+};
+
+static char samsung_wxga_video_on_cmd2[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xFC, 0xA5, 0xA5, 0xFF,
+};
+
+static char samsung_wxga_video_on_cmd3[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xD0, 0x00, 0x10, 0xFF,
+};
+
+static char samsung_wxga_video_on_cmd4[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xB1, 0x10, 0xA0, 0xFF,
+};
+
+static char samsung_wxga_video_on_cmd5[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xC3, 0x40, 0x00, 0x28,
+};
+
+static char samsung_wxga_video_on_cmd6[] = {
+ 0x36, 0x04, 0x05, 0x80
+};
+
+static char samsung_wxga_video_on_cmd7[] = {
+ 0x07, 0x00, 0x39, 0xC0,
+ 0xF6, 0x63, 0x20, 0x86,
+ 0x00, 0x00, 0x10, 0xFF,
+};
+
+static char samsung_wxga_video_on_cmd8[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char samsung_wxga_video_on_cmd9[] = {
+ 0x36, 0x00, 0x05, 0x80
+};
+
+static char samsung_wxga_video_on_cmd10[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xF0, 0x5A, 0x5A, 0xFF,
+};
+
+static char samsung_wxga_video_on_cmd11[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xF1, 0x5A, 0x5A, 0xFF,
+};
+
+static char samsung_wxga_video_on_cmd12[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xFC, 0xA5, 0xA5, 0xFF,
+};
+
+static char samsung_wxga_video_on_cmd13[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd samsung_wxga_video_on_command[] = {
+ {0x8, samsung_wxga_video_on_cmd0, 0x05},
+ {0x8, samsung_wxga_video_on_cmd1, 0x05},
+ {0x8, samsung_wxga_video_on_cmd2, 0x05},
+ {0x8, samsung_wxga_video_on_cmd3, 0x05},
+ {0x8, samsung_wxga_video_on_cmd4, 0x05},
+ {0x8, samsung_wxga_video_on_cmd5, 0x14},
+ {0x4, samsung_wxga_video_on_cmd6, 0x00},
+ {0xc, samsung_wxga_video_on_cmd7, 0x00},
+ {0x4, samsung_wxga_video_on_cmd8, 0x96},
+ {0x4, samsung_wxga_video_on_cmd9, 0x00},
+ {0x8, samsung_wxga_video_on_cmd10, 0x05},
+ {0x8, samsung_wxga_video_on_cmd11, 0x05},
+ {0x8, samsung_wxga_video_on_cmd12, 0x05},
+ {0x4, samsung_wxga_video_on_cmd13, 0x32}
+};
+
+#define SAMSUNG_WXGA_VIDEO_ON_COMMAND 14
+
+
+static char samsung_wxga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char samsung_wxga_videooff_cmd1[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xC3, 0x40, 0x00, 0x20,
+};
+
+static char samsung_wxga_videooff_cmd2[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd samsung_wxga_video_off_command[] = {
+ {0x4, samsung_wxga_videooff_cmd0, 0x32},
+ {0x8, samsung_wxga_videooff_cmd1, 0x00},
+ {0x4, samsung_wxga_videooff_cmd2, 0x96}
+};
+
+#define SAMSUNG_WXGA_VIDEO_OFF_COMMAND 3
+
+
+static struct command_state samsung_wxga_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info samsung_wxga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info samsung_wxga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration samsung_wxga_video_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t samsung_wxga_video_timings[] = {
+ 0x92, 0x1A, 0x12, 0x00, 0x3E, 0x42, 0x16, 0x1E, 0x14, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing samsung_wxga_video_timing_info = {
+ 0, 4, 0x1E, 0x38
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence samsung_wxga_video_reset_seq = {
+ {1, 0, 1, }, {10, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight samsung_wxga_video_backlight = {
+ 0, 1, 255, 2, 0, "PMIC_8941"
+};
+
+#endif /*_PANEL_SAMSUNG_WXGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_sharp_qhd_video.h b/dev/gcdb/display/include/panel_sharp_qhd_video.h
index df8c5a5..00f0147 100755
--- a/dev/gcdb/display/include/panel_sharp_qhd_video.h
+++ b/dev/gcdb/display/include/panel_sharp_qhd_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -76,38 +76,31 @@
static char sharp_qhd_video_on_cmd2[] = {
-0x53, 0x2c, 0x15, 0x80 };
+0x53, 0x0c, 0x15, 0x80 };
static char sharp_qhd_video_on_cmd3[] = {
-0x51, 0xff, 0x15, 0x80 };
-
-
-static char sharp_qhd_video_on_cmd4[] = {
0x29, 0x00, 0x05, 0x80 };
-static char sharp_qhd_video_on_cmd5[] = {
+static char sharp_qhd_video_on_cmd4[] = {
0xae, 0x03, 0x15, 0x80 };
-static char sharp_qhd_video_on_cmd6[] = {
+static char sharp_qhd_video_on_cmd5[] = {
0x3a, 0x77, 0x15, 0x80 };
-
-
static struct mipi_dsi_cmd sharp_qhd_video_on_command[] = {
{ 0x4 , sharp_qhd_video_on_cmd0},
{ 0x4 , sharp_qhd_video_on_cmd1},
{ 0x4 , sharp_qhd_video_on_cmd2},
{ 0x4 , sharp_qhd_video_on_cmd3},
{ 0x4 , sharp_qhd_video_on_cmd4},
-{ 0x4 , sharp_qhd_video_on_cmd5},
-{ 0x4 , sharp_qhd_video_on_cmd6}
+{ 0x4 , sharp_qhd_video_on_cmd5}
};
-#define SHARP_QHD_VIDEO_ON_COMMAND 7
+#define SHARP_QHD_VIDEO_ON_COMMAND 6
static char sharp_qhd_videooff_cmd0[] = {
0x28, 0x00, 0x05, 0x80 };
@@ -151,7 +144,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration sharp_qhd_video_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
diff --git a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
index 2fccf8c..a1b57d3 100644
--- a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -119,7 +119,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration sharp_wqxga_dualdsi_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
@@ -147,6 +147,17 @@
1, 1, 4095, 100, 1, "PMIC_8941" /* BL_WLED */
};
+static struct labibb_desc sharp_wqxga_dualdsi_video_labibb = {
+ 0, 1, 5500000, 5500000, 5500000, 5500000, 3, 3, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Dynamic fps supported frequencies by panel */
+/*---------------------------------------------------------------------------*/
+static const struct dfps_panel_info sharp_wqxga_dualdsi_video_dfps = {
+ 1, 8, {53, 54, 55, 56, 57, 58, 59, 60}
+};
+
#define SHARP_WQXGA_DUALDSI_VIDEO_SIGNATURE 0x210000
#endif /*_PANEL_SHARP_WQXGA_DUALDSI_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
index 7a1c8e5..74bfd7b 100755
--- a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
+++ b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -457,7 +457,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration ssd2080m_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_toshiba_720p_video.h b/dev/gcdb/display/include/panel_toshiba_720p_video.h
index 7b16246..12c6326 100755
--- a/dev/gcdb/display/include/panel_toshiba_720p_video.h
+++ b/dev/gcdb/display/include/panel_toshiba_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -309,7 +309,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration toshiba_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_truly_wvga_cmd.h b/dev/gcdb/display/include/panel_truly_wvga_cmd.h
index c443766..89a9994 100644
--- a/dev/gcdb/display/include/panel_truly_wvga_cmd.h
+++ b/dev/gcdb/display/include/panel_truly_wvga_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -413,18 +413,18 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration truly_wvga_cmd_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
/* Panel timing */
/*---------------------------------------------------------------------------*/
static const uint32_t truly_wvga_cmd_timings[] = {
- 0x5D, 0x12, 0x0C, 0x00, 0x33, 0x38, 0x10, 0x16, 0x1E, 0x03, 0x04, 0x00
+ 0x7B, 0x1A, 0x10, 0x00, 0x3C, 0x42, 0x14, 0x1C, 0x15, 0x3, 0x4, 0x00
};
static struct panel_timing truly_wvga_cmd_timing_info = {
- 2, 4, 0x04, 0x1b
+ 2, 4, 0x04, 0x1a
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_truly_wvga_video.h b/dev/gcdb/display/include/panel_truly_wvga_video.h
index ee1ab28..18ee099 100644
--- a/dev/gcdb/display/include/panel_truly_wvga_video.h
+++ b/dev/gcdb/display/include/panel_truly_wvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -291,7 +291,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration truly_wvga_video_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index c09da68..d2675dc 100755
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -33,19 +33,72 @@
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
+#include <mdp5.h>
#include <sys/types.h>
#include <platform/iomap.h>
#include <err.h>
#include <reg.h>
-#include <mdp5.h>
#include <string.h>
-
/*---------------------------------------------------------------------------*/
/* Panel Header */
/*---------------------------------------------------------------------------*/
#include "panel_display.h"
#include "include/panel.h"
+#include "target/display.h"
+
+static int dsi_platform_base_offset_adjust(uint32_t base)
+{
+ return target_display_get_base_offset(base);
+}
+
+static int dsi_panel_ctl_base_setup(struct msm_panel_info *pinfo,
+ char *panel_destination)
+{
+ int base_offset = 0, base1_offset = 0;
+
+ /*
+ * Base offsets may vary for few platforms. Add the difference to get
+ * proper base offset for the respective platform.
+ */
+ base_offset = dsi_platform_base_offset_adjust(MIPI_DSI0_BASE);
+ base1_offset = dsi_platform_base_offset_adjust(MIPI_DSI1_BASE);
+ dprintf(SPEW, "base offset = %d, %x\n", base_offset, base_offset);
+
+ if (!strcmp(panel_destination, "DISPLAY_1")) {
+ pinfo->dest = DISPLAY_1;
+ pinfo->mipi.ctl_base = MIPI_DSI0_BASE + base_offset;
+ pinfo->mipi.phy_base = DSI0_PHY_BASE + base_offset;
+ pinfo->mipi.sctl_base = MIPI_DSI1_BASE + base1_offset;
+ pinfo->mipi.sphy_base = DSI1_PHY_BASE + base1_offset;
+ } else if (!strcmp(panel_destination, "DISPLAY_2")) {
+ pinfo->dest = DISPLAY_2;
+ pinfo->mipi.ctl_base = MIPI_DSI1_BASE + base1_offset;
+ pinfo->mipi.phy_base = DSI1_PHY_BASE + base1_offset;
+ pinfo->mipi.sctl_base = MIPI_DSI0_BASE + base_offset;
+ pinfo->mipi.sphy_base = DSI0_PHY_BASE + base_offset;
+ } else {
+ pinfo->dest = DISPLAY_UNKNOWN;
+ dprintf(CRITICAL, "%s: Unkown panel destination: %d\n",
+ __func__, pinfo->dest);
+ return ERROR;
+ }
+
+ pinfo->mipi.pll_0_base = DSI0_PLL_BASE + base_offset;
+ pinfo->mipi.pll_1_base = DSI1_PLL_BASE + base1_offset;
+
+ /* Both DSI0 and DSI1 use the same regulator */
+ pinfo->mipi.reg_base = DSI0_REGULATOR_BASE + base_offset;
+ pinfo->mipi.sreg_base = DSI0_REGULATOR_BASE + base_offset;
+
+ dprintf(SPEW, "%s: panel dest=%s, ctl_base=0x%08x, phy_base=0x%08x\n",
+ __func__, panel_destination, pinfo->mipi.ctl_base,
+ pinfo->mipi.phy_base);
+ dprintf(SPEW, "pll_0_base=%08x, pll_1_base=0x%08x, reg_base=0x%08x, sreg_base=%08x\n",
+ pinfo->mipi.pll_0_base, pinfo->mipi.pll_1_base,
+ pinfo->mipi.reg_base, pinfo->mipi.sreg_base);
+ return NO_ERROR;
+}
/*---------------------------------------------------------------------------*/
/* Panel Init */
@@ -53,6 +106,7 @@
int dsi_panel_init(struct msm_panel_info *pinfo,
struct panel_struct *pstruct)
{
+ int ret = NO_ERROR;
/* Resolution setting*/
pinfo->xres = pstruct->panelres->panel_width;
pinfo->yres = pstruct->panelres->panel_height;
@@ -89,6 +143,7 @@
pinfo->lcdc.border_clr = pstruct->color->border_color;
pinfo->lcdc.underflow_clr = pstruct->color->underflow_color;
pinfo->mipi.rgb_swap = pstruct->color->color_order;
+ pinfo->bpp = pstruct->color->color_format;
switch (pinfo->bpp) {
case BPP_16:
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB565;
@@ -114,7 +169,6 @@
} else {
pinfo->type = MIPI_VIDEO_PANEL;
}
- pinfo->bpp = pstruct->color->color_format;
pinfo->clk_rate = pstruct->paneldata->panel_clockrate;
pinfo->orientation = pstruct->paneldata->panel_orientation;
pinfo->mipi.interleave_mode = pstruct->paneldata->interleave_mode;
@@ -126,8 +180,16 @@
pinfo->mipi.dual_dsi = 1;
pinfo->mipi.mode_gpio_state = pstruct->paneldata->mode_gpio_state;
pinfo->mipi.bitclock = pstruct->paneldata->panel_bitclock_freq;
+ if (pinfo->mipi.bitclock) {
+ /* panel_clockrate is depcrated in favor of bitclock_freq */
+ pinfo->clk_rate = pinfo->mipi.bitclock;
+ }
pinfo->mipi.use_enable_gpio =
pstruct->paneldata->panel_with_enable_gpio;
+ ret = dsi_panel_ctl_base_setup(pinfo,
+ pstruct->paneldata->panel_destination);
+ if (ret)
+ return ret;
/* Video Panel configuration */
pinfo->mipi.pulse_mode_hsa_he = pstruct->videopanel->hsync_pulse;
@@ -155,6 +217,7 @@
pinfo->mipi.data_lane2 = pstruct->laneconfig->lane2_state;
pinfo->mipi.data_lane3 = pstruct->laneconfig->lane3_state;
pinfo->mipi.lane_swap = pstruct->laneconfig->dsi_lanemap;
+ pinfo->mipi.force_clk_lane_hs = pstruct->laneconfig->force_clk_lane_hs;
pinfo->mipi.t_clk_post = pstruct->paneltiminginfo->tclk_post;
pinfo->mipi.t_clk_pre = pstruct->paneltiminginfo->tclk_pre;
@@ -178,6 +241,10 @@
pinfo->fbc.lossy_mode_thd = pstruct->fbcinfo.lossy_mode_thd;
pinfo->fbc.lossy_rgb_thd = pstruct->fbcinfo.lossy_rgb_thd;
pinfo->fbc.lossy_mode_idx = pstruct->fbcinfo.lossy_mode_idx;
+ pinfo->fbc.slice_height = pstruct->fbcinfo.slice_height;
+ pinfo->fbc.pred_mode = pstruct->fbcinfo.pred_mode;
+ pinfo->fbc.max_pred_err = pstruct->fbcinfo.max_pred_err;
+
} else {
pinfo->fbc.comp_ratio = 1;
}
@@ -242,7 +309,7 @@
uint32_t panel_width = pinfo->xres;
uint32_t final_xres, final_yres, final_width;
uint32_t final_height, final_hbp, final_hfp,final_vbp;
- uint32_t final_vfp, final_hpw, final_vpw;
+ uint32_t final_vfp, final_hpw, final_vpw, low_pwr_stop;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
@@ -273,6 +340,9 @@
final_vfp = pinfo->lcdc.v_front_porch;
final_hpw = pinfo->lcdc.h_pulse_width;
final_vpw = pinfo->lcdc.v_pulse_width;
+ low_pwr_stop = (pinfo->mipi.hfp_power_stop << 8) |
+ (pinfo->mipi.hbp_power_stop << 4) |
+ pinfo->mipi.hsa_power_stop;
ret = mdss_dsi_video_mode_config(final_width, final_height,
final_xres, final_yres,
@@ -282,10 +352,11 @@
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
- pinfo->mipi.hsa_power_stop,
+ pinfo->mipi.pulse_mode_hsa_he,
+ low_pwr_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
- MIPI_DSI0_BASE);
+ pinfo->mipi.ctl_base);
if (pinfo->mipi.dual_dsi)
ret = mdss_dsi_video_mode_config(final_width, final_height,
@@ -296,10 +367,11 @@
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
- pinfo->mipi.hsa_power_stop,
+ pinfo->mipi.pulse_mode_hsa_he,
+ low_pwr_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
- MIPI_DSI1_BASE);
+ pinfo->mipi.sctl_base);
return ret;
}
@@ -311,6 +383,8 @@
uint8_t lane_en = 0;
uint8_t ystride = pinfo->bpp / 8;
uint32_t panel_width = pinfo->xres;
+ uint32_t final_xres, final_yres, final_width;
+ uint32_t final_height;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
@@ -324,22 +398,32 @@
if (pinfo->mipi.data_lane3)
lane_en |= (1 << 3);
- ret = mdss_dsi_cmd_mode_config((panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- panel_width, (pinfo->yres),
+ final_xres = panel_width;
+ final_width = panel_width + pinfo->lcdc.xres_pad;
+
+ if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
+ final_xres /= pinfo->fbc.comp_ratio;
+ final_width /= pinfo->fbc.comp_ratio;
+ dprintf(SPEW, "DSI xres =%d final_width=%d\n", final_xres,
+ final_width);
+ }
+ final_yres = pinfo->yres;
+ final_height = pinfo->yres + pinfo->lcdc.yres_pad;
+
+ ret = mdss_dsi_cmd_mode_config(final_width, final_height,
+ final_xres, final_yres,
pinfo->mipi.dst_format,
ystride, lane_en,
pinfo->mipi.interleave_mode,
- MIPI_DSI0_BASE);
+ pinfo->mipi.ctl_base);
if (pinfo->mipi.dual_dsi)
- ret = mdss_dsi_cmd_mode_config((panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- panel_width, (pinfo->yres),
- pinfo->mipi.dst_format,
- ystride, lane_en,
- pinfo->mipi.interleave_mode,
- MIPI_DSI1_BASE);
+ ret = mdss_dsi_cmd_mode_config(final_width, final_height,
+ final_xres, final_yres,
+ pinfo->mipi.dst_format,
+ ystride, lane_en,
+ pinfo->mipi.interleave_mode,
+ pinfo->mipi.sctl_base);
return ret;
}
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index 3c99289..8860f00 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -52,7 +52,7 @@
/*---------------------------------------------------------------------------*/
/* struct definition */
/*---------------------------------------------------------------------------*/
-typedef struct panel_struct{
+struct panel_struct{
struct panel_config *paneldata;
struct panel_resolution *panelres;
struct color_info *color;
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 6dfc10a..6e89f57 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -219,6 +219,7 @@
uint32_t pm8x41_v2_resin_status();
uint32_t pm8x41_resin_status();
void pm8x41_reset_configure(uint8_t);
+void pm8994_reset_configure(uint8_t);
void pm8x41_v2_reset_configure(uint8_t);
int pm8x41_ldo_set_voltage(struct pm8x41_ldo *ldo, uint32_t voltage);
int pm8x41_ldo_control(struct pm8x41_ldo *ldo, uint8_t enable);
@@ -234,4 +235,7 @@
void pm8x41_diff_clock_ctrl(uint8_t enable);
void pm8x41_clear_pmic_watchdog(void);
void pm8x41_lnbb_clock_ctrl(uint8_t enable);
+void pmi8994_config_mpp_slave_id(uint8_t slave_id);
+void pm_pwm_enable(bool enable);
+int pm_pwm_config(unsigned int duty_us, unsigned int period_us);
#endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index db4473c..44e9599 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -143,6 +143,16 @@
#define VBAT_DET_HI_RT_STS 0x02
#define VCP_ENABLE 0x01
+#define PMI8994_CHGR_CFG2 0x210FC
+#define CURRENT_TERM_EN BIT(3)
+#define PMI8994_FCC_CFG 0x210F2
+#define PMI8994_FV_CFG 0x210F4
+#define PMI8994_INT_RT_STS 0x21010
+#define BAT_TAPER_MODE_CHARGING_RT_STS BIT(6)
+#define PMI8994_CHGR_TRIM_OPTIONS_7_0 0x216F6
+#define INPUT_MISSING_POLLER_EN BIT(3)
+
int pm8xxx_is_battery_broken(void);
+bool pmi8994_battery_broken(void);
#endif
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index dc4c32d..1784534 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -77,6 +77,24 @@
return val;
}
+/* SPMI helper function which takes slave id as the i/p */
+void pm8xxx_reg_write(uint8_t slave_id, uint32_t addr, uint8_t val)
+{
+ struct pmic_arb_cmd cmd;
+ struct pmic_arb_param param;
+
+ cmd.address = PERIPH_ID(addr);
+ cmd.offset = REG_OFFSET(addr);
+ cmd.slave_id = slave_id;
+
+ cmd.priority = 0;
+
+ param.buffer = &val;
+ param.size = 1;
+
+ pmic_arb_write_cmd(&cmd, ¶m);
+}
+
void pm8x41_reg_write(uint32_t addr, uint8_t val)
{
struct pmic_arb_cmd cmd;
@@ -333,6 +351,24 @@
return 0;
}
+void pm8994_reset_configure(uint8_t reset_type)
+{
+ /* Slave ID 14 is global slave ID for all the pmics */
+ uint8_t slave_id = 14;
+
+ /* disable PS_HOLD_RESET */
+ pm8xxx_reg_write(slave_id, PON_PS_HOLD_RESET_CTL2, 0x0);
+
+ /* Delay needed for disable to kick in. */
+ udelay(300);
+
+ /* configure reset type */
+ pm8xxx_reg_write(slave_id, PON_PS_HOLD_RESET_CTL, reset_type);
+
+ /* enable PS_HOLD_RESET */
+ pm8xxx_reg_write(slave_id, PON_PS_HOLD_RESET_CTL2, BIT(S2_RESET_EN_BIT));
+}
+
void pm8x41_v2_reset_configure(uint8_t reset_type)
{
uint8_t val;
@@ -625,3 +661,38 @@
return batt_is_broken;
}
+
+/* Detect broken battery for pmi 8994*/
+bool pmi8994_is_battery_broken()
+{
+ bool batt_is_broken;
+ uint8_t fast_charge = 0;
+
+ /* Disable the input missing ppoller */
+ REG_WRITE(PMI8994_CHGR_TRIM_OPTIONS_7_0, REG_READ(PMI8994_CHGR_TRIM_OPTIONS_7_0) & ~INPUT_MISSING_POLLER_EN);
+ /* Disable current termination */
+ REG_WRITE(PMI8994_CHGR_CFG2, REG_READ(PMI8994_CHGR_CFG2) & ~CURRENT_TERM_EN);
+ /* Fast-charge current to 300 mA */
+ fast_charge = REG_READ(PMI8994_FCC_CFG);
+ REG_WRITE(PMI8994_FCC_CFG, 0x0);
+ /* Change the float voltage to 4.50V */
+ REG_WRITE(PMI8994_FV_CFG, 0x3F);
+
+ mdelay(5);
+
+ if (REG_READ(PMI8994_INT_RT_STS) & BAT_TAPER_MODE_CHARGING_RT_STS)
+ batt_is_broken = true;
+ else
+ batt_is_broken = false;
+
+ /* Set float voltage back to 4.35V */
+ REG_WRITE(PMI8994_FV_CFG, 0x2B);
+ /* Enable current termination */
+ REG_WRITE(PMI8994_CHGR_CFG2, REG_READ(PMI8994_CHGR_CFG2) | CURRENT_TERM_EN);
+ /* Fast-charge current back to default mA */
+ REG_WRITE(PMI8994_FCC_CFG, fast_charge);
+ /* Re-enable the input missing poller */
+ REG_WRITE(PMI8994_CHGR_TRIM_OPTIONS_7_0, REG_READ(PMI8994_CHGR_TRIM_OPTIONS_7_0) | INPUT_MISSING_POLLER_EN);
+
+ return batt_is_broken;
+}
diff --git a/dev/pmic/pm8x41/pm_pwm.c b/dev/pmic/pm8x41/pm_pwm.c
index b7ecf68..87e2651 100644
--- a/dev/pmic/pm8x41/pm_pwm.c
+++ b/dev/pmic/pm8x41/pm_pwm.c
@@ -165,7 +165,8 @@
unsigned int period_us,
unsigned int duty_us)
{
- unsigned int max_pwm_value, tmp;
+ int max_pwm_value;
+ unsigned int tmp;
/* Figure out pwm_value with overflow handling */
tmp = 1 << (sizeof(tmp) * 8 - pwm_config->pwm_size);
diff --git a/dev/qpnp_led/include/qpnp_led.h b/dev/qpnp_led/include/qpnp_led.h
new file mode 100644
index 0000000..834b29d
--- /dev/null
+++ b/dev/qpnp_led/include/qpnp_led.h
@@ -0,0 +1,72 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <board.h>
+
+#define PERPH_SUBTYPE(base) (base + 0x05)
+#define RGB_LED_PERPH_TYPE(base) (base + 0x04)
+#define RGB_LED_SRC_SEL(base) (base + 0x45)
+#define RGB_LED_EN_CTL(base) (base + 0x46)
+#define RGB_LED_ATC_CTL(base) (base + 0x47)
+#define LPG_PERPH_TYPE(base) (base + 0x04)
+#define LPG_PERPH_SUBTYPE(base) (base + 0x05)
+#define LPG_PATTERN_CONFIG(base) (base + 0x40)
+#define LPG_PWM_SIZE_CLK(base) (base + 0x41)
+#define LPG_PWM_FREQ_PREDIV_CLK(base) (base + 0x42)
+#define LPG_PWM_TYPE_CONFIG(base) (base + 0x43)
+#define PWM_VALUE_LSB(base) (base + 0x44)
+#define PWM_VALUE_MSB(base) (base + 0x45)
+#define LPG_ENABLE_CONTROL(base) (base + 0x46)
+#define PWM_SYNC(base) (base + 0x47)
+
+#define RGB_LED_ENABLE_BLUE 0x20
+#define RGB_LED_ENABLE_GREEN 0x40
+#define RGB_LED_ENABLE_RED 0x80
+#define RGB_LED_SOURCE_VPH_PWR 0x01
+#define RGB_LED_ENABLE_MASK 0xE0
+#define RGB_LED_SRC_MASK 0xfc
+#define PWM_6BIT_1KHZ_CLK 0x01
+#define PWM_FREQ 0x05
+#define RGB_LED_ENABLE_PWM 0xe4
+
+enum qpnp_led_op {
+ QPNP_LED_RED,
+ QPNP_LED_GREEN,
+ QPNP_LED_BLUE,
+};
+
+struct qpnp_led_data {
+ uint16_t base;
+ uint16_t lpg_base;
+ enum qpnp_led_op color_sel;
+};
+
+/* LED Initial Setup */
+void qpnp_led_init(enum qpnp_led_op color, uint16_t led_base_addr,
+ uint16_t lpg_base_addr);
diff --git a/dev/qpnp_led/qpnp_led.c b/dev/qpnp_led/qpnp_led.c
new file mode 100644
index 0000000..a1503a2
--- /dev/null
+++ b/dev/qpnp_led/qpnp_led.c
@@ -0,0 +1,94 @@
+ /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <qpnp_led.h>
+#include <platform/iomap.h>
+#include <pm8x41_wled.h>
+
+static void qpnp_led_config(struct qpnp_led_data *led)
+{
+ pm8x41_wled_reg_write(RGB_LED_SRC_SEL(led->base),
+ RGB_LED_SOURCE_VPH_PWR);
+ pm8x41_wled_reg_write(LPG_PATTERN_CONFIG(led->lpg_base), 0x00);
+ pm8x41_wled_reg_write(LPG_PWM_SIZE_CLK(led->lpg_base),
+ PWM_6BIT_1KHZ_CLK);
+ pm8x41_wled_reg_write(LPG_PWM_FREQ_PREDIV_CLK(led->lpg_base),
+ PWM_FREQ);
+ pm8x41_wled_reg_write(LPG_PWM_TYPE_CONFIG(led->lpg_base), 0x00);
+ pm8x41_wled_reg_write(PWM_VALUE_LSB(led->lpg_base), 0x20);
+ pm8x41_wled_reg_write(PWM_VALUE_MSB(led->lpg_base), 0x00);
+ pm8x41_wled_reg_write(PWM_SYNC(led->lpg_base), 0x01);
+ pm8x41_wled_reg_write(LPG_ENABLE_CONTROL(led->lpg_base),
+ RGB_LED_ENABLE_PWM);
+}
+
+static int qpnp_led_setup(struct qpnp_led_data *led)
+{
+ uint8_t reg = 0;
+
+ reg = pm8x41_wled_reg_read(RGB_LED_EN_CTL(led->base));
+
+ switch (led->color_sel) {
+ case QPNP_LED_RED:
+ reg |= RGB_LED_ENABLE_RED;
+ break;
+ case QPNP_LED_GREEN:
+ reg |= RGB_LED_ENABLE_GREEN;
+ break;
+ case QPNP_LED_BLUE:
+ reg |= RGB_LED_ENABLE_BLUE;
+ break;
+ default:
+ return -1;
+ };
+
+ pm8x41_wled_reg_write(RGB_LED_EN_CTL(led->base), reg);
+
+ return 0;
+}
+
+void qpnp_led_init(enum qpnp_led_op color, uint16_t led_base_addr,
+ uint16_t lpg_base_addr)
+{
+ int rc;
+ struct qpnp_led_data led;
+
+ led.base = led_base_addr;
+ led.lpg_base = lpg_base_addr;
+ led.color_sel = color;
+
+ rc = qpnp_led_setup(&led);
+ if (rc) {
+ dprintf(INFO, "%s : failed\n", __func__);
+ return;
+ }
+
+ qpnp_led_config(&led);
+}
+
diff --git a/dev/qpnp_led/rules.mk b/dev/qpnp_led/rules.mk
new file mode 100644
index 0000000..b35e459
--- /dev/null
+++ b/dev/qpnp_led/rules.mk
@@ -0,0 +1,6 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include
+
+OBJS += \
+ $(LOCAL_DIR)/qpnp_led.o
diff --git a/dev/qpnp_wled/include/qpnp_wled.h b/dev/qpnp_wled/include/qpnp_wled.h
index 8c6bb64..a04680d 100644
--- a/dev/qpnp_wled/include/qpnp_wled.h
+++ b/dev/qpnp_wled/include/qpnp_wled.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -141,9 +141,15 @@
#define QPNP_WLED_IBB_BIAS_SHIFT 7
#define QPNP_WLED_IBB_PWRUP_DLY_MASK 0xCF
#define QPNP_WLED_IBB_PWRUP_DLY_SHIFT 4
-#define QPNP_WLED_IBB_PWRUP_DLY_MIN_MS 1
-#define QPNP_WLED_IBB_PWRUP_DLY_MAX_MS 8
-
+#define QPNP_WLED_IBB_PWRUP_DLY_MIN_MS 0
+#define QPNP_WLED_IBB_PWRUP_DLY_MAX_MS 3
+#define QPNP_WLED_IBB_PWRDN_DLY_MIN_MS 0
+#define QPNP_WLED_IBB_PWRDN_DLY_MAX_MS 3
+#define IBB_LAB_VREG_STEP_SIZE 100000
+#define QPNP_LABIBB_OUTPUT_VOLTAGE 0x41
+#define QPNP_LAB_OUTPUT_OVERRIDE_EN BIT(7)
+#define QPNP_LAB_SET_VOLTAGE_MASK (BIT(4) - 1)
+#define QPNP_IBB_SET_VOLTAGE_MASK (BIT(6) - 1)
#define QPNP_WLED_LAB_IBB_RDY_REG(b) (b + 0x49)
#define QPNP_WLED_LAB_FAST_PC_REG(b) (b + 0x5E)
#define QPNP_WLED_LAB_FAST_PC_MASK 0xFB
@@ -162,6 +168,8 @@
#define QPNP_WLED_MIN_MSLEEP 20
#define QPNP_WLED_MAX_BR_LEVEL 1638
+#define PWRDN_DLY2_MASK 0x3
+
/* output feedback mode */
enum qpnp_wled_fdbk_op {
QPNP_WLED_FDBK_AUTO,
@@ -233,6 +241,8 @@
uint16_t boost_duty_ns;
uint16_t fs_curr_ua;
uint16_t ibb_pwrup_dly_ms;
+ uint16_t ibb_pwrdn_dly_ms;
+ uint16_t ibb_discharge_en;
uint16_t ramp_ms;
uint16_t ramp_step;
uint8_t strings[QPNP_WLED_MAX_STRINGS];
@@ -243,11 +253,29 @@
bool disp_type_amoled;
bool ibb_bias_active;
bool lab_fast_precharge;
+ uint32_t lab_min_volt;
+ uint32_t lab_max_volt;
+ uint32_t ibb_min_volt;
+ uint32_t ibb_max_volt;
+ uint32_t ibb_init_volt;
+ uint32_t lab_init_volt;
};
+struct qpnp_wled_config_data {
+ bool display_type;
+ char pwr_up_delay;
+ char pwr_down_delay;
+ char ibb_discharge_en;
+ uint32_t lab_min_volt;
+ uint32_t lab_max_volt;
+ uint32_t ibb_min_volt;
+ uint32_t ibb_max_volt;
+ uint32_t ibb_init_volt;
+ uint32_t lab_init_volt;
+};
/* WLED Initial Setup */
-int qpnp_wled_init();
+int qpnp_wled_init(struct qpnp_wled_config_data *config);
/* Enable IBB */
-int qpnp_ibb_enable();
+int qpnp_ibb_enable(bool state);
void qpnp_wled_enable_backlight(int enable);
diff --git a/dev/qpnp_wled/qpnp_wled.c b/dev/qpnp_wled/qpnp_wled.c
index a342197..2f4b196 100644
--- a/dev/qpnp_wled/qpnp_wled.c
+++ b/dev/qpnp_wled/qpnp_wled.c
@@ -1,4 +1,4 @@
- /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -27,8 +27,12 @@
*/
#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
#include <err.h>
#include <qpnp_wled.h>
+#include <pm8x41_wled.h>
+#include <qtimer.h>
static int fls(uint16_t n)
{
@@ -38,10 +42,10 @@
}
static struct qpnp_wled *gwled;
+static int qpnp_labibb_regulator_set_voltage(struct qpnp_wled *wled);
static int qpnp_wled_sec_access(struct qpnp_wled *wled, uint16_t base_addr)
{
- int rc;
uint8_t reg = QPNP_WLED_SEC_UNLOCK;
pm8x41_wled_reg_write(QPNP_WLED_SEC_ACCESS_REG(base_addr), reg);
@@ -52,7 +56,7 @@
/* set wled to a level of brightness */
static int qpnp_wled_set_level(struct qpnp_wled *wled, int level)
{
- int i, rc;
+ int i;
uint8_t reg;
/* set brightness registers */
@@ -84,8 +88,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_MODULE_EN_REG(base_addr));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MODULE_EN_MASK;
reg |= (state << QPNP_WLED_MODULE_EN_SHIFT);
pm8x41_wled_reg_write(QPNP_WLED_MODULE_EN_REG(base_addr), reg);
@@ -106,13 +108,11 @@
/* enable lab */
if (gwled->ibb_bias_active) {
rc = qpnp_wled_enable(gwled, gwled->lab_base, state);
+ udelay(QPNP_WLED_LAB_START_DLY_US + 1);
if (rc < 0)
return rc;
- udelay(QPNP_WLED_LAB_START_DLY_US + 1);
} else {
reg = pm8x41_wled_reg_read(QPNP_WLED_LAB_IBB_RDY_REG(gwled->lab_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MODULE_EN_MASK;
reg |= (state << QPNP_WLED_MODULE_EN_SHIFT);
@@ -127,11 +127,11 @@
/* enable / disable wled brightness */
void qpnp_wled_enable_backlight(int enable)
{
- int level, rc;
+ int rc;
if (!gwled) {
dprintf(CRITICAL, "%s: wled is not initialized yet\n", __func__);
- return ERROR;
+ return;
}
if (enable) {
@@ -153,13 +153,10 @@
static int qpnp_wled_set_display_type(struct qpnp_wled *wled, uint16_t base_addr)
{
- int rc;
uint8_t reg = 0;
/* display type */
reg = pm8x41_wled_reg_read(QPNP_WLED_DISP_SEL_REG(base_addr));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_DISP_SEL_MASK;
reg |= (wled->disp_type_amoled << QPNP_WLED_DISP_SEL_SHIFT);
@@ -170,13 +167,10 @@
static int qpnp_wled_module_ready(struct qpnp_wled *wled, uint16_t base_addr, bool state)
{
- int rc;
uint8_t reg;
reg = pm8x41_wled_reg_read(
QPNP_WLED_MODULE_RDY_REG(base_addr));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MODULE_RDY_MASK;
reg |= (state << QPNP_WLED_MODULE_RDY_SHIFT);
pm8x41_wled_reg_write(QPNP_WLED_MODULE_RDY_REG(base_addr), reg);
@@ -198,8 +192,6 @@
/* Configure the FEEDBACK OUTPUT register */
reg = pm8x41_wled_reg_read(
QPNP_WLED_FDBK_OP_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_FDBK_OP_MASK;
reg |= wled->fdbk_op;
pm8x41_wled_reg_write(QPNP_WLED_FDBK_OP_REG(wled->ctrl_base), reg);
@@ -212,8 +204,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_VREF_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_VREF_MASK;
temp = wled->vref_mv - QPNP_WLED_VREF_MIN_MV;
reg |= (temp / QPNP_WLED_VREF_STEP_MV);
@@ -227,8 +217,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_ILIM_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_ILIM_MASK;
reg |= (wled->ilim_ma / QPNP_WLED_ILIM_STEP_MA);
pm8x41_wled_reg_write(QPNP_WLED_ILIM_REG(wled->ctrl_base), reg);
@@ -241,8 +229,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_BOOST_DUTY_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_BOOST_DUTY_MASK;
reg |= (wled->boost_duty_ns / QPNP_WLED_BOOST_DUTY_STEP_NS);
pm8x41_wled_reg_write(QPNP_WLED_BOOST_DUTY_REG(wled->ctrl_base), reg);
@@ -255,8 +241,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_SWITCH_FREQ_MASK;
reg |= temp;
pm8x41_wled_reg_write(QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base), reg);
@@ -278,8 +262,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_OVP_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_OVP_MASK;
reg |= temp;
pm8x41_wled_reg_write(QPNP_WLED_OVP_REG(wled->ctrl_base), reg);
@@ -299,8 +281,6 @@
temp = 0;
}
reg = pm8x41_wled_reg_read(QPNP_WLED_MOD_REG(wled->sink_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MOD_FREQ_MASK;
reg |= (temp << QPNP_WLED_MOD_FREQ_SHIFT);
@@ -331,8 +311,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_HYB_THRES_REG(wled->sink_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_HYB_THRES_MASK;
temp = fls(wled->hyb_thres / QPNP_WLED_HYB_THRES_MIN) - 1;
@@ -349,24 +327,18 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_MOD_EN_REG(wled->sink_base,
wled->strings[i]));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MOD_EN_MASK;
reg |= (QPNP_WLED_MOD_EN << QPNP_WLED_MOD_EN_SHFT);
pm8x41_wled_reg_write(QPNP_WLED_MOD_EN_REG(wled->sink_base,
wled->strings[i]), reg);
/* SYNC DELAY */
- if (wled->sync_dly_us < QPNP_WLED_SYNC_DLY_MIN_US)
- wled->sync_dly_us = QPNP_WLED_SYNC_DLY_MIN_US;
- else if (wled->sync_dly_us > QPNP_WLED_SYNC_DLY_MAX_US)
+ if (wled->sync_dly_us > QPNP_WLED_SYNC_DLY_MAX_US)
wled->sync_dly_us = QPNP_WLED_SYNC_DLY_MAX_US;
reg = pm8x41_wled_reg_read(
QPNP_WLED_SYNC_DLY_REG(wled->sink_base,
wled->strings[i]));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_SYNC_DLY_MASK;
temp = wled->sync_dly_us / QPNP_WLED_SYNC_DLY_STEP_US;
reg |= temp;
@@ -374,16 +346,12 @@
wled->strings[i]), reg);
/* FULL SCALE CURRENT */
- if (wled->fs_curr_ua < QPNP_WLED_FS_CURR_MIN_UA)
- wled->fs_curr_ua = QPNP_WLED_FS_CURR_MIN_UA;
- else if (wled->fs_curr_ua > QPNP_WLED_FS_CURR_MAX_UA)
+ if (wled->fs_curr_ua > QPNP_WLED_FS_CURR_MAX_UA)
wled->fs_curr_ua = QPNP_WLED_FS_CURR_MAX_UA;
reg = pm8x41_wled_reg_read(
QPNP_WLED_FS_CURR_REG(wled->sink_base,
wled->strings[i]));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_FS_CURR_MASK;
temp = wled->fs_curr_ua / QPNP_WLED_FS_CURR_STEP_UA;
reg |= temp;
@@ -394,8 +362,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_CABC_REG(wled->sink_base,
wled->strings[i]));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_CABC_MASK;
reg |= (wled->en_cabc << QPNP_WLED_CABC_SHIFT);
pm8x41_wled_reg_write(QPNP_WLED_CABC_REG(wled->sink_base,
@@ -404,8 +370,6 @@
/* Enable CURRENT SINK */
reg = pm8x41_wled_reg_read(
QPNP_WLED_CURR_SINK_REG(wled->sink_base));
- if (reg < 0)
- return reg;
temp = wled->strings[i] + QPNP_WLED_CURR_SINK_SHIFT;
reg |= (1 << temp);
pm8x41_wled_reg_write(QPNP_WLED_CURR_SINK_REG(wled->sink_base), reg);
@@ -414,8 +378,6 @@
/* LAB fast precharge */
reg = pm8x41_wled_reg_read(
QPNP_WLED_LAB_FAST_PC_REG(wled->lab_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_LAB_FAST_PC_MASK;
reg |= (wled->lab_fast_precharge << QPNP_WLED_LAB_FAST_PC_SHIFT);
pm8x41_wled_reg_write(QPNP_WLED_LAB_FAST_PC_REG(wled->lab_base), reg);
@@ -431,22 +393,27 @@
return rc;
/* IBB active bias */
- if (wled->ibb_pwrup_dly_ms < QPNP_WLED_IBB_PWRUP_DLY_MIN_MS)
- wled->ibb_pwrup_dly_ms = QPNP_WLED_IBB_PWRUP_DLY_MIN_MS;
- else if (wled->ibb_pwrup_dly_ms > QPNP_WLED_IBB_PWRUP_DLY_MAX_MS)
+ if (wled->ibb_pwrup_dly_ms > QPNP_WLED_IBB_PWRUP_DLY_MAX_MS)
wled->ibb_pwrup_dly_ms = QPNP_WLED_IBB_PWRUP_DLY_MAX_MS;
+ if (wled->ibb_pwrdn_dly_ms > QPNP_WLED_IBB_PWRDN_DLY_MAX_MS)
+ wled->ibb_pwrdn_dly_ms = QPNP_WLED_IBB_PWRDN_DLY_MAX_MS;
+
reg = pm8x41_wled_reg_read(
QPNP_WLED_IBB_BIAS_REG(wled->ibb_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_IBB_BIAS_MASK;
reg |= (!wled->ibb_bias_active << QPNP_WLED_IBB_BIAS_SHIFT);
- temp = fls(wled->ibb_pwrup_dly_ms) - 1;
+ temp = wled->ibb_pwrup_dly_ms;
reg &= QPNP_WLED_IBB_PWRUP_DLY_MASK;
reg |= (temp << QPNP_WLED_IBB_PWRUP_DLY_SHIFT);
+ /* Power down delay bits could already be set, clear them before
+ * or'ing new values
+ */
+ reg &= ~(PWRDN_DLY2_MASK);
+ reg |= wled->ibb_pwrdn_dly_ms;
+ reg |= (wled->ibb_discharge_en << 2);
rc = qpnp_wled_sec_access(wled, wled->ibb_base);
if (rc)
@@ -464,13 +431,17 @@
if (rc < 0)
return rc;
+ rc = qpnp_labibb_regulator_set_voltage(wled);
+ if (rc < 0)
+ return rc;
+
return 0;
}
/* Setup wled default parameters */
-static int qpnp_wled_setup(struct qpnp_wled *wled)
+static int qpnp_wled_setup(struct qpnp_wled *wled, struct qpnp_wled_config_data *config)
{
- int rc, i;
+ int i;
wled->sink_base = QPNP_WLED_SINK_BASE;
wled->ctrl_base = QPNP_WLED_CTRL_BASE;
@@ -501,16 +472,24 @@
wled->strings[i] = i;
wled->ibb_bias_active = false;
- wled->ibb_pwrup_dly_ms = 8;
- wled->lab_fast_precharge = false;
- wled->disp_type_amoled = false;
+ wled->lab_fast_precharge = true;
+ wled->ibb_pwrup_dly_ms = config->pwr_up_delay;
+ wled->ibb_pwrdn_dly_ms = config->pwr_down_delay;
+ wled->ibb_discharge_en = config->ibb_discharge_en;
+ wled->disp_type_amoled = config->display_type;
+ wled->lab_min_volt = config->lab_min_volt;
+ wled->lab_max_volt = config->lab_max_volt;
+ wled->ibb_min_volt = config->ibb_min_volt;
+ wled->ibb_max_volt = config->ibb_max_volt;
+ wled->ibb_init_volt = config->ibb_init_volt;
+ wled->lab_init_volt = config->lab_init_volt;
return 0;
}
-int qpnp_wled_init()
+int qpnp_wled_init(struct qpnp_wled_config_data *config)
{
- int rc, i;
+ int rc;
struct qpnp_wled *wled;
wled = malloc(sizeof(struct qpnp_wled));
@@ -519,7 +498,7 @@
memset(wled, 0, sizeof(struct qpnp_wled));
- rc = qpnp_wled_setup(wled);
+ rc = qpnp_wled_setup(wled, config);
if (rc) {
dprintf(CRITICAL, "Setting WLED parameters failed\n");
return rc;
@@ -535,3 +514,56 @@
return rc;
}
+
+static int qpnp_labibb_regulator_set_voltage(struct qpnp_wled *wled)
+{
+ int rc = -1;
+ uint32_t new_uV;
+ uint8_t val, mask=0;
+
+ if (wled->lab_min_volt < wled->lab_init_volt) {
+ dprintf(CRITICAL,"qpnp_lab_regulator_set_voltage failed, min_uV %d is less than init volt %d\n",
+ wled->lab_min_volt, wled->lab_init_volt);
+ return rc;
+ }
+
+ val = (((wled->lab_min_volt - wled->lab_init_volt) + (IBB_LAB_VREG_STEP_SIZE - 1)) / IBB_LAB_VREG_STEP_SIZE);
+ new_uV = val * IBB_LAB_VREG_STEP_SIZE + wled->lab_init_volt;
+
+ if (new_uV > wled->lab_max_volt) {
+ dprintf(CRITICAL,"qpnp_ibb_regulator_set_voltage unable to set voltage (%d %d)\n",
+ wled->lab_min_volt, wled->lab_max_volt);
+ return rc;
+ }
+ val |= QPNP_LAB_OUTPUT_OVERRIDE_EN;
+ mask = pm8x41_wled_reg_read(wled->lab_base + QPNP_LABIBB_OUTPUT_VOLTAGE);
+ mask &= ~(QPNP_LAB_SET_VOLTAGE_MASK | QPNP_LAB_OUTPUT_OVERRIDE_EN);
+ mask |= val & (QPNP_LAB_SET_VOLTAGE_MASK | QPNP_LAB_OUTPUT_OVERRIDE_EN);
+
+ pm8x41_wled_reg_write(wled->lab_base + QPNP_LABIBB_OUTPUT_VOLTAGE, mask);
+ udelay(2);
+
+ /* IBB Set Voltage */
+ if (wled->ibb_min_volt < wled->ibb_init_volt) {
+ dprintf(CRITICAL, "qpnp_ibb_regulator_set_voltage failed, min_uV %d is less than init volt %d\n",
+ wled->ibb_min_volt, wled->ibb_init_volt);
+ return rc;
+ }
+
+ val = (((wled->ibb_min_volt - wled->ibb_init_volt) + (IBB_LAB_VREG_STEP_SIZE - 1)) / IBB_LAB_VREG_STEP_SIZE);
+ new_uV = val * IBB_LAB_VREG_STEP_SIZE + wled->ibb_init_volt;
+ if (new_uV > wled->ibb_max_volt) {
+ dprintf(CRITICAL,"qpnp_ibb_regulator_set_voltage unable to set voltage %d %d\n",
+ wled->ibb_min_volt, wled->ibb_max_volt);
+ return rc;
+ }
+ val |= QPNP_LAB_OUTPUT_OVERRIDE_EN;
+ mask = pm8x41_wled_reg_read(wled->ibb_base + QPNP_LABIBB_OUTPUT_VOLTAGE);
+ udelay(2);
+ mask &= ~(QPNP_IBB_SET_VOLTAGE_MASK | QPNP_LAB_OUTPUT_OVERRIDE_EN);
+ mask |= (val & (QPNP_IBB_SET_VOLTAGE_MASK | QPNP_LAB_OUTPUT_OVERRIDE_EN));
+
+ pm8x41_wled_reg_write(wled->ibb_base + QPNP_LABIBB_OUTPUT_VOLTAGE,mask);
+
+ return 0;
+}
diff --git a/include/dev/fbcon.h b/include/dev/fbcon.h
index a817675..2587277 100644
--- a/include/dev/fbcon.h
+++ b/include/dev/fbcon.h
@@ -2,7 +2,7 @@
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -42,7 +42,6 @@
uint32_t width; // logo's width, little endian
uint32_t height; // logo's height, little endian
uint32_t offset;
- unsigned char reserved[512-20];
};
struct fbimage {
diff --git a/include/dev/flash-ubi.h b/include/dev/flash-ubi.h
new file mode 100644
index 0000000..50577cc
--- /dev/null
+++ b/include/dev/flash-ubi.h
@@ -0,0 +1,158 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FLASH_UBI_H_
+#define _FLASH_UBI_H_
+
+#include <sys/types.h>
+#include <lib/ptable.h>
+#include <stdint.h>
+
+struct __attribute__ ((packed)) ubifs_ch {
+ uint32_t magic;
+ uint32_t crc;
+ uint64_t sqnum;
+ uint32_t len;
+#define UBIFS_SB_NODE 6
+ uint8_t node_type;
+ uint8_t group_type;
+ uint8_t padding[2];
+};
+
+/* UBIFS superblock node */
+struct __attribute__ ((packed)) ubifs_sb_node {
+ struct ubifs_ch ch;
+ uint8_t padding[2];
+ uint8_t key_hash;
+ uint8_t key_fmt;
+#define UBIFS_FLG_SPACE_FIXUP 0x04
+ uint32_t flags;
+ uint32_t min_io_size;
+ uint32_t leb_size;
+ uint32_t leb_cnt;
+ uint32_t max_leb_cnt;
+ uint64_t max_bud_bytes;
+ uint32_t log_lebs;
+ uint32_t lpt_lebs;
+ uint32_t orph_lebs;
+ uint32_t jhead_cnt;
+ uint32_t fanout;
+ uint32_t lsave_cnt;
+ uint32_t fmt_version;
+ uint16_t default_compr;
+ uint8_t padding1[2];
+ uint32_t rp_uid;
+ uint32_t rp_gid;
+ uint64_t rp_size;
+ uint32_t time_gran;
+ uint8_t uuid[16];
+ uint32_t ro_compat_version;
+ uint8_t padding2[3968];
+};
+
+/* Erase counter header magic number (ASCII "UBI#") */
+#define UBI_EC_HDR_MAGIC 0x55424923
+
+#define UBI_MAGIC "UBI#"
+#define UBI_MAGIC_SIZE 0x04
+
+#define UBI_VERSION 1
+#define UBI_MAX_ERASECOUNTER 0x7FFFFFFF
+#define UBI_IMAGE_SEQ_BASE 0x12345678
+#define UBI_DEF_ERACE_COUNTER 0
+#define UBI_CRC32_INIT 0xFFFFFFFFU
+#define UBIFS_CRC32_INIT 0xFFFFFFFFU
+
+/* Erase counter header fields */
+struct __attribute__ ((packed)) ubi_ec_hdr {
+ uint32_t magic;
+ uint8_t version;
+ uint8_t padding1[3];
+ uint64_t ec; /* Warning: the current limit is 31-bit anyway! */
+ uint32_t vid_hdr_offset;
+ uint32_t data_offset;
+ uint32_t image_seq;
+ uint8_t padding2[32];
+ uint32_t hdr_crc;
+};
+
+/* Volume identifier header fields */
+struct __attribute__ ((packed)) ubi_vid_hdr {
+ uint32_t magic;
+ uint8_t version;
+ uint8_t vol_type;
+ uint8_t copy_flag;
+ uint8_t compat;
+ uint32_t vol_id;
+ uint32_t lnum;
+ uint8_t padding1[4];
+ uint32_t data_size;
+ uint32_t used_ebs;
+ uint32_t data_pad;
+ uint32_t data_crc;
+ uint8_t padding2[4];
+ uint64_t sqnum;
+ uint8_t padding3[12];
+ uint32_t hdr_crc;
+};
+
+#define UBI_EC_HDR_SIZE sizeof(struct ubi_ec_hdr)
+#define UBI_VID_HDR_SIZE sizeof(struct ubi_vid_hdr)
+#define UBI_EC_HDR_SIZE_CRC (UBI_EC_HDR_SIZE - sizeof(uint32_t))
+#define UBI_VID_HDR_SIZE_CRC (UBI_VID_HDR_SIZE - sizeof(uint32_t))
+
+#define UBI_MAX_VOLUMES 128
+#define UBI_INTERNAL_VOL_START (0x7FFFFFFF - 4096)
+#define UBI_LAYOUT_VOLUME_ID UBI_INTERNAL_VOL_START
+#define UBI_FM_SB_VOLUME_ID (UBI_INTERNAL_VOL_START + 1)
+
+/**
+ * struct ubi_scan_info - UBI scanning information.
+ * @ec: erase counters or eraseblock status for all eraseblocks
+ * @mean_ec: mean erase counter
+ * @bad_cnt: count of bad eraseblocks
+ * @good_cnt: count of non-bad eraseblocks
+ * @empty_cnt: count of empty eraseblocks
+ * @vid_hdr_offs: volume ID header offset from the found EC headers (%-1 means
+ * undefined)
+ * @data_offs: data offset from the found EC headers (%-1 means undefined)
+ * @image_seq: image sequence
+ */
+struct ubi_scan_info {
+ uint64_t *ec;
+ uint64_t mean_ec;
+ int bad_cnt;
+ int good_cnt;
+ int empty_cnt;
+ unsigned vid_hdr_offs;
+ unsigned data_offs;
+ uint32_t image_seq;
+};
+
+int flash_ubi_img(struct ptentry *ptn, void *data, unsigned size);
+#endif
diff --git a/include/dev/flash.h b/include/dev/flash.h
index 6c2402d..9c41561 100644
--- a/include/dev/flash.h
+++ b/include/dev/flash.h
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
@@ -40,6 +41,7 @@
struct flash_info {
unsigned id;
+ unsigned id2;
unsigned type;
unsigned vendor;
unsigned device;
@@ -70,13 +72,14 @@
unsigned offset, void *data, unsigned bytes);
int flash_write(struct ptentry *ptn, unsigned write_extra_bytes, const void *data,
unsigned bytes);
-
static inline int flash_read(struct ptentry *ptn, unsigned offset, void *data,
unsigned bytes)
{
return flash_read_ext(ptn, 0, offset, data, bytes);
}
unsigned flash_page_size(void);
+unsigned flash_block_size(void);
+unsigned flash_spare_size(void);
int flash_ecc_bch_enabled(void);
diff --git a/include/platform.h b/include/platform.h
index a76c68b..e71c407 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -53,6 +53,7 @@
unsigned board_machtype(void);
unsigned board_platform_id(void);
unsigned check_reboot_mode(void);
+unsigned check_hard_reboot_mode(void);
void platform_uninit_timer(void);
void reboot_device(unsigned);
int set_download_mode(enum dload_mode mode);
@@ -60,4 +61,8 @@
uint32_t platform_get_sclk_count(void);
void clock_config_cdc(uint32_t interface);
int platform_is_msm8939();
+int platform_is_msm8909();
+int platform_is_msm8992();
+int boot_device_mask(int);
+uint32_t platform_detect_panel();
#endif
diff --git a/include/string.h b/include/string.h
index 661e746..593ecf2 100644
--- a/include/string.h
+++ b/include/string.h
@@ -33,6 +33,8 @@
void *memchr (void const *, int, size_t) __PURE;
int memcmp (void const *, const void *, size_t) __PURE;
void *memcpy (void *, void const *, size_t);
+/* secure memcpy, does not copy beyong size of dest buffer*/
+size_t memscpy (void *, size_t, void const *, size_t);
void *memmove(void *, void const *, size_t);
void *memset (void *, int, size_t);
diff --git a/include/target.h b/include/target.h
index 055634b..772afdf 100644
--- a/include/target.h
+++ b/include/target.h
@@ -83,4 +83,7 @@
bool target_use_signed_kernel(void);
int _emmc_recovery_init(void);
void ulpi_write(unsigned val, unsigned reg);
+void target_crypto_init_params(void);
+int target_cont_splash_screen(void);
+bool target_build_variant_user();
#endif
diff --git a/lib/debug/debug.c b/lib/debug/debug.c
index f239bbe..e62f806 100644
--- a/lib/debug/debug.c
+++ b/lib/debug/debug.c
@@ -43,6 +43,7 @@
__stack_chk_fail (void)
{
panic("stack smashing detected.");
+ for(;;);
}
void spin(uint32_t usecs)
@@ -97,7 +98,7 @@
char ts_buf[13];
int err;
- snprintf(ts_buf, sizeof(ts_buf), "[%u] ", current_time());
+ snprintf(ts_buf, sizeof(ts_buf), "[%u] ",(unsigned int)current_time());
dputs(ALWAYS, ts_buf);
va_list ap;
diff --git a/lib/libc/string/memscpy.c b/lib/libc/string/memscpy.c
new file mode 100644
index 0000000..3dd4d6b
--- /dev/null
+++ b/lib/libc/string/memscpy.c
@@ -0,0 +1,37 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Fundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <string.h>
+
+size_t memscpy(void *dest, size_t dst_size, const void *src, size_t src_size)
+{
+ size_t copy_size = dst_size < src_size ? dst_size : src_size;
+ memcpy(dest, src, copy_size);
+ return copy_size;
+}
diff --git a/lib/libc/string/rules.mk b/lib/libc/string/rules.mk
index fc1ceb2..97a5db8 100644
--- a/lib/libc/string/rules.mk
+++ b/lib/libc/string/rules.mk
@@ -8,6 +8,7 @@
memcpy \
memmove \
memset \
+ memscpy \
strcat \
strchr \
strcmp \
diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c
index 3267a1c..c43b83e 100644
--- a/lib/libfdt/fdt.c
+++ b/lib/libfdt/fdt.c
@@ -91,7 +91,7 @@
const char *p;
if (fdt_version(fdt) >= 0x11)
- if (((offset + len) < offset)
+ if (((int)(offset + len) < offset)
|| ((offset + len) > fdt_size_dt_struct(fdt)))
return NULL;
@@ -226,7 +226,7 @@
{
FDT_CHECK_HEADER(fdt);
- if (fdt_totalsize(fdt) > bufsize)
+ if (fdt_totalsize(fdt) > (uint32_t)bufsize)
return -FDT_ERR_NOSPACE;
memmove(buf, fdt, fdt_totalsize(fdt));
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 02b6d68..1e6b2e7 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -85,7 +85,7 @@
{
const char *p = fdt_string(fdt, stroffset);
- return (strlen(p) == len) && (memcmp(p, s, len) == 0);
+ return (strlen(p) == (size_t)len) && (memcmp(p, s, len) == 0);
}
int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
@@ -494,7 +494,7 @@
{
int offset;
- if ((phandle == 0) || (phandle == -1))
+ if ((phandle == 0))
return -FDT_ERR_BADPHANDLE;
FDT_CHECK_HEADER(fdt);
diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index 269073c..974108e 100644
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
@@ -467,9 +467,9 @@
fdtend = fdtstart + fdt_totalsize(fdt);
FDT_CHECK_HEADER(fdt);
- if ((fdt_num_mem_rsv(fdt)+1) > (UINT_MAX / sizeof(struct fdt_reserve_entry))) {
+ if ((fdt_num_mem_rsv(fdt) + 1) >
+ (int) (UINT_MAX / sizeof(struct fdt_reserve_entry)))
return err;
- }
mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
* sizeof(struct fdt_reserve_entry);
@@ -504,7 +504,7 @@
/* Need to reorder */
newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
+ struct_size + fdt_size_dt_strings(fdt);
- if (bufsize < newsize)
+ if (bufsize < (int) newsize)
return -FDT_ERR_NOSPACE;
/* First attempt to build converted tree at beginning of buffer */
diff --git a/lib/libfdt/fdt_strerror.c b/lib/libfdt/fdt_strerror.c
index e6c3cee..f1ce5ad 100644
--- a/lib/libfdt/fdt_strerror.c
+++ b/lib/libfdt/fdt_strerror.c
@@ -85,7 +85,7 @@
return "<valid offset/length>";
else if (errval == 0)
return "<no error>";
- else if (errval > -FDT_ERRTABSIZE) {
+ else if (errval > (int) -FDT_ERRTABSIZE) {
const char *s = fdt_errtable[-errval].str;
if (s)
diff --git a/lib/libfdt/fdt_sw.c b/lib/libfdt/fdt_sw.c
index 55ebebf..c8d998c 100644
--- a/lib/libfdt/fdt_sw.c
+++ b/lib/libfdt/fdt_sw.c
@@ -78,7 +78,7 @@
spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt)
- fdt_size_dt_strings(fdt);
- if ((offset + len < offset) || (offset + len > spaceleft))
+ if (((int)(offset + len) < offset) || ((int)(offset + len) > spaceleft))
return NULL;
fdt_set_size_dt_struct(fdt, offset + len);
@@ -89,7 +89,7 @@
{
void *fdt = buf;
- if (bufsize < sizeof(struct fdt_header))
+ if (bufsize < (int)sizeof(struct fdt_header))
return -FDT_ERR_NOSPACE;
memset(buf, 0, bufsize);
@@ -180,7 +180,7 @@
/* Add it */
offset = -strtabsize - len;
struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
- if (fdt_totalsize(fdt) + offset < struct_top)
+ if ((int)(fdt_totalsize(fdt) + offset) < struct_top)
return 0; /* no more room :( */
memcpy(strtab + offset, s, len);
diff --git a/lib/openssl/crypto/asn1/a_int.c b/lib/openssl/crypto/asn1/a_int.c
index c6fd204..3348b87 100644
--- a/lib/openssl/crypto/asn1/a_int.c
+++ b/lib/openssl/crypto/asn1/a_int.c
@@ -273,7 +273,7 @@
{
ASN1_INTEGER *ret=NULL;
const unsigned char *p;
- unsigned char *to,*s;
+ unsigned char *s;
long len;
int inf,tag,xclass;
int i;
@@ -308,7 +308,6 @@
i=ERR_R_MALLOC_FAILURE;
goto err;
}
- to=s;
ret->type=V_ASN1_INTEGER;
if(len) {
if ((*p == 0) && (len != 1))
diff --git a/lib/openssl/crypto/asn1/a_strnid.c b/lib/openssl/crypto/asn1/a_strnid.c
index 753021a..f0af42f 100644
--- a/lib/openssl/crypto/asn1/a_strnid.c
+++ b/lib/openssl/crypto/asn1/a_strnid.c
@@ -57,10 +57,12 @@
*/
#include <stdio.h>
+#include <stdlib.h>
#include <ctype.h>
#include "cryptlib.h"
#include <openssl/asn1.h>
#include <openssl/objects.h>
+#include "../../e_os.h"
static STACK_OF(ASN1_STRING_TABLE) *stable = NULL;
diff --git a/lib/openssl/crypto/asn1/ameth_lib.c b/lib/openssl/crypto/asn1/ameth_lib.c
index c52f9c9..5565ba4 100644
--- a/lib/openssl/crypto/asn1/ameth_lib.c
+++ b/lib/openssl/crypto/asn1/ameth_lib.c
@@ -59,6 +59,7 @@
#include "cryptlib.h"
#include <openssl/asn1t.h>
#include <openssl/x509.h>
+#include <string.h>
#ifndef OPENSSL_NO_ENGINE
#include <openssl/engine.h>
#endif
diff --git a/lib/openssl/crypto/asn1/n_pkey.c b/lib/openssl/crypto/asn1/n_pkey.c
index 60bc437..e7d0439 100644
--- a/lib/openssl/crypto/asn1/n_pkey.c
+++ b/lib/openssl/crypto/asn1/n_pkey.c
@@ -242,7 +242,7 @@
int sgckey)
{
RSA *ret=NULL;
- const unsigned char *p, *kp;
+ const unsigned char *p;
NETSCAPE_ENCRYPTED_PKEY *enckey = NULL;
p = *pp;
@@ -265,7 +265,6 @@
ASN1err(ASN1_F_D2I_RSA_NET,ASN1_R_UNSUPPORTED_ENCRYPTION_ALGORITHM);
goto err;
}
- kp = enckey->enckey->digest->data;
if (cb == NULL)
cb=EVP_read_pw_string;
if ((ret=d2i_RSA_NET_2(a, enckey->enckey->digest,cb, sgckey)) == NULL) goto err;
diff --git a/lib/openssl/crypto/asn1/t_crl.c b/lib/openssl/crypto/asn1/t_crl.c
index bdb244c..ee5a687 100644
--- a/lib/openssl/crypto/asn1/t_crl.c
+++ b/lib/openssl/crypto/asn1/t_crl.c
@@ -87,7 +87,7 @@
STACK_OF(X509_REVOKED) *rev;
X509_REVOKED *r;
long l;
- int i, n;
+ int i;
char *p;
BIO_printf(out, "Certificate Revocation List (CRL):\n");
@@ -107,7 +107,6 @@
else BIO_printf(out,"NONE");
BIO_printf(out,"\n");
- n=X509_CRL_get_ext_count(x);
X509V3_extensions_print(out, "CRL extensions",
x->crl->extensions, 0, 8);
diff --git a/lib/openssl/crypto/asn1/tasn_dec.c b/lib/openssl/crypto/asn1/tasn_dec.c
index 3bee439..87d7dfd 100644
--- a/lib/openssl/crypto/asn1/tasn_dec.c
+++ b/lib/openssl/crypto/asn1/tasn_dec.c
@@ -168,7 +168,7 @@
int i;
int otag;
int ret = 0;
- ASN1_VALUE *pchval, **pchptr, *ptmpval;
+ ASN1_VALUE **pchptr, *ptmpval;
if (!pval)
return 0;
if (aux && aux->asn1_cb)
@@ -319,7 +319,6 @@
goto err;
}
/* CHOICE type, try each possibility in turn */
- pchval = NULL;
p = *in;
for (i = 0, tt=it->templates; i < it->tcount; i++, tt++)
{
diff --git a/lib/openssl/crypto/asn1/x_bignum.c b/lib/openssl/crypto/asn1/x_bignum.c
index 9cf3204..827d7af 100644
--- a/lib/openssl/crypto/asn1/x_bignum.c
+++ b/lib/openssl/crypto/asn1/x_bignum.c
@@ -81,7 +81,8 @@
bn_free,
0,
bn_c2i,
- bn_i2c
+ bn_i2c,
+ NULL
};
ASN1_ITEM_start(BIGNUM)
diff --git a/lib/openssl/crypto/bn/bn_mul.c b/lib/openssl/crypto/bn/bn_mul.c
index a0e9ec3..ce7ca1d 100644
--- a/lib/openssl/crypto/bn/bn_mul.c
+++ b/lib/openssl/crypto/bn/bn_mul.c
@@ -551,7 +551,7 @@
int tna, int tnb, BN_ULONG *t)
{
int i,j,n2=n*2;
- int c1,c2,neg,zero;
+ int c1,c2,neg;
BN_ULONG ln,lo,*p;
# ifdef BN_COUNT
@@ -567,7 +567,7 @@
/* r=(a[0]-a[1])*(b[1]-b[0]) */
c1=bn_cmp_part_words(a,&(a[n]),tna,n-tna);
c2=bn_cmp_part_words(&(b[n]),b,tnb,tnb-n);
- zero=neg=0;
+ neg=0;
switch (c1*3+c2)
{
case -4:
@@ -575,8 +575,6 @@
bn_sub_part_words(&(t[n]),b, &(b[n]),tnb,n-tnb); /* - */
break;
case -3:
- zero=1;
- /* break; */
case -2:
bn_sub_part_words(t, &(a[n]),a, tna,tna-n); /* - */
bn_sub_part_words(&(t[n]),&(b[n]),b, tnb,tnb-n); /* + */
@@ -585,16 +583,12 @@
case -1:
case 0:
case 1:
- zero=1;
- /* break; */
case 2:
bn_sub_part_words(t, a, &(a[n]),tna,n-tna); /* + */
bn_sub_part_words(&(t[n]),b, &(b[n]),tnb,n-tnb); /* - */
neg=1;
break;
case 3:
- zero=1;
- /* break; */
case 4:
bn_sub_part_words(t, a, &(a[n]),tna,n-tna);
bn_sub_part_words(&(t[n]),&(b[n]),b, tnb,tnb-n);
@@ -1012,7 +1006,6 @@
{
if (i >= -1 && i <= 1)
{
- int sav_j =0;
/* Find out the power of two lower or equal
to the longest of the two numbers */
if (i >= 0)
@@ -1023,7 +1016,6 @@
{
j = BN_num_bits_word((BN_ULONG)bl);
}
- sav_j = j;
j = 1<<(j-1);
assert(j <= al || j <= bl);
k = j+j;
diff --git a/lib/openssl/crypto/conf/conf_api.c b/lib/openssl/crypto/conf/conf_api.c
index d39503c..586b03c 100644
--- a/lib/openssl/crypto/conf/conf_api.c
+++ b/lib/openssl/crypto/conf/conf_api.c
@@ -65,6 +65,7 @@
#include <assert.h>
#include <string.h>
+#include <stdlib.h>
#include <openssl/conf.h>
#include <openssl/conf_api.h>
#include <openssl/e_os.h>
diff --git a/lib/openssl/crypto/conf/conf_def.c b/lib/openssl/crypto/conf/conf_def.c
index 0b571b0..5e8506c 100644
--- a/lib/openssl/crypto/conf/conf_def.c
+++ b/lib/openssl/crypto/conf/conf_def.c
@@ -68,6 +68,7 @@
#include "conf_def.h"
#include <openssl/buffer.h>
#include <openssl/err.h>
+#include <bio.h>
static char *eat_ws(CONF *conf, char *p);
static char *eat_alpha_numeric(CONF *conf, char *p);
@@ -187,9 +188,9 @@
BIO *in=NULL;
#ifdef OPENSSL_SYS_VMS
- in=BIO_new_file(name, "r");
+ in= (BIO *)BIO_new_file(name, "r");
#else
- in=BIO_new_file(name, "rb");
+ in= (BIO *)BIO_new_file(name, "rb");
#endif
if (in == NULL)
{
@@ -213,13 +214,12 @@
int bufnum=0,i,ii;
BUF_MEM *buff=NULL;
char *s,*p,*end;
- int again,n;
+ int again;
long eline=0;
char btmp[DECIMAL_SIZE(eline)+1];
CONF_VALUE *v=NULL,*tv;
CONF_VALUE *sv=NULL;
char *section=NULL,*buf;
- STACK_OF(CONF_VALUE) *section_sk=NULL,*ts;
char *start,*psection,*pname;
void *h = (void *)(conf->data);
@@ -250,8 +250,6 @@
CONF_R_UNABLE_TO_CREATE_NEW_SECTION);
goto err;
}
- section_sk=(STACK_OF(CONF_VALUE) *)sv->value;
-
bufnum=0;
again=0;
for (;;)
@@ -309,7 +307,6 @@
buf=buff->data;
clear_comments(conf, buf);
- n=strlen(buf);
s=eat_ws(conf, buf);
if (IS_EOF(conf,*s)) continue; /* blank line */
if (*s == '[')
@@ -343,7 +340,6 @@
CONF_R_UNABLE_TO_CREATE_NEW_SECTION);
goto err;
}
- section_sk=(STACK_OF(CONF_VALUE) *)sv->value;
continue;
}
else
@@ -406,12 +402,10 @@
CONF_R_UNABLE_TO_CREATE_NEW_SECTION);
goto err;
}
- ts=(STACK_OF(CONF_VALUE) *)tv->value;
}
else
{
tv=sv;
- ts=section_sk;
}
#if 1
if (_CONF_add_string(conf, tv, v) == 0)
@@ -465,9 +459,6 @@
static void clear_comments(CONF *conf, char *p)
{
- char *to;
-
- to=p;
for (;;)
{
if (IS_FCOMMENT(conf,*p))
diff --git a/lib/openssl/crypto/conf/conf_lib.c b/lib/openssl/crypto/conf/conf_lib.c
index 54046de..a82c838 100644
--- a/lib/openssl/crypto/conf/conf_lib.c
+++ b/lib/openssl/crypto/conf/conf_lib.c
@@ -62,6 +62,7 @@
#include <openssl/conf.h>
#include <openssl/conf_api.h>
#include <openssl/lhash.h>
+#include <bio.h>
const char CONF_version[]="CONF" OPENSSL_VERSION_PTEXT;
@@ -94,9 +95,9 @@
BIO *in=NULL;
#ifdef OPENSSL_SYS_VMS
- in=BIO_new_file(file, "r");
+ in= (BIO *)BIO_new_file(file, "r");
#else
- in=BIO_new_file(file, "rb");
+ in= (BIO *)BIO_new_file(file, "rb");
#endif
if (in == NULL)
{
diff --git a/lib/openssl/crypto/err/err.c b/lib/openssl/crypto/err/err.c
index 6237c1b..bd0d402 100644
--- a/lib/openssl/crypto/err/err.c
+++ b/lib/openssl/crypto/err/err.c
@@ -713,7 +713,7 @@
* anyways for now.
*/
#ifdef LK_NO_ERR_STATE
- return
+ return;
#endif
#ifdef _OSD_POSIX
diff --git a/lib/openssl/crypto/evp/encode.c b/lib/openssl/crypto/evp/encode.c
index b42c747..28546a8 100644
--- a/lib/openssl/crypto/evp/encode.c
+++ b/lib/openssl/crypto/evp/encode.c
@@ -235,7 +235,7 @@
int EVP_DecodeUpdate(EVP_ENCODE_CTX *ctx, unsigned char *out, int *outl,
const unsigned char *in, int inl)
{
- int seof= -1,eof=0,rv= -1,ret=0,i,v,tmp,n,ln,tmp2,exp_nl;
+ int seof= -1,eof=0,rv= -1,ret=0,i,v,tmp,n,ln,exp_nl;
unsigned char *d;
n=ctx->num;
@@ -319,7 +319,6 @@
* lines. We process the line and then need to
* accept the '\n' */
if ((v != B64_EOF) && (n >= 64)) exp_nl=1;
- tmp2=v;
if (n > 0)
{
v=EVP_DecodeBlock(out,d,n);
diff --git a/lib/openssl/crypto/evp/m_dss.c b/lib/openssl/crypto/evp/m_dss.c
index 48c2689..7bcc274 100644
--- a/lib/openssl/crypto/evp/m_dss.c
+++ b/lib/openssl/crypto/evp/m_dss.c
@@ -90,6 +90,7 @@
EVP_PKEY_DSA_method,
SHA_CBLOCK,
sizeof(EVP_MD *)+sizeof(SHA_CTX),
+ NULL
};
const EVP_MD *EVP_dss(void)
diff --git a/lib/openssl/crypto/evp/m_dss1.c b/lib/openssl/crypto/evp/m_dss1.c
index 4f03fb7..40460b7 100644
--- a/lib/openssl/crypto/evp/m_dss1.c
+++ b/lib/openssl/crypto/evp/m_dss1.c
@@ -91,6 +91,7 @@
EVP_PKEY_DSA_method,
SHA_CBLOCK,
sizeof(EVP_MD *)+sizeof(SHA_CTX),
+ NULL
};
const EVP_MD *EVP_dss1(void)
diff --git a/lib/openssl/crypto/evp/m_null.c b/lib/openssl/crypto/evp/m_null.c
index cb07216..b6e6d76 100644
--- a/lib/openssl/crypto/evp/m_null.c
+++ b/lib/openssl/crypto/evp/m_null.c
@@ -85,6 +85,7 @@
EVP_PKEY_NULL_method,
0,
sizeof(EVP_MD *),
+ NULL
};
const EVP_MD *EVP_md_null(void)
diff --git a/lib/openssl/crypto/evp/m_ripemd.c b/lib/openssl/crypto/evp/m_ripemd.c
index a1d60ee..fb639d1 100644
--- a/lib/openssl/crypto/evp/m_ripemd.c
+++ b/lib/openssl/crypto/evp/m_ripemd.c
@@ -92,6 +92,7 @@
EVP_PKEY_RSA_method,
RIPEMD160_CBLOCK,
sizeof(EVP_MD *)+sizeof(RIPEMD160_CTX),
+ NULL
};
const EVP_MD *EVP_ripemd160(void)
diff --git a/lib/openssl/crypto/evp/m_sha1.c b/lib/openssl/crypto/evp/m_sha1.c
index 9a2790f..bd8c5e3 100644
--- a/lib/openssl/crypto/evp/m_sha1.c
+++ b/lib/openssl/crypto/evp/m_sha1.c
@@ -91,6 +91,7 @@
EVP_PKEY_RSA_method,
SHA_CBLOCK,
sizeof(EVP_MD *)+sizeof(SHA_CTX),
+ NULL
};
const EVP_MD *EVP_sha1(void)
@@ -128,6 +129,7 @@
EVP_PKEY_RSA_method,
SHA256_CBLOCK,
sizeof(EVP_MD *)+sizeof(SHA256_CTX),
+ NULL
};
const EVP_MD *EVP_sha224(void)
@@ -147,6 +149,7 @@
EVP_PKEY_RSA_method,
SHA256_CBLOCK,
sizeof(EVP_MD *)+sizeof(SHA256_CTX),
+ NULL
};
const EVP_MD *EVP_sha256(void)
@@ -178,6 +181,7 @@
EVP_PKEY_RSA_method,
SHA512_CBLOCK,
sizeof(EVP_MD *)+sizeof(SHA512_CTX),
+ NULL
};
const EVP_MD *EVP_sha384(void)
@@ -197,6 +201,7 @@
EVP_PKEY_RSA_method,
SHA512_CBLOCK,
sizeof(EVP_MD *)+sizeof(SHA512_CTX),
+ NULL
};
const EVP_MD *EVP_sha512(void)
diff --git a/lib/openssl/crypto/mem_dbg.c b/lib/openssl/crypto/mem_dbg.c
index 9a07537..236431e 100644
--- a/lib/openssl/crypto/mem_dbg.c
+++ b/lib/openssl/crypto/mem_dbg.c
@@ -537,7 +537,11 @@
m->addr, m->num);
#endif
if (options & V_CRYPTO_MDEBUG_TIME)
+#ifndef LK_NO_TIME
m->time=time(NULL);
+#else
+ m->time=0;
+#endif
else
m->time=0;
@@ -753,6 +757,10 @@
}
#endif
}
+#else
+static void print_leak_doall_arg(const MEM *m, MEM_LEAK *l)
+{
+}
#endif
static IMPLEMENT_LHASH_DOALL_ARG_FN(print_leak, const MEM, MEM_LEAK)
diff --git a/lib/openssl/crypto/modes/cbc128.c b/lib/openssl/crypto/modes/cbc128.c
index 8f8bd56..af2d93a 100644
--- a/lib/openssl/crypto/modes/cbc128.c
+++ b/lib/openssl/crypto/modes/cbc128.c
@@ -176,7 +176,7 @@
for(n=0; n<16; n+=sizeof(size_t)) {
c = *(size_t *)(in+n);
*(size_t *)(out+n) =
- *(size_t *)(tmp.c+n) ^ *(size_t *)(ivec+n);
+ *(tmp.c+n) ^ *(size_t *)(ivec+n);
*(size_t *)(ivec+n) = c;
}
len -= 16;
diff --git a/lib/openssl/crypto/pkcs7/pk7_doit.c b/lib/openssl/crypto/pkcs7/pk7_doit.c
index 451de84..3bf1a36 100644
--- a/lib/openssl/crypto/pkcs7/pk7_doit.c
+++ b/lib/openssl/crypto/pkcs7/pk7_doit.c
@@ -422,7 +422,6 @@
X509_ALGOR *enc_alg=NULL;
STACK_OF(X509_ALGOR) *md_sk=NULL;
STACK_OF(PKCS7_RECIP_INFO) *rsk=NULL;
- X509_ALGOR *xalg=NULL;
PKCS7_RECIP_INFO *ri=NULL;
i=OBJ_obj2nid(p7->type);
@@ -445,7 +444,6 @@
PKCS7err(PKCS7_F_PKCS7_DATADECODE,PKCS7_R_UNSUPPORTED_CIPHER_TYPE);
goto err;
}
- xalg=p7->d.signed_and_enveloped->enc_data->algorithm;
break;
case NID_pkcs7_enveloped:
rsk=p7->d.enveloped->recipientinfo;
@@ -457,7 +455,6 @@
PKCS7err(PKCS7_F_PKCS7_DATADECODE,PKCS7_R_UNSUPPORTED_CIPHER_TYPE);
goto err;
}
- xalg=p7->d.enveloped->enc_data->algorithm;
break;
default:
PKCS7err(PKCS7_F_PKCS7_DATADECODE,PKCS7_R_UNSUPPORTED_CONTENT_TYPE);
diff --git a/lib/openssl/crypto/pkcs7/pk7_lib.c b/lib/openssl/crypto/pkcs7/pk7_lib.c
index 3ca0952..d411269 100644
--- a/lib/openssl/crypto/pkcs7/pk7_lib.c
+++ b/lib/openssl/crypto/pkcs7/pk7_lib.c
@@ -591,7 +591,6 @@
int PKCS7_set_cipher(PKCS7 *p7, const EVP_CIPHER *cipher)
{
int i;
- ASN1_OBJECT *objtmp;
PKCS7_ENC_CONTENT *ec;
i=OBJ_obj2nid(p7->type);
@@ -614,7 +613,6 @@
PKCS7err(PKCS7_F_PKCS7_SET_CIPHER,PKCS7_R_CIPHER_HAS_NO_OBJECT_IDENTIFIER);
return(0);
}
- objtmp = OBJ_nid2obj(i);
ec->cipher = cipher;
return 1;
diff --git a/lib/openssl/crypto/rsa/rsa_ameth.c b/lib/openssl/crypto/rsa/rsa_ameth.c
index 033e2b6..806c263 100644
--- a/lib/openssl/crypto/rsa/rsa_ameth.c
+++ b/lib/openssl/crypto/rsa/rsa_ameth.c
@@ -352,6 +352,27 @@
{
EVP_PKEY_RSA2,
EVP_PKEY_RSA,
- ASN1_PKEY_ALIAS
+ ASN1_PKEY_ALIAS,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL
}
};
diff --git a/lib/openssl/crypto/rules.mk b/lib/openssl/crypto/rules.mk
index d149473..63c4d0f 100644
--- a/lib/openssl/crypto/rules.mk
+++ b/lib/openssl/crypto/rules.mk
@@ -13,7 +13,8 @@
-I$(LOCAL_DIR)/x509 \
-I$(LOCAL_DIR)/../.. \
-I$(LOCAL_DIR)/../include \
- -I$(LOCAL_DIR)/../include/openssl
+ -I$(LOCAL_DIR)/../include/openssl \
+ -I$(LOCAL_DIR)/../../openssl
OBJS += $(LOCAL_DIR)/bn/asm/armv4-mont.o
diff --git a/lib/openssl/crypto/x509/x509_vfy.c b/lib/openssl/crypto/x509/x509_vfy.c
index 16baf47..67a3051 100644
--- a/lib/openssl/crypto/x509/x509_vfy.c
+++ b/lib/openssl/crypto/x509/x509_vfy.c
@@ -155,7 +155,6 @@
int X509_verify_cert(X509_STORE_CTX *ctx)
{
X509 *x,*xtmp,*chain_ss=NULL;
- X509_NAME *xn;
int bad_chain = 0;
X509_VERIFY_PARAM *param = ctx->param;
int depth,i,ok=0;
@@ -207,7 +206,6 @@
*/
/* If we are self signed, we break */
- xn=X509_get_issuer_name(x);
if (ctx->check_issued(ctx, x,x)) break;
/* If we were passed a cert chain, use it first */
@@ -244,7 +242,6 @@
i=sk_X509_num(ctx->chain);
x=sk_X509_value(ctx->chain,i-1);
- xn = X509_get_subject_name(x);
if (ctx->check_issued(ctx, x, x))
{
/* we have a self signed certificate */
@@ -293,7 +290,6 @@
if (depth < num) break;
/* If we are self signed, we break */
- xn=X509_get_issuer_name(x);
if (ctx->check_issued(ctx,x,x)) break;
ok = ctx->get_issuer(&xtmp, ctx, x);
@@ -311,8 +307,6 @@
num++;
}
- /* we now have our chain, lets check it... */
- xn=X509_get_issuer_name(x);
/* Is last certificate looked up self signed? */
if (!ctx->check_issued(ctx,x,x))
diff --git a/lib/openssl/crypto/x509v3/pcy_tree.c b/lib/openssl/crypto/x509v3/pcy_tree.c
index 92f6b24..04e3d59 100644
--- a/lib/openssl/crypto/x509v3/pcy_tree.c
+++ b/lib/openssl/crypto/x509v3/pcy_tree.c
@@ -341,9 +341,7 @@
const X509_POLICY_CACHE *cache)
{
int i;
- X509_POLICY_LEVEL *last;
X509_POLICY_DATA *data;
- last = curr - 1;
for (i = 0; i < sk_X509_POLICY_DATA_num(cache->data); i++)
{
data = sk_X509_POLICY_DATA_value(cache->data, i);
diff --git a/lib/openssl/crypto/x509v3/v3_ncons.c b/lib/openssl/crypto/x509v3/v3_ncons.c
index ec200ba..d7e9c4c 100644
--- a/lib/openssl/crypto/x509v3/v3_ncons.c
+++ b/lib/openssl/crypto/x509v3/v3_ncons.c
@@ -62,6 +62,7 @@
#include <openssl/asn1t.h>
#include <openssl/conf.h>
#include <openssl/x509v3.h>
+#include <e_os.h>
static void *v2i_NAME_CONSTRAINTS(const X509V3_EXT_METHOD *method,
X509V3_CTX *ctx, STACK_OF(CONF_VALUE) *nval);
diff --git a/lib/openssl/crypto/x509v3/v3_utl.c b/lib/openssl/crypto/x509v3/v3_utl.c
index e030234..87cfceb 100644
--- a/lib/openssl/crypto/x509v3/v3_utl.c
+++ b/lib/openssl/crypto/x509v3/v3_utl.c
@@ -365,7 +365,7 @@
char *tmp, *q;
const unsigned char *p;
int i;
- const static char hexdig[] = "0123456789ABCDEF";
+ static const char hexdig[] = "0123456789ABCDEF";
if(!buffer || !len) return NULL;
if(!(tmp = OPENSSL_malloc(len * 3 + 1))) {
X509V3err(X509V3_F_HEX_TO_STRING,ERR_R_MALLOC_FAILURE);
diff --git a/lib/openssl/e_os.h b/lib/openssl/e_os.h
index f527ae9..26f9bac 100644
--- a/lib/openssl/e_os.h
+++ b/lib/openssl/e_os.h
@@ -62,6 +62,7 @@
#include <openssl/opensslconf.h>
#include <openssl/e_os2.h>
+#include <stdlib.h>
/* <openssl/e_os2.h> contains what we can justify to make visible
* to the outside; this file e_os.h is not part of the exported
* interface. */
@@ -645,7 +646,7 @@
# endif
#endif
-#if defined(sun) && !defined(__svr4__) && !defined(__SVR4)
+#if defined(OPENSSL_LK) || defined(sun) && !defined(__svr4__) && !defined(__SVR4)
/* include headers first, so our defines don't break it */
#include <stdlib.h>
#include <string.h>
@@ -679,9 +680,9 @@
#define IRIX_CC_BUG /* CDS++ up to V2.0Bsomething suffered from the same bug.*/
#endif
-#if defined(OPENSSL_SYS_WINDOWS)
-# define strcasecmp _stricmp
-# define strncasecmp _strnicmp
+#if defined(OPENSSL_SYS_WINDOWS) || defined(OPENSSL_LK)
+# define strcasecmp strcmp
+# define strncasecmp strnicmp
#elif defined(OPENSSL_SYS_VMS)
/* VMS below version 7.0 doesn't have strcasecmp() */
# include "o_str.h"
diff --git a/lib/openssl/include/openssl/bio.h b/lib/openssl/include/openssl/bio.h
index 152802f..f7eac3e 100644
--- a/lib/openssl/include/openssl/bio.h
+++ b/lib/openssl/include/openssl/bio.h
@@ -61,7 +61,7 @@
#include <openssl/e_os2.h>
-#ifndef OPENSSL_NO_FP_API
+#if !defined(OPENSSL_NO_FP_API)|| defined(OPENSSL_LK)
# include <stdio.h>
#endif
#include <stdarg.h>
@@ -564,7 +564,7 @@
int BIO_asn1_get_suffix(BIO *b, asn1_ps_func **psuffix,
asn1_ps_func **psuffix_free);
-# ifndef OPENSSL_NO_FP_API
+# if !(defined(OPENSSL_NO_FP_API)) || defined(OPENSSL_LK)
BIO_METHOD *BIO_s_file(void );
BIO *BIO_new_file(const char *filename, const char *mode);
BIO *BIO_new_fp(FILE *stream, int close_flag);
diff --git a/makefile b/makefile
index 1056726..252903e 100644
--- a/makefile
+++ b/makefile
@@ -97,6 +97,14 @@
# Useful for header files that may be included by one or more source files.
SRCDEPS := $(CONFIGHEADER)
+ifeq ($(VERIFIED_BOOT),1)
+ DEFINES += VERIFIED_BOOT=1
+ DEFINES += _SIGNED_KERNEL=1
+ ifeq ($(DEFAULT_UNLOCK),true)
+ DEFINES += DEFAULT_UNLOCK=1
+ endif
+endif
+
# these need to be filled out by the project/target/platform rules.mk files
TARGET :=
PLATFORM :=
diff --git a/platform/apq8084/include/platform/clock.h b/platform/apq8084/include/platform/clock.h
index a3bb284..0a07c14 100644
--- a/platform/apq8084/include/platform/clock.h
+++ b/platform/apq8084/include/platform/clock.h
@@ -119,4 +119,12 @@
void clock_ce_disable(uint8_t instance);
void clock_usb30_init(void);
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+ uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d);
+void mmss_dsi_clock_disable(uint32_t dual_dsi);
+void mmss_bus_clock_enable(void);
+void mmss_bus_clock_disable(void);
+void mdp_clock_enable(void);
+void mdp_clock_disable();
+
#endif
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index 67a6f5b..fe66038 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -228,6 +228,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
@@ -247,7 +248,8 @@
#define DSI1_PHY_BASE (0xFD923100)
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE (0xFD923000)
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+#define DSI0_REGULATOR_BASE (0xFD922D80)
+#define DSI1_REGULATOR_BASE (0xFD923380)
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
@@ -285,6 +287,10 @@
#define HDMI_BASE 0xFD922100
#define REG_HDMI(off) (HDMI_BASE + (off))
+#define HDMI_ACR_32_0 REG_HDMI(0xC4)
+#define HDMI_ACR_32_1 REG_HDMI(0xC8)
+#define HDMI_ACR_44_0 REG_HDMI(0xCC)
+#define HDMI_ACR_44_1 REG_HDMI(0xD0)
#define HDMI_ACR_48_0 REG_HDMI(0xD4)
#define HDMI_ACR_48_1 REG_HDMI(0xD8)
#define HDMI_AUDIO_PKT_CTRL2 REG_HDMI(0x44)
@@ -304,6 +310,17 @@
#define LPASS_LPAIF_RDDMA_PER_LEN0 0xFE152010
#define LPASS_LPAIF_DEBUG_CTL 0xFE15E004
+#define HDMI_DDC_SPEED REG_HDMI(0x220)
+#define HDMI_DDC_SETUP REG_HDMI(0x224)
+#define HDMI_DDC_REF REG_HDMI(0x27C)
+#define HDMI_DDC_DATA REG_HDMI(0x238)
+#define HDMI_DDC_TRANS0 REG_HDMI(0x228)
+#define HDMI_DDC_TRANS1 REG_HDMI(0x22C)
+#define HDMI_DDC_CTRL REG_HDMI(0x20C)
+#define HDMI_DDC_INT_CTRL REG_HDMI(0x214)
+#define HDMI_DDC_SW_STATUS REG_HDMI(0x218)
+#define HDMI_DDC_ARBITRATION REG_HDMI(0x210)
+
#define HDMI_USEC_REFTIMER REG_HDMI(0x208)
#define HDMI_CTRL REG_HDMI(0x000)
#define HDMI_HPD_INT_STATUS REG_HDMI(0x250)
diff --git a/platform/fsm9010/acpuclock.c b/platform/fsm9010/acpuclock.c
index a8a8f54..289e360 100644
--- a/platform/fsm9010/acpuclock.c
+++ b/platform/fsm9010/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -149,14 +149,14 @@
}
else
{
- dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ret = 0;
ASSERT(0);
}
-
if(ret)
{
- dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+ dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
ASSERT(0);
}
@@ -170,21 +170,23 @@
void clock_config_uart_dm(uint8_t id)
{
int ret;
- char str[256];
+ char iclk[64];
+ char cclk[64];
- sprintf(str, "uart%d_iface_clk", id);
- ret = clk_get_set_enable(str, 0, 1);
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
if(ret)
{
- dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret);
+ dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret);
ASSERT(0);
}
- sprintf(str, "uart%d_core_clk", id);
- ret = clk_get_set_enable(str, 7372800, 1);
+ ret = clk_get_set_enable(cclk, 7372800, 1);
if(ret)
{
- dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret);
+ dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
ASSERT(0);
}
}
@@ -343,3 +345,66 @@
return;
}
}
+
+/* enables usb30 clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_sleep_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void clock_bumpup_pipe3_clk()
+{
+ int ret = 0;
+
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ return;
+}
+
diff --git a/platform/fsm9010/fsm9010-clock.c b/platform/fsm9010/fsm9010-clock.c
index a3d03e4..6bff69f 100644
--- a/platform/fsm9010/fsm9010-clock.c
+++ b/platform/fsm9010/fsm9010-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -49,6 +49,11 @@
/* Clock Operations */
+static struct clk_ops clk_ops_rst =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
static struct clk_ops clk_ops_branch =
{
.enable = clock_lib2_branch_clk_enable,
@@ -357,6 +362,160 @@
},
};
+/* USB30 Clocks */
+
+static struct branch_clk gcc_sys_noc_usb30_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_SYS_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "sys_noc_usb30_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb2b_phy_sleep_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB2A_PHY_SLEEP_CBCR,
+ .bcr_reg = (uint32_t *) GCC_USB2A_PHY_BCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb2b_phy_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = {
+ F( 125000000, gpll0, 1, 5, 24),
+ F_END
+};
+
+static struct rcg_clk usb30_master_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) GCC_USB30_MASTER_M,
+ .n_reg = (uint32_t *) GCC_USB30_MASTER_N,
+ .d_reg = (uint32_t *) GCC_USB30_MASTER_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_master_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_master_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR,
+ .bcr_reg = (uint32_t *) GCC_USB30_BCR,
+ .parent = &usb30_master_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_master_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+ F( 60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_USB30_MOCK_UTMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_USB30_MOCK_UTMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB30_MOCK_UTMI_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_mock_utmi_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB30_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_phy_aux_clk_src[] = {
+ F( 1200000, cxo, 16, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_phy_aux_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_USB3_PHY_AUX_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_USB3_PHY_AUX_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_phy_aux_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_phy_aux_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_phy_aux_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB3_PHY_AUX_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_phy_aux_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_phy_aux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) GCC_USB3PHY_PHY_BCR,
+ .cbcr_reg = (uint32_t *) GCC_USB3_PHY_PIPE_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_pipe_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t ) GCC_USB3_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_rst,
+ },
+};
+
+static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB_HS_PHY_CFG_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* CE Clocks */
static struct clk_freq_tbl ftbl_gcc_ce2_clk[] = {
F( 50000000, gpll0, 12, 0, 0),
@@ -481,6 +640,17 @@
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+ CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2b_phy_sleep_clk.c),
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
+ CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_aux_clk", gcc_usb30_phy_aux_clk.c),
+ CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+
+ CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c),
+
CLK_LOOKUP("ce2_ahb_clk", gcc_ce2_ahb_clk.c),
CLK_LOOKUP("ce2_axi_clk", gcc_ce2_axi_clk.c),
CLK_LOOKUP("ce2_core_clk", gcc_ce2_clk.c),
diff --git a/platform/fsm9010/gpio.c b/platform/fsm9010/gpio.c
index e4d38c3..538831f 100644
--- a/platform/fsm9010/gpio.c
+++ b/platform/fsm9010/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -57,23 +57,24 @@
static struct {
unsigned int gpio_tx;
unsigned int gpio_rx;
+ unsigned int function;
} gpio_table[] = {
- { 12, 13 },
- { 4, 5 },
- { 8, 6 },
- { 10, 11 },
+ { 8, 6, 3 },
+ { 4, 5, 2 },
+ { 12, 13, 2 },
+ { 10, 11, 1 },
};
if (id >= ARRAY_SIZE(gpio_table))
return;
/* configure rx gpio */
- gpio_tlmm_config(gpio_table[id].gpio_rx, 2, GPIO_INPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(gpio_table[id].gpio_rx, gpio_table[id].function,
+ GPIO_INPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
/* configure tx gpio */
- gpio_tlmm_config(gpio_table[id].gpio_tx, 2, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(gpio_table[id].gpio_tx, gpio_table[id].function,
+ GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
}
void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
diff --git a/platform/fsm9010/include/platform/clock.h b/platform/fsm9010/include/platform/clock.h
index 2690f53..fdb68d2 100644
--- a/platform/fsm9010/include/platform/clock.h
+++ b/platform/fsm9010/include/platform/clock.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -32,7 +32,7 @@
#include <clock.h>
#include <clock_lib2.h>
-#define UART_DM_CLK_RX_TX_BIT_RATE 0x99
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xcc
void platform_clock_init(void);
@@ -43,5 +43,6 @@
void clock_config_ce(uint8_t instance);
void clock_ce_enable(uint8_t instance);
void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
#endif
diff --git a/platform/fsm9010/include/platform/iomap.h b/platform/fsm9010/include/platform/iomap.h
index fca1800..68ebd32 100644
--- a/platform/fsm9010/include/platform/iomap.h
+++ b/platform/fsm9010/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -67,6 +67,7 @@
#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000)
#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00200000)
+#define TCSR_PHSS_USB2_PHY_SEL 0xFD4AB000
#define CLK_CTL_BASE 0xFC400000
@@ -176,4 +177,60 @@
#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+
+/* USB 3.0 clocks */
+#define GCC_USB30_MASTER_CBCR (CLK_CTL_BASE + 0x0240)
+#define GCC_USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x0244)
+#define GCC_USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x0248)
+#define GCC_USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x024C)
+#define GCC_USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x0250)
+#define GCC_USB30_MASTER_M (CLK_CTL_BASE + 0x0254)
+#define GCC_USB30_MASTER_N (CLK_CTL_BASE + 0x0258)
+#define GCC_USB30_MASTER_D (CLK_CTL_BASE + 0x025C)
+#define GCC_USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x0260)
+#define GCC_USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x0264)
+
+/* USB Phy */
+#define GCC_USB3_PHY_BCR (CLK_CTL_BASE + 0x280)
+#define GCC_USB3PHY_PHY_BCR (CLK_CTL_BASE + 0x284)
+#define GCC_USB3_PHY_AUX_CBCR (CLK_CTL_BASE + 0x288)
+#define GCC_USB3_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x28C)
+#define GCC_USB3_PHY_PIPE_MISC (CLK_CTL_BASE + 0x290)
+#define GCC_USB3_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x294)
+#define GCC_USB3_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x298)
+
+#define GCC_USB30_BCR (CLK_CTL_BASE + 0x274)
+#define GCC_SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x278)
+
+/* USB Misc */
+#define GCC_USB_HS_HSIC_BCR (CLK_CTL_BASE + 0x3C0)
+#define GCC_USB_HS_HSIC_GDSCR (CLK_CTL_BASE + 0x3C4)
+#define GCC_USB_BOOT_CLOCK_CTL (CLK_CTL_BASE + 0x1A00)
+#define GCC_USB_HS_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x3EC0)
+#define GCC_USB_SS_PHY_LDO_EN (CLK_CTL_BASE + 0x3F00)
+
+/* USB HS */
+#define GCC_USB_HS_BCR (CLK_CTL_BASE + 0x480)
+#define GCC_USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
+#define GCC_USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488)
+#define GCC_USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
+#define GCC_USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
+#define GCC_USB2A_PHY_BCR (CLK_CTL_BASE + 0x4A8)
+#define GCC_USB2A_PHY_SLEEP_CBCR (CLK_CTL_BASE + 0x4AC)
+#define GCC_USB2_HS_PHY_ONLY_BCR (CLK_CTL_BASE + 0x4B0)
+
+#define GCC_QUSB2_PHY_BCR GCC_USB2A_PHY_BCR
+
+/* USB30 base */
+#define MSM_USB30_BASE 0xF9200000
+#define MSM_USB30_QSCRATCH_BASE 0xF92F8800
+
+/* USB PHY */
+#define CM_DWC_USB2_CM_DWC_USB2_BASE 0xFCA00000
+#define CM_DWC_USB3_CM_DWC_USB3_BASE 0xFCA10000
+#define AHB2PHY_AHB2PHY_BASE 0xFCA06000
+
+#define QMP_PHY_BASE 0xF9B38000
+#define PLATFORM_QMP_OFFSET 0x8
+
#endif
diff --git a/platform/fsm9010/include/platform/irqs.h b/platform/fsm9010/include/platform/irqs.h
index 6b4900f..cba9a03 100644
--- a/platform/fsm9010/include/platform/irqs.h
+++ b/platform/fsm9010/include/platform/irqs.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -45,9 +45,11 @@
#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 8)
-#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
#define USB1_HS_IRQ (GIC_SPI_START + 134)
-#define USB1_IRQ (GIC_SPI_START + 142)
+#define USB30_EE1_IRQ (GIC_SPI_START + 224)
+#define USB30_EE2_IRQ (GIC_SPI_START + 225)
+#define USB30_POWER_EVENT_IRQ (GIC_SPI_START + 226)
+#define USB30_HS_PHY_IRQ (GIC_SPI_START + 227)
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
diff --git a/platform/init.c b/platform/init.c
index 095f6e2..34c5726 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -130,3 +130,18 @@
{
return 0;
}
+
+__WEAK int boot_device_mask(int val)
+{
+ return ((val & 0x3E) >> 1);
+}
+
+__WEAK uint32_t platform_detect_panel()
+{
+ return 0;
+}
+
+__WEAK uint32_t use_hsonly_mode()
+{
+ return 0;
+}
diff --git a/platform/msmzirc/acpuclock.c b/platform/mdm9640/acpuclock.c
similarity index 99%
rename from platform/msmzirc/acpuclock.c
rename to platform/mdm9640/acpuclock.c
index 950049b..59ff6b3 100644
--- a/platform/msmzirc/acpuclock.c
+++ b/platform/mdm9640/acpuclock.c
@@ -133,8 +133,7 @@
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
- int ret;
- uint32_t reg;
+ int ret = 0;
char clk_name[64];
snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
diff --git a/platform/msmzirc/gpio.c b/platform/mdm9640/gpio.c
similarity index 100%
rename from platform/msmzirc/gpio.c
rename to platform/mdm9640/gpio.c
diff --git a/platform/msmzirc/include/platform/clock.h b/platform/mdm9640/include/platform/clock.h
similarity index 94%
rename from platform/msmzirc/include/platform/clock.h
rename to platform/mdm9640/include/platform/clock.h
index 19efae5..e450661 100644
--- a/platform/msmzirc/include/platform/clock.h
+++ b/platform/mdm9640/include/platform/clock.h
@@ -26,12 +26,13 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __PLATFORM_MSMZIRC_CLOCK_H
-#define __PLATFORM_MSMZIRC_CLOCK_H
+#ifndef __PLATFORM_MDM9640_CLOCK_H
+#define __PLATFORM_MDM9640_CLOCK_H
#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
void hsusb_clock_init(void);
+void platform_clock_init(void);
void clock_config_uart_dm(uint8_t id);
void clock_usb30_init(void);
diff --git a/platform/msmzirc/include/platform/gpio.h b/platform/mdm9640/include/platform/gpio.h
similarity index 97%
rename from platform/msmzirc/include/platform/gpio.h
rename to platform/mdm9640/include/platform/gpio.h
index 792565f..897043a 100644
--- a/platform/msmzirc/include/platform/gpio.h
+++ b/platform/mdm9640/include/platform/gpio.h
@@ -26,8 +26,8 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __PLATFORM_MSMZIRC_GPIO_H
-#define __PLATFORM_MSMZIRC_GPIO_H
+#ifndef __PLATFORM_MDM9640_GPIO_H
+#define __PLATFORM_MDM9640_GPIO_H
#include <bits.h>
#include <gpio.h>
diff --git a/platform/msmzirc/include/platform/iomap.h b/platform/mdm9640/include/platform/iomap.h
similarity index 97%
rename from platform/msmzirc/include/platform/iomap.h
rename to platform/mdm9640/include/platform/iomap.h
index 5aefde8..3d63543 100644
--- a/platform/msmzirc/include/platform/iomap.h
+++ b/platform/mdm9640/include/platform/iomap.h
@@ -26,8 +26,8 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _PLATFORM_MSMZIRC_IOMAP_H_
-#define _PLATFORM_MSMZIRC_IOMAP_H_
+#ifndef _PLATFORM_MDM9640_IOMAP_H_
+#define _PLATFORM_MDM9640_IOMAP_H_
/* NAND */
#define MSM_NAND_BASE 0x079B0000
@@ -190,4 +190,7 @@
#define BOOT_CONFIG_OFFSET 0x0000602C
#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
+/* QPIC DISPLAY */
+#define QPIC_BASE 0x7980000
+#define APCS_ALIAS0_IPC_INTERRUPT 0xB011008
#endif
diff --git a/platform/msmzirc/include/platform/irqs.h b/platform/mdm9640/include/platform/irqs.h
similarity index 94%
rename from platform/msmzirc/include/platform/irqs.h
rename to platform/mdm9640/include/platform/irqs.h
index c6740d0..a9e8fc5 100644
--- a/platform/msmzirc/include/platform/irqs.h
+++ b/platform/mdm9640/include/platform/irqs.h
@@ -26,8 +26,8 @@
*
*/
-#ifndef __IRQS_MSMZIRC_H
-#define __IRQS_MSMZIRC_H
+#ifndef __IRQS_MDM9640_H
+#define __IRQS_MDM9640_H
/* TBD: The numbers need to be reviewed */
@@ -58,5 +58,5 @@
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
NR_BOARD_IRQS)
-
-#endif /* __IRQS_9635_H */
+#define SMD_IRQ (GIC_SPI_START + 168)
+#endif /* __IRQS_9640_H */
diff --git a/platform/msmzirc/msmzirc-clock.c b/platform/mdm9640/mdm9640-clock.c
similarity index 97%
rename from platform/msmzirc/msmzirc-clock.c
rename to platform/mdm9640/mdm9640-clock.c
index 497ed35..b7361f5 100644
--- a/platform/msmzirc/msmzirc-clock.c
+++ b/platform/mdm9640/mdm9640-clock.c
@@ -351,7 +351,7 @@
};
static struct reset_clk gcc_usb30_phy_reset = {
- .bcr_reg = (uint32_t *) USB3_PHY_BCR,
+ .bcr_reg = (uint32_t) USB3_PHY_BCR,
.c = {
.dbg_name = "usb30_phy_reset",
@@ -360,7 +360,7 @@
};
static struct reset_clk gcc_usb2a_phy_sleep_clk = {
- .bcr_reg = (uint32_t *) QUSB2A_PHY_BCR,
+ .bcr_reg = (uint32_t) QUSB2A_PHY_BCR,
.c = {
.dbg_name = "usb2b_phy_sleep_clk",
@@ -368,7 +368,7 @@
},
};
-static struct clk_lookup msm_clocks_zirc[] =
+static struct clk_lookup msm_clocks_9640[] =
{
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
@@ -389,5 +389,5 @@
void platform_clock_init(void)
{
- clk_init(msm_clocks_zirc, ARRAY_SIZE(msm_clocks_zirc));
+ clk_init(msm_clocks_9640, ARRAY_SIZE(msm_clocks_9640));
}
diff --git a/platform/msmzirc/platform.c b/platform/mdm9640/platform.c
similarity index 98%
rename from platform/msmzirc/platform.c
rename to platform/mdm9640/platform.c
index 7b9c115..c549287 100644
--- a/platform/msmzirc/platform.c
+++ b/platform/mdm9640/platform.c
@@ -31,19 +31,18 @@
#include <qgic.h>
#include <qtimer.h>
#include <board.h>
+#include <boot_device.h>
#include <mmu.h>
#include <arch/arm/mmu.h>
#include <platform/iomap.h>
+#include <platform/clock.h>
#include <smem.h>
#include <reg.h>
-#include <board.h>
#include <qpic_nand.h>
#include <target.h>
extern struct smem_ram_ptable* target_smem_ram_ptable_init();
-#define MB (1024*1024)
-
#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
/* LK memory - Strongly ordered, executable */
diff --git a/platform/msmzirc/rules.mk b/platform/mdm9640/rules.mk
similarity index 92%
rename from platform/msmzirc/rules.mk
rename to platform/mdm9640/rules.mk
index 91fb286..57427f2 100644
--- a/platform/msmzirc/rules.mk
+++ b/platform/mdm9640/rules.mk
@@ -12,7 +12,7 @@
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/acpuclock.o \
- $(LOCAL_DIR)/msmzirc-clock.o
+ $(LOCAL_DIR)/mdm9640-clock.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/platform/msm8226/acpuclock.c b/platform/msm8226/acpuclock.c
index 503ad7b..a6523d5 100755
--- a/platform/msm8226/acpuclock.c
+++ b/platform/msm8226/acpuclock.c
@@ -112,8 +112,7 @@
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
- int ret;
- uint32_t reg;
+ int ret = 0;
char clk_name[64];
snprintf(clk_name, 64, "sdc%u_core_clk", interface);
diff --git a/platform/msm8226/include/platform/clock.h b/platform/msm8226/include/platform/clock.h
index 399c765..3ada195 100755
--- a/platform/msm8226/include/platform/clock.h
+++ b/platform/msm8226/include/platform/clock.h
@@ -83,5 +83,10 @@
void clock_ce_disable(uint8_t instance);
void mdp_clock_init(void);
void mdp_gdsc_ctrl(uint8_t enable);
-
+void mdp_clock_disable(void);
+void mdp_clock_enable(void);
+void mmss_bus_clocks_enable(void);
+void mmss_bus_clocks_disable(void);
+void mmss_dsi_clocks_enable(uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d);
+void mmss_dsi_clocks_disable(void);
#endif
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index 4429c0a..4efca64 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -176,7 +176,8 @@
#define DSI1_PHY_BASE DSI0_PHY_BASE
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE DSI0_PLL_BASE
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+#define DSI0_REGULATOR_BASE (0xFD922D80)
+#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
@@ -201,6 +202,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
diff --git a/platform/msm8226/msm8226-clock.c b/platform/msm8226/msm8226-clock.c
index d79b895..09a854a 100644
--- a/platform/msm8226/msm8226-clock.c
+++ b/platform/msm8226/msm8226-clock.c
@@ -501,7 +501,7 @@
};
static struct branch_clk mdss_mdp_lut_clk = {
- .cbcr_reg = MDP_LUT_CBCR,
+ .cbcr_reg = (uint32_t *)MDP_LUT_CBCR,
.parent = &mdss_mdp_clk_src.c,
.has_sibling = 1,
@@ -512,7 +512,7 @@
};
static struct branch_clk mdss_vsync_clk = {
- .cbcr_reg = MDSS_VSYNC_CBCR,
+ .cbcr_reg = (uint32_t *)MDSS_VSYNC_CBCR,
.parent = &vsync_clk_src.c,
.has_sibling = 0,
diff --git a/platform/msm8226/platform.c b/platform/msm8226/platform.c
index 1d15a62..9735fba 100644
--- a/platform/msm8226/platform.c
+++ b/platform/msm8226/platform.c
@@ -38,8 +38,6 @@
#include <board.h>
#include <boot_stats.h>
-#define MB (1024*1024)
-
#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
/* LK memory - cacheable, write through */
diff --git a/platform/msm8610/include/platform/iomap.h b/platform/msm8610/include/platform/iomap.h
index 65f5dc6..4605314 100644
--- a/platform/msm8610/include/platform/iomap.h
+++ b/platform/msm8610/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
@@ -183,6 +183,7 @@
#define ERR_INT_MASK0 0x108
#define RDBK_DATA0 0x068
+#define LANE_CTL 0x0A8
#define LANE_SWAP_CTL 0x0AC
#define TIMING_CTL 0x0C0
diff --git a/platform/msm8909/acpuclock.c b/platform/msm8909/acpuclock.c
index 413816b..b8e0df4 100644
--- a/platform/msm8909/acpuclock.c
+++ b/platform/msm8909/acpuclock.c
@@ -393,3 +393,42 @@
ASSERT(0);
}
}
+
+void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+ uint8_t ret = 0;
+ char clk_name[64];
+
+ struct clk *qup_clk;
+ qup_id = qup_id + 1;
+
+ if((blsp_id != BLSP_ID_1)) {
+ dprintf(CRITICAL, "Incorrect BLSP-%d configuration\n", blsp_id);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "blsp1_qup%u_ahb_iface_clk", qup_id);
+
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+
+ if (ret) {
+ dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name);
+ return;
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup%u_i2c_apps_clk", qup_id);
+
+ qup_clk = clk_get(clk_name);
+
+ if (!qup_clk) {
+ dprintf(CRITICAL, "Failed to get %s\n", clk_name);
+ return;
+ }
+
+ ret = clk_enable(qup_clk);
+
+ if (ret) {
+ dprintf(CRITICAL, "Failed to enable %s\n", clk_name);
+ return;
+ }
+}
diff --git a/platform/msm8909/gpio.c b/platform/msm8909/gpio.c
index 70d4dc4..6ec4e33 100644
--- a/platform/msm8909/gpio.c
+++ b/platform/msm8909/gpio.c
@@ -68,3 +68,62 @@
return readl(GPIO_IN_OUT_ADDR(gpio)) & GPIO_IN;
}
+void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+ if(blsp_id == BLSP_ID_1) {
+ switch (qup_id) {
+ case QUP_ID_1:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(6, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(7, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ case QUP_ID_2:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(111, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(112, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ case QUP_ID_3:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(29, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(30, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ case QUP_ID_4:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(14, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(15, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ case QUP_ID_5:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(18, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(19, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+
+ default:
+ dprintf(CRITICAL, "Incorrect QUP id %d\n",qup_id);
+ ASSERT(0);
+ };
+ } else {
+ dprintf(CRITICAL, "Incorrect BLSP id %d\n",blsp_id);
+ ASSERT(0);
+ }
+}
diff --git a/platform/msm8909/include/platform/clock.h b/platform/msm8909/include/platform/clock.h
index ffdaef0..ce98437 100644
--- a/platform/msm8909/include/platform/clock.h
+++ b/platform/msm8909/include/platform/clock.h
@@ -73,5 +73,7 @@
void hsusb_clock_init(void);
void clock_config_ce(uint8_t instance);
void mdp_clock_init(void);
+void mdp_clock_enable(void);
+void mdp_clock_disable(void);
void mdp_gdsc_ctrl(uint8_t enable);
#endif
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index b47fede..e2a66fe 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -103,10 +103,30 @@
#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
/* I2C */
-#define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010)
-#define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3018)
-#define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3014)
+#define BLSP_QUP_BASE(blsp_id, qup_id) (PERIPH_SS_BASE + 0xB5000 + 0x1000 * qup_id)
+#define GCC_BLSP1_QUP1_APPS_CBCR (CLK_CTL_BASE + 0x2008)
+#define GCC_BLSP1_QUP1_CFG_RCGR (CLK_CTL_BASE + 0x2010)
+#define GCC_BLSP1_QUP1_CMD_RCGR (CLK_CTL_BASE + 0x200C)
+#define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010)
+#define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3004)
+#define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3000)
+
+#define GCC_BLSP1_QUP3_APPS_CBCR (CLK_CTL_BASE + 0x4020)
+#define GCC_BLSP1_QUP3_CFG_RCGR (CLK_CTL_BASE + 0x4004)
+#define GCC_BLSP1_QUP3_CMD_RCGR (CLK_CTL_BASE + 0x4000)
+
+#define GCC_BLSP1_QUP4_APPS_CBCR (CLK_CTL_BASE + 0x5020)
+#define GCC_BLSP1_QUP4_CFG_RCGR (CLK_CTL_BASE + 0x5004)
+#define GCC_BLSP1_QUP4_CMD_RCGR (CLK_CTL_BASE + 0x5000)
+
+#define GCC_BLSP1_QUP5_APPS_CBCR (CLK_CTL_BASE + 0x6020)
+#define GCC_BLSP1_QUP5_CFG_RCGR (CLK_CTL_BASE + 0x6004)
+#define GCC_BLSP1_QUP5_CMD_RCGR (CLK_CTL_BASE + 0x6000)
+
+#define GCC_BLSP1_QUP6_APPS_CBCR (CLK_CTL_BASE + 0x7020)
+#define GCC_BLSP1_QUP6_CFG_RCGR (CLK_CTL_BASE + 0x7004)
+#define GCC_BLSP1_QUP6_CMD_RCGR (CLK_CTL_BASE + 0x7000)
/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x21024)
@@ -167,8 +187,8 @@
#define DSI1_PHY_BASE DSI0_PHY_BASE
#define DSI0_PLL_BASE (0x1AC8300)
#define DSI1_PLL_BASE DSI0_PLL_BASE
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
-
+#define DSI0_REGULATOR_BASE (0x1AC8780)
+#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
/* MDP */
#define MDP_BASE 0x1A00000
@@ -180,6 +200,14 @@
#define MDP_DMA_P_BUF_ADDR REG_MDP(0x90008)
#define MDP_DMA_P_BUF_Y_STRIDE REG_MDP(0x9000C)
+#define MDP_DMA_P_QOS_REMAPPER REG_MDP(0x90090)
+#define MDP_DMA_P_WATERMARK_0 REG_MDP(0x90094)
+#define MDP_DMA_P_WATERMARK_1 REG_MDP(0x90098)
+#define MDP_DMA_P_WATERMARK_2 REG_MDP(0x9009C)
+#define MDP_PANIC_ROBUST_CTRL REG_MDP(0x900A0)
+#define MDP_PANIC_LUT0 REG_MDP(0x900A4)
+#define MDP_ROBUST_LUT REG_MDP(0x900AC)
+
#define MDP_DSI_VIDEO_EN REG_MDP(0xF0000)
#define MDP_DSI_VIDEO_HSYNC_CTL REG_MDP(0xF0004)
#define MDP_DSI_VIDEO_VSYNC_PERIOD REG_MDP(0xF0008)
@@ -219,6 +247,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
@@ -248,6 +277,7 @@
#define BOOT_CONFIG_OFFSET 0x0000602C
#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
+#define SECURITY_CONTROL_CORE_FEATURE_CONFIG0 0x0005E004
/* EBI2 */
#define TLMM_EBI2_EMMC_GPIO_CFG (TLMM_BASE_ADDR + 0x00111000)
#endif
diff --git a/platform/msm8909/include/platform/irqs.h b/platform/msm8909/include/platform/irqs.h
index 3ef97b1..3bb43ac 100644
--- a/platform/msm8909/include/platform/irqs.h
+++ b/platform/msm8909/include/platform/irqs.h
@@ -64,4 +64,5 @@
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
NR_BOARD_IRQS)
+#define BLSP_QUP_IRQ(blsp_id, qup_id) (GIC_SPI_START + 95 + qup_id)
#endif /* __IRQS_MSM8909_H */
diff --git a/platform/msm8909/msm8909-clock.c b/platform/msm8909/msm8909-clock.c
index 78ece16..da7e222 100644
--- a/platform/msm8909/msm8909-clock.c
+++ b/platform/msm8909/msm8909-clock.c
@@ -389,6 +389,30 @@
},
};
+static struct rcg_clk gcc_blsp1_qup1_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP1_APPS_CBCR,
+ .parent = &gcc_blsp1_qup1_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct rcg_clk gcc_blsp1_qup2_i2c_apps_clk_src =
{
@@ -414,6 +438,102 @@
},
};
+static struct rcg_clk gcc_blsp1_qup3_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP3_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP3_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP3_APPS_CBCR,
+ .parent = &gcc_blsp1_qup3_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk gcc_blsp1_qup4_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP4_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP4_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP4_APPS_CBCR,
+ .parent = &gcc_blsp1_qup4_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk gcc_blsp1_qup5_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP5_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP5_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP5_APPS_CBCR,
+ .parent = &gcc_blsp1_qup5_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk gcc_blsp1_qup6_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP6_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP6_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP6_APPS_CBCR,
+ .parent = &gcc_blsp1_qup6_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* Display clocks */
static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
F_MM(19200000, cxo, 1, 0, 0),
@@ -548,8 +668,18 @@
CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
CLK_LOOKUP("blsp1_qup2_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup1_i2c_apps_clk_src", gcc_blsp1_qup1_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup1_i2c_apps_clk", gcc_blsp1_qup1_i2c_apps_clk.c),
CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk_src", gcc_blsp1_qup2_i2c_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk", gcc_blsp1_qup2_i2c_apps_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup3_i2c_apps_clk_src", gcc_blsp1_qup3_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup3_i2c_apps_clk", gcc_blsp1_qup3_i2c_apps_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk_src", gcc_blsp1_qup4_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk", gcc_blsp1_qup4_i2c_apps_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup5_i2c_apps_clk_src", gcc_blsp1_qup5_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup5_i2c_apps_clk", gcc_blsp1_qup5_i2c_apps_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup6_i2c_apps_clk_src", gcc_blsp1_qup5_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup6_i2c_apps_clk", gcc_blsp1_qup5_i2c_apps_clk.c),
CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
diff --git a/platform/msm8909/platform.c b/platform/msm8909/platform.c
index 1ea030a..97c6838 100644
--- a/platform/msm8909/platform.c
+++ b/platform/msm8909/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -184,3 +184,47 @@
return MSM_SHARED_BASE;
}
+int platform_is_msm8909()
+{
+ uint32_t platform = board_platform_id();
+ uint32_t ret = 0;
+
+ switch(platform)
+ {
+ case MSM8909:
+ case MSM8209:
+ case MSM8208:
+ case APQ8009:
+ case MSM8609:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
+int boot_device_mask(int val)
+{
+ return ((val & 0x0E) >> 1);
+}
+
+uint32_t platform_detect_panel()
+{
+ uint32_t panel;
+
+ /* Bits 28:29 of this register are read to know
+ the panel config, and pick up DT accordingly.
+
+ 00 -no limit, suport HD
+ 01 - limit to 720P
+ 10- limit to qHD
+ 11- limit to fWVGA
+
+ */
+ panel = readl(SECURITY_CONTROL_CORE_FEATURE_CONFIG0);
+ panel = (panel & 0x30000000) >> 28;
+
+ return panel;
+}
diff --git a/platform/msm8916/acpuclock.c b/platform/msm8916/acpuclock.c
index bcc65f0..663a6ce 100644
--- a/platform/msm8916/acpuclock.c
+++ b/platform/msm8916/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -36,6 +36,7 @@
#include <clock.h>
#include <platform/clock.h>
#include <blsp_qup.h>
+#include <platform.h>
void hsusb_clock_init(void)
{
@@ -112,8 +113,7 @@
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
- int ret;
- uint32_t reg;
+ int ret = 1;
char clk_name[64];
snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
@@ -205,7 +205,7 @@
ASSERT(0);
}
- if (platform_is_msm8939())
+ if (platform_is_msm8939() || platform_is_msm8929())
ret = clk_get_set_enable("mdss_mdp_clk_src", 307200000, 1);
else
/* Set MDP clock to 320MHz */
diff --git a/platform/msm8916/gpio.c b/platform/msm8916/gpio.c
index a0af57c..2453b33 100644
--- a/platform/msm8916/gpio.c
+++ b/platform/msm8916/gpio.c
@@ -51,22 +51,6 @@
return;
}
-void gpio_set_value(uint32_t gpio, uint32_t value)
-{
- /* GPIO_OUTPUT */
- if (value) {
- writel(GPIO_OUT_VAL(gpio),
- (uint32_t *)GPIO_OUT_SET_ADDR(gpio));
- } else {
- writel(GPIO_OUT_VAL(gpio),
- (uint32_t *)GPIO_OUT_CLR_ADDR(gpio));
- }
- /* GPIO_OE */
- writel(GPIO_OUT_OE_VAL(gpio),
- (uint32_t *)GPIO_OUT_OE_SET_ADDR(gpio));
- return;
-}
-
uint32_t gpio_status(uint32_t gpio)
{
return readl(GPIO_IN_OUT_ADDR(gpio)) & GPIO_IN;
diff --git a/platform/msm8916/include/platform/clock.h b/platform/msm8916/include/platform/clock.h
index 4b0a5ef..fab6259 100644
--- a/platform/msm8916/include/platform/clock.h
+++ b/platform/msm8916/include/platform/clock.h
@@ -79,7 +79,8 @@
#define DSI_PIXEL1_D REG_MM(0x4D0C8)
void platform_clock_init(void);
-
+void mdp_clock_enable(void);
+void mdp_clock_disable(void);
void clock_init_mmc(uint32_t interface);
void clock_config_mmc(uint32_t interface, uint32_t freq);
void clock_config_uart_dm(uint8_t id);
@@ -87,6 +88,10 @@
void clock_config_ce(uint8_t instance);
void mdp_clock_init(void);
void mdp_gdsc_ctrl(uint8_t enable);
+void mdss_bus_clocks_enable(void);
+void mdss_bus_clocks_disable(void);
+void gcc_dsi_clocks_enable(uint8_t dual_dsi,uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d);
+void gcc_dsi_clocks_disable(uint8_t dual_dsi);
void clock_ce_enable(uint8_t instance);
void clock_ce_disable(uint8_t instance);
void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id);
diff --git a/platform/msm8916/include/platform/gpio.h b/platform/msm8916/include/platform/gpio.h
index 5b4552b..0437aff 100644
--- a/platform/msm8916/include/platform/gpio.h
+++ b/platform/msm8916/include/platform/gpio.h
@@ -69,6 +69,5 @@
uint8_t pull,
uint8_t drvstr,
uint32_t enable);
-void gpio_set_value(uint32_t gpio, uint32_t value);
void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id);
#endif
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index 2532601..fd56c0e 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -159,10 +159,14 @@
#define DSI1_PHY_BASE (0x1AA0500)
#define DSI0_PLL_BASE (0x1A98300)
#define DSI1_PLL_BASE DSI0_PLL_BASE
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+#define DSI0_REGULATOR_BASE (0x1A98780)
+#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
#define MDP_BASE (0x1A00000)
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_HW_REV REG_MDP(0x1000)
+#define MDP_INTR_EN REG_MDP(0x1010)
+#define MDP_INTR_CLEAR REG_MDP(0x1018)
+#define MDP_HIST_INTR_EN REG_MDP(0x101C)
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
@@ -220,6 +224,10 @@
#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xc8074)
#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xc80A8)
+#define MDSS_MDP_REG_PP_FBC_MODE 0x034
+#define MDSS_MDP_REG_PP_FBC_BUDGET_CTL 0x038
+#define MDSS_MDP_REG_PP_FBC_LOSSY_MODE 0x03C
+
#define SOFT_RESET 0x118
#define CLK_CTRL 0x11C
#define TRIG_CTRL 0x084
@@ -233,6 +241,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
diff --git a/platform/msm8916/msm8916-clock.c b/platform/msm8916/msm8916-clock.c
index d4289c1..c2ec604 100644
--- a/platform/msm8916/msm8916-clock.c
+++ b/platform/msm8916/msm8916-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -34,6 +34,7 @@
#include <clock_lib2.h>
#include <platform/clock.h>
#include <platform/iomap.h>
+#include <platform.h>
/* Mux source select values */
@@ -44,7 +45,6 @@
#define gpll1_mm_source_val 1
struct clk_freq_tbl rcg_dummy_freq = F_END;
-
/* Clock Operations */
static struct clk_ops clk_ops_branch =
{
@@ -477,7 +477,7 @@
};
static struct branch_clk mdss_vsync_clk = {
- .cbcr_reg = MDSS_VSYNC_CBCR,
+ .cbcr_reg = (uint32_t *) MDSS_VSYNC_CBCR,
.parent = &vsync_clk_src.c,
.has_sibling = 0,
@@ -554,7 +554,7 @@
};
static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
- .cbcr_reg = GCC_BLSP1_QUP2_APPS_CBCR,
+ .cbcr_reg = (uint32_t *) GCC_BLSP1_QUP2_APPS_CBCR,
.parent = &gcc_blsp1_qup2_i2c_apps_clk_src.c,
.c = {
@@ -602,7 +602,7 @@
void platform_clock_init(void)
{
- if (platform_is_msm8939())
+ if (platform_is_msm8939() || platform_is_msm8929())
msm8939_clock_override();
clk_init(msm_clocks_8916, ARRAY_SIZE(msm_clocks_8916));
}
diff --git a/platform/msm8916/platform.c b/platform/msm8916/platform.c
index 0558b35..4b646fe 100644
--- a/platform/msm8916/platform.c
+++ b/platform/msm8916/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -30,6 +30,7 @@
#include <reg.h>
#include <platform/iomap.h>
#include <platform/irqs.h>
+#include <platform/clock.h>
#include <qgic.h>
#include <qtimer.h>
#include <mmu.h>
@@ -37,14 +38,13 @@
#include <smem.h>
#include <board.h>
#include <boot_stats.h>
-
-#define MB (1024*1024)
+#include <platform.h>
#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
#define A53_SS_SIZE ((A53_SS_END - A53_SS_BASE)/MB)
/* LK memory - cacheable, write through */
-#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
MMU_MEMORY_AP_READ_WRITE)
/* Peripherals - non-shared device */
@@ -55,6 +55,9 @@
#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
static mmu_section_t mmu_section_table[] = {
/* Physical addr, Virtual addr, Size (in MB), Flags */
{ MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
@@ -63,13 +66,13 @@
{ SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, COMMON_MEMORY},
{ MSM_SHARED_BASE, MSM_SHARED_BASE, 1, COMMON_MEMORY},
{ BASE_ADDR, BASE_ADDR, 90, COMMON_MEMORY},
- { SCRATCH_ADDR, SCRATCH_ADDR, 256, COMMON_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, 256, SCRATCH_MEMORY},
{ BASE_ADDR_1, BASE_ADDR_1, 1024, COMMON_MEMORY},
};
-static struct smem_ram_ptable ram_ptable;
int platform_is_msm8939();
+int platform_is_msm8929();
void platform_early_init(void)
{
@@ -82,7 +85,7 @@
int qtmr_irq()
{
- if (platform_is_msm8939())
+ if (platform_is_msm8939() || platform_is_msm8929())
return INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP_8x39;
else
return INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP_8x16;
@@ -172,6 +175,26 @@
return ret;
}
+int platform_is_msm8929()
+{
+ uint32_t platform = board_platform_id();
+ uint32_t ret = 0;
+
+ switch(platform)
+ {
+ case MSM8929:
+ case MSM8629:
+ case MSM8229:
+ case APQ8029:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
/* DYNAMIC SMEM REGION feature enables LK to dynamically
* read the SMEM addr info from TCSR_TZ_WONCE register.
* The first word read, if indicates a MAGIC number, then
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index 3f6bd14..a8d63e0 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -108,6 +108,8 @@
void hsusb_clock_init(void);
void clock_config_ce(uint8_t instance);
void mdp_clock_init(void);
+void mdp_clock_enable(void);
+void mdp_clock_disable(uint32_t dual_dsi);
void mdp_gdsc_ctrl(uint8_t enable);
void edp_clk_enable(void);
void clock_ce_enable(uint8_t instance);
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 8463a77..ccb086f 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -224,7 +224,8 @@
#define DSI1_PHY_BASE (0xFD923100)
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE (0xFD923000)
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+#define DSI0_REGULATOR_BASE (0xFD922D80)
+#define DSI1_REGULATOR_BASE (0xFD923380)
#define EDP_BASE (0xFD923400)
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
@@ -250,6 +251,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index 5e2d5a6..6b77ea0 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -31,8 +31,30 @@
#include <reg.h>
#include <mmc.h>
#include <clock.h>
+#include <pm8x41.h>
#include <platform/clock.h>
#include <platform/iomap.h>
+#include <platform/timer.h>
+#include <rpm-smd.h>
+#include <regulator.h>
+
+#define RPM_CE_CLK_TYPE 0x6563
+#define CE2_CLK_ID 0x1
+#define RPM_SMD_KEY_RATE 0x007A484B
+
+uint32_t CE2_CLK[][8]=
+{
+ {
+ RPM_CE_CLK_TYPE, CE2_CLK_ID,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+ RPM_SMD_KEY_RATE, 4, 0,
+ },
+ {
+ RPM_CE_CLK_TYPE, CE2_CLK_ID,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+ RPM_SMD_KEY_RATE, 4, 176128,
+ },
+};
void hsusb_clock_init(void)
{
@@ -120,8 +142,7 @@
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
- int ret;
- uint32_t reg;
+ int ret = 0;
char clk_name[64];
snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
@@ -194,14 +215,42 @@
*/
static void ce_async_reset(uint8_t instance)
{
+ if (instance == 2)
+ {
+ /* Start the block reset for CE */
+ writel(1, GCC_CE2_BCR);
+ udelay(2);
+ /* Take CE block out of reset */
+ writel(0, GCC_CE2_BCR);
+ udelay(2);
+ }
+ else
+ {
+ dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance);
+ ASSERT(0);
+ }
}
void clock_ce_enable(uint8_t instance)
{
+ if (instance == 2)
+ rpm_send_data(&CE2_CLK[GENERIC_ENABLE][0], 24, RPM_REQUEST_TYPE);
+ else
+ {
+ dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance);
+ ASSERT(0);
+ }
}
void clock_ce_disable(uint8_t instance)
{
+ if (instance == 2)
+ rpm_send_data(&CE2_CLK[GENERIC_DISABLE][0], 24, RPM_REQUEST_TYPE);
+ else
+ {
+ dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance);
+ ASSERT(0);
+ }
}
void clock_config_ce(uint8_t instance)
@@ -399,41 +448,39 @@
clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
}
-void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t flags,
uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
{
int ret;
- /* Configure Byte clock -autopll- This will not change because
- byte clock does not need any divider*/
- writel(0x100, DSI_BYTE0_CFG_RCGR);
- writel(0x1, DSI_BYTE0_CMD_RCGR);
- writel(0x1, DSI_BYTE0_CBCR);
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
+ /* Enable DSI0 branch clocks */
+ writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(0x1, DSI_BYTE0_CMD_RCGR);
+ writel(0x1, DSI_BYTE0_CBCR);
- /* Configure Pixel clock */
- writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
- writel(0x1, DSI_PIXEL0_CMD_RCGR);
- writel(0x1, DSI_PIXEL0_CBCR);
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ writel(0x1, DSI_PIXEL0_CBCR);
- writel(pclk0_m, DSI_PIXEL0_M);
- writel(pclk0_n, DSI_PIXEL0_N);
- writel(pclk0_d, DSI_PIXEL0_D);
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
- /* Configure ESC clock */
- ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
- if(ret)
- {
- dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
- ASSERT(0);
+ ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
- if (dual_dsi) {
- /* Configure Byte 1 clock */
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
+ /* Enable DSI1 branch clocks */
writel(0x100, DSI_BYTE1_CFG_RCGR);
writel(0x1, DSI_BYTE1_CMD_RCGR);
writel(0x1, DSI_BYTE1_CBCR);
- /* Configure Pixel clock */
writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
writel(0x1, DSI_PIXEL1_CMD_RCGR);
writel(0x1, DSI_PIXEL1_CBCR);
@@ -442,7 +489,6 @@
writel(pclk0_n, DSI_PIXEL1_N);
writel(pclk0_d, DSI_PIXEL1_D);
- /* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
if(ret)
{
@@ -452,15 +498,15 @@
}
}
-void mmss_dsi_clock_disable(uint32_t dual_dsi)
+void mmss_dsi_clock_disable(uint32_t flags)
{
- /* Disable ESC clock */
- clk_disable(clk_get("mdss_esc0_clk"));
- writel(0x0, DSI_BYTE0_CBCR);
- writel(0x0, DSI_PIXEL0_CBCR);
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
+ clk_disable(clk_get("mdss_esc0_clk"));
+ writel(0x0, DSI_BYTE0_CBCR);
+ writel(0x0, DSI_PIXEL0_CBCR);
+ }
- if (dual_dsi) {
- /* Disable ESC clock */
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
clk_disable(clk_get("mdss_esc1_clk"));
writel(0x0, DSI_BYTE1_CBCR);
writel(0x0, DSI_PIXEL1_CBCR);
diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index c50fef7..c4efe85 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -100,6 +100,9 @@
#define EDPAUX_CFG_RCGR REG_MM(0x20E4)
#define EDPAUX_CMD_RCGR REG_MM(0x20E0)
+#define MMSS_DSI_CLKS_FLAG_DSI0 BIT(0)
+#define MMSS_DSI_CLKS_FLAG_DSI1 BIT(1)
+
void platform_clock_init(void);
void clock_init_mmc(uint32_t interface);
@@ -112,4 +115,12 @@
void clock_ce_disable(uint8_t instance);
void clock_usb30_init(void);
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+ uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d);
+void mmss_dsi_clock_disable(uint32_t dual_dsi);
+void mmss_bus_clock_enable(void);
+void mmss_bus_clock_disable(void);
+void mdp_clock_enable(void);
+void mdp_clock_disable(void);
+
#endif
diff --git a/platform/msm8994/include/platform/gpio.h b/platform/msm8994/include/platform/gpio.h
index bce399b..154fbdf 100644
--- a/platform/msm8994/include/platform/gpio.h
+++ b/platform/msm8994/include/platform/gpio.h
@@ -57,4 +57,7 @@
void gpio_config_uart_dm(uint8_t id);
void gpio_config_blsp_i2c(uint8_t, uint8_t);
+void gpio_set(uint32_t gpio, uint32_t dir);
+void gpio_tlmm_config(uint32_t gpio, uint8_t func, uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable);
#endif
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 341c0a6..bb9709f 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -197,6 +197,7 @@
#define MSM_CE2_BAM_BASE 0xFD444000
#define MSM_CE2_BASE 0xFD45A000
+#define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080)
#define TLMM_BASE_ADDR 0xFD510000
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
@@ -239,7 +240,11 @@
#define DSI1_PHY_BASE (0xFD9A0500)
#define DSI0_PLL_BASE (0xFD998300)
#define DSI1_PLL_BASE (0xFD9A0300)
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+#define DSI0_REGULATOR_BASE (0xFD998780)
+#define DSI1_REGULATOR_BASE (0xFD9A0780)
+
+#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0160
+#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0168
#define MDP_BASE (0xfd900000)
@@ -255,68 +260,255 @@
#define MDP_PP_1_BASE REG_MDP(0x71800)
#define REG_MDP(off) (MDP_BASE + (off))
+
+#ifdef MDP_HW_REV
+#undef MDP_HW_REV
+#endif
#define MDP_HW_REV REG_MDP(0x1000)
+
+#ifdef MDP_INTR_EN
+#undef MDP_INTR_EN
+#endif
#define MDP_INTR_EN REG_MDP(0x1010)
+
+#ifdef MDP_INTR_CLEAR
+#undef MDP_INTR_CLEAR
+#endif
#define MDP_INTR_CLEAR REG_MDP(0x1018)
+
+#ifdef MDP_HIST_INTR_EN
+#undef MDP_HIST_INTR_EN
+#endif
#define MDP_HIST_INTR_EN REG_MDP(0x101C)
+#ifdef MDP_DISP_INTF_SEL
+#undef MDP_DISP_INTF_SEL
+#endif
#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
+
+#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
+#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
+#endif
#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
+
+#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
+#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
+#endif
#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
+
+#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
+#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
+#endif
#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
+#ifdef MDP_INTF_0_TIMING_ENGINE_EN
+#undef MDP_INTF_0_TIMING_ENGINE_EN
+#endif
#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
+
+#ifdef MDP_INTF_1_TIMING_ENGINE_EN
+#undef MDP_INTF_1_TIMING_ENGINE_EN
+#endif
#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
-#define MDP_CTL_0_BASE REG_MDP(0x2000)
-#define MDP_CTL_1_BASE REG_MDP(0x2200)
+#ifdef MDP_INTF_2_TIMING_ENGINE_EN
+#undef MDP_INTF_2_TIMING_ENGINE_EN
+#endif
+#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x6C000)
+#ifdef MDP_CTL_0_BASE
+#undef MDP_CTL_0_BASE
+#endif
+#define MDP_CTL_0_BASE REG_MDP(0x2000)
+
+#ifdef MDP_CTL_1_BASE
+#undef MDP_CTL_1_BASE
+#endif
+#define MDP_CTL_1_BASE REG_MDP(0x2200)
+
+#ifdef MDP_REG_SPLIT_DISPLAY_EN
+#undef MDP_REG_SPLIT_DISPLAY_EN
+#endif
#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
+
+#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
+#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
+#endif
#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
+
+#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
+#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
+#endif
#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
-/* can not find following two registers */
-#define MDP_REG_PPB0_CNTL REG_MDP(0x1420)
-#define MDP_REG_PPB0_CONFIG REG_MDP(0x1424)
-
+#ifdef MDP_INTF_0_BASE
+#undef MDP_INTF_0_BASE
+#endif
#define MDP_INTF_0_BASE REG_MDP(0x6b000)
+
+#ifdef MDP_INTF_1_BASE
+#undef MDP_INTF_1_BASE
+#endif
#define MDP_INTF_1_BASE REG_MDP(0x6b800)
+
+#ifdef MDP_INTF_2_BASE
+#undef MDP_INTF_2_BASE
+#endif
#define MDP_INTF_2_BASE REG_MDP(0x6c000)
-
+#ifdef MDP_CLK_CTRL0
+#undef MDP_CLK_CTRL0
+#endif
#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
+
+#ifdef MDP_CLK_CTRL1
+#undef MDP_CLK_CTRL1
+#endif
#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
+
+#ifdef MDP_CLK_CTRL2
+#undef MDP_CLK_CTRL2
+#endif
#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
+
+#ifdef MDP_CLK_CTRL3
+#undef MDP_CLK_CTRL3
+#endif
#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
+
+#ifdef MDP_CLK_CTRL4
+#undef MDP_CLK_CTRL4
+#endif
#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
+
+#ifdef MDP_CLK_CTRL5
+#undef MDP_CLK_CTRL5
+#endif
#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
+
+#ifdef MDP_CLK_CTRL6
+#undef MDP_CLK_CTRL6
+#endif
#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
+
+#ifdef MDP_CLK_CTRL7
+#undef MDP_CLK_CTRL7
+#endif
#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
+#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
+#undef MMSS_MDP_SMP_ALLOC_W_BASE
+#endif
#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
+
+#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
+#undef MMSS_MDP_SMP_ALLOC_R_BASE
+#endif
#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
+#ifdef MDP_QOS_REMAPPER_CLASS_0
+#undef MDP_QOS_REMAPPER_CLASS_0
+#endif
#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
+
+#ifdef MDP_QOS_REMAPPER_CLASS_1
+#undef MDP_QOS_REMAPPER_CLASS_1
+#endif
#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
+#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
+#undef VBIF_VBIF_DDR_FORCE_CLK_ON
+#endif
#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
+
+#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
+#undef VBIF_VBIF_DDR_OUT_MAX_BURST
+#endif
#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
+
+#ifdef VBIF_VBIF_DDR_ARB_CTRL
+#undef VBIF_VBIF_DDR_ARB_CTRL
+#endif
#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
+
+#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
+#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
+#endif
#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
+
+#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
+#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
+#endif
#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
+
+#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
+#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
+#endif
#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
+
+#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
+#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
+#endif
#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
+
+#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
+#undef VBIF_VBIF_DDR_OUT_AX_AOOO
+#endif
#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
+
+#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
+#undef VBIF_VBIF_IN_RD_LIM_CONF0
+#endif
#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
+
+#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
+#undef VBIF_VBIF_IN_RD_LIM_CONF1
+#endif
#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
+
+#ifdef VBIF_VBIF_IN_RD_LIM_CONF2
+#undef VBIF_VBIF_IN_RD_LIM_CONF2
+#endif
#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xc80B8)
+
+#ifdef VBIF_VBIF_IN_RD_LIM_CONF3
+#undef VBIF_VBIF_IN_RD_LIM_CONF3
+#endif
#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xc80BC)
+
+#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
+#undef VBIF_VBIF_IN_WR_LIM_CONF0
+#endif
#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
+
+#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
+#undef VBIF_VBIF_IN_WR_LIM_CONF1
+#endif
#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
+
+#ifdef VBIF_VBIF_IN_WR_LIM_CONF2
+#undef VBIF_VBIF_IN_WR_LIM_CONF2
+#endif
#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xc80C8)
+
+#ifdef VBIF_VBIF_IN_WR_LIM_CONF3
+#undef VBIF_VBIF_IN_WR_LIM_CONF3
+#endif
#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xc80CC)
+
+#ifdef VBIF_VBIF_ABIT_SHORT
+#undef VBIF_VBIF_ABIT_SHORT
+#endif
#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xc8070)
+
+#ifdef VBIF_VBIF_ABIT_SHORT_CONF
+#undef VBIF_VBIF_ABIT_SHORT_CONF
+#endif
#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xc8074)
+
+#ifdef VBIF_VBIF_GATE_OFF_WRREQ_EN
+#undef VBIF_VBIF_GATE_OFF_WRREQ_EN
+#endif
#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xc80A8)
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
@@ -353,6 +545,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
@@ -363,4 +556,9 @@
#define VIDEO_MODE_VSYNC 0x034
#define VIDEO_MODE_VSYNC_VPOS 0x038
+#define QPNP_LED_CTRL_BASE 0xD000
+#define QPNP_BLUE_LPG_CTRL_BASE 0xB100
+#define QPNP_GREEN_LPG_CTRL_BASE 0xB200
+#define QPNP_RED_LPG_CTRL_BASE 0xB300
+
#endif
diff --git a/platform/msm8994/msm8994-clock.c b/platform/msm8994/msm8994-clock.c
index 5ee2d5c..358db25 100644
--- a/platform/msm8994/msm8994-clock.c
+++ b/platform/msm8994/msm8994-clock.c
@@ -158,24 +158,6 @@
F_END
};
-static struct rcg_clk blsp2_uart2_apps_clk_src =
-{
- .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
-
- .set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
- .current_freq = &rcg_dummy_freq,
-
- .c = {
- .dbg_name = "blsp1_uart2_apps_clk",
- .ops = &clk_ops_rcg_mnd,
- },
-};
-
static struct rcg_clk blsp1_uart2_apps_clk_src =
{
.cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
@@ -194,17 +176,6 @@
},
};
-static struct branch_clk gcc_blsp2_uart2_apps_clk =
-{
- .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
- .parent = &blsp2_uart2_apps_clk_src.c,
-
- .c = {
- .dbg_name = "gcc_blsp2_uart2_apps_clk",
- .ops = &clk_ops_branch,
- },
-};
-
static struct branch_clk gcc_blsp1_uart2_apps_clk =
{
.cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
@@ -227,17 +198,6 @@
},
};
-static struct vote_clk gcc_blsp2_ahb_clk = {
- .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
- .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
- .en_mask = BIT(15),
-
- .c = {
- .dbg_name = "gcc_blsp2_ahb_clk",
- .ops = &clk_ops_vote,
- },
-};
-
/* USB Clocks */
static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
{
@@ -708,7 +668,7 @@
};
static struct branch_clk mdss_mdp_lut_clk = {
- .cbcr_reg = MDP_LUT_CBCR,
+ .cbcr_reg = (uint32_t *) MDP_LUT_CBCR,
.parent = &mdss_mdp_clk_src.c,
.has_sibling = 1,
@@ -719,7 +679,7 @@
};
static struct branch_clk mdss_vsync_clk = {
- .cbcr_reg = MDSS_VSYNC_CBCR,
+ .cbcr_reg = (uint32_t *) MDSS_VSYNC_CBCR,
.parent = &vsync_clk_src.c,
.has_sibling = 0,
@@ -746,7 +706,7 @@
};
static struct branch_clk mdss_edpaux_clk = {
- .cbcr_reg = MDSS_EDPAUX_CBCR,
+ .cbcr_reg = (uint32_t *) MDSS_EDPAUX_CBCR,
.parent = &edpaux_clk_src.c,
.has_sibling = 0,
@@ -811,7 +771,7 @@
};
static struct branch_clk mmss_misc_ahb_clk = {
- .cbcr_reg = MMSS_MISC_AHB_CBCR,
+ .cbcr_reg = (uint32_t *) MMSS_MISC_AHB_CBCR,
.has_sibling = 1,
.c = {
diff --git a/platform/msm8994/platform.c b/platform/msm8994/platform.c
index 8c6d5f4..507158b 100644
--- a/platform/msm8994/platform.c
+++ b/platform/msm8994/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -37,8 +37,6 @@
#include <smem.h>
#include <board.h>
-#define MB (1024*1024)
-
#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
/* LK memory - cacheable, write through */
@@ -175,6 +173,23 @@
return 0;
}
+int platform_is_msm8992()
+{
+ int ret;
+
+ uint32_t platform = board_platform_id();
+ switch (platform) {
+ case MSM8992:
+ case APQ8092:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ }
+
+ return ret;
+}
+
addr_t get_bs_info_addr()
{
if (platform_is_msm8994())
diff --git a/platform/msm8x60/rules.mk b/platform/msm8x60/rules.mk
index 5f58ee1..9b0f4f1 100644
--- a/platform/msm8x60/rules.mk
+++ b/platform/msm8x60/rules.mk
@@ -8,6 +8,7 @@
MMC_SLOT := 1
+DEFINES += DEFINE_GSBI_I2C=1
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
MMC_SLOT=$(MMC_SLOT) MDP4=1 \
SSD_ENABLE TZ_TAMPER_FUSE
diff --git a/platform/msm_shared/bam.c b/platform/msm_shared/bam.c
index 00abeda..f123b87 100644
--- a/platform/msm_shared/bam.c
+++ b/platform/msm_shared/bam.c
@@ -79,7 +79,6 @@
enum p_int_type interrupt)
{
uint32_t val;
- uint32_t bamsts;
while (1)
{
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index 07d4f8a..a2ea734 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -31,6 +31,7 @@
#include <board.h>
#include <smem.h>
#include <baseband.h>
+#include <boot_device.h>
static struct board_data board = {UNKNOWN,
0,
@@ -40,7 +41,9 @@
HW_PLATFORM_SUBTYPE_UNKNOWN,
LINUX_MACHTYPE_UNKNOWN,
BASEBAND_MSM,
- {{PMIC_IS_INVALID, 0}, {PMIC_IS_INVALID, 0}, {PMIC_IS_INVALID, 0}},
+ {{PMIC_IS_INVALID, 0, 0}, {PMIC_IS_INVALID, 0, 0},
+ {PMIC_IS_INVALID, 0, 0}},
+ 0,
};
static void platform_detect()
@@ -48,6 +51,8 @@
struct smem_board_info_v6 board_info_v6;
struct smem_board_info_v7 board_info_v7;
struct smem_board_info_v8 board_info_v8;
+ struct smem_board_info_v9 board_info_v9;
+ struct smem_board_info_v10 board_info_v10;
unsigned int board_info_len = 0;
unsigned ret = 0;
unsigned format = 0;
@@ -102,10 +107,8 @@
board.pmic_info[0].pmic_type = board_info_v7.pmic_type;
board.pmic_info[0].pmic_version = board_info_v7.pmic_version;
}
- else if (format_minor >= 8)
+ else if (format_minor == 8)
{
- dprintf(INFO, "Minor socinfo format detected: %u.%u\n", format_major, format_minor);
-
board_info_len = sizeof(board_info_v8);
ret = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
@@ -145,20 +148,101 @@
board.pmic_info[i].pmic_target = (((board_info_v8.pmic_info[i].pmic_version >> 16) & 0xff) << 16) |
((board_info_v8.pmic_info[i].pmic_version & 0xff) << 8) | (pmic_type & 0xff);
}
+ }
+ else if (format_minor == 0x9)
+ {
+ board_info_len = sizeof(board_info_v9);
- if (format_minor == 0x9)
- board.foundry_id = board_info_v8.foundry_id;
+ ret = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v9,
+ board_info_len);
+ if (ret)
+ return;
- if (format_minor == 0xA)
- board.chip_serial = board_info_v8.chip_serial;
+ board.platform = board_info_v9.board_info_v3.msm_id;
+ board.platform_version = board_info_v9.board_info_v3.msm_version;
+ board.platform_hw = board_info_v9.board_info_v3.hw_platform;
+ board.platform_subtype = board_info_v9.platform_subtype;
+
+ /*
+ * fill in board.target with variant_id information
+ * bit no |31 24 | 23 16 | 15 8 |7 0|
+ * board.target = |subtype| plat_hw_ver major | plat_hw_ver minor |hw_platform|
+ *
+ */
+ board.target = (((board_info_v9.platform_subtype & 0xff) << 24) |
+ (((board_info_v9.platform_version >> 16) & 0xff) << 16) |
+ ((board_info_v9.platform_version & 0xff) << 8) |
+ (board_info_v9.board_info_v3.hw_platform & 0xff));
+
+ for (i = 0; i < SMEM_V8_SMEM_MAX_PMIC_DEVICES; i++) {
+ board.pmic_info[i].pmic_type = board_info_v9.pmic_info[i].pmic_type;
+ board.pmic_info[i].pmic_version = board_info_v9.pmic_info[i].pmic_version;
+
+ /*
+ * fill in pimc_board_info with pmic type and pmic version information
+ * bit no |31 24 | 23 16 | 15 8 |7 0|
+ * pimc_board_info = |Unused | Major version | Minor version|PMIC_MODEL|
+ *
+ */
+ pmic_type = board_info_v9.pmic_info[i].pmic_type == PMIC_IS_INVALID? 0 : board_info_v9.pmic_info[i].pmic_type;
+
+ board.pmic_info[i].pmic_target = (((board_info_v9.pmic_info[i].pmic_version >> 16) & 0xff) << 16) |
+ ((board_info_v9.pmic_info[i].pmic_version & 0xff) << 8) | (pmic_type & 0xff);
+ }
+ board.foundry_id = board_info_v9.foundry_id;
+ }
+ else if (format_minor >= 0xA)
+ {
+ board_info_len = sizeof(board_info_v10);
+
+ ret = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v10,
+ board_info_len);
+ if (ret)
+ return;
+
+ board.platform = board_info_v10.board_info_v3.msm_id;
+ board.platform_version = board_info_v10.board_info_v3.msm_version;
+ board.platform_hw = board_info_v10.board_info_v3.hw_platform;
+ board.platform_subtype = board_info_v10.platform_subtype;
+
+ /*
+ * fill in board.target with variant_id information
+ * bit no |31 24 | 23 16 | 15 8 |7 0|
+ * board.target = |subtype| plat_hw_ver major | plat_hw_ver minor |hw_platform|
+ *
+ */
+ board.target = (((board_info_v10.platform_subtype & 0xff) << 24) |
+ (((board_info_v10.platform_version >> 16) & 0xff) << 16) |
+ ((board_info_v10.platform_version & 0xff) << 8) |
+ (board_info_v10.board_info_v3.hw_platform & 0xff));
+
+ for (i = 0; i < SMEM_V8_SMEM_MAX_PMIC_DEVICES; i++) {
+ board.pmic_info[i].pmic_type = board_info_v10.pmic_info[i].pmic_type;
+ board.pmic_info[i].pmic_version = board_info_v10.pmic_info[i].pmic_version;
+
+ /*
+ * fill in pimc_board_info with pmic type and pmic version information
+ * bit no |31 24 | 23 16 | 15 8 |7 0|
+ * pimc_board_info = |Unused | Major version | Minor version|PMIC_MODEL|
+ *
+ */
+ pmic_type = board_info_v10.pmic_info[i].pmic_type == PMIC_IS_INVALID? 0 : board_info_v10.pmic_info[i].pmic_type;
+
+ board.pmic_info[i].pmic_target = (((board_info_v10.pmic_info[i].pmic_version >> 16) & 0xff) << 16) |
+ ((board_info_v10.pmic_info[i].pmic_version & 0xff) << 8) | (pmic_type & 0xff);
+ }
+ board.foundry_id = board_info_v10.foundry_id;
+ board.chip_serial = board_info_v10.chip_serial;
}
/* HLOS subtype
- * bit no |31 20 | 19 16| 15 8 | 7 0|
- * board.platform_hlos_subtype = |reserved | Boot device | DDR detection | subtype|
- * | bits | | bits |
+ * bit no |31 20 | 19 16|15 13 |12 11 | 10 8 | 7 0|
+ * board.platform_hlos_subtype = |reserved | Boot device |Reserved | Panel | DDR detection | subtype|
+ * | bits | | bits | Detection |
*/
- board.platform_hlos_subtype = (board_get_ddr_subtype() << 8) | (platform_get_boot_dev() << 16);
+ board.platform_hlos_subtype = (board_get_ddr_subtype() << 8) | (platform_get_boot_dev() << 16) | (platform_detect_panel() << 11);
}
else
{
diff --git a/platform/msm_shared/boot_device.c b/platform/msm_shared/boot_device.c
index c120b6c..ac29dac 100644
--- a/platform/msm_shared/boot_device.c
+++ b/platform/msm_shared/boot_device.c
@@ -69,9 +69,7 @@
void platform_boot_dev_cmdline(char *buf)
{
uint32_t val = 0;
- void *dev;
-
- dev = target_mmc_device();
+ void *dev = target_mmc_device();
val = platform_get_boot_dev();
switch(val)
diff --git a/platform/msm_shared/boot_stats.c b/platform/msm_shared/boot_stats.c
index 551000e..20635f2 100644
--- a/platform/msm_shared/boot_stats.c
+++ b/platform/msm_shared/boot_stats.c
@@ -30,6 +30,7 @@
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
+#include <platform.h>
static uint32_t kernel_load_start;
void bs_set_timestamp(enum bs_entry bs_id)
diff --git a/platform/msm_shared/boot_verifier.c b/platform/msm_shared/boot_verifier.c
index 79accbf..0457ee3 100644
--- a/platform/msm_shared/boot_verifier.c
+++ b/platform/msm_shared/boot_verifier.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -26,6 +26,7 @@
*/
#include <stdlib.h>
+#include <stdint.h>
#include <crypto_hash.h>
#include <boot_verifier.h>
#include <image_verify.h>
@@ -36,6 +37,7 @@
#include <partition_parser.h>
#include <rsa.h>
#include <string.h>
+#include <openssl/err.h>
static KEYSTORE *oem_keystore;
static KEYSTORE *user_keystore;
@@ -43,7 +45,7 @@
BUF_DMA_ALIGN(keystore_buf, 4096);
char KEYSTORE_PTN_NAME[] = "keystore";
-static char *VERIFIED_FLASH_ALLOWED_PTN[] = {
+static const char *VERIFIED_FLASH_ALLOWED_PTN[] = {
"aboot",
"boot",
"recovery",
@@ -138,7 +140,7 @@
return ret;
}
- sig = d2i_X509_SIG(NULL, &input, len);
+ sig = d2i_X509_SIG(NULL, (const unsigned char **) &input, len);
if(sig == NULL)
{
dprintf(CRITICAL, "boot_verifier: Reading digest failed\n");
@@ -221,7 +223,7 @@
/* Verify target name */
if(strncmp((char*)(sig->auth_attr->target->data), pname,
sig->auth_attr->target->length) ||
- (strlen(pname) != sig->auth_attr->target->length))
+ (strlen(pname) != (unsigned long) sig->auth_attr->target->length))
{
dprintf(CRITICAL,
"boot_verifier: verification failure due to target name mismatch\n");
@@ -308,19 +310,19 @@
{
KEYSTORE *ks = NULL;
uint32_t len = 0;
- unsigned char *input = OEM_KEYSTORE;
+ const unsigned char *input = OEM_KEYSTORE;
if(oem_keystore != NULL)
return;
- len = read_der_message_length(input);
+ len = read_der_message_length((unsigned char *)input);
if(!len)
{
dprintf(CRITICAL, "boot_verifier: oem keystore length is invalid.\n");
return;
}
- ks = d2i_KEYSTORE(NULL, &input, len);
+ ks = d2i_KEYSTORE(NULL, (const unsigned char **) &input, len);
if(ks != NULL)
{
oem_keystore = ks;
@@ -358,7 +360,7 @@
return;
}
- ks = d2i_KEYSTORE(NULL, &input, len);
+ ks = d2i_KEYSTORE(NULL, (const unsigned char **)&input, len);
if(ks != NULL)
{
if(verify_keystore(user_addr, ks) == false)
@@ -407,7 +409,7 @@
goto verify_image_error;
}
- if((sig = d2i_VERIFIED_BOOT_SIG(NULL, &sig_addr, sig_len)) == NULL)
+ if((sig = d2i_VERIFIED_BOOT_SIG(NULL, (const unsigned char **) &sig_addr, sig_len)) == NULL)
{
dprintf(CRITICAL,
"boot_verifier: verification failure due to target name mismatch\n");
@@ -485,7 +487,7 @@
return ret;
}
- ks = d2i_KEYSTORE(NULL, &input, len);
+ ks = d2i_KEYSTORE(NULL, (const unsigned char **)&input, len);
if(ks != NULL)
{
ret = true;
@@ -493,9 +495,8 @@
return ret;
}
-static bool check_list(char**list, char* entry)
+static bool check_list(const char **list, const char* entry)
{
- int i = 0;
if(list == NULL || entry == NULL)
return false;
@@ -510,7 +511,7 @@
return false;
}
-bool boot_verify_flash_allowed(char * entry)
+bool boot_verify_flash_allowed(const char * entry)
{
return check_list(VERIFIED_FLASH_ALLOWED_PTN, entry);
}
diff --git a/platform/msm_shared/clock_lib2.c b/platform/msm_shared/clock_lib2.c
index f5e321a..cc87c92 100644
--- a/platform/msm_shared/clock_lib2.c
+++ b/platform/msm_shared/clock_lib2.c
@@ -270,5 +270,5 @@
if (!bclk)
return 0;
- return __clock_lib2_branch_clk_reset(bclk->bcr_reg, action);
+ return __clock_lib2_branch_clk_reset((uint32_t)bclk->bcr_reg, action);
}
diff --git a/platform/msm_shared/crypto5_eng.c b/platform/msm_shared/crypto5_eng.c
index 0f592f9..8caad79 100644
--- a/platform/msm_shared/crypto5_eng.c
+++ b/platform/msm_shared/crypto5_eng.c
@@ -139,6 +139,8 @@
#else
ret = (uint32_t)bam_add_cmd_element(&cmd_list_ptr, reg_addr, val, CE_WRITE_TYPE);
+ arch_clean_invalidate_cache_range((addr_t)&cmd_list_ptr, sizeof(struct cmd_element));
+
/* Enqueue the desc for the above command */
ret = bam_add_one_desc(bam_core,
CRYPTO_WRITE_PIPE_INDEX,
diff --git a/platform/msm_shared/crypto_hash.c b/platform/msm_shared/crypto_hash.c
index 0d3cce8..9a2cdc9 100644
--- a/platform/msm_shared/crypto_hash.c
+++ b/platform/msm_shared/crypto_hash.c
@@ -27,6 +27,7 @@
*/
#include <string.h>
+#include <sha.h>
#include <debug.h>
#include <sys/types.h>
#include "crypto_hash.h"
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
old mode 100644
new mode 100755
index 36b2a3a..0abf723
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -37,6 +37,8 @@
#include <board.h>
#include <list.h>
#include <kernel/thread.h>
+#include <target.h>
+#include <partial_goods.h>
struct dt_entry_v1
{
@@ -455,7 +457,7 @@
break;
dtb_size = fdt_totalsize(&dtb_hdr);
- if (check_aboot_addr_range_overlap(tags, dtb_size)) {
+ if (check_aboot_addr_range_overlap((uint32_t)tags, dtb_size)) {
dprintf(CRITICAL, "Tags addresses overlap with aboot addresses.\n");
return NULL;
}
@@ -484,7 +486,7 @@
}
/* free queue's memory */
list_for_every_entry(&dt_entry_queue->node, dt_node_tmp1, dt_node, node) {
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
}
@@ -540,7 +542,7 @@
static int platform_dt_absolute_match(struct dt_entry *cur_dt_entry, struct dt_entry_node *dt_list)
{
- uint32_t cur_dt_hlos_subtype;
+ uint32_t cur_dt_hlos_ddr;
uint32_t cur_dt_hw_platform;
uint32_t cur_dt_hw_subtype;
uint32_t cur_dt_msm_id;
@@ -554,9 +556,8 @@
cur_dt_hw_platform = (cur_dt_entry->variant_id & 0x000000ff);
cur_dt_hw_subtype = (cur_dt_entry->board_hw_subtype & 0xff);
-
- /* Determine the bits 23:8 to check the DT with the DDR Size */
- cur_dt_hlos_subtype = (cur_dt_entry->board_hw_subtype & 0xffff00);
+ /* Determine the bits 10:8 to check the DT with the DDR Size */
+ cur_dt_hlos_ddr = (cur_dt_entry->board_hw_subtype & 0x700);
/* 1. must match the msm_id, platform_hw_id, platform_subtype and DDR size
* soc, board major/minor, pmic major/minor must less than board info
@@ -566,7 +567,7 @@
if((cur_dt_msm_id == (board_platform_id() & 0x0000ffff)) &&
(cur_dt_hw_platform == board_hardware_id()) &&
(cur_dt_hw_subtype == board_hardware_subtype()) &&
- (cur_dt_hlos_subtype == target_get_hlos_subtype()) &&
+ (cur_dt_hlos_ddr == (target_get_hlos_subtype() & 0x700)) &&
(cur_dt_entry->soc_rev <= board_soc_version()) &&
((cur_dt_entry->variant_id & 0x00ffff00) <= (board_target_id() & 0x00ffff00)) &&
((cur_dt_entry->pmic_rev[0] & 0x00ffff00) <= (board_pmic_target(0) & 0x00ffff00)) &&
@@ -622,6 +623,14 @@
board_pmic_model[i] = (board_pmic_target(i) & 0xff);
}
break;
+ case DTB_PANEL_TYPE:
+ current_info = ((dt_node_tmp1->dt_entry_m->board_hw_subtype) & 0x1800);
+ board_info = (target_get_hlos_subtype() & 0x1800);
+ break;
+ case DTB_BOOT_DEVICE:
+ current_info = ((dt_node_tmp1->dt_entry_m->board_hw_subtype) & 0xf0000);
+ board_info = (target_get_hlos_subtype() & 0xf0000);
+ break;
default:
dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
dtb_info);
@@ -661,6 +670,12 @@
current_pmic_model[i] = (dt_node_tmp1->dt_entry_m->pmic_rev[i] & 0xff);
}
break;
+ case DTB_PANEL_TYPE:
+ current_info = ((dt_node_tmp1->dt_entry_m->board_hw_subtype) & 0x1800);
+ break;
+ case DTB_BOOT_DEVICE:
+ current_info = ((dt_node_tmp1->dt_entry_m->board_hw_subtype) & 0xf0000);
+ break;
default:
dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
dtb_info);
@@ -689,7 +704,7 @@
dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
delete_current_dt = 0;
@@ -758,7 +773,7 @@
dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
}
@@ -802,7 +817,7 @@
dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
}
@@ -828,6 +843,20 @@
if (!platform_dt_absolute_compat_match(dt_list, DTB_PMIC_MODEL))
return NULL;
+ /* check panel type
+ * the panel type must exact match board panel type, this is compatibility check,
+ * if couldn't find the exact match from DTB, will exact match 0x0.
+ */
+ if (!platform_dt_absolute_compat_match(dt_list, DTB_PANEL_TYPE))
+ return NULL;
+
+ /* check boot device subtype
+ * the boot device subtype must exact match board boot device subtype, this is compatibility check,
+ * if couldn't find the exact match from DTB, will exact match 0x0.
+ */
+ if (!platform_dt_absolute_compat_match(dt_list, DTB_BOOT_DEVICE))
+ return NULL;
+
/* check soc version
* the suitable soc version must less than or equal to board soc version
*/
@@ -1012,7 +1041,7 @@
list_for_every_entry(&dt_entry_queue->node, dt_node_tmp1, dt_node, node) {
/* free node memory */
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
}
@@ -1300,6 +1329,10 @@
fdt_pack(fdt);
+#if ENABLE_PARTIAL_GOODS_SUPPORT
+ update_partial_goods_dtb_nodes(fdt);
+#endif
+
return ret;
}
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index f0b6020..ecffcc4 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -32,6 +32,13 @@
#include <mdp4.h>
#include <mipi_dsi.h>
#include <boot_stats.h>
+#include <platform.h>
+#include <malloc.h>
+#include <qpic.h>
+#include <target.h>
+#ifdef DISPLAY_TYPE_MDSS
+#include <target/display.h>
+#endif
static struct msm_fb_panel_data *panel;
@@ -56,7 +63,9 @@
int msm_display_config()
{
int ret = NO_ERROR;
+#ifdef DISPLAY_TYPE_MDSS
int mdp_rev;
+#endif
struct msm_panel_info *pinfo;
if (!panel)
@@ -132,7 +141,7 @@
#ifdef DISPLAY_TYPE_QPIC
case QPIC_PANEL:
dprintf(INFO, "Config QPIC_PANEL.\n");
- qpic_init(pinfo, panel->fb.base);
+ qpic_init(pinfo, (int) panel->fb.base);
break;
#endif
default:
@@ -142,14 +151,18 @@
if (pinfo->config)
ret = pinfo->config((void *)pinfo);
+#ifdef DISPLAY_TYPE_MDSS
msm_display_config_out:
+#endif
return ret;
}
int msm_display_on()
{
int ret = NO_ERROR;
+#ifdef DISPLAY_TYPE_MDSS
int mdp_rev;
+#endif
struct msm_panel_info *pinfo;
if (!panel)
@@ -186,7 +199,7 @@
if (ret)
goto msm_display_on_out;
- ret = mipi_dsi_on();
+ ret = mipi_dsi_on(pinfo);
if (ret)
goto msm_display_on_out;
break;
@@ -220,7 +233,7 @@
if (ret)
goto msm_display_on_out;
- ret = mdss_hdmi_on();
+ ret = mdss_hdmi_on(pinfo);
if (ret)
goto msm_display_on_out;
break;
@@ -270,9 +283,12 @@
if (ret)
goto msm_display_init_out;
+ if (pdata->dfps_func)
+ ret = pdata->dfps_func(&(panel->panel_info));
+
/* Enable clock */
if (pdata->clk_func)
- ret = pdata->clk_func(1);
+ ret = pdata->clk_func(1, &(panel->panel_info));
/* Only enabled for auto PLL calculation */
if (pdata->pll_clk_func)
@@ -348,7 +364,7 @@
break;
case MIPI_VIDEO_PANEL:
dprintf(INFO, "Turn off MIPI_VIDEO_PANEL.\n");
- ret = mdp_dsi_video_off();
+ ret = mdp_dsi_video_off(pinfo);
if (ret)
goto msm_display_off_out;
ret = mipi_dsi_off(pinfo);
@@ -404,7 +420,7 @@
/* Disable clock */
if (panel->clk_func)
- ret = panel->clk_func(0);
+ ret = panel->clk_func(0, pinfo);
/* Only for AUTO PLL calculation */
if (panel->pll_clk_func)
diff --git a/platform/msm_shared/dme.c b/platform/msm_shared/dme.c
index 61efb47..e128453 100644
--- a/platform/msm_shared/dme.c
+++ b/platform/msm_shared/dme.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -101,6 +101,7 @@
switch (resp_upiu->opcode)
{
+ case UPIU_QUERY_OP_READ_ATTRIBUTE:
case UPIU_QUERY_OP_READ_FLAG:
case UPIU_QUERY_OP_SET_FLAG:
if (buf_len < sizeof(uint32_t))
@@ -137,7 +138,7 @@
req_upiu.idn = query->idn;
req_upiu.trans_type = UPIU_TYPE_QUERY_REQ;
req_upiu.dd = UTRD_NO_DATA_TRANSFER;
- req_upiu.resp_ptr = (struct upiu_basic_hdr *) &resp_upiu;
+ req_upiu.resp_ptr = (struct upiu_basic_resp_hdr *) &resp_upiu;
req_upiu.resp_len = sizeof(resp_upiu);
req_upiu.resp_data_ptr = query->buf;
req_upiu.timeout_msecs = UTP_GENERIC_CMD_TIMEOUT;
@@ -159,6 +160,79 @@
return ret;
}
+int dme_set_fpurgeenable(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
+ STACKBUF_DMA_ALIGN(status, sizeof(uint32_t));
+ uint32_t try_again = DME_BPURGESTATUS_RETRIES;
+ struct utp_query_req_upiu_type set_query = {UPIU_QUERY_OP_SET_FLAG,
+ UFS_IDX_fPurgeEn,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+ struct utp_query_req_upiu_type read_query = {UPIU_QUERY_OP_READ_ATTRIBUTE,
+ UFS_IDX_bPurgeStatus,
+ 0,
+ 0,
+ (addr_t)status,
+ sizeof(uint32_t)};
+
+ if (dme_send_query_upiu(dev, &set_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Purge Enable failed\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ }
+
+ arch_invalidate_cache_range((addr_t) result, sizeof(uint32_t));
+ dprintf(INFO, "%s:%d Purge enable status: %u\n", __func__,__LINE__, *result);
+
+ do {
+ *status = 0;
+ arch_invalidate_cache_range((addr_t) status, sizeof(uint32_t));
+ if (dme_send_query_upiu(dev, &read_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Purge Status Read failed\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ }
+
+ switch (*status)
+ {
+
+ case 0x0:
+#ifdef DEBUG_UFS
+ dprintf(INFO, "%s:%d Purge operation returning to ufs_erase. Purge Status 0x0\n", __func__, __LINE__);
+#endif
+ return UFS_SUCCESS;
+ case 0x3:
+#ifdef DEBUG_UFS
+ dprintf(INFO, "%s:%d Purge operation has completed. Purge Status:0x3\n", __func__, __LINE__);
+#endif
+ // next read of status will move to 0
+ continue;
+ case 0x1:
+#ifdef DEBUG_UFS
+ dprintf(INFO, "%s:%d Purge operation is still in progress.. Retrying\n", __func__, __LINE__);
+#endif
+ try_again--;
+ continue;
+ case 0x2:
+ dprintf(CRITICAL, "%s:%d Purge operation stopped prematurely\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ case 0x4:
+ dprintf(CRITICAL, "%s:%d Purge operation failed due to logical unit queue not empty\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ case 0x5:
+ dprintf(CRITICAL, "%s:%d Purge operation general failure\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ }
+ } while((*status == 0x1 || *status == 0x3) && try_again);
+
+ // should not come here
+ dprintf(CRITICAL, "%s:%d Purge operation timed out after checking status %d times\n", __func__, __LINE__, DME_BPURGESTATUS_RETRIES);
+ return -UFS_FAILURE;
+}
+
int dme_set_fpoweronwpen(struct ufs_dev *dev)
{
STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
@@ -430,7 +504,7 @@
int dme_send_nop_query(struct ufs_dev *dev)
{
struct upiu_req_build_type req_upiu;
- struct upiu_basic_hdr resp_upiu;
+ struct upiu_basic_resp_hdr resp_upiu;
int ret;
unsigned try_again;
@@ -491,6 +565,7 @@
switch (upiu_data->opcode)
{
case UPIU_QUERY_OP_READ_FLAG:
+ case UPIU_QUERY_OP_READ_ATTRIBUTE:
case UPIU_QUERY_OP_READ_DESCRIPTOR:
req_upiu->basic_hdr.query_task_mgmt_func = UPIU_QUERY_FUNC_STD_READ_REQ;
break;
diff --git a/platform/msm_shared/flash-ubi.c b/platform/msm_shared/flash-ubi.c
new file mode 100644
index 0000000..0051a3a
--- /dev/null
+++ b/platform/msm_shared/flash-ubi.c
@@ -0,0 +1,615 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <dev/flash-ubi.h>
+#include <dev/flash.h>
+#include <qpic_nand.h>
+#include <rand.h>
+
+static
+const uint32_t crc32_table[256] = {
+ 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
+ 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
+ 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
+ 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
+ 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
+ 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
+ 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
+ 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
+ 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
+ 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
+ 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
+ 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
+ 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
+ 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
+ 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
+ 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
+ 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
+ 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
+ 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
+ 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
+ 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
+ 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
+ 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
+ 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
+ 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
+ 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
+ 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
+ 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
+ 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
+ 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
+ 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
+ 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
+ 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
+ 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
+ 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
+ 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
+ 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
+ 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
+ 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
+ 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
+ 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
+ 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
+ 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
+ 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
+ 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
+ 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
+ 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
+ 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
+ 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
+ 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
+ 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
+ 0x2d02ef8dL
+};
+
+static uint32_t mtd_crc32(uint32_t crc, const void *buf, size_t size)
+{
+ const uint8_t *p = buf;
+
+ while (size--)
+ crc = crc32_table[(crc ^ *p++) & 0xff] ^ (crc >> 8);
+ return crc;
+}
+
+/**
+ * check_pattern - check if buffer contains only a certain byte pattern.
+ * @buf: buffer to check
+ * @patt: the pattern to check
+ * @size: buffer size in bytes
+ *
+ * This function returns %1 if there are only @patt bytes in @buf, and %0 if
+ * something else was also found.
+ */
+int check_pattern(const void *buf, uint8_t patt, int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++)
+ if (((const uint8_t *)buf)[i] != patt)
+ return 0;
+ return 1;
+}
+
+/**
+ * read_ec_hdr - read and check an erase counter header.
+ * @peb: number of the physical erase block to read the header for
+ * @ec_hdr: a &struct ubi_ec_hdr object where to store the read erase counter
+ * header
+ *
+ * This function reads erase counter header from physical eraseblock @peb and
+ * stores it in @ec_hdr. This function also checks the validity of the read
+ * header.
+ *
+ * Return codes:
+ * -1 - in case of error
+ * 0 - if PEB was found valid
+ * 1 - if PEB is empty
+ */
+static int read_ec_hdr(uint32_t peb, struct ubi_ec_hdr *ec_hdr)
+{
+ unsigned char *spare, *tmp_buf;
+ int ret = -1;
+ uint32_t crc;
+ int page_size = flash_page_size();
+ int num_pages_per_blk = flash_block_size()/page_size;
+
+ spare = (unsigned char *)malloc(flash_spare_size());
+ if (!spare)
+ {
+ dprintf(CRITICAL, "read_ec_hdr: Mem allocation failed\n");
+ return ret;
+ }
+
+ tmp_buf = (unsigned char *)malloc(page_size);
+ if (!tmp_buf)
+ {
+ dprintf(CRITICAL, "read_ec_hdr: Mem allocation failed\n");
+ goto out_tmp_buf;
+ }
+
+ if (qpic_nand_block_isbad(peb * num_pages_per_blk)) {
+ dprintf(CRITICAL, "read_ec_hdr: Bad block @ %d\n", peb);
+ goto out;
+ }
+
+ if (qpic_nand_read(peb * num_pages_per_blk, 1, tmp_buf, spare)) {
+ dprintf(CRITICAL, "read_ec_hdr: Read %d failed \n", peb);
+ goto out;
+ }
+ memcpy(ec_hdr, tmp_buf, UBI_EC_HDR_SIZE);
+
+ if (check_pattern((void *)ec_hdr, 0xFF, UBI_EC_HDR_SIZE)) {
+ ret = 1;
+ goto out;
+ }
+
+ /* Make sure we read a valid UBI EC_HEADER */
+ if (BE32(ec_hdr->magic) != (uint32_t)UBI_EC_HDR_MAGIC) {
+ dprintf(CRITICAL,
+ "read_ec_hdr: Wrong magic at peb-%d Expected: %d, received %d\n",
+ peb, UBI_EC_HDR_MAGIC, BE32(ec_hdr->magic));
+ goto out;
+ }
+
+ if (ec_hdr->version != UBI_VERSION) {
+ dprintf(CRITICAL,
+ "read_ec_hdr: Wrong version at peb-%d Expected: %d, received %d\n",
+ peb, UBI_VERSION, ec_hdr->version);
+ goto out;
+ }
+
+ if (BE64(ec_hdr->ec) > UBI_MAX_ERASECOUNTER) {
+ dprintf(CRITICAL,
+ "read_ec_hdr: Wrong ec at peb-%d: %lld \n",
+ peb, BE64(ec_hdr->ec));
+ goto out;
+ }
+
+ crc = mtd_crc32(UBI_CRC32_INIT, ec_hdr, UBI_EC_HDR_SIZE_CRC);
+ if (BE32(ec_hdr->hdr_crc) != crc) {
+ dprintf(CRITICAL,
+ "read_ec_hdr: Wrong crc at peb-%d: calculated %d, recived %d\n",
+ peb,crc, BE32(ec_hdr->hdr_crc));
+ goto out;
+ }
+
+ ret = 0;
+out:
+ free(tmp_buf);
+out_tmp_buf:
+ free(spare);
+ return ret;
+}
+
+/**
+ * write_ec_header() - Write provided ec_header for given PEB
+ * @peb: number of the physical erase block to write the header to
+ * @new_ech: the ec_header to write
+ *
+ * Return codes:
+ * -1 - in case of error
+ * 0 - on success
+ */
+static int write_ec_header(uint32_t peb, struct ubi_ec_hdr *new_ech)
+{
+ unsigned page_size = flash_page_size();
+ int num_pages_per_blk = flash_block_size()/page_size;
+ unsigned char *buf;
+ int ret = 0;
+
+ buf = malloc(sizeof(uint8_t) * page_size);
+ if (!buf) {
+ dprintf(CRITICAL, "write_ec_header: Mem allocation failed\n");
+ return -1;
+ }
+
+ memset(buf, 0, page_size);
+ ASSERT(page_size > sizeof(*new_ech));
+ memcpy(buf, new_ech, UBI_EC_HDR_SIZE);
+ ret = qpic_nand_write(peb * num_pages_per_blk, 1, buf, 0);
+ if (ret) {
+ dprintf(CRITICAL,
+ "write_ec_header: qpic_nand_write failed with %d\n", ret);
+ ret = -1;
+ goto out;
+ }
+
+out:
+ free(buf);
+ return ret;
+}
+
+/**
+ * scan_partition() - Collect the ec_headers info of a given partition
+ * @ptn: partition to read the headers of
+ *
+ * Returns allocated and filled struct ubi_scan_info (si).
+ * Note: si should be released by caller.
+ */
+static struct ubi_scan_info *scan_partition(struct ptentry *ptn)
+{
+ struct ubi_scan_info *si;
+ struct ubi_ec_hdr *ec_hdr;
+ unsigned i, curr_peb;
+ unsigned long long sum = 0;
+ int page_size = flash_page_size();
+ int ret;
+
+ si = malloc(sizeof(*si));
+ if (!si) {
+ dprintf(CRITICAL,"scan_partition: (%s) Memory allocation failed\n",
+ ptn->name);
+ return NULL;
+ }
+
+ memset((void *)si, 0, sizeof(*si));
+ si->ec = malloc(ptn->length * sizeof(uint64_t));
+ if (!si->ec) {
+ dprintf(CRITICAL,"scan_partition: (%s) Memory allocation failed\n",
+ ptn->name);
+ goto out_failed_ec;
+ }
+ memset((void *)si->ec, 0, ptn->length * sizeof(uint64_t));
+
+ ec_hdr = malloc(UBI_EC_HDR_SIZE);
+ if (!ec_hdr) {
+ dprintf(CRITICAL,"scan_partition: (%s) Memory allocation failed\n",
+ ptn->name);
+ goto out_failed;
+ }
+
+ curr_peb = ptn->start;
+ si->vid_hdr_offs = 0;
+ si->image_seq = rand() & UBI_IMAGE_SEQ_BASE;
+
+ for (i = 0; i < ptn->length; i++){
+ ret = read_ec_hdr(curr_peb + i, ec_hdr);
+ switch (ret) {
+ case 1:
+ si->empty_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ break;
+ case 0:
+ if (!si->vid_hdr_offs) {
+ si->vid_hdr_offs = BE32(ec_hdr->vid_hdr_offset);
+ si->data_offs = BE32(ec_hdr->data_offset);
+ if (!si->vid_hdr_offs || !si->data_offs ||
+ si->vid_hdr_offs % page_size ||
+ si->data_offs % page_size) {
+ si->bad_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ si->vid_hdr_offs = 0;
+ continue;
+ }
+ if (BE32(ec_hdr->vid_hdr_offset) != si->vid_hdr_offs) {
+ si->bad_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ continue;
+ }
+ if (BE32(ec_hdr->data_offset) != si->data_offs) {
+ si->bad_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ continue;
+ }
+ }
+ si->good_cnt++;
+ si->ec[i] = BE64(ec_hdr->ec);
+ break;
+ case -1:
+ default:
+ si->bad_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ break;
+ }
+ }
+
+ /*
+ * If less then 95% of the PEBs were "bad" (didn't have valid
+ * ec header), then set mean_ec = UBI_DEF_ERACE_COUNTER.
+ */
+ sum = 0;
+ if (si->good_cnt && (double)(si->good_cnt / ptn->length) * 100 > 95) {
+ for (i = 0; i < ptn->length; i++) {
+ if (si->ec[i] == UBI_MAX_ERASECOUNTER)
+ continue;
+ sum += si->ec[i];
+ }
+ si->mean_ec = sum / si->good_cnt;
+ } else {
+ si->mean_ec = UBI_DEF_ERACE_COUNTER;
+ }
+ free(ec_hdr);
+ return si;
+
+out_failed:
+ free(si->ec);
+out_failed_ec:
+ free(si);
+ return NULL;
+}
+
+/**
+ * update_ec_header() - Update provided ec_header
+ * @si: pointer to struct ubi_scan_info, holding the collected
+ * ec_headers information of the partition
+ * @index: index in si->ec[] of this peb. Relative to ptn->start
+ * @new_header: False if this is an update of an existing header.
+ * True if new header needs to be filled in
+ */
+static void update_ec_header(struct ubi_ec_hdr *old_ech,
+ const struct ubi_scan_info *si,
+ int index, bool new_header)
+{
+ uint32_t crc;
+
+ if (si->ec[index] < UBI_MAX_ERASECOUNTER)
+ old_ech->ec = BE64(si->ec[index] + 1);
+ else
+ old_ech->ec = BE64(si->mean_ec);
+
+ if (new_header) {
+ old_ech->vid_hdr_offset = BE32(si->vid_hdr_offs);
+ old_ech->data_offset = BE32(si->data_offs);
+ old_ech->magic = BE32(UBI_EC_HDR_MAGIC);
+ old_ech->version = UBI_VERSION;
+ }
+ old_ech->image_seq = BE32(si->image_seq);
+ crc = mtd_crc32(UBI_CRC32_INIT,
+ (const void *)old_ech, UBI_EC_HDR_SIZE_CRC);
+ old_ech->hdr_crc = BE32(crc);
+}
+
+/**
+ * calc_data_len - calculate how much real data is stored in the buffer
+ * @page_size: min I/O of the device
+ * @buf: a buffer with the contents of the physical eraseblock
+ * @len: the buffer length
+ *
+ * This function calculates how much "real data" is stored in @buf and
+ * returns the length (in number of pages). Continuous 0xFF bytes at the end
+ * of the buffer are not considered as "real data".
+ */
+static int calc_data_len(int page_size, const void *buf, int len)
+{
+ int i;
+
+ for (i = len - 1; i >= 0; i--)
+ if (((const uint8_t *)buf)[i] != 0xFF)
+ break;
+
+ /* The resulting length must be aligned to the minimum flash I/O size */
+ len = i + 1;
+ len = (len + page_size - 1) / page_size;
+ return len;
+}
+
+/**
+ * fastmap_present - returns true if Fastmap superblock is found
+ * @data: raw data to test
+ *
+ * This function returns 1 if the provided PEB data contains
+ * Fastmap superblock, 0 otherwise
+ */
+static int fastmap_present(const void *data){
+ struct ubi_ec_hdr *ec_hdr = (struct ubi_ec_hdr *)(data);
+ struct ubi_vid_hdr *vid_hdr;
+
+ vid_hdr = (struct ubi_vid_hdr *)(data + BE32(ec_hdr->vid_hdr_offset));
+ if (BE32(vid_hdr->vol_id) == UBI_FM_SB_VOLUME_ID)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * ubi_erase_peb - Erase PEB and update EC header
+ * @peb_num: number of the PEB to erase
+ * @need_erase: if true PEB will be erased
+ * @si: UBI scan information
+ * @ptn_start: first PEB of the flashed partition
+ *
+ * This function erases the given PEB (if required) and writes a new EC
+ * header for it.
+ *
+ * Returns: -1 on error
+ * 0 on success
+ */
+static int ubi_erase_peb(int peb_num, int need_erase,
+ struct ubi_scan_info *si, int ptn_start)
+{
+ struct ubi_ec_hdr new_ech;
+ int page_size = flash_page_size();
+ int num_pages_per_blk = flash_block_size() / page_size;
+ int ret;
+
+ if (need_erase && qpic_nand_blk_erase(peb_num * num_pages_per_blk)) {
+ dprintf(INFO, "flash_ubi_img: erase of %d failed\n", peb_num);
+ return -1;
+ }
+ memset(&new_ech, 0xff, sizeof(new_ech));
+ update_ec_header(&new_ech, si, peb_num - ptn_start, true);
+
+ /* Write new ec_header */
+ ret = write_ec_header(peb_num, &new_ech);
+ if (ret) {
+ dprintf(CRITICAL, "flash_ubi_img: write ec_header to %d failed\n",
+ peb_num);
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * remove_F_flag() - Turn off space-fixup flag in the ubifs superblock
+ * @data: pointer to the peb to check in the flashed image
+ *
+ * The UBIFS Superblock will be located at LEB 0 of the image. LEB 0 will be
+ * mapped as follows:
+ * If the image contains Fastmap superblock:
+ * - LEB 0 will be at PEB3
+ * else:
+ * - LEB 0 will be at PEB2
+ */
+static void remove_F_flag(const void *leb_data)
+{
+ struct ubifs_ch *ch;
+ struct ubifs_sb_node *ubifs_sb;
+ struct ubi_ec_hdr *ech;
+ struct ubi_vid_hdr *vidh;
+ int vol_id;
+
+ ech = (struct ubi_ec_hdr *)leb_data;
+ vidh = (struct ubi_vid_hdr *)(leb_data + BE32(ech->vid_hdr_offset));
+ vol_id = BE32(vidh->vol_id);
+
+ if (vol_id > UBI_MAX_VOLUMES &&
+ vol_id != UBI_LAYOUT_VOLUME_ID &&
+ vol_id != UBI_FM_SB_VOLUME_ID)
+ return;
+
+ ubifs_sb = (struct ubifs_sb_node *)(leb_data + BE32(ech->data_offset));
+ ch = (struct ubifs_ch *)ubifs_sb;
+ if (ch->node_type != UBIFS_SB_NODE)
+ return;
+ if (ubifs_sb->flags & UBIFS_FLG_SPACE_FIXUP) {
+ ubifs_sb->flags &= (~UBIFS_FLG_SPACE_FIXUP);
+ ch->crc = mtd_crc32(UBIFS_CRC32_INIT, (void *)ubifs_sb + 8,
+ sizeof(struct ubifs_sb_node) - 8);
+ }
+}
+
+/**
+ * flash_ubi_img() - Write the provided (UBI) image to given partition
+ * @ptn: partition to write the image to
+ * @data: the image to write
+ * @size: size of the image to write
+ *
+ * Return codes:
+ * -1 - in case of error
+ * 0 - on success
+ */
+int flash_ubi_img(struct ptentry *ptn, void *data, unsigned size)
+{
+ struct ubi_scan_info *si;
+ struct ubi_ec_hdr *old_ech;
+ uint32_t curr_peb = ptn->start;
+ void *img_peb;
+ unsigned page_size = flash_page_size();
+ unsigned block_size = flash_block_size();
+ int num_pages_per_blk = block_size / page_size;
+ int num_pages;
+ int ret, need_erase;
+ int bad_blocks_cnt = 0;
+ int fmsb_peb = 0;
+
+ si = scan_partition(ptn);
+ if (!si) {
+ dprintf(CRITICAL, "flash_ubi_img: scan_partition failed\n");
+ return -1;
+ }
+
+ /*
+ * In case si->vid_hdr_offs is still -1 (non UBI image was
+ * flashed on device, get the value from the image to flush
+ */
+ if (!si->vid_hdr_offs){
+ struct ubi_ec_hdr *echd = (struct ubi_ec_hdr *)data;
+ si->vid_hdr_offs = BE32(echd->vid_hdr_offset);
+ si->data_offs = BE32(echd->data_offset);
+ }
+
+ need_erase = (si->empty_cnt == (int)ptn->length ? 0 : 1);
+ /* Update the "to be" flashed image and flash it */
+ img_peb = data;
+ while (size && curr_peb < ptn->start + ptn->length) {
+ if (need_erase && qpic_nand_blk_erase(curr_peb * num_pages_per_blk)) {
+ dprintf(CRITICAL, "flash_ubi_img: erase of %d failed\n",
+ curr_peb);
+ bad_blocks_cnt++;
+ curr_peb++;
+ continue;
+ }
+ remove_F_flag(img_peb);
+ /* Update the ec_header in the image */
+ old_ech = (struct ubi_ec_hdr *)img_peb;
+ update_ec_header(old_ech, si, curr_peb - ptn->start, false);
+ if (size < block_size)
+ num_pages = size / page_size;
+ else
+ num_pages = calc_data_len(page_size, img_peb, block_size);
+ /* Write one block from image */
+ ret = qpic_nand_write(curr_peb * num_pages_per_blk,
+ num_pages, img_peb, 0);
+ if (ret) {
+ dprintf(CRITICAL, "flash_ubi_img: writing to peb-%d failed\n",
+ curr_peb);
+ bad_blocks_cnt++;
+ curr_peb++;
+ continue;
+ }
+ if (size < block_size)
+ size = 0;
+ else
+ size -= block_size;
+
+ if (fastmap_present(img_peb))
+ fmsb_peb = curr_peb;
+ img_peb += flash_block_size();
+ curr_peb++;
+ }
+
+ if (size) {
+ dprintf(CRITICAL,
+ "flash_ubi_img: Not enough good blocks to flash image!");
+ ret = -1;
+ goto out;
+ }
+
+ /* Erase and write ec_header for the rest of the blocks */
+ for (; curr_peb < ptn->start + ptn->length; curr_peb++)
+ if (ubi_erase_peb(curr_peb, need_erase, si, ptn->start))
+ bad_blocks_cnt++;
+
+ ret = 0;
+ /*
+ * If flashed image contains fastmap data and bad blocks were found
+ * we need to invalidate the flashed fastmap since it isn't accurate
+ * anymore.
+ */
+ if (bad_blocks_cnt && fmsb_peb) {
+ dprintf(CRITICAL, "flash_ubi_img: invalidate fmsb\n");
+ ret = ubi_erase_peb(ptn->start + 2, 1, si, ptn->start);
+ }
+
+out:
+ free(si->ec);
+ free(si);
+ return ret;
+}
diff --git a/platform/msm_shared/hsusb.c b/platform/msm_shared/hsusb.c
index 49da56c..0967cd1 100644
--- a/platform/msm_shared/hsusb.c
+++ b/platform/msm_shared/hsusb.c
@@ -2,7 +2,7 @@
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -41,6 +41,7 @@
#include <kernel/thread.h>
#include <reg.h>
#include <dev/udc.h>
+#include <target.h>
#include "hsusb.h"
#define MAX_TD_XFER_SIZE (16 * 1024)
@@ -182,6 +183,11 @@
ept->next = ept_list;
ept_list = ept;
+ arch_clean_invalidate_cache_range((addr_t) ept,
+ sizeof(struct udc_endpoint));
+ arch_clean_invalidate_cache_range((addr_t) ept->head,
+ sizeof(struct ept_queue_head));
+
DBG("ept%d %s @%p/%p max=%d bit=%x\n",
num, in ? "in" : "out", ept, ept->head, max_pkt, ept->bit);
@@ -307,21 +313,19 @@
item = memalign(CACHE_LINE,
ROUNDUP(sizeof(struct ept_queue_item), CACHE_LINE));
if (!item) {
- dprintf(ALWAYS, "allocate USB item fail ept%d"
- "%s queue\n",
- "td count = %d\n",
+ dprintf(ALWAYS, "allocate USB item fail ept%d\n %s queue\ntd count = %d\n",
ept->num,
ept->in ? "in" : "out",
count);
return -1;
} else {
count ++;
- curr_item->next = PA(item);
+ curr_item->next = PA((addr_t)item);
item->next = TERMINATE;
}
} else
/* Since next TD in chain already exists */
- item = VA(curr_item->next);
+ item = (struct ept_queue_item *)VA(curr_item->next);
/* Update TD with transfer information */
item->info = INFO_BYTES(xfer) | INFO_ACTIVE;
@@ -340,7 +344,7 @@
curr_item->next = TERMINATE;
curr_item->info |= INFO_IOC;
enter_critical_section();
- ept->head->next = PA(req->item);
+ ept->head->next = PA((addr_t)req->item);
ept->head->info = 0;
ept->req = req;
arch_clean_invalidate_cache_range((addr_t) ept,
@@ -349,7 +353,7 @@
sizeof(struct ept_queue_head));
arch_clean_invalidate_cache_range((addr_t) ept->req,
sizeof(struct usb_request));
- arch_clean_invalidate_cache_range((addr_t) VA(req->req.buf),
+ arch_clean_invalidate_cache_range((addr_t) VA((addr_t)req->req.buf),
req->req.length);
item = req->item;
@@ -359,7 +363,7 @@
if (curr_item->next == TERMINATE)
item = NULL;
else
- item = curr_item->next;
+ item = (struct ept_queue_item *)curr_item->next;
arch_clean_invalidate_cache_range((addr_t) curr_item,
sizeof(struct ept_queue_item));
}
@@ -374,9 +378,8 @@
{
struct ept_queue_item *item;
unsigned actual, total_len;
- int status, len;
+ int status;
struct usb_request *req=NULL;
- void *buf;
DBG("ept%d %s complete req=%p\n",
ept->num, ept->in ? "in" : "out", ept->req);
@@ -386,13 +389,13 @@
if(ept->req)
{
- req = VA(ept->req);
+ req = (struct usb_request *)VA((addr_t)ept->req);
arch_invalidate_cache_range((addr_t) ept->req,
sizeof(struct usb_request));
}
if (req) {
- item = VA(req->item);
+ item = (struct ept_queue_item *)VA((addr_t)req->item);
/* total transfer length for transacation */
total_len = req->req.length;
ept->req = 0;
@@ -426,7 +429,7 @@
/*
* Record the data transferred for the last TD
*/
- actual += total_len - (item->info >> 16)
+ actual += (total_len - (item->info >> 16))
& 0x7FFF;
total_len = 0;
break;
@@ -437,10 +440,10 @@
* TD woulb the max possible TD transfer size
* (16K)
*/
- actual += MAX_TD_XFER_SIZE - (item->info >> 16) & 0x7FFF;
- total_len -= MAX_TD_XFER_SIZE - (item->info >> 16) & 0x7FFF;
+ actual += (MAX_TD_XFER_SIZE - (item->info >> 16)) & 0x7FFF;
+ total_len -= (MAX_TD_XFER_SIZE - (item->info >> 16)) & 0x7FFF;
/*Move to next item in chain*/
- item = VA(item->next);
+ item = (struct ept_queue_item *)VA(item->next);
}
}
status = 0;
@@ -526,7 +529,8 @@
{
DBG("setup_tx %p %d\n", buf, len);
memcpy(ep0req->buf, buf, len);
- ep0req->buf = PA((addr_t)ep0req->buf);
+ ep0req->buf = (void *)PA((addr_t)ep0req->buf);
+ arch_clean_invalidate_cache_range((addr_t)ep0req->buf, len);
ep0req->complete = ep0in_complete;
ep0req->length = len;
udc_request_queue(ep0in, ep0req);
@@ -543,6 +547,7 @@
arch_clean_invalidate_cache_range((addr_t) ept->head->setup_data,
sizeof(struct ept_queue_head));
memcpy(&s, ept->head->setup_data, sizeof(s));
+ arch_clean_invalidate_cache_range((addr_t)&s, sizeof(s));
writel(ept->bit, USB_ENDPTSETUPSTAT);
DBG("handle_setup type=0x%02x req=0x%02x val=%d idx=%d len=%d (%s)\n",
diff --git a/platform/msm_shared/i2c_qup.c b/platform/msm_shared/i2c_qup.c
index 916d865..dc8481d 100644
--- a/platform/msm_shared/i2c_qup.c
+++ b/platform/msm_shared/i2c_qup.c
@@ -702,6 +702,7 @@
mask_interrupt(dev->qup_irq);
}
+#if DEFINE_GSBI_I2C
struct qup_i2c_dev *qup_i2c_init(uint8_t gsbi_id, unsigned clk_freq,
unsigned src_clk_freq)
{
@@ -739,6 +740,7 @@
return dev;
}
+#endif
struct qup_i2c_dev *qup_blsp_i2c_init(uint8_t blsp_id, uint8_t qup_id,
uint32_t clk_freq, uint32_t src_clk_freq)
diff --git a/platform/msm_shared/image_verify.c b/platform/msm_shared/image_verify.c
index bc2017d..cfdb5b9 100644
--- a/platform/msm_shared/image_verify.c
+++ b/platform/msm_shared/image_verify.c
@@ -25,11 +25,15 @@
* SUCH DAMAGE.
*/
#include <x509.h>
+#include <err.h>
#include <certificate.h>
#include <crypto_hash.h>
+#include <string.h>
+#include <openssl/err.h>
#include "image_verify.h"
#include "scm.h"
+
/*
* Returns -1 if decryption failed otherwise size of plain_text in bytes
*/
@@ -62,7 +66,7 @@
*/
int ret = -1;
X509 *x509_certificate = NULL;
- unsigned char *cert_ptr = certBuffer;
+ const unsigned char *cert_ptr = (const unsigned char *)certBuffer;
unsigned int cert_size = sizeof(certBuffer);
EVP_PKEY *pub_key = NULL;
RSA *rsa_key = NULL;
@@ -133,7 +137,7 @@
int auth = 0;
unsigned char *plain_text = NULL;
unsigned int digest[8];
- unsigned int hash_size;
+ int hash_size;
plain_text = (unsigned char *)calloc(sizeof(char), SIGNATURE_SIZE);
if (plain_text == NULL) {
diff --git a/platform/msm_shared/include/boot_device.h b/platform/msm_shared/include/boot_device.h
index 1f195b9..c216586 100644
--- a/platform/msm_shared/include/boot_device.h
+++ b/platform/msm_shared/include/boot_device.h
@@ -30,11 +30,12 @@
#define __BOOT_DEVICE_H
#include <sys/types.h>
+#include <platform.h>
#if USE_MDM_BOOT_CFG
#define BOOT_DEVICE_MASK(val) ((val & 0x1E) >> 1)
#else
-#define BOOT_DEVICE_MASK(val) ((val & 0x3E) >> 1)
+#define BOOT_DEVICE_MASK(val) boot_device_mask(val)
#endif
/* Boot device */
@@ -57,4 +58,6 @@
uint32_t platform_get_boot_dev();
uint32_t platform_boot_dev_isemmc();
void platform_boot_dev_cmdline(char *buf);
+
+void *target_mmc_device();
#endif
diff --git a/platform/msm_shared/include/boot_verifier.h b/platform/msm_shared/include/boot_verifier.h
index 616f23c..972086d 100644
--- a/platform/msm_shared/include/boot_verifier.h
+++ b/platform/msm_shared/include/boot_verifier.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -156,5 +156,5 @@
/* Function to validate keystore */
bool boot_verify_validate_keystore(unsigned char * user_addr);
/* Function to check if partition is allowed to flash in verified mode */
-bool boot_verify_flash_allowed(char * entry);
+bool boot_verify_flash_allowed(const char * entry);
#endif
diff --git a/platform/msm_shared/include/clock.h b/platform/msm_shared/include/clock.h
index fd878d2..1369b55 100644
--- a/platform/msm_shared/include/clock.h
+++ b/platform/msm_shared/include/clock.h
@@ -193,4 +193,6 @@
* @action: clock assert or deassert
*/
int clk_reset(struct clk *clk, enum clk_reset_action);
+
+void clock_bumpup_pipe3_clk();
#endif
diff --git a/platform/msm_shared/include/crypto4_eng.h b/platform/msm_shared/include/crypto4_eng.h
index dde7794..4a8b037 100644
--- a/platform/msm_shared/include/crypto4_eng.h
+++ b/platform/msm_shared/include/crypto4_eng.h
@@ -73,4 +73,5 @@
#define GOPROC_GO 1
+void crypto_eng_cleanup(void);
#endif
diff --git a/platform/msm_shared/include/crypto5_wrapper.h b/platform/msm_shared/include/crypto5_wrapper.h
index 9c9af9b..0ae4ff0 100644
--- a/platform/msm_shared/include/crypto5_wrapper.h
+++ b/platform/msm_shared/include/crypto5_wrapper.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012,2014 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -33,5 +33,6 @@
void crypto_init_params(struct crypto_init_params * params);
uint32_t crypto_get_max_auth_blk_size();
+void crypto_eng_cleanup(void);
#endif
diff --git a/platform/msm_shared/include/crypto_hash.h b/platform/msm_shared/include/crypto_hash.h
index bdcf7e0..44e227a 100644
--- a/platform/msm_shared/include/crypto_hash.h
+++ b/platform/msm_shared/include/crypto_hash.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -132,4 +132,9 @@
unsigned char *digest_ptr);
bool crypto_initialized(void);
+void
+hash_find(unsigned char *addr, unsigned int size, unsigned char *digest,
+ unsigned char auth_alg);
+
+crypto_engine_type board_ce_type(void);
#endif
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
old mode 100644
new mode 100755
index a6534c0..04ce64d
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -123,6 +123,8 @@
DTB_PMIC2,
DTB_PMIC3,
DTB_PMIC_MODEL,
+ DTB_PANEL_TYPE,
+ DTB_BOOT_DEVICE,
};
enum dt_err_codes
diff --git a/platform/msm_shared/include/dme.h b/platform/msm_shared/include/dme.h
index 0bc2b3d..aa11c54 100644
--- a/platform/msm_shared/include/dme.h
+++ b/platform/msm_shared/include/dme.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -51,6 +51,7 @@
#define DME_NOP_NUM_RETRIES 20
#define DME_FDEVICEINIT_RETRIES 20
#define DME_FPOWERONWPEN_RETRIES 20
+#define DME_BPURGESTATUS_RETRIES 500000
/* Timeout value for commands. */
#define DME_NOP_QUERY_TIMEOUT 10
@@ -72,6 +73,7 @@
#define UFS_IDX_bBootLunEn 0x00
#define UFS_IDX_bCurrentPowerMode 0x01
#define UFS_IDX_bActiveICCLevel 0x03
+#define UFS_IDX_bPurgeStatus 0x06
#define UFS_IDX_bRefClkFreq 0x0a
#define UFS_IDX_bConfigDescrLock 0x0b
@@ -84,6 +86,7 @@
/* Flags definitions */
#define UFS_IDX_fDeviceInit 0x01
#define UFS_IDX_fPowerOnWPEn 0x03
+#define UFS_IDX_fPurgeEn 0x06
enum utp_query_response_upiu_type
{
@@ -246,6 +249,9 @@
*/
int dme_set_fpoweronwpen(struct ufs_dev *dev);
+/* Purge is used to securely erase blocks that are unmapped in ufs */
+int dme_set_fpurgeenable(struct ufs_dev *dev);
+
/* Unit descriptor gives the characteristics and capabilities of
* logical units.
*/
diff --git a/platform/msm_shared/include/image_verify.h b/platform/msm_shared/include/image_verify.h
index 0819421..fe20c9f 100644
--- a/platform/msm_shared/include/image_verify.h
+++ b/platform/msm_shared/include/image_verify.h
@@ -47,4 +47,5 @@
/* Find hash of image */
void image_find_digest(unsigned char *image_ptr, unsigned int image_size,
unsigned hash_type, unsigned char *digest);
+void save_kernel_hash_cmd(void *digest);
#endif
diff --git a/platform/msm_shared/include/mdp4.h b/platform/msm_shared/include/mdp4.h
index d979645..ee4e4fc 100644
--- a/platform/msm_shared/include/mdp4.h
+++ b/platform/msm_shared/include/mdp4.h
@@ -104,8 +104,11 @@
void mdp_disable(void);
void mdp_start_dma(void);
int mdp_dsi_video_off();
+int mdp_dsi_cmd_off(void);
int mdp_dsi_video_on(struct msm_panel_info *pinfo);
+int mdp_dma_on(struct msm_panel_info *pinfo);
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
int mdp_lcdc_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
int mdp_lcdc_on();
int mdp_lcdc_off();
@@ -117,4 +120,7 @@
int mdp_edp_on(struct msm_panel_info *pinfo);
int mdp_edp_off(void);
+int mdss_hdmi_init(void);
+int mdss_hdmi_on(struct msm_panel_info *pinfo);
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
#endif
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 8e17def..9515354 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -82,6 +82,7 @@
#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */
+#define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */
#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
#define MDSS_MAX_LINE_BUF_WIDTH 2048
@@ -98,6 +99,7 @@
#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x12500)
#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x12700)
+#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x12900)
#define MDP_INTF_3_TIMING_ENGINE_EN REG_MDP(0x12B00)
#define MDP_CTL_0_BASE REG_MDP(0x600)
@@ -116,9 +118,6 @@
#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x3F8)
#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x4F0)
-#define MDP_REG_PPB0_CNTL REG_MDP(0x1420)
-#define MDP_REG_PPB0_CONFIG REG_MDP(0x1424)
-
#define MDP_INTF_0_BASE REG_MDP(0x12500)
#define MDP_INTF_1_BASE REG_MDP(0x12700)
#define MDP_INTF_2_BASE REG_MDP(0x12900)
@@ -163,7 +162,6 @@
#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x02E0)
#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x02E4)
-#define VBIF_VBIF_QOS_REMAP_00 REG_MDP(0xC8020)
#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0x24004)
#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0x240D8)
#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0x240F0)
@@ -191,6 +189,7 @@
void mdp_set_revision(int rev);
int mdp_get_revision();
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
unsigned short num_of_lanes);
int mdp_dsi_video_on(struct msm_panel_info *pinfo);
@@ -199,5 +198,17 @@
int mdp_edp_on(struct msm_panel_info *pinfo);
int mdp_edp_off(void);
void mdp_disable(void);
-
+void mdp_gdsc_ctrl(uint8_t enable);
+int mdp_get_revision();
+uint8_t target_is_edp();
+void target_edp_panel_init(struct msm_panel_info *pinfo);
+int target_edp_panel_clock(uint8_t enable, struct msm_panel_info *pinfo);
+int target_edp_panel_enable(void);
+int target_edp_panel_disable(void);
+int target_edp_bl_ctrl(int enable);
+int mdss_hdmi_init(void);
+int mdss_hdmi_on(struct msm_panel_info *pinfo);
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int msm_display_off();
+void display_shutdown(void);
#endif
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 0741851..c2ddd9b 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -35,49 +35,27 @@
#define PASS 0
#define FAIL 1
-/**********************************************************
- DSI register offset
- **********************************************************/
+/*
+ * DSI register offsets defined here are only used for non-MDSS targets.
+ * For MDSS targets, all offset definitions are picked up from corresponding
+ * target files.
+ */
+#if (DISPLAY_TYPE_MDSS == 0)
#define DSI_CLKOUT_TIMING_CTRL REG_DSI(0x0C0)
#define DSI_SOFT_RESET REG_DSI(0x114)
-#define DSI_CAL_CTRL REG_DSI(0x0F4)
-
#define DSIPHY_SW_RESET REG_DSI(0x128)
#define DSIPHY_PLL_RDY REG_DSI(0x280)
-#define DSIPHY_REGULATOR_CAL_PWR_CFG REG_DSI(0x518)
-
#define DSI_CLK_CTRL REG_DSI(0x118)
#define DSI_TRIG_CTRL REG_DSI(0x080)
-#define DSI_CTRL REG_DSI(0x000)
#define DSI_COMMAND_MODE_DMA_CTRL REG_DSI(0x038)
-#define DSI_COMMAND_MODE_MDP_CTRL REG_DSI(0x03C)
-#define DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL REG_DSI(0x040)
-#define DSI_DMA_CMD_OFFSET REG_DSI(0x044)
-#define DSI_DMA_CMD_LENGTH REG_DSI(0x048)
-#define DSI_COMMAND_MODE_MDP_STREAM0_CTRL REG_DSI(0x054)
-#define DSI_COMMAND_MODE_MDP_STREAM0_TOTAL REG_DSI(0x058)
-#define DSI_COMMAND_MODE_MDP_STREAM1_CTRL REG_DSI(0x05C)
-#define DSI_COMMAND_MODE_MDP_STREAM1_TOTAL REG_DSI(0x060)
#define DSI_ERR_INT_MASK0 REG_DSI(0x108)
#define DSI_INT_CTRL REG_DSI(0x10C)
-
-#define DSI_VIDEO_MODE_ACTIVE_H REG_DSI(0x020)
-#define DSI_VIDEO_MODE_ACTIVE_V REG_DSI(0x024)
-#define DSI_VIDEO_MODE_TOTAL REG_DSI(0x028)
-#define DSI_VIDEO_MODE_HSYNC REG_DSI(0x02C)
-#define DSI_VIDEO_MODE_VSYNC REG_DSI(0x030)
-#define DSI_VIDEO_MODE_VSYNC_VPOS REG_DSI(0x034)
-
-#define DSI_MISR_CMD_CTRL REG_DSI(0x09C)
-#define DSI_MISR_VIDEO_CTRL REG_DSI(0x0A0)
-#define DSI_EOT_PACKET_CTRL REG_DSI(0x0C8)
-#define DSI_VIDEO_MODE_CTRL REG_DSI(0x00C)
-#define DSI_CAL_STRENGTH_CTRL REG_DSI(0x100)
#define DSI_CMD_MODE_DMA_SW_TRIGGER REG_DSI(0x08C)
+#define DSI_DMA_CMD_OFFSET REG_DSI(0x044)
+#define DSI_DMA_CMD_LENGTH REG_DSI(0x048)
+#define DSI_CTRL REG_DSI(0x000)
#define DSI_CMD_MODE_MDP_SW_TRIGGER REG_DSI(0x090)
-#define DSI_HS_TIMER_CTRL REG_DSI(0x0B8)
-
-#define DSI_LANE_CTRL REG_DSI(0x0A8)
+#endif
#define DSI_VIDEO_MODE_DONE_MASK BIT(17)
#define DSI_VIDEO_MODE_DONE_AK BIT(16)
@@ -176,7 +154,7 @@
int is_pll_20nm;
};
-typedef struct mdss_dsi_pll_config {
+struct mdss_dsi_pll_config {
uint32_t pixel_clock;
uint32_t pixel_clock_mhz;
uint32_t byte_clock;
@@ -184,6 +162,9 @@
uint32_t halfbit_clock;
uint32_t vco_clock;
uint32_t vco_delay;
+ uint32_t vco_min;
+ uint32_t vco_max;
+ uint32_t en_vco_zero_phase;
uint8_t directpath;
uint8_t posdiv1;
uint8_t posdiv3;
@@ -202,7 +183,7 @@
};
struct mipi_dsi_cmd {
- int size;
+ uint32_t size;
char *payload;
int wait;
};
@@ -222,10 +203,6 @@
char cmds_post_tg;
};
-static char read_id_a1h_cmd[4] = { 0xA1, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */
-static struct mipi_dsi_cmd read_ddb_start_cmd =
- {sizeof(read_id_a1h_cmd), read_id_a1h_cmd};
-
enum { /* mipi dsi panel */
DSI_VIDEO_MODE,
DSI_CMD_MODE,
@@ -236,10 +213,11 @@
**********************************************************/
int mipi_config(struct msm_fb_panel_data *panel);
int mdss_dsi_config(struct msm_fb_panel_data *panel);
-int mdss_dsi_phy_init(struct mipi_dsi_panel_config *,
- uint32_t ctl_base, uint32_t phy_base);
-void mdss_dsi_phy_contention_detection(struct mipi_dsi_panel_config *,
+void mdss_dsi_phy_sw_reset(uint32_t ctl_base);
+int mdss_dsi_phy_init(struct mipi_panel_info *mipi);
+void mdss_dsi_phy_contention_detection(struct mipi_panel_info *mipi,
uint32_t phy_base);
+int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo);
int mdss_dsi_video_mode_config(uint16_t disp_width,
uint16_t disp_height,
@@ -254,14 +232,35 @@
uint16_t dst_format,
uint16_t traffic_mode,
uint8_t lane_en,
- uint16_t low_pwr_stop_mode,
+ uint8_t pulse_mode_hsa_he,
+ uint32_t low_pwr_stop_mode,
uint8_t eof_bllp_pwr,
uint8_t interleav,
uint32_t ctl_base);
+int mdss_dsi_cmd_mode_config(uint16_t disp_width,
+ uint16_t disp_height,
+ uint16_t img_width,
+ uint16_t img_height,
+ uint16_t dst_format,
+ uint8_t ystride,
+ uint8_t lane_en,
+ uint8_t interleav,
+ uint32_t ctl_base);
-int mipi_dsi_on();
+int mipi_dsi_on(struct msm_panel_info *pinfo);
+int mipi_cmd_trigger();
int mipi_dsi_off(struct msm_panel_info *pinfo);
-int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count);
-int mipi_dsi_cmds_rx(char **rp, int len);
-
+int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi,
+ struct mipi_dsi_cmd *cmds, int count, char dual_dsi);
+int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len,
+ int rdbk_len);
+int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd);
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t pll_1_base,
+ struct mdss_dsi_pll_config *pd);
+void mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base);
+uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base);
+void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t pll_base);
+void mdss_dsi_uniphy_pll_sw_reset(uint32_t pll_base);
+int mdss_dsi_post_on(struct msm_fb_panel_data *panel);
#endif
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index 5f5ba72..1612e61 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -204,7 +204,7 @@
({ \
uint32_t indx = (start) / (size_of); \
uint32_t offset = (start) % (size_of); \
- uint32_t mask = (((len)<(size_of))? 1<<(len):0) - 1; \
+ uint32_t mask = (((len)<(size_of))? 1ULL<<(len):0) - 1; \
uint32_t unpck = array[indx] >> offset; \
uint32_t indx2 = ((start) + (len) - 1) / (size_of); \
if(indx2 > indx) \
@@ -306,6 +306,7 @@
uint32_t pwrctl_base; /* Base address for power control registers */
uint16_t bus_width; /* Bus width used */
uint32_t max_clk_rate; /* Max clock rate supported */
+ uint8_t hs200_support; /* SDHC HS200 mode supported or not */
uint8_t hs400_support; /* SDHC HS400 mode supported or not */
uint8_t use_io_switch; /* IO pad switch flag for shared sdc controller */
};
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 1d0d17b..4b09f69 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -36,6 +36,9 @@
#define TRUE 1
#define FALSE 0
+#define DFPS_MAX_FRAME_RATE 10
+#define DFPS_PLL_CODES_SIZE 0x1000 /* One page */
+
/* panel type list */
#define NO_PANEL 0xffff /* No Panel */
#define MDDI_PANEL 1 /* MDDI */
@@ -52,6 +55,10 @@
#define EDP_PANEL 12 /* EDP */
#define QPIC_PANEL 13 /* QPIC */
+#define DISPLAY_UNKNOWN 0
+#define DISPLAY_1 1
+#define DISPLAY_2 2
+
enum mdss_mdp_pipe_type {
MDSS_MDP_PIPE_TYPE_VIG,
MDSS_MDP_PIPE_TYPE_RGB,
@@ -133,6 +140,34 @@
uint32_t lossy_mode_thd;
uint32_t lossy_rgb_thd;
uint32_t lossy_mode_idx;
+
+ uint32_t slice_height;
+ uint32_t pred_mode;
+ uint32_t max_pred_err;
+};
+
+
+struct dfps_panel_info {
+ uint32_t enabled;
+ uint32_t frame_rate_cnt;
+ uint32_t frame_rate[DFPS_MAX_FRAME_RATE];
+};
+
+struct dfps_pll_codes {
+ uint32_t codes[2];
+};
+
+struct dfps_codes_info {
+ uint32_t is_valid;
+ uint32_t frame_rate;
+ uint32_t clk_rate;
+ struct dfps_pll_codes pll_codes;
+};
+
+struct dfps_info {
+ struct dfps_panel_info panel_dfps;
+ struct dfps_codes_info codes_dfps[DFPS_MAX_FRAME_RATE];
+ void *dfps_fb_base;
};
/* intf timing settings */
@@ -214,6 +249,16 @@
uint8_t mode_gpio_state;
uint32_t signature;
uint32_t use_enable_gpio;
+ uint32_t ctl_base;
+ uint32_t phy_base;
+ uint32_t sctl_base;
+ uint32_t sphy_base;
+ uint32_t reg_base;
+ uint32_t sreg_base;
+ uint32_t pll_0_base;
+ uint32_t pll_1_base;
+
+ struct dfps_pll_codes pll_codes;
};
struct edp_panel_info {
@@ -232,6 +277,18 @@
char channel_swap;
};
+struct labibb_desc {
+ char amoled_panel; /* lcd = 0, amoled = 1*/
+ char force_config; /* 0 to use default value */
+ uint32_t ibb_min_volt;
+ uint32_t ibb_max_volt;
+ uint32_t lab_min_volt;
+ uint32_t lab_max_volt;
+ char pwr_up_delay; /* ndx to => 1250, 2500, 5000 and 10000 us */
+ char pwr_down_delay; /* ndx to => 1250, 2500, 5000 and 10000 us */
+ char ibb_discharge_en;
+};
+
struct msm_panel_info {
uint32_t xres;
uint32_t yres;
@@ -240,6 +297,7 @@
uint32_t wait_cycle;
uint32_t clk_rate;
uint32_t orientation;
+ uint32_t dest;
/* Select pipe type for handoff */
uint32_t pipe_type;
char lowpowerstop;
@@ -257,6 +315,10 @@
struct hdmi_panel_info hdmi;
struct edp_panel_info edp;
+ struct dfps_info dfps;
+
+ struct labibb_desc *labibb;
+
int (*on) (void);
int (*off) (void);
int (*pre_on) (void);
@@ -274,10 +336,11 @@
int rotate;
/* function entry chain */
- int (*power_func) (int enable, struct msm_panel_info *);
- int (*clk_func) (int enable);
- int (*bl_func) (int enable);
- int (*pll_clk_func) (int enable, struct msm_panel_info *);
+ int (*power_func) (uint8_t enable, struct msm_panel_info *);
+ uint32_t (*clk_func) (uint8_t enable, struct msm_panel_info *pinfo);
+ int (*bl_func) (uint8_t enable);
+ uint32_t (*pll_clk_func) (uint8_t enable, struct msm_panel_info *);
+ int (*dfps_func)(struct msm_panel_info *);
int (*post_power_func)(int enable);
int (*pre_init_func)(void);
};
diff --git a/platform/msm_shared/include/partial_goods.h b/platform/msm_shared/include/partial_goods.h
new file mode 100644
index 0000000..881cfa2
--- /dev/null
+++ b/platform/msm_shared/include/partial_goods.h
@@ -0,0 +1,59 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+
+#define DTB_MAX_SUBNODE 128
+#define DEFAULT_STATUS_PROP_LEN 3
+
+enum property_type
+{
+ DEVICE_TYPE = 1,
+ STATUS_TYPE,
+};
+
+/* Sub node name, property pair */
+struct subnode_list
+{
+ const char *subnode; /* Subnode name */
+ const char *property; /* Property name */
+};
+
+/* Look up table for partial goods */
+struct partial_goods
+{
+ uint32_t val; /* Value for the defect */
+ const char *parent_node; /* Parent Node name*/
+ struct subnode_list subnode[DTB_MAX_SUBNODE]; /* Sub node name list*/
+};
+
+/* API: Update device tree with partial goods info.
+ * params:
+ * @fdt: Pointer to device tree
+ */
+void update_partial_goods_dtb_nodes(void *fdt);
diff --git a/platform/msm_shared/include/qgic.h b/platform/msm_shared/include/qgic.h
index cb4c573..9bc66ff 100644
--- a/platform/msm_shared/include/qgic.h
+++ b/platform/msm_shared/include/qgic.h
@@ -31,6 +31,9 @@
#define __PLATFORM_MSM_SHARED_QGIC_H
#include "qgic_common.h"
+#include <platform/iomap.h>
+#include <platform/interrupts.h>
+#include <arch/arm.h>
#define GIC_CPU_REG(off) (MSM_GIC_CPU_BASE + (off))
@@ -50,4 +53,9 @@
uint32_t qgic_read_iar(void);
void qgic_write_eoi(uint32_t);
+enum handler_return gic_platform_irq(struct arm_iframe *frame);
+void gic_platform_fiq(struct arm_iframe *frame);
+status_t gic_mask_interrupt(unsigned int vector);
+status_t gic_unmask_interrupt(unsigned int vector);
+void gic_register_int_handler(unsigned int vector, int_handler func, void *arg);
#endif
diff --git a/platform/msm_shared/include/qmp_phy.h b/platform/msm_shared/include/qmp_phy.h
index c112919..4558abe 100644
--- a/platform/msm_shared/include/qmp_phy.h
+++ b/platform/msm_shared/include/qmp_phy.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -30,6 +30,12 @@
#include <platform/iomap.h>
+struct qmp_reg
+{
+ uint32_t off;
+ uint32_t val;
+};
+
/* QMP register offsets */
#define QSERDES_COM_DEC_START1 (PLATFORM_QMP_OFFSET + 0xA4)
#define QSERDES_COM_DEC_START2 (PLATFORM_QMP_OFFSET + 0x104)
@@ -81,5 +87,6 @@
void usb30_qmp_phy_reset(void);
void usb30_qmp_phy_init(void);
+bool use_hsonly_mode();
#endif
diff --git a/platform/msm_shared/include/qpic.h b/platform/msm_shared/include/qpic.h
index 237923c..d2fc453 100644
--- a/platform/msm_shared/include/qpic.h
+++ b/platform/msm_shared/include/qpic.h
@@ -30,6 +30,7 @@
#ifndef MDSS_QPIC_H
#define MDSS_QPIC_H
+#include <msm_panel.h>
#include "qpic_panel.h"
#define QPIC_REG_QPIC_LCDC_CTRL 0x22000
@@ -64,6 +65,10 @@
uint32_t qpic_read_data(uint32_t cmd_index, uint32_t size);
int mdss_qpic_panel_on(struct qpic_panel_io_desc *panel_io);
int mdss_qpic_panel_off(struct qpic_panel_io_desc *panel_io);
+void qpic_init(struct msm_panel_info *pinfo, int base);
+int qpic_on(void);
+int qpic_off(void);
+void qpic_update(void);
struct qpic_data_type {
uint32_t rev;
diff --git a/platform/msm_shared/include/qpic_nand.h b/platform/msm_shared/include/qpic_nand.h
index bb429fb..14282ec 100644
--- a/platform/msm_shared/include/qpic_nand.h
+++ b/platform/msm_shared/include/qpic_nand.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
- * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -52,6 +52,7 @@
#define NAND_SFLASHC_EXEC_CMD NAND_REG(0x003C)
#define NAND_READ_ID NAND_REG(0x0040)
#define NAND_READ_STATUS NAND_REG(0x0044)
+#define NAND_READ_ID2 NAND_REG(0x0048)
#define NAND_CONFIG_DATA NAND_REG(0x0050)
#define NAND_CONFIG NAND_REG(0x0054)
#define NAND_CONFIG_MODE NAND_REG(0x0058)
@@ -310,7 +311,9 @@
struct flash_id
{
unsigned flash_id;
+ unsigned flash_id2;
unsigned mask;
+ unsigned mask2;
unsigned density;
unsigned widebus;
unsigned pagesize;
@@ -342,11 +345,18 @@
void
qpic_nand_init(struct qpic_nand_init_config *config);
+unsigned flash_num_blocks(void);
unsigned
flash_block_size(void);
void
qpic_nand_uninit();
/* Api to return the nand base */
uint32_t nand_device_base();
+nand_result_t qpic_nand_read(uint32_t start_page, uint32_t num_pages,
+ unsigned char* buffer, unsigned char* spareaddr);
+nand_result_t qpic_nand_write(uint32_t start_page, uint32_t num_pages,
+ unsigned char* buffer, unsigned write_extra_bytes);
+nand_result_t qpic_nand_block_isbad(unsigned page);
+nand_result_t qpic_nand_blk_erase(uint32_t page);
#endif
diff --git a/platform/msm_shared/include/qtimer.h b/platform/msm_shared/include/qtimer.h
index fd680a0..d914a88 100644
--- a/platform/msm_shared/include/qtimer.h
+++ b/platform/msm_shared/include/qtimer.h
@@ -44,3 +44,5 @@
void qtimer_uninit();
void qtimer_init();
uint32_t qtimer_tick_rate();
+void udelay(unsigned usecs);
+void mdelay(unsigned msecs);
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index de046a4..283f1cc 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -123,6 +123,23 @@
} feature_version_rsp;
typedef struct{
+ uint32 *status_ptr;
+ uint32 status_len;
+} get_secure_state_req;
+
+typedef struct{
+ uint32 status_low;
+ uint32 status_high;
+} get_secure_state_rsp;
+
+typedef struct{
+ uint32 row_address;
+ uint32 addr_type;
+ uint32 *row_data;
+ uint32 *qfprom_api_status;
+} qfprom_read_row_req;
+
+typedef struct{
uint32 *keystore_ptr;
uint32 keystore_len;
} ssd_protect_keystore_req;
@@ -152,7 +169,15 @@
struct tz_prng_data {
uint8_t *out_buf;
uint32_t out_buf_size;
-}__packed;
+}__PACKED;
+
+typedef struct {
+ uint8_t *in_buf;
+ uint32_t in_buf_size;
+ uint8_t *out_buf;
+ uint32_t out_buf_size;
+ uint32_t direction;
+} mdtp_cipher_dip_req;
/* SCM support as per ARM spec */
/*
@@ -227,12 +252,13 @@
#define IOMMU_SECURE_CFG 0x02
#define TZ_INFO_GET_FEATURE_ID 0x03
+#define TZ_INFO_GET_SECURE_STATE 0x04
#define PRNG_CMD_ID 0x01
#define IS_CALL_AVAIL_CMD 0x01
/* Download Mode specific arguments to be passed to TZ */
-#define SCM_EDLOAD_MODE 0x02
+#define SCM_EDLOAD_MODE 0x01
#define SCM_DLOAD_MODE 0x10
/* SSD parsing status messages from TZ */
@@ -272,11 +298,30 @@
int decrypt_scm_v2(uint32_t ** img_ptr, uint32_t * img_len_ptr);
int encrypt_scm(uint32_t ** img_ptr, uint32_t * img_len_ptr);
int scm_svc_version(uint32 * major, uint32 * minor);
+
+/**
+ * Check security status on the device. Returns the security check result.
+ * Bit value 0 means the check passing, and bit value 1 means the check failing.
+ *
+ * @state_low[out] : lower 32 bits of the state:
+ * Bit 0: secboot enabling check failed
+ * Bit 1: Sec HW key is not programmed
+ * Bit 2: debug disable check failed
+ * Bit 3: Anti-rollback check failed
+ * Bit 4: fuse config check failed
+ * Bit 5: rpmb fuse check failed
+ * @state_high[out] : highr 32 bits of the state.
+ *
+ * Returns 0 on success, negative on failure.
+ */
+int scm_svc_get_secure_state(uint32_t *state_low, uint32_t *state_high);
+
int scm_protect_keystore(uint32_t * img_ptr, uint32_t img_len);
#define SCM_SVC_FUSE 0x08
#define SCM_BLOW_SW_FUSE_ID 0x01
#define SCM_IS_SW_FUSE_BLOWN_ID 0x02
+#define SCM_QFPROM_READ_ROW_ID 0x05
#define HLOS_IMG_TAMPER_FUSE 0
@@ -287,6 +332,9 @@
#define SCM_SVC_ES 0x10
#define SCM_SAVE_PARTITION_HASH_ID 0x01
+#define SCM_SVC_MDTP 0x12
+#define SCM_MDTP_CIPHER_DIP 0x01
+
#define SCM_SVC_PWR 0x9
#define SCM_IO_DISABLE_PMIC_ARBITER 0x1
@@ -303,11 +351,40 @@
uint8_t switch_ce_chn_cmd(enum ap_ce_channel_type channel);
+/**
+ * Encrypt or Decrypt a Data Integrity Partition (DIP) structure using a
+ * HW derived key. The DIP is used for storing integrity information for
+ * Mobile Device Theft Protection (MDTP) service.
+ *
+ * @in_buf[in] : Pointer to plain text buffer.
+ * @in_buf_size[in] : Plain text buffer size.
+ * @out_buf[in] : Pointer to encrypted buffer.
+ * @out_buf_size[in] : Encrypted buffer size.
+ * @direction[in] : 0 for ENCRYPTION, 1 for DECRYPTION.
+ *
+ * Returns 0 on success, negative on failure.
+ */
+int mdtp_cipher_dip_cmd(uint8_t *in_buf, uint32_t in_buf_size, uint8_t *out_buf,
+ uint32_t out_buf_size, uint32_t direction);
void set_tamper_fuse_cmd();
+/**
+ * Reads the row data of the specified QFPROM row address.
+ *
+ * @row_address[in] : Row address in the QFPROM region to read.
+ * @addr_type[in] : Raw or corrected address.
+ * @row_data[in] : Pointer to the data to be read.
+ * @qfprom_api_status[out] : Status of the read operation.
+ *
+ * Returns Any errors while reading data from the specified
+ * Returns 0 on success, negative on failure.
+ */
+int qfprom_read_row_cmd(uint32_t row_address, uint32_t addr_type, uint32_t *row_data, uint32_t *qfprom_api_status);
+
int scm_halt_pmic_arbiter();
int scm_call_atomic2(uint32_t svc, uint32_t cmd, uint32_t arg1, uint32_t arg2);
+int restore_secure_cfg(uint32_t id);
void scm_elexec_call(paddr_t kernel_entry, paddr_t dtb_offset);
void *get_canary();
diff --git a/platform/msm_shared/include/sdhci.h b/platform/msm_shared/include/sdhci.h
index 7dc93a6..604ac81 100644
--- a/platform/msm_shared/include/sdhci.h
+++ b/platform/msm_shared/include/sdhci.h
@@ -56,6 +56,7 @@
uint8_t ddr_support; /* Dual Data rate */
uint8_t sdr50_support; /* UHS mode, with 100 MHZ clock */
uint8_t sdr104_support; /* UHS mode, with 200 MHZ clock */
+ uint8_t hs200_support; /* Hs200 mode, with 200 MHZ clock */
uint8_t hs400_support; /* Hs400 mode, with 400 MHZ clock */
};
@@ -98,7 +99,7 @@
uint32_t trans_mode; /* Transfer mode, read/write */
uint32_t cmd_retry; /* Retry the command, if card is busy */
uint32_t cmd23_support; /* If card supports cmd23 */
- uint64_t cmd_timeout; /* Command timeout in ms */
+ uint64_t cmd_timeout; /* Command timeout in us */
struct mmc_data data; /* Data pointer */
};
diff --git a/platform/msm_shared/include/sdhci_msm.h b/platform/msm_shared/include/sdhci_msm.h
index fe68140..d3bc7f5 100644
--- a/platform/msm_shared/include/sdhci_msm.h
+++ b/platform/msm_shared/include/sdhci_msm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -30,6 +30,7 @@
#define __SDHCI_MSM_H__
#include <kernel/event.h>
+#include <mmc_sdhci.h>
#define SDHCI_HC_START_BIT 0x0
#define SDHCI_HC_WIDTH 0x1
@@ -75,7 +76,9 @@
#define SDCC_DLL_EN BIT(16)
#define SDCC_DLL_CDR_EN BIT(17)
#define SDCC_DLL_CLK_OUT_EN BIT(18)
+#define SDCC_FLL_CYCLE_CNT BIT(18)
#define SDCC_DLL_CDR_EXT_EN BIT(19)
+#define SDCC_DLL_CLOCK_DISABLE BIT(21)
#define SDCC_DLL_PDN_EN BIT(29)
#define SDCC_DLL_RESET_EN BIT(30)
#define SDCC_DLL_CONFIG_MCLK_START 0x18
@@ -123,6 +126,8 @@
#define SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0 0x11C
+#define TCXO_FREQ 19200000
+
struct sdhci_msm_data
{
uint32_t pwrctl_base;
@@ -140,4 +145,5 @@
void sdhci_mode_disable(struct sdhci_host *host);
/* API: Toggle the bit for clock-data recovery */
void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable);
+void sdhci_msm_set_mci_clk(struct sdhci_host *host);
#endif
diff --git a/platform/msm_shared/include/smd.h b/platform/msm_shared/include/smd.h
index 0daaace..00cd4ec 100644
--- a/platform/msm_shared/include/smd.h
+++ b/platform/msm_shared/include/smd.h
@@ -118,10 +118,10 @@
int smd_init(smd_channel_info_t *ch, uint32_t ch_type);
void smd_uninit(smd_channel_info_t *ch);
-uint8_t* smd_read(smd_channel_info_t *ch, uint32_t *len, int ch_type);
+void smd_read(smd_channel_info_t *ch, uint32_t *len, int ch_type, uint32_t *response);
int smd_write(smd_channel_info_t *ch, void *data, uint32_t len, int type);
int smd_get_channel_info(smd_channel_info_t *ch, uint32_t ch_type);
-void smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type);
+int smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type);
void smd_notify_rpm();
enum handler_return smd_irq_handler(void* data);
void smd_set_state(smd_channel_info_t *ch, uint32_t state, uint32_t flag);
diff --git a/platform/msm_shared/include/splash.h b/platform/msm_shared/include/splash.h
index 2afa254..76e867d 100644
--- a/platform/msm_shared/include/splash.h
+++ b/platform/msm_shared/include/splash.h
@@ -30,9 +30,6 @@
#ifndef __PLATFORM_SPLASH_H
#define __PLATFORM_SPLASH_H
-#define SPLASH_IMAGE_WIDTH 113
-#define SPLASH_IMAGE_HEIGHT 124
-
#if (!DISPLAY_TYPE_MIPI)
#define SPLASH_IMAGE_WIDTH 124
#define SPLASH_IMAGE_HEIGHT 113
@@ -3546,6 +3543,10 @@
};
#else
+
+#define SPLASH_IMAGE_WIDTH 113
+#define SPLASH_IMAGE_HEIGHT 124
+
/* This image is 228x113 raw Image resembling QuIC logo*/
static char imageBuffer_rgb888[] = {
diff --git a/platform/msm_shared/include/ucs.h b/platform/msm_shared/include/ucs.h
index 094946e..48c50db 100644
--- a/platform/msm_shared/include/ucs.h
+++ b/platform/msm_shared/include/ucs.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -175,4 +175,6 @@
int ucs_do_scsi_rpmb_read(struct ufs_dev *dev, uint32_t *req_buf, uint32_t blk_cnt,
uint32_t *resp_buffer, uint32_t *response_length);
+/* This function parses the first byte of the sense data and returns the sense key */
+int parse_sense_key(uint32_t sense_data);
#endif
diff --git a/platform/msm_shared/include/upiu.h b/platform/msm_shared/include/upiu.h
index 1c9968d..e081909 100644
--- a/platform/msm_shared/include/upiu.h
+++ b/platform/msm_shared/include/upiu.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -44,6 +44,27 @@
uint16_t data_seg_len;
} __PACKED;
+
+struct upiu_basic_resp_hdr
+{
+ uint8_t trans_type;
+ uint8_t flags;
+ uint8_t lun;
+ uint8_t task_tag;
+ uint8_t cmd_set_type;
+ uint8_t query_task_mgmt_func;
+ uint8_t response;
+ uint8_t status;
+ uint8_t total_ehs_len;
+ uint8_t device_info;
+ uint16_t data_seg_len;
+ uint32_t residual_transfer_count;
+ uint32_t reserved[4];
+ uint16_t sense_length;
+ uint16_t sense_response_code;
+ uint32_t sense_data[4];
+} __PACKED;
+
struct upiu_trans_mgmt_query_hdr
{
struct upiu_basic_hdr basic_hdr;
@@ -149,7 +170,7 @@
uint8_t idn;
uint8_t index;
uint8_t selector;
- struct upiu_basic_hdr *resp_ptr;
+ struct upiu_basic_resp_hdr *resp_ptr;
uint64_t resp_len;
uint16_t resp_data_len;
addr_t resp_data_ptr;
diff --git a/platform/msm_shared/interrupts.c b/platform/msm_shared/interrupts.c
index 9d84bb2..2fdaf35 100644
--- a/platform/msm_shared/interrupts.c
+++ b/platform/msm_shared/interrupts.c
@@ -31,6 +31,7 @@
#include <platform/irqs.h>
#include <platform/interrupts.h>
#include <debug.h>
+#include <qgic.h>
extern int target_supports_qgic();
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index f466d26..43f5123 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -66,6 +66,18 @@
}
vsync_period = vsync_period_intmd * hsync_period;
+ /* Program QOS remapper settings */
+ writel(0x1A9, MDP_DMA_P_QOS_REMAPPER);
+ writel(0x0, MDP_DMA_P_WATERMARK_0);
+ writel(0x0, MDP_DMA_P_WATERMARK_1);
+ writel(0x0, MDP_DMA_P_WATERMARK_2);
+ if (pinfo->xres >= 720)
+ writel(0xFFFF, MDP_PANIC_LUT0);
+ else
+ writel(0x00FF, MDP_PANIC_LUT0);
+ writel(0x1, MDP_PANIC_ROBUST_CTRL);
+ writel(0xFF00, MDP_ROBUST_LUT);
+
// ------------- programming MDP_DMA_P_CONFIG ---------------------
writel(0x1800bf, MDP_DMA_P_CONFIG); // rgb888
@@ -110,6 +122,18 @@
unsigned short pack_pattern = 0x21;
unsigned char ystride = 3;
+ /* Program QOS remapper settings */
+ writel(0x1A9, MDP_DMA_P_QOS_REMAPPER);
+ writel(0x0, MDP_DMA_P_WATERMARK_0);
+ writel(0x0, MDP_DMA_P_WATERMARK_1);
+ writel(0x0, MDP_DMA_P_WATERMARK_2);
+ if (pinfo->xres >= 720)
+ writel(0xFFFF, MDP_PANIC_LUT0);
+ else
+ writel(0x00FF, MDP_PANIC_LUT0);
+ writel(0x1, MDP_PANIC_ROBUST_CTRL);
+ writel(0xFF00, MDP_ROBUST_LUT);
+
writel(0x03ffffff, MDP_INTR_ENABLE);
// ------------- programming MDP_DMA_P_CONFIG ---------------------
@@ -217,7 +241,7 @@
return NO_ERROR;
}
-int mdss_hdmi_on(void)
+int mdss_hdmi_on(struct msm_panel_info *pinfo)
{
return NO_ERROR;
}
diff --git a/platform/msm_shared/mdp4.c b/platform/msm_shared/mdp4.c
index 705819e..f592a19 100644
--- a/platform/msm_shared/mdp4.c
+++ b/platform/msm_shared/mdp4.c
@@ -429,7 +429,7 @@
return NO_ERROR;
}
-int mdss_hdmi_on(void)
+int mdss_hdmi_on(struct msm_panel_info *pinfo)
{
return NO_ERROR;
}
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 5509bc8..ddda7ee 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -73,6 +73,32 @@
return mdss_mdp_intf_off;
}
+static uint32_t mdss_mdp_get_ppb_offset()
+{
+ uint32_t mdss_mdp_ppb_off = 0;
+ uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
+
+ /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */
+ if (mdss_mdp_rev == MDSS_MDP_HW_REV_108)
+ mdss_mdp_ppb_off = 0x1420;
+ else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
+ mdss_mdp_ppb_off = 0x1334;
+ else
+ dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n");
+
+ return mdss_mdp_ppb_off;
+}
+
+static uint32_t mdss_mdp_vbif_qos_remap_get_offset()
+{
+ uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
+
+ if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
+ return 0xB0020;
+ else
+ return 0xC8020;
+}
+
void mdp_clk_gating_ctrl(void)
{
writel(0x40000000, MDP_CLK_CTRL0);
@@ -118,6 +144,9 @@
else
*ctl0_reg_val = 0x22048;
*ctl1_reg_val = 0x24090;
+
+ if (pinfo->lcdc.dst_split)
+ *ctl0_reg_val |= BIT(4);
break;
case MDSS_MDP_PIPE_TYPE_DMA:
if (dual_pipe_single_ctl)
@@ -125,6 +154,8 @@
else
*ctl0_reg_val = 0x22840;
*ctl1_reg_val = 0x25080;
+ if (pinfo->lcdc.dst_split)
+ *ctl0_reg_val |= BIT(12);
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
@@ -133,17 +164,30 @@
else
*ctl0_reg_val = 0x22041;
*ctl1_reg_val = 0x24082;
+ if (pinfo->lcdc.dst_split)
+ *ctl0_reg_val |= BIT(1);
break;
}
/* For targets from MDP v1.5, MDP INTF registers are double buffered */
if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_108)) {
+ if (pinfo->dest == DISPLAY_2) {
+ *ctl0_reg_val |= BIT(31);
+ *ctl1_reg_val |= BIT(30);
+ } else {
*ctl0_reg_val |= BIT(30);
*ctl1_reg_val |= BIT(31);
+ }
} else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) ||
- (mdss_mdp_rev == MDSS_MDP_HW_REV_109)) {
+ (mdss_mdp_rev == MDSS_MDP_HW_REV_109) ||
+ (mdss_mdp_rev == MDSS_MDP_HW_REV_110)) {
+ if (pinfo->dest == DISPLAY_2) {
+ *ctl0_reg_val |= BIT(29);
+ *ctl1_reg_val |= BIT(30);
+ } else {
*ctl0_reg_val |= BIT(30);
*ctl1_reg_val |= BIT(29);
+ }
}
}
@@ -182,8 +226,7 @@
dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n",
__func__, out_size, fb_off, src_xy, dst_xy);
-
- writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR);
+ writel((uint32_t) fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR);
writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE);
writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE);
writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE);
@@ -386,23 +429,22 @@
free_smp_offset);
}
-void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
+static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
{
uint32_t hsync_period, vsync_period;
uint32_t hsync_start_x, hsync_end_x;
uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
- uint32_t mdss_mdp_intf_off;
uint32_t adjust_xres = 0;
struct lcdc_panel_info *lcdc = NULL;
struct intf_timing_params itp = {0};
if (pinfo == NULL)
- return ERR_INVALID_ARGS;
+ return;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
- return ERR_INVALID_ARGS;
+ return;
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display) {
@@ -415,8 +457,9 @@
}
if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) {
- writel(BIT(16), MDP_REG_PPB0_CONFIG);
- writel(BIT(5), MDP_REG_PPB0_CNTL);
+ uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
+ writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
+ writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
}
if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
@@ -437,9 +480,6 @@
itp.underflow_clr = pinfo->lcdc.underflow_clr;
itp.hsync_skew = pinfo->lcdc.hsync_skew;
-
- mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
-
hsync_period = itp.hsync_pulse_width + itp.h_back_porch +
itp.width + itp.h_front_porch;
@@ -466,41 +506,41 @@
hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
- writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off);
+ writel(hsync_ctl, MDP_HSYNC_CTL + intf_base);
writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
- mdss_mdp_intf_off);
- writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
+ intf_base);
+ writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base);
writel(itp.vsync_pulse_width*hsync_period,
MDP_VSYNC_PULSE_WIDTH_F0 +
- mdss_mdp_intf_off);
- writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
- writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off);
+ intf_base);
+ writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base);
+ writel(display_hctl, MDP_DISPLAY_HCTL + intf_base);
writel(display_vstart, MDP_DISPLAY_V_START_F0 +
- mdss_mdp_intf_off);
- writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off);
+ intf_base);
+ writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base);
writel(display_vend, MDP_DISPLAY_V_END_F0 +
- mdss_mdp_intf_off);
- writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off);
- writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off);
+ intf_base);
+ writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base);
+ writel(0x00, MDP_ACTIVE_HCTL + intf_base);
+ writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base);
+ writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base);
+ writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base);
+ writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base);
+ writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base);
- if (intf_base == MDP_INTF_0_BASE) /* eDP */
- writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */
+ writel(0x212A, MDP_PANEL_FORMAT + intf_base);
else
- writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ writel(0x213F, MDP_PANEL_FORMAT + intf_base);
}
-void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo,
+static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo,
uint32_t intf_base)
{
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
- uint32_t mdss_mdp_intf_off;
uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines;
uint32_t adjust_xres = 0;
+ uint32_t fetch_enable = BIT(31);
struct lcdc_panel_info *lcdc = NULL;
@@ -520,8 +560,6 @@
lcdc->v_back_porch >= MDP_MIN_FETCH)
return;
- mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
-
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display)
adjust_xres /= 2;
@@ -547,8 +585,11 @@
fetch_start = (v_total - fetch_lines) * h_total + 1;
- writel(fetch_start, MDP_PROG_FETCH_START + mdss_mdp_intf_off);
- writel(BIT(31), MDP_INTF_CONFIG + mdss_mdp_intf_off);
+ if (pinfo->dfps.panel_dfps.enabled)
+ fetch_enable |= BIT(23);
+
+ writel_relaxed(fetch_start, MDP_PROG_FETCH_START + intf_base);
+ writel_relaxed(fetch_enable, MDP_INTF_CONFIG + intf_base);
}
void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
@@ -560,7 +601,7 @@
height = fb->height;
width = fb->width;
- if (pinfo->lcdc.dual_pipe)
+ if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
width /= 2;
/* write active region size*/
@@ -593,10 +634,17 @@
break;
}
+ /*
+ * When ping-pong split is enabled and two pipes are used,
+ * both the pipes need to be staged on the same layer mixer.
+ */
+ if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split)
+ left_staging_level |= right_staging_level;
+
/* Base layer for layer mixer 0 */
writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0);
- if (pinfo->lcdc.dual_pipe) {
+ if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) {
writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE);
writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE);
writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP);
@@ -621,39 +669,46 @@
uint32_t mode = 0;
uint32_t budget_ctl = 0;
uint32_t lossy_mode = 0;
- uint32_t xres;
struct fbc_panel_info *fbc;
- uint32_t enc_mode;
+ uint32_t enc_mode, width;
fbc = &pinfo->fbc;
- xres = pinfo->xres;
if (!pinfo->fbc.enabled)
return;
- if (pinfo->mipi.dual_dsi)
- xres /= 2;
-
/* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */
enc_mode = (fbc->comp_ratio == 2) ? 0 : 1;
- mode = ((xres) << 16) | (enc_mode) << 9 | ((fbc->comp_mode) << 8) |
- ((fbc->qerr_enable) << 7) | ((fbc->cd_bias) << 4) |
- ((fbc->pat_enable) << 3) | ((fbc->vlc_enable) << 2) |
- ((fbc->bflc_enable) << 1) | 1;
+ width = pinfo->xres;
+ if (enc_mode)
+ width = (pinfo->xres/fbc->comp_ratio);
- dprintf(SPEW, "xres = %d, comp_mode %d, qerr_enable = %d, cd_bias = %d\n",
- xres, fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias);
- dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable\n",
+ if (pinfo->mipi.dual_dsi)
+ width /= 2;
+
+ mode = ((width) << 16) | ((fbc->slice_height) << 11) |
+ ((fbc->pred_mode) << 10) | (enc_mode) << 9 |
+ ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) |
+ ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) |
+ ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1;
+
+ dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \
+ comp_mode %d, qerr_enable = %d, cd_bias = %d\n",
+ width, fbc->slice_height, fbc->pred_mode, enc_mode,
+ fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias);
+ dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable = %d\n",
fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable);
budget_ctl = ((fbc->line_x_budget) << 12) |
((fbc->block_x_budget) << 8) | fbc->block_budget;
- lossy_mode = ((fbc->lossless_mode_thd) << 16) |
+ lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) |
((fbc->lossy_mode_thd) << 8) |
((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx;
+ dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n",
+ mode, budget_ctl, lossy_mode);
writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE);
writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
@@ -687,7 +742,9 @@
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_105) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_109))
+ MDSS_MDP_HW_REV_109) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_110))
map = 0xA4;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_103))
@@ -704,6 +761,7 @@
uint32_t left_pipe_xin_id, right_pipe_xin_id;
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
uint32_t vbif_qos[4] = {0, 0, 0, 0};
+ uint32_t vbif_offset;
mdp_select_pipe_xin_id(pinfo,
&left_pipe_xin_id, &right_pipe_xin_id);
@@ -715,7 +773,8 @@
vbif_qos[2] = 2;
vbif_qos[3] = 2;
} else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) ||
- MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109)) {
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) {
vbif_qos[0] = 1;
vbif_qos[1] = 2;
vbif_qos[2] = 2;
@@ -724,8 +783,11 @@
return;
}
+ vbif_offset = mdss_mdp_vbif_qos_remap_get_offset();
+
for (i = 0; i < 4; i++) {
- reg_val = readl(VBIF_VBIF_QOS_REMAP_00 + i*4);
+ /* VBIF_VBIF_QOS_REMAP_00 */
+ reg_val = readl(REG_MDP(vbif_offset) + i*4);
mask = 0x3 << (left_pipe_xin_id * 2);
reg_val &= ~(mask);
reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2);
@@ -735,41 +797,66 @@
reg_val &= ~(mask);
reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2);
}
- writel(reg_val, VBIF_VBIF_QOS_REMAP_00 + i*4);
+ writel(reg_val, REG_MDP(vbif_offset) + i*4);
}
}
static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo,
int is_main_ctl)
{
- if (pinfo->lcdc.pipe_swap) {
- if (is_main_ctl)
- return BIT(4) | BIT(5); /* Interface 2 */
- else
- return BIT(5); /* Interface 1 */
+ uint32_t mctl_intf_sel;
+ uint32_t sctl_intf_sel;
+
+ if ((pinfo->dest == DISPLAY_2) ||
+ ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) {
+ mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */
+ sctl_intf_sel = BIT(5); /* Interface 1 */
} else {
- if (is_main_ctl)
- return BIT(5); /* Interface 1 */
- else
- return BIT(4) | BIT(5); /* Interface 2 */
+ mctl_intf_sel = BIT(5); /* Interface 1 */
+ sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */
}
+ dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__,
+ (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1",
+ (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1");
+ return is_main_ctl ? mctl_intf_sel : sctl_intf_sel;
+}
+
+static void mdp_set_intf_base(struct msm_panel_info *pinfo,
+ uint32_t *intf_sel, uint32_t *sintf_sel,
+ uint32_t *intf_base, uint32_t *sintf_base)
+{
+ if (pinfo->dest == DISPLAY_2) {
+ *intf_sel = BIT(16);
+ *sintf_sel = BIT(8);
+ *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset();
+ *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset();
+ } else {
+ *intf_sel = BIT(8);
+ *sintf_sel = BIT(16);
+ *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset();
+ *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset();
+ }
+ dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__,
+ (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1",
+ (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2");
}
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
- int ret = NO_ERROR;
- struct lcdc_panel_info *lcdc = NULL;
- uint32_t intf_sel = 0x100;
+ uint32_t intf_sel, sintf_sel;
+ uint32_t intf_base, sintf_base;
uint32_t left_pipe, right_pipe;
uint32_t reg;
- mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE);
- mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE);
+ mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base);
+
+ mdss_intf_tg_setup(pinfo, intf_base);
+ mdss_intf_fetch_start_config(pinfo, intf_base);
if (pinfo->mipi.dual_dsi) {
- mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE);
- mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE);
+ mdss_intf_tg_setup(pinfo, sintf_base);
+ mdss_intf_fetch_start_config(pinfo, sintf_base);
}
mdp_clk_gating_ctrl();
@@ -808,7 +895,7 @@
reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0);
writel(reg, MDP_CTL_1_BASE + CTL_TOP);
}
- intf_sel |= BIT(16); /* INTF 2 enable */
+ intf_sel |= sintf_sel; /* INTF 2 enable */
}
writel(intf_sel, MDP_DISP_INTF_SEL);
@@ -822,8 +909,6 @@
int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
{
- int ret = NO_ERROR;
- struct lcdc_panel_info *lcdc = NULL;
uint32_t left_pipe, right_pipe;
mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE);
@@ -858,8 +943,6 @@
int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
{
- int ret = NO_ERROR;
- struct lcdc_panel_info *lcdc = NULL;
uint32_t left_pipe, right_pipe;
mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE);
@@ -894,13 +977,13 @@
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
- uint32_t intf_sel = BIT(8);
+ uint32_t intf_sel, sintf_sel;
+ uint32_t intf_base, sintf_base;
uint32_t reg;
int ret = NO_ERROR;
uint32_t left_pipe, right_pipe;
struct lcdc_panel_info *lcdc = NULL;
- uint32_t mdss_mdp_intf_off = 0;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
@@ -909,8 +992,12 @@
if (lcdc == NULL)
return ERR_INVALID_ARGS;
+ mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base);
+
if (pinfo->lcdc.split_display) {
reg = BIT(1); /* Command mode */
+ if (pinfo->lcdc.dst_split)
+ reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */
if (pinfo->lcdc.pipe_swap)
reg |= BIT(4); /* Use intf2 as trigger */
else
@@ -921,16 +1008,15 @@
}
if (pinfo->lcdc.dst_split) {
- writel(BIT(16), MDP_REG_PPB0_CONFIG);
- writel(BIT(5), MDP_REG_PPB0_CNTL);
+ uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
+ writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
+ writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
}
- mdss_mdp_intf_off = mdss_mdp_intf_offset();
-
mdp_clk_gating_ctrl();
if (pinfo->mipi.dual_dsi)
- intf_sel |= BIT(16); /* INTF 2 enable */
+ intf_sel |= sintf_sel; /* INTF 2 enable */
writel(intf_sel, MDP_DISP_INTF_SEL);
@@ -947,7 +1033,7 @@
mdss_layer_mixer_setup(fb, pinfo);
- writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ writel(0x213F, MDP_PANEL_FORMAT + intf_base);
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
writel(reg, MDP_CTL_0_BASE + CTL_TOP);
@@ -955,7 +1041,7 @@
mdss_fbc_cfg(pinfo);
if (pinfo->mipi.dual_dsi) {
- writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ writel(0x213F, sintf_base + MDP_PANEL_FORMAT);
if (!pinfo->lcdc.dst_split) {
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
writel(reg, MDP_CTL_1_BASE + CTL_TOP);
@@ -968,20 +1054,34 @@
int mdp_dsi_video_on(struct msm_panel_info *pinfo)
{
uint32_t ctl0_reg_val, ctl1_reg_val;
+ uint32_t timing_engine_en;
+
mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
- writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
+ if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
+ writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
+
+ if (pinfo->dest == DISPLAY_1)
+ timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
+ else
+ timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN;
+ writel(0x01, timing_engine_en + mdss_mdp_intf_offset());
return NO_ERROR;
}
-int mdp_dsi_video_off()
+int mdp_dsi_video_off(struct msm_panel_info *pinfo)
{
+ uint32_t timing_engine_en;
+
+ if (pinfo->dest == DISPLAY_1)
+ timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
+ else
+ timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN;
+
if(!target_cont_splash_screen())
{
- writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN +
- mdss_mdp_intf_offset());
+ writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset());
mdelay(60);
/* Ping-Pong done Tear Check Read/Write */
/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
@@ -1011,7 +1111,9 @@
uint32_t ctl0_reg_val, ctl1_reg_val;
mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
+ if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
+ writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
+
writel(0x01, MDP_CTL_0_BASE + CTL_START);
return NO_ERROR;
}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 1ac8fbd..f8ff3bb 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -35,11 +35,13 @@
#include <string.h>
#include <debug.h>
#include <target/display.h>
+#include <mdp5.h>
#include <platform/iomap.h>
#include <platform/clock.h>
#include <platform/timer.h>
#include <err.h>
#include <msm_panel.h>
+#include <arch/ops.h>
extern void mdp_disable(void);
extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
@@ -52,7 +54,7 @@
#define MIPI_DSI1_BASE MIPI_DSI_BASE
#endif
-static struct fbcon_config mipi_fb_cfg = {
+struct fbcon_config mipi_fb_cfg = {
.height = 0,
.width = 0,
.stride = 0,
@@ -62,26 +64,30 @@
.update_done = NULL,
};
-static int cmd_mode_status = 0;
+static char read_id_a1h_cmd[4] = { 0xA1, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */
+static struct mipi_dsi_cmd read_ddb_start_cmd =
+ {sizeof(read_id_a1h_cmd), read_id_a1h_cmd, 0x00};
+
void secure_writel(uint32_t, uint32_t);
uint32_t secure_readl(uint32_t);
static uint32_t response_value = 0;
-uint32_t mdss_dsi_read_panel_signature(uint32_t panel_signature)
+static uint32_t mdss_dsi_read_panel_signature(struct mipi_panel_info *mipi)
{
uint32_t rec_buf[1];
uint32_t *lp = rec_buf, data;
- int ret = response_value;
+ uint32_t ret = response_value;
+ uint32_t panel_signature = mipi->signature;
#if (DISPLAY_TYPE_MDSS == 1)
if (ret && ret != panel_signature)
goto exit_read_signature;
- ret = mipi_dsi_cmds_tx(&read_ddb_start_cmd, 1);
+ ret = mdss_dsi_cmds_tx(mipi, &read_ddb_start_cmd, 1, 0);
if (ret)
goto exit_read_signature;
- if (!mdss_dsi_cmds_rx(&lp, 1, 1))
+ if (!mdss_dsi_cmds_rx(mipi, &lp, 1, 1))
goto exit_read_signature;
data = ntohl(*lp);
@@ -92,30 +98,34 @@
exit_read_signature:
/* Keep the non detectable panel at the end and set panel signature 0xFFFF */
- if (panel_signature == 0xFFFF)
+ if ((panel_signature == 0) || (panel_signature == 0xFFFF))
ret = 0;
#endif
return ret;
}
-int mdss_dual_dsi_cmd_dma_trigger_for_panel()
+static int mdss_dsi_cmd_dma_trigger_for_panel(char dual_dsi,
+ uint32_t ctl_base, uint32_t sctl_base)
{
uint32_t ReadValue;
uint32_t count = 0;
int status = 0;
+ uint32_t base = dual_dsi ? sctl_base : ctl_base;
#if (DISPLAY_TYPE_MDSS == 1)
- writel(0x03030303, MIPI_DSI0_BASE + INT_CTRL);
- writel(0x1, MIPI_DSI0_BASE + CMD_MODE_DMA_SW_TRIGGER);
+ writel(0x03030303, ctl_base + INT_CTRL);
+ writel(0x1, ctl_base + CMD_MODE_DMA_SW_TRIGGER);
dsb();
- writel(0x03030303, MIPI_DSI1_BASE + INT_CTRL);
- writel(0x1, MIPI_DSI1_BASE + CMD_MODE_DMA_SW_TRIGGER);
- dsb();
+ if (dual_dsi) {
+ writel(0x03030303, sctl_base + INT_CTRL);
+ writel(0x1, sctl_base + CMD_MODE_DMA_SW_TRIGGER);
+ dsb();
+ }
- ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001;
+ ReadValue = readl(base + INT_CTRL) & 0x00000001;
while (ReadValue != 0x00000001) {
- ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001;
+ ReadValue = readl(base + INT_CTRL) & 0x00000001;
count++;
if (count > 0xffff) {
status = FAIL;
@@ -125,57 +135,30 @@
}
}
- writel((readl(MIPI_DSI1_BASE + INT_CTRL) | 0x01000001),
- MIPI_DSI1_BASE + INT_CTRL);
+ writel((readl(base + INT_CTRL) | 0x01000001), base + INT_CTRL);
dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
#endif
return status;
}
-int dsi_cmd_dma_trigger_for_panel()
-{
- unsigned long ReadValue;
- unsigned long count = 0;
- int status = 0;
-
- writel(0x03030303, DSI_INT_CTRL);
- writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
- dsb();
- ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
- while (ReadValue != 0x00000001) {
- ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
- count++;
- if (count > 0xffff) {
- status = FAIL;
- dprintf(CRITICAL,
- "Panel CMD: command mode dma test failed\n");
- return status;
- }
- }
-
- writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
- dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
- return status;
-}
-
-int mdss_dsi_wait4_video_done()
+static int mdss_dsi_wait4_video_done(uint32_t ctl_base)
{
unsigned long read;
unsigned long count = 0;
int status = 0;
/* If video mode is not enabled, return here */
- if ((readl(DSI_CTRL) & BIT(1)) == 0)
+ if ((readl(ctl_base + CTRL) & BIT(1)) == 0)
return 0;
- read = readl(DSI_INT_CTRL);
+ read = readl(ctl_base + INT_CTRL);
/* Enable VIDEO MODE DONE MASK and clear the interrupt */
read = read | DSI_VIDEO_MODE_DONE_MASK | DSI_VIDEO_MODE_DONE_AK;
- writel(read, DSI_INT_CTRL);
+ writel(read, ctl_base + INT_CTRL);
dsb();
- read = readl(DSI_INT_CTRL) & DSI_VIDEO_MODE_DONE_STAT;
- while (!read) {
- read = readl(DSI_INT_CTRL) & DSI_VIDEO_MODE_DONE_STAT;
+ do {
+ read = readl(ctl_base + INT_CTRL) &
+ DSI_VIDEO_MODE_DONE_STAT;
count++;
if (count > 0xffff) {
status = FAIL;
@@ -183,48 +166,69 @@
"Panel CMD: Did not recieve video mode done interrupt\n");
return status;
}
- }
+ } while (!read);
- writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
+ writel((readl(ctl_base + INT_CTRL) | 0x01000001), ctl_base + INT_CTRL);
dprintf(SPEW, "Panel wait_4_video_done: Recieved video mode done ack\n");
/* Skip BLLP 4ms */
mdelay(4);
return status;
-
}
-int mdss_dual_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
+int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi,
+ struct mipi_dsi_cmd *cmds, int count, char dual_dsi)
{
int ret = 0;
+#if (DISPLAY_TYPE_MDSS == 1)
struct mipi_dsi_cmd *cm;
int i = 0;
- char pload[256];
+ uint8_t pload[256];
uint32_t off;
+ uint32_t size;
+ uint32_t ctl_base, sctl_base;
-#if (DISPLAY_TYPE_MDSS == 1)
- /* Align pload at 8 byte boundry */
- off = pload;
+ /* if dest controller is not specified, default to DSI0 */
+ if (!mipi) {
+ ctl_base = MIPI_DSI0_BASE;
+ sctl_base = MIPI_DSI1_BASE;
+ } else {
+ ctl_base = mipi->ctl_base;
+ sctl_base = mipi->sctl_base;
+ }
+
+ /* Align pload at 8 byte boundary */
+ off = (uint32_t) pload;
off &= 0x07;
if (off)
off = 8 - off;
- off += pload;
+ off += (uint32_t) pload;
cm = cmds;
for (i = 0; i < count; i++) {
/* Wait for VIDEO_MODE_DONE */
- ret = mdss_dsi_wait4_video_done();
+ ret = mdss_dsi_wait4_video_done(ctl_base);
if (ret)
goto wait4video_error;
- memcpy((void *)off, (cm->payload), cm->size);
- writel(off, MIPI_DSI0_BASE + DMA_CMD_OFFSET);
- writel(cm->size, MIPI_DSI0_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build
- writel(off, MIPI_DSI1_BASE + DMA_CMD_OFFSET);
- writel(cm->size, MIPI_DSI1_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build
+ /* The payload size has to be a multiple of 4 */
+ size = cm->size;
+ size &= 0x03;
+ if (size)
+ size = 4 - size;
+ size += cm->size;
+ memcpy((uint8_t *)off, (cm->payload), size);
+ arch_clean_invalidate_cache_range((addr_t)(off), size);
+ writel(off, ctl_base + DMA_CMD_OFFSET);
+ writel(size, ctl_base + DMA_CMD_LENGTH);
+ if (dual_dsi) {
+ writel(off, sctl_base + DMA_CMD_OFFSET);
+ writel(size, sctl_base + DMA_CMD_LENGTH);
+ }
dsb();
- ret += mdss_dual_dsi_cmd_dma_trigger_for_panel();
+ ret += mdss_dsi_cmd_dma_trigger_for_panel(dual_dsi, ctl_base,
+ sctl_base);
if (cm->wait)
mdelay(cm->wait);
else
@@ -236,12 +240,20 @@
return ret;
}
-int mdss_dsi_cmds_rx(uint32_t **rp, int rp_len, int rdbk_len)
+int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len,
+ int rdbk_len)
{
uint32_t *lp, data;
- char *dp;
+ uint32_t *dp;
int i, off;
int rlen, res;
+ uint32_t ctl_base;
+
+ /* if dest controller is not specified, default to DSI0 */
+ if (!mipi)
+ ctl_base = MIPI_DSI0_BASE;
+ else
+ ctl_base = mipi->ctl_base;
if (rdbk_len > rp_len) {
return 0;
@@ -271,7 +283,7 @@
off += ((rlen - 1) * 4);
for (i = 0; i < rlen; i++) {
- data = readl(MIPI_DSI_BASE + off);
+ data = readl(ctl_base + off);
*lp = ntohl(data); /* to network byte order */
lp++;
@@ -288,6 +300,509 @@
return rdbk_len;
}
+static int mdss_dsi_cmd_bta_sw_trigger(uint32_t ctl_base)
+{
+ uint32_t data;
+ int cnt = 0;
+ int err = 0;
+
+ writel(0x01, ctl_base + 0x094); /* trigger */
+ while (cnt < 10000) {
+ data = readl(ctl_base + 0x0004); /*DSI_STATUS */
+ if ((data & 0x0010) == 0)
+ break;
+ cnt++;
+ }
+ if (cnt == 10000)
+ err = 1;
+ return err;
+}
+
+int mdss_dsi_host_init(struct mipi_panel_info *mipi, uint32_t
+ dual_dsi, uint32_t broadcast)
+{
+ uint8_t DMA_STREAM1 = 0; // for mdp display processor path
+ uint8_t EMBED_MODE1 = 1; // from frame buffer
+ uint8_t POWER_MODE2 = 1; // from frame buffer
+ uint8_t PACK_TYPE1 = 0; // long packet
+ uint8_t VC1 = 0;
+ uint8_t DT1 = 0; // non embedded mode
+ uint8_t WC1 = 0; // for non embedded mode only
+ uint8_t DLNx_EN;
+ uint8_t lane_swap = 0;
+ uint32_t timing_ctl = 0;
+ uint32_t lane_swap_dsi1 = 0;
+ uint32_t ctrl_mode = 0x105; //Default is command mode to send cmds.
+
+#if (DISPLAY_TYPE_MDSS == 1)
+ switch (mipi->num_of_lanes) {
+ default:
+ case 1:
+ DLNx_EN = 1; // 1 lane
+ break;
+ case 2:
+ DLNx_EN = 3; // 2 lane
+ break;
+ case 3:
+ DLNx_EN = 7; // 3 lane
+ break;
+ case 4:
+ DLNx_EN = 0x0F; /* 4 lanes */
+ break;
+ }
+
+ lane_swap = mipi->lane_swap;
+ timing_ctl = ((mipi->t_clk_post << 8) | mipi->t_clk_pre);
+
+ if (mipi->cmds_post_tg) {
+ /*
+ * Need to send pixel data before sending the ON commands
+ * so need to configure controller to VIDEO MODE.
+ */
+ ctrl_mode = 0x103;
+ }
+
+ if (dual_dsi) {
+ writel(0x0001, mipi->sctl_base + SOFT_RESET);
+ writel(0x0000, mipi->sctl_base + SOFT_RESET);
+
+ /* Turn on all DSI Clks */
+ writel((0 << 16) | 0x3f, mipi->sctl_base + CLK_CTRL);
+ writel(DMA_STREAM1 << 8 | 0x04, mipi->sctl_base + TRIG_CTRL);
+
+ writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->sctl_base + CTRL);
+ writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26
+ | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
+ mipi->sctl_base + COMMAND_MODE_DMA_CTRL);
+
+ /* for 8939 hw dsi1 has Lane_map as 3210 */
+ if (readl(mipi->ctl_base) == DSI_HW_REV_103_1)
+ lane_swap_dsi1 = 0x7;
+ else
+ lane_swap_dsi1 = lane_swap;
+ writel(lane_swap_dsi1, mipi->sctl_base + LANE_SWAP_CTL);
+ writel(timing_ctl, mipi->sctl_base + TIMING_CTL);
+
+ if (mipi->force_clk_lane_hs) {
+ uint32_t tmp;
+
+ tmp = readl(mipi->sctl_base + LANE_CTL);
+ tmp |= BIT(28);
+ writel(tmp, mipi->sctl_base + LANE_CTL);
+ }
+ }
+
+ writel(0x0001, mipi->ctl_base + SOFT_RESET);
+ writel(0x0000, mipi->ctl_base + SOFT_RESET);
+
+ /* Turn on all DSI Clks */
+ writel((0 << 16) | 0x3f, mipi->ctl_base + CLK_CTRL);
+ writel(DMA_STREAM1 << 8 | 0x04, mipi->ctl_base + TRIG_CTRL);
+
+ writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->ctl_base + CTRL);
+ writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26
+ | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
+ mipi->ctl_base + COMMAND_MODE_DMA_CTRL);
+
+ writel(lane_swap, mipi->ctl_base + LANE_SWAP_CTL);
+ writel(timing_ctl, mipi->ctl_base + TIMING_CTL);
+
+ if (mipi->force_clk_lane_hs) {
+ uint32_t tmp;
+
+ tmp = readl(mipi->ctl_base + LANE_CTL);
+ tmp |= BIT(28);
+ writel(tmp, mipi->ctl_base + LANE_CTL);
+ }
+#endif
+
+ return 0;
+}
+
+void mdss_dsi_panel_shutdown(struct msm_panel_info *pinfo)
+{
+#if (DISPLAY_TYPE_MDSS == 1)
+ unsigned long read_val = 0;
+ uint32_t ctl_base = pinfo->mipi.ctl_base;
+ uint32_t sctl_base = pinfo->mipi.sctl_base;
+
+ if (pinfo->mipi.panel_off_cmds) {
+ /*
+ * Once MDP TG is disabled, reset of DSI controller is
+ * needed before we send panel OFF commands.
+ */
+ if (pinfo->type == MIPI_VIDEO_PANEL) {
+ read_val = readl(ctl_base + CTRL);
+ writel((read_val & ~BIT(0)), ctl_base + CTRL);
+ writel(0x0001, ctl_base + SOFT_RESET);
+ dsb();
+ writel(0x0000, ctl_base + SOFT_RESET);
+ dsb();
+ /* Enable cmd mode only */
+ writel(((read_val & ~BIT(1)) | BIT(2)),
+ ctl_base + CTRL);
+ }
+
+ if (pinfo->mipi.broadcast) {
+ if (pinfo->type == MIPI_VIDEO_PANEL) {
+ read_val = readl(sctl_base + CTRL);
+ writel((read_val & ~BIT(0)),
+ sctl_base + CTRL);
+
+ writel(0x0001, sctl_base + SOFT_RESET);
+ dsb();
+ writel(0x0000, sctl_base + SOFT_RESET);
+ dsb();
+
+ writel(((read_val & ~BIT(1)) | BIT(2)),
+ sctl_base + CTRL);
+ }
+ }
+ mdss_dsi_cmds_tx(&pinfo->mipi, pinfo->mipi.panel_off_cmds,
+ pinfo->mipi.num_of_panel_off_cmds,
+ pinfo->mipi.broadcast);
+ }
+#endif
+}
+
+int mdss_dsi_panel_initialize(struct mipi_panel_info *mipi, uint32_t
+ broadcast)
+{
+ int status = 0;
+ uint32_t ctrl_mode = 0;
+
+#if (DISPLAY_TYPE_MDSS == 1)
+ if (!mipi->panel_on_cmds)
+ goto end;
+
+ ctrl_mode = readl(mipi->ctl_base + CTRL);
+
+ /* Enable command mode before sending the commands. */
+ writel(ctrl_mode | 0x04, mipi->ctl_base + CTRL);
+ if (broadcast)
+ writel(ctrl_mode | 0x04, mipi->sctl_base + CTRL);
+ status = mdss_dsi_cmds_tx(mipi, mipi->panel_on_cmds,
+ mipi->num_of_panel_on_cmds, broadcast);
+ writel(ctrl_mode, mipi->ctl_base + CTRL);
+ if (broadcast)
+ writel(ctrl_mode, mipi->sctl_base + CTRL);
+
+ if (!broadcast && !status && target_panel_auto_detect_enabled())
+ status = mdss_dsi_read_panel_signature(mipi);
+
+end:
+#endif
+ return status;
+}
+
+int mdss_dsi_video_mode_config(uint16_t disp_width,
+ uint16_t disp_height,
+ uint16_t img_width,
+ uint16_t img_height,
+ uint16_t hsync_porch0_fp,
+ uint16_t hsync_porch0_bp,
+ uint16_t vsync_porch0_fp,
+ uint16_t vsync_porch0_bp,
+ uint16_t hsync_width,
+ uint16_t vsync_width,
+ uint16_t dst_format,
+ uint16_t traffic_mode,
+ uint8_t lane_en,
+ uint8_t pulse_mode_hsa_he,
+ uint32_t low_pwr_stop_mode,
+ uint8_t eof_bllp_pwr,
+ uint8_t interleav,
+ uint32_t ctl_base)
+{
+ int status = 0;
+
+#if (DISPLAY_TYPE_MDSS == 1)
+ int last_line_interleave_en = 0;
+
+ /*Check if EOF_BLLP_PWR_MODE bit is set*/
+ if(eof_bllp_pwr & 0x8)
+ last_line_interleave_en = 1;
+
+ /* disable mdp first */
+ mdp_disable();
+
+ writel(0x00000000, ctl_base + CLK_CTRL);
+ writel(0x00000002, ctl_base + CLK_CTRL);
+ writel(0x00000006, ctl_base + CLK_CTRL);
+ writel(0x0000000e, ctl_base + CLK_CTRL);
+ writel(0x0000001e, ctl_base + CLK_CTRL);
+ writel(0x0000023f, ctl_base + CLK_CTRL);
+
+ writel(0, ctl_base + CTRL);
+
+ writel(0x03f03fe0, ctl_base + ERR_INT_MASK0);
+
+ writel(0x02020202, ctl_base + INT_CTRL);
+
+ /* For 8916/8939, enable DSI timing double buffering */
+ if (readl(ctl_base) >= DSI_HW_REV_103 &&
+ mdp_get_revision() != MDP_REV_305)
+ writel(0x1, ctl_base + TIMING_DB_MODE);
+
+ writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
+ ctl_base + VIDEO_MODE_ACTIVE_H);
+
+ writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
+ ctl_base + VIDEO_MODE_ACTIVE_V);
+
+ if (mdp_get_revision() >= MDP_REV_41 ||
+ mdp_get_revision() == MDP_REV_304 ||
+ mdp_get_revision() == MDP_REV_305) {
+ writel(((disp_height + vsync_porch0_fp
+ + vsync_porch0_bp - 1) << 16)
+ | (disp_width + hsync_porch0_fp
+ + hsync_porch0_bp - 1),
+ ctl_base + VIDEO_MODE_TOTAL);
+ } else {
+ writel(((disp_height + vsync_porch0_fp
+ + vsync_porch0_bp) << 16)
+ | (disp_width + hsync_porch0_fp
+ + hsync_porch0_bp),
+ ctl_base + VIDEO_MODE_TOTAL);
+ }
+
+ writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC);
+
+ writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC);
+
+ writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS);
+
+ /* For 8916/8939, flush the DSI timing registers */
+ if (readl(ctl_base) >= DSI_HW_REV_103 &&
+ mdp_get_revision() != MDP_REV_305)
+ writel(0x1, ctl_base + TIMING_FLUSH);
+
+ writel(0x0, ctl_base + EOT_PACKET_CTRL);
+
+ writel(0x00000100, ctl_base + MISR_VIDEO_CTRL);
+
+ if (mdp_get_revision() >= MDP_REV_41 || mdp_get_revision() == MDP_REV_305) {
+ writel(last_line_interleave_en << 31 | pulse_mode_hsa_he << 28 |
+ low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 |
+ traffic_mode << 8 | dst_format << 4 | 0x0,
+ ctl_base + VIDEO_MODE_CTRL);
+ } else {
+ writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
+ eof_bllp_pwr << 12 | traffic_mode << 8
+ | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL);
+ }
+
+ writel(0x3fd08, ctl_base + HS_TIMER_CTRL);
+ writel(0x00010100, ctl_base + MISR_VIDEO_CTRL);
+
+ writel(0x00010100, ctl_base + INT_CTRL);
+ writel(0x02010202, ctl_base + INT_CTRL);
+ writel(0x02030303, ctl_base + INT_CTRL);
+
+ writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
+ | 0x103, ctl_base + CTRL);
+#endif
+
+ return status;
+}
+
+int mdss_dsi_config(struct msm_fb_panel_data *panel)
+{
+ int ret = NO_ERROR;
+ struct msm_panel_info *pinfo;
+ struct mipi_panel_info *mipi;
+
+#if (DISPLAY_TYPE_MDSS == 1)
+ if (!panel)
+ return ERR_INVALID_ARGS;
+
+ pinfo = &(panel->panel_info);
+ mipi = &(pinfo->mipi);
+
+ dprintf(SPEW, "ctl_base=0x%08x, phy_base=0x%08x\n", mipi->ctl_base,
+ mipi->phy_base);
+
+ mdss_dsi_phy_init(mipi);
+
+ ret = mdss_dsi_host_init(mipi, mipi->dual_dsi,
+ mipi->broadcast);
+ if (ret) {
+ dprintf(CRITICAL, "dsi host init error\n");
+ goto error;
+ }
+
+ mdss_dsi_phy_contention_detection(mipi, mipi->phy_base);
+ if (mipi->dual_dsi)
+ mdss_dsi_phy_contention_detection(mipi, mipi->sphy_base);
+
+ if (panel->pre_init_func) {
+ ret = panel->pre_init_func();
+ if (ret) {
+ dprintf(CRITICAL, "pre_init_func error\n");
+ goto error;
+ }
+ }
+
+ if (!mipi->cmds_post_tg) {
+ ret = mdss_dsi_panel_initialize(mipi, mipi->broadcast);
+ if (ret) {
+ dprintf(CRITICAL, "dsi panel init error\n");
+ goto error;
+ }
+ }
+
+ if (pinfo->rotate && panel->rotate)
+ pinfo->rotate();
+#endif
+
+error:
+ return ret;
+}
+
+int mdss_dsi_post_on(struct msm_fb_panel_data *panel)
+{
+ int ret = 0;
+ struct msm_panel_info *pinfo = &(panel->panel_info);
+
+ if (pinfo->mipi.cmds_post_tg) {
+ ret = mdss_dsi_panel_initialize(&pinfo->mipi, pinfo->mipi.broadcast);
+ if (ret) {
+ dprintf(CRITICAL, "dsi panel init error\n");
+ }
+ }
+ return ret;
+}
+
+int mdss_dsi_cmd_mode_config(uint16_t disp_width,
+ uint16_t disp_height,
+ uint16_t img_width,
+ uint16_t img_height,
+ uint16_t dst_format,
+ uint8_t ystride,
+ uint8_t lane_en,
+ uint8_t interleav,
+ uint32_t ctl_base)
+{
+ uint16_t dst_fmt = 0;
+
+ switch (dst_format) {
+ case DSI_VIDEO_DST_FORMAT_RGB565:
+ dst_fmt = DSI_CMD_DST_FORMAT_RGB565;
+ break;
+ case DSI_VIDEO_DST_FORMAT_RGB666:
+ case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE:
+ dst_fmt = DSI_CMD_DST_FORMAT_RGB666;
+ break;
+ case DSI_VIDEO_DST_FORMAT_RGB888:
+ dst_fmt = DSI_CMD_DST_FORMAT_RGB888;
+ break;
+ default:
+ dprintf(CRITICAL, "unsupported dst format\n");
+ return ERROR;
+ }
+
+#if (DISPLAY_TYPE_MDSS == 1)
+ writel(0x00000000, ctl_base + CLK_CTRL);
+ writel(0x00000000, ctl_base + CLK_CTRL);
+ writel(0x00000000, ctl_base + CLK_CTRL);
+ writel(0x00000000, ctl_base + CLK_CTRL);
+ writel(0x00000002, ctl_base + CLK_CTRL);
+ writel(0x00000006, ctl_base + CLK_CTRL);
+ writel(0x0000000e, ctl_base + CLK_CTRL);
+ writel(0x0000001e, ctl_base + CLK_CTRL);
+ writel(0x0000023f, ctl_base + CLK_CTRL);
+
+ writel(0, ctl_base + CTRL);
+
+ writel(0x03f03fe0, ctl_base + ERR_INT_MASK0);
+
+ writel(0x02020202, ctl_base + INT_CTRL);
+
+ writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL);
+ writel((img_width * ystride + 1) << 16 | 0x0039,
+ ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL);
+ writel((img_width * ystride + 1) << 16 | 0x0039,
+ ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL);
+ writel(img_height << 16 | img_width,
+ ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL);
+ writel(img_height << 16 | img_width,
+ ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL);
+ writel(0x13c2c, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL);
+ writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105,
+ ctl_base + CTRL);
+ writel(0x14000000, ctl_base + COMMAND_MODE_DMA_CTRL);
+ writel(0x10000000, ctl_base + MISR_CMD_CTRL);
+ writel(0x1, ctl_base + EOT_PACKET_CTRL);
+#endif
+ return 0;
+}
+
+int mipi_dsi_on(struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ unsigned long ReadValue;
+ unsigned long count = 0;
+
+ ReadValue = readl(pinfo->mipi.ctl_base + INT_CTRL) & 0x00010000;
+
+ mdelay(10);
+
+ while (ReadValue != 0x00010000) {
+ ReadValue = readl(pinfo->mipi.ctl_base + INT_CTRL) & 0x00010000;
+ count++;
+ if (count > 0xffff) {
+ dprintf(CRITICAL, "Video lane test failed\n");
+ return ERROR;
+ }
+ }
+
+ dprintf(INFO, "Video lane tested successfully\n");
+ return ret;
+}
+
+int mipi_dsi_off(struct msm_panel_info *pinfo)
+{
+ if(!target_cont_splash_screen())
+ {
+ mdss_dsi_panel_shutdown(pinfo);
+ writel(0, pinfo->mipi.ctl_base + CLK_CTRL);
+ writel(0x1F1, pinfo->mipi.ctl_base + CTRL);
+ }
+
+ writel(0x1115501, pinfo->mipi.ctl_base + INT_CTRL);
+ if (pinfo->mipi.broadcast)
+ writel(0x1115501, pinfo->mipi.sctl_base + INT_CTRL);
+
+ return NO_ERROR;
+}
+
+#if (DISPLAY_TYPE_MDSS == 0)
+static int dsi_cmd_dma_trigger_for_panel()
+{
+ unsigned long ReadValue;
+ unsigned long count = 0;
+ int status = 0;
+
+ writel(0x03030303, DSI_INT_CTRL);
+ writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
+ dsb();
+ ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
+ while (ReadValue != 0x00000001) {
+ ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
+ count++;
+ if (count > 0xffff) {
+ status = FAIL;
+ dprintf(CRITICAL,
+ "Panel CMD: command mode dma test failed\n");
+ return status;
+ }
+ }
+
+ writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
+ dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
+ return status;
+}
+
int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
{
int ret = 0;
@@ -311,6 +826,7 @@
goto mipi_cmds_error;
memcpy((void *)off, (cm->payload), cm->size);
+ arch_clean_invalidate_cache_range((addr_t)(off), size);
writel(off, DSI_DMA_CMD_OFFSET);
writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
dsb();
@@ -382,146 +898,7 @@
return len;
}
-static int mipi_dsi_cmd_bta_sw_trigger(void)
-{
- uint32_t data;
- int cnt = 0;
- int err = 0;
-
- writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */
- while (cnt < 10000) {
- data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS */
- if ((data & 0x0010) == 0)
- break;
- cnt++;
- }
- if (cnt == 10000)
- err = 1;
- return err;
-}
-
-int mdss_dsi_host_init(struct mipi_dsi_panel_config *pinfo, uint32_t
- dual_dsi, uint32_t broadcast)
-{
- uint8_t DMA_STREAM1 = 0; // for mdp display processor path
- uint8_t EMBED_MODE1 = 1; // from frame buffer
- uint8_t POWER_MODE2 = 1; // from frame buffer
- uint8_t PACK_TYPE1; // long packet
- uint8_t VC1 = 0;
- uint8_t DT1 = 0; // non embedded mode
- uint8_t WC1 = 0; // for non embedded mode only
- uint8_t DLNx_EN;
- uint8_t lane_swap = 0;
- uint32_t timing_ctl = 0;
- uint32_t lane_swap_dsi1 = 0;
- uint32_t ctrl_mode = 0x105; //Default is command mode to send cmds.
-
-#if (DISPLAY_TYPE_MDSS == 1)
- switch (pinfo->num_of_lanes) {
- default:
- case 1:
- DLNx_EN = 1; // 1 lane
- break;
- case 2:
- DLNx_EN = 3; // 2 lane
- break;
- case 3:
- DLNx_EN = 7; // 3 lane
- break;
- case 4:
- DLNx_EN = 0x0F; /* 4 lanes */
- break;
- }
-
- PACK_TYPE1 = pinfo->pack;
- lane_swap = pinfo->lane_swap;
- timing_ctl = ((pinfo->t_clk_post << 8) | pinfo->t_clk_pre);
-
- if (pinfo->cmds_post_tg) {
- /*
- * Need to send pixel data before sending the ON commands
- * so need to configure controller to VIDEO MODE.
- */
- ctrl_mode = 0x103;
- }
-
- if (dual_dsi) {
- writel(0x0001, MIPI_DSI1_BASE + SOFT_RESET);
- writel(0x0000, MIPI_DSI1_BASE + SOFT_RESET);
-
- writel((0 << 16) | 0x3f, MIPI_DSI1_BASE + CLK_CTRL); /* Turn on all DSI Clks */
- writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI1_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw
- // trigger 0x4; dma stream1
-
- writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, MIPI_DSI1_BASE + CTRL); // reg 0x00 for this
- // build
- writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26
- | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
- MIPI_DSI1_BASE + COMMAND_MODE_DMA_CTRL);
-
- if (readl(MIPI_DSI_BASE) == DSI_HW_REV_103_1) /*for 8939 hw dsi1 has Lane_map as 3210*/
- lane_swap_dsi1 = 0x7;
- else
- lane_swap_dsi1 = lane_swap;
- writel(lane_swap_dsi1, MIPI_DSI1_BASE + LANE_SWAP_CTL);
- writel(timing_ctl, MIPI_DSI1_BASE + TIMING_CTL);
- }
-
- writel(0x0001, MIPI_DSI0_BASE + SOFT_RESET);
- writel(0x0000, MIPI_DSI0_BASE + SOFT_RESET);
-
- writel((0 << 16) | 0x3f, MIPI_DSI0_BASE + CLK_CTRL); /* Turn on all DSI Clks */
- writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI0_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw
- // trigger 0x4; dma stream1
-
- writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, MIPI_DSI0_BASE + CTRL); // reg 0x00 for this
- // build
- writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26
- | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
- MIPI_DSI0_BASE + COMMAND_MODE_DMA_CTRL);
-
- writel(lane_swap, MIPI_DSI0_BASE + LANE_SWAP_CTL);
- writel(timing_ctl, MIPI_DSI0_BASE + TIMING_CTL);
-#endif
-
- return 0;
-}
-
-int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t
- broadcast)
-{
- int status = 0;
- uint32_t ctrl_mode = 0;
-
-#if (DISPLAY_TYPE_MDSS == 1)
- if (pinfo->panel_on_cmds) {
-
- ctrl_mode = readl(MIPI_DSI0_BASE + CTRL);
- if (broadcast) {
- /* Enable command mode before sending the commands. */
- writel(ctrl_mode | 0x04, MIPI_DSI0_BASE + CTRL);
- writel(ctrl_mode | 0x04, MIPI_DSI1_BASE + CTRL);
- status = mdss_dual_dsi_cmds_tx(pinfo->panel_on_cmds,
- pinfo->num_of_panel_on_cmds);
- writel(ctrl_mode, MIPI_DSI0_BASE + CTRL);
- writel(ctrl_mode, MIPI_DSI1_BASE + CTRL);
-
- } else {
- /* Enable command mode before sending the commands. */
- writel(ctrl_mode | 0x04, MIPI_DSI0_BASE + CTRL);
- status = mipi_dsi_cmds_tx(pinfo->panel_on_cmds,
- pinfo->num_of_panel_on_cmds);
- writel(ctrl_mode, MIPI_DSI0_BASE + CTRL);
- if (!status && target_panel_auto_detect_enabled())
- status =
- mdss_dsi_read_panel_signature(pinfo->signature);
- }
- }
-#endif
- return status;
-}
-
-int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo)
+static int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo)
{
uint8_t DMA_STREAM1 = 0; // for mdp display processor path
uint8_t EMBED_MODE1 = 1; // from frame buffer
@@ -570,9 +947,11 @@
return status;
}
+#endif
void mipi_dsi_shutdown(void)
{
+#if (DISPLAY_TYPE_MDSS == 0)
if(!target_cont_splash_screen())
{
mdp_shutdown();
@@ -591,11 +970,21 @@
writel(0x01010101, DSI_INT_CTRL);
writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
}
+#endif
+}
+
+int mipi_cmd_trigger()
+{
+#if (DISPLAY_TYPE_MDSS == 0)
+ writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
+#endif
+ return NO_ERROR;
}
int mipi_config(struct msm_fb_panel_data *panel)
{
int ret = NO_ERROR;
+#if (DISPLAY_TYPE_MDSS == 0)
struct msm_panel_info *pinfo;
struct mipi_dsi_panel_config mipi_pinfo;
@@ -623,302 +1012,6 @@
if (pinfo->rotate && panel->rotate)
pinfo->rotate();
-
- return ret;
-}
-
-int mdss_dsi_video_mode_config(uint16_t disp_width,
- uint16_t disp_height,
- uint16_t img_width,
- uint16_t img_height,
- uint16_t hsync_porch0_fp,
- uint16_t hsync_porch0_bp,
- uint16_t vsync_porch0_fp,
- uint16_t vsync_porch0_bp,
- uint16_t hsync_width,
- uint16_t vsync_width,
- uint16_t dst_format,
- uint16_t traffic_mode,
- uint8_t lane_en,
- uint16_t low_pwr_stop_mode,
- uint8_t eof_bllp_pwr,
- uint8_t interleav,
- uint32_t ctl_base)
-{
- int status = 0;
-
-#if (DISPLAY_TYPE_MDSS == 1)
- /* disable mdp first */
- mdp_disable();
-
- writel(0x00000000, ctl_base + CLK_CTRL);
- writel(0x00000002, ctl_base + CLK_CTRL);
- writel(0x00000006, ctl_base + CLK_CTRL);
- writel(0x0000000e, ctl_base + CLK_CTRL);
- writel(0x0000001e, ctl_base + CLK_CTRL);
- writel(0x0000023f, ctl_base + CLK_CTRL);
-
- writel(0, ctl_base + CTRL);
-
- writel(0x13ff3fe0, ctl_base + ERR_INT_MASK0);
-
- writel(0x02020202, ctl_base + INT_CTRL);
-
- /* For 8916/8939, enable DSI timing double buffering */
- if (readl(ctl_base) >= DSI_HW_REV_103 &&
- mdp_get_revision() != MDP_REV_305)
- writel(0x1, ctl_base + TIMING_DB_MODE);
-
- writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
- ctl_base + VIDEO_MODE_ACTIVE_H);
-
- writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
- ctl_base + VIDEO_MODE_ACTIVE_V);
-
- if (mdp_get_revision() >= MDP_REV_41 ||
- mdp_get_revision() == MDP_REV_304 ||
- mdp_get_revision() == MDP_REV_305) {
- writel(((disp_height + vsync_porch0_fp
- + vsync_porch0_bp - 1) << 16)
- | (disp_width + hsync_porch0_fp
- + hsync_porch0_bp - 1),
- ctl_base + VIDEO_MODE_TOTAL);
- } else {
- writel(((disp_height + vsync_porch0_fp
- + vsync_porch0_bp) << 16)
- | (disp_width + hsync_porch0_fp
- + hsync_porch0_bp),
- ctl_base + VIDEO_MODE_TOTAL);
- }
-
- writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC);
-
- writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC);
-
- writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS);
-
- /* For 8916/8939, flush the DSI timing registers */
- if (readl(ctl_base) >= DSI_HW_REV_103 &&
- mdp_get_revision() != MDP_REV_305)
- writel(0x1, ctl_base + TIMING_FLUSH);
-
- writel(0x0, ctl_base + EOT_PACKET_CTRL);
-
- writel(0x00000100, ctl_base + MISR_VIDEO_CTRL);
-
- if (mdp_get_revision() >= MDP_REV_41 || mdp_get_revision() == MDP_REV_305) {
- writel(low_pwr_stop_mode << 16 |
- eof_bllp_pwr << 12 | traffic_mode << 8
- | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL);
- } else {
- writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
- eof_bllp_pwr << 12 | traffic_mode << 8
- | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL);
- }
-
- writel(0x3fd08, ctl_base + HS_TIMER_CTRL);
- writel(0x00010100, ctl_base + MISR_VIDEO_CTRL);
-
- writel(0x00010100, ctl_base + INT_CTRL);
- writel(0x02010202, ctl_base + INT_CTRL);
- writel(0x02030303, ctl_base + INT_CTRL);
-
- writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
- | 0x103, ctl_base + CTRL);
#endif
-
- return status;
-}
-
-int mdss_dsi_config(struct msm_fb_panel_data *panel)
-{
- int ret = NO_ERROR;
- struct msm_panel_info *pinfo;
- struct mipi_dsi_panel_config mipi_pinfo;
-
-#if (DISPLAY_TYPE_MDSS == 1)
- if (!panel)
- return ERR_INVALID_ARGS;
-
- pinfo = &(panel->panel_info);
- mipi_pinfo.mode = pinfo->mipi.mode;
- mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes;
- mipi_pinfo.mdss_dsi_phy_config = pinfo->mipi.mdss_dsi_phy_db;
- mipi_pinfo.panel_on_cmds = pinfo->mipi.panel_on_cmds;
- mipi_pinfo.num_of_panel_on_cmds = pinfo->mipi.num_of_panel_on_cmds;
- mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
- mipi_pinfo.pack = 0;
- mipi_pinfo.t_clk_pre = pinfo->mipi.t_clk_pre;
- mipi_pinfo.t_clk_post = pinfo->mipi.t_clk_post;
- mipi_pinfo.signature = pinfo->mipi.signature;
- mipi_pinfo.cmds_post_tg = pinfo->mipi.cmds_post_tg;
-
- mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI0_BASE, DSI0_PHY_BASE);
- if (pinfo->mipi.dual_dsi)
- mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE, DSI1_PHY_BASE);
-
- ret = mdss_dsi_host_init(&mipi_pinfo, pinfo->mipi.dual_dsi,
- pinfo->mipi.broadcast);
- if (ret) {
- dprintf(CRITICAL, "dsi host init error\n");
- goto error;
- }
-
- mdss_dsi_phy_contention_detection(&mipi_pinfo, DSI0_PHY_BASE);
-
- if (panel->pre_init_func) {
- ret = panel->pre_init_func();
- if (ret) {
- dprintf(CRITICAL, "pre_init_func error\n");
- goto error;
- }
- }
-
- if (!mipi_pinfo.cmds_post_tg) {
- ret = mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast);
- if (ret) {
- dprintf(CRITICAL, "dsi panel init error\n");
- goto error;
- }
- }
-
- if (pinfo->rotate && panel->rotate)
- pinfo->rotate();
-#endif
-
-error:
return ret;
}
-
-int mdss_dsi_post_on(struct msm_fb_panel_data *panel)
-{
- int ret = 0;
- struct msm_panel_info *pinfo = &(panel->panel_info);
- struct mipi_dsi_panel_config mipi_pinfo;
-
- if (pinfo->mipi.cmds_post_tg) {
- mipi_pinfo.panel_on_cmds = pinfo->mipi.panel_on_cmds;
- mipi_pinfo.num_of_panel_on_cmds =
- pinfo->mipi.num_of_panel_on_cmds;
- mipi_pinfo.signature = pinfo->mipi.signature;
-
- ret = mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast);
- if (ret) {
- dprintf(CRITICAL, "dsi panel init error\n");
- }
- }
- return ret;
-}
-
-int mdss_dsi_cmd_mode_config(uint16_t disp_width,
- uint16_t disp_height,
- uint16_t img_width,
- uint16_t img_height,
- uint16_t dst_format,
- uint8_t ystride,
- uint8_t lane_en,
- uint8_t interleav,
- uint32_t ctl_base)
-{
- uint16_t dst_fmt = 0;
-
- switch (dst_format) {
- case DSI_VIDEO_DST_FORMAT_RGB565:
- dst_fmt = DSI_CMD_DST_FORMAT_RGB565;
- break;
- case DSI_VIDEO_DST_FORMAT_RGB666:
- case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE:
- dst_fmt = DSI_CMD_DST_FORMAT_RGB666;
- break;
- case DSI_VIDEO_DST_FORMAT_RGB888:
- dst_fmt = DSI_CMD_DST_FORMAT_RGB888;
- break;
- default:
- dprintf(CRITICAL, "unsupported dst format\n");
- return ERROR;
- }
-
-#if (DISPLAY_TYPE_MDSS == 1)
- writel(0x00000000, ctl_base + CLK_CTRL);
- writel(0x00000000, ctl_base + CLK_CTRL);
- writel(0x00000000, ctl_base + CLK_CTRL);
- writel(0x00000000, ctl_base + CLK_CTRL);
- writel(0x00000002, ctl_base + CLK_CTRL);
- writel(0x00000006, ctl_base + CLK_CTRL);
- writel(0x0000000e, ctl_base + CLK_CTRL);
- writel(0x0000001e, ctl_base + CLK_CTRL);
- writel(0x0000023f, ctl_base + CLK_CTRL);
-
- writel(0, ctl_base + CTRL);
-
- writel(0x13ff3fe0, ctl_base + ERR_INT_MASK0);
-
- writel(0x02020202, ctl_base + INT_CTRL);
-
- writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL);
- writel((img_width * ystride + 1) << 16 | 0x0039,
- ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL);
- writel((img_width * ystride + 1) << 16 | 0x0039,
- ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL);
- writel(img_height << 16 | img_width,
- ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL);
- writel(img_height << 16 | img_width,
- ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL);
- writel(0x13c2c, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL);
- writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105,
- ctl_base + CTRL);
- writel(0x14000000, ctl_base + COMMAND_MODE_DMA_CTRL);
- writel(0x10000000, ctl_base + MISR_CMD_CTRL);
- writel(0x1, ctl_base + EOT_PACKET_CTRL);
-#endif
- return 0;
-}
-
-int mipi_dsi_on()
-{
- int ret = NO_ERROR;
- unsigned long ReadValue;
- unsigned long count = 0;
-
- ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
-
- mdelay(10);
-
- while (ReadValue != 0x00010000) {
- ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
- count++;
- if (count > 0xffff) {
- dprintf(CRITICAL, "Video lane test failed\n");
- return ERROR;
- }
- }
-
- dprintf(INFO, "Video lane tested successfully\n");
- return ret;
-}
-
-int mipi_dsi_off(struct msm_panel_info *pinfo)
-{
- if(!target_cont_splash_screen())
- {
- writel(0, DSI_CLK_CTRL);
- writel(0x1F1, DSI_CTRL);
- mdelay(10);
- writel(0x0001, DSI_SOFT_RESET);
- writel(0x0000, DSI_SOFT_RESET);
- writel(0, DSI_CTRL);
- }
-
- writel(0x1115501, MIPI_DSI0_BASE + INT_CTRL);
- if (pinfo->mipi.broadcast)
- writel(0x1115501, MIPI_DSI1_BASE + INT_CTRL);
-
- return NO_ERROR;
-}
-
-int mipi_cmd_trigger()
-{
- writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
-
- return NO_ERROR;
-}
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index b5d386f..69bd7a1 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -32,6 +32,7 @@
#include <smem.h>
#include <mipi_dsi.h>
#include <platform/iomap.h>
+#include <platform/timer.h>
#define LPFR_LUT_SIZE 10
@@ -39,7 +40,7 @@
#define FRAC_DIVIDER 10000
-typedef struct lpfr_cfg {
+struct lpfr_cfg {
uint32_t vco_rate;
uint8_t resistance;
};
@@ -89,7 +90,6 @@
uint32_t ref_clk_to_pll = 0, frac_n_value = 0;
uint32_t sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
uint32_t gen_vco_clk, cal_cfg10, cal_cfg11;
- uint32_t res;
uint8_t i, rc = NO_ERROR;
/* Configure the Loop filter resistance */
@@ -189,4 +189,5 @@
writel(cal_cfg10, pll_base + 0x0094); /* CAL CFG10 */
writel(cal_cfg11, pll_base + 0x0098); /* CAL CFG11 */
writel(0x20, pll_base + 0x009c); /* EFUSE CFG */
+ return rc;
}
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
index 0f7052a..da0551e 100644
--- a/platform/msm_shared/mipi_dsi_autopll_20nm.c
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -32,6 +32,8 @@
#include <smem.h>
#include <mipi_dsi.h>
#include <platform/iomap.h>
+#include <qtimer.h>
+#include <arch/defines.h>
#define LPFR_LUT_SIZE 10
@@ -154,29 +156,37 @@
return status;
}
-uint32_t mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_common_block_1(uint32_t pll_base)
{
- writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG1);
- writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG2);
- writel(0x15, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL);
-
- writel(0x20, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL);
- writel(0x07, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL2);
+ writel(0x82, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x2a, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
+ writel(0x2b, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
writel(0x02, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
- writel(0x03, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
}
-static void pll_20nm_phy_kvco_config(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_common_block_2(uint32_t pll_base)
{
-
+ writel(0x40, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IE_TRIM);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IP_TRIM);
+ writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL);
+ writel(0x0e, pll_base + MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL);
+ writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN);
+ writel(0x4a, pll_base + MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND);
writel(0x00, pll_base + MMSS_DSI_PHY_PLL_DIV_REF1);
writel(0x01, pll_base + MMSS_DSI_PHY_PLL_DIV_REF2);
+ writel(0x07, pll_base + MMSS_DSI_PHY_PLL_PLL_CNTRL);
+ writel(0x1f, pll_base + MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL);
writel(0x8a, pll_base + MMSS_DSI_PHY_PLL_KVCO_COUNT1);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CODE);
+ writel(0x10, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG3);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_SSC_EN_CENTER);
+ writel(0x0c, pll_base + MMSS_DSI_PHY_PLL_FAUX_EN);
+ writel(0x0a, pll_base + MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CMN_MODE);
}
-static void pll_20nm_phy_loop_bw_config(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_loop_bw(uint32_t pll_base)
{
writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_IP_SETI);
writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_PLL_CP_SETI);
@@ -185,74 +195,10 @@
writel(0x77, pll_base + MMSS_DSI_PHY_PLL_PLL_CRCTRL);
}
-static void pll_20nm_phy_config(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_vco_rate(uint32_t pll_base, struct mdss_dsi_pll_config *pd)
{
- writel(0x40, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CMN_MODE);
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IE_TRIM);
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IP_TRIM);
- writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL);
- writel(0x0e, pll_base + MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_DC);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CORE_CLK_IN_SYNC_SEL);
- writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN);
- writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL1);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL2);
- writel(0x4b, pll_base + MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND);
- udelay(1000);
- pll_20nm_phy_kvco_config(pll_base);
-
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG1);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG2);
- writel(0x10, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG3);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG4);
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_BGTC);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_TEST_UPDN);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCO_TUNE);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_AMP_OS);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_SSC_EN_CENTER);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_UP);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_DN);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_CAL_CSR);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_EN_VCOCALDONE);
- writel(0x0c, pll_base + MMSS_DSI_PHY_PLL_FAUX_EN);
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN);
-
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL);
- udelay(1000);
-
- pll_20nm_phy_loop_bw_config(pll_base);
-}
-
-static void mdss_dsi_pll_20nm_disable(uint32_t pll_base)
-{
- dprintf(SPEW, "Disabling DSI PHY PLL \n");
- writel(0x042, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
- writel(0x002, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
- writel(0x002, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
- dmb();
-}
-
-int32_t mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
- struct mdss_dsi_pll_config *pd)
-{
uint32_t data;
-
- mdss_dsi_phy_sw_reset(ctl_base);
- pll_20nm_phy_config(pll_base);
-
- /*
- * For 20nm PHY, DSI PLL 1 drains some current in its reset state.
- * Need to turn off the DSI1 PLL explicitly.
- */
- if (ctl_base == MIPI_DSI0_BASE) {
- dprintf(SPEW, "Calling disable function for PHY PLL 1 \n");
- mdss_dsi_pll_20nm_disable(DSI1_PLL_BASE);
- }
-
/* set up divider */
data = readl(pll_base + MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
data |= 0x080; /* bit 7 */
@@ -285,6 +231,23 @@
writel(((pd->lock_comp >> 16) & 0xff),
pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP3);
+ if (pd->en_vco_zero_phase)
+ writel(0x01, pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN);
+ else
+ writel(0x0d, pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN);
+
+ dprintf(SPEW, "div frac1=0x%x, div frac2 = 0x%x, div frac3=0x%x\n",
+ readl(pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START1),
+ readl(pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START2),
+ readl(pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START3));
+ dprintf(SPEW, "dec start1=0x%x, dec start2 = 0x%x\n",
+ readl(pll_base + MMSS_DSI_PHY_PLL_DEC_START1),
+ readl(pll_base + MMSS_DSI_PHY_PLL_DEC_START2));
+ dprintf(SPEW, "plllock cmp1=0x%x,plllock cmp2= 0x%x, plllock cmp3=0x%x\n",
+ readl(pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP1),
+ readl(pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP2),
+ readl(pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP3));
+
/*
* Make sure that PLL vco configuration is complete
* before controlling the state machine.
@@ -292,3 +255,48 @@
udelay(1000);
dmb();
}
+
+static void mdss_dsi_pll_20nm_config_resetsm(uint32_t pll_base)
+{
+ writel(0x24, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL);
+ writel(0x07, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL2);
+}
+
+static void mdss_dsi_pll_20nm_config_vco_start(uint32_t pll_base)
+{
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x02, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+ udelay(10);
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+}
+
+static void mdss_dsi_pll_20nm_config_powerdown(uint32_t pll_base)
+{
+ dprintf(SPEW, "Powerdown DSI PHY PLL \n");
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
+ writel(0x01, pll_base + MMSS_DSI_PHY_PLL_CMN_MODE);
+ writel(0x82, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x02, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
+ dmb();
+}
+
+
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t pll_1_base,
+ struct mdss_dsi_pll_config *pd)
+{
+ /*
+ * For 20nm PHY, DSI PLL 1 drains some current in its reset state.
+ * Need to turn off the DSI1 PLL explicitly.
+ */
+ mdss_dsi_pll_20nm_config_common_block_1(pll_1_base);
+ mdss_dsi_pll_20nm_config_powerdown(pll_1_base);
+
+ mdss_dsi_pll_20nm_config_common_block_1(pll_base);
+ mdss_dsi_pll_20nm_config_common_block_2(pll_base);
+ mdss_dsi_pll_20nm_config_loop_bw(pll_base);
+ mdss_dsi_pll_20nm_config_vco_rate(pll_base, pd);
+ mdss_dsi_pll_20nm_config_resetsm(pll_base);
+ mdss_dsi_pll_20nm_config_vco_start(pll_base);
+
+ udelay(1000);
+}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 9fd69a4..32ed968 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -29,7 +29,10 @@
#include <debug.h>
#include <reg.h>
#include <mipi_dsi.h>
+#include <mdp5.h>
+#include <platform/timer.h>
#include <platform/iomap.h>
+#include <arch/defines.h>
#if (DISPLAY_TYPE_MDSS == 0)
#define MIPI_DSI0_BASE MIPI_DSI_BASE
@@ -45,6 +48,12 @@
#define MMSS_DSI_PHY_STRENGTH_CTRL_1 0x0188
#define MMSS_DSI_PHY_BIST_CTRL_0 0x01b4
#define MMSS_DSI_PHY_GLBL_TEST_CTRL 0x01d4
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_0 0x00
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_1 0x04
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_2 0x08
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_3 0x0c
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_4 0x10
+#define MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG 0x18
#define MMSS_DSI_PHY_LDO_CTRL 0x01dc
#define TOTAL_TIMING_CTRL_CONFIG 12
@@ -53,33 +62,33 @@
#define TOTAL_LANE_COUNT 5
#define CONFIG_REG_FOR_EACH_LANE 9
-static void mipi_dsi_calibration(void)
+static void mipi_dsi_calibration(uint32_t ctl_base)
{
uint32_t i = 0;
uint32_t term_cnt = 5000;
- int32_t cal_busy = readl(MIPI_DSI_BASE + 0x550);
+ int32_t cal_busy = readl(ctl_base + 0x550);
/* DSI1_DSIPHY_REGULATOR_CAL_PWR_CFG */
- writel(0x01, MIPI_DSI_BASE + 0x0518);
+ writel(0x01, ctl_base + 0x0518);
/* DSI1_DSIPHY_CAL_SW_CFG2 */
- writel(0x0, MIPI_DSI_BASE + 0x0534);
+ writel(0x0, ctl_base + 0x0534);
/* DSI1_DSIPHY_CAL_HW_CFG1 */
- writel(0x5a, MIPI_DSI_BASE + 0x053c);
+ writel(0x5a, ctl_base + 0x053c);
/* DSI1_DSIPHY_CAL_HW_CFG3 */
- writel(0x10, MIPI_DSI_BASE + 0x0544);
+ writel(0x10, ctl_base + 0x0544);
/* DSI1_DSIPHY_CAL_HW_CFG4 */
- writel(0x01, MIPI_DSI_BASE + 0x0548);
+ writel(0x01, ctl_base + 0x0548);
/* DSI1_DSIPHY_CAL_HW_CFG0 */
- writel(0x01, MIPI_DSI_BASE + 0x0538);
+ writel(0x01, ctl_base + 0x0538);
/* DSI1_DSIPHY_CAL_HW_TRIGGER */
- writel(0x01, MIPI_DSI_BASE + 0x0528);
+ writel(0x01, ctl_base + 0x0528);
/* DSI1_DSIPHY_CAL_HW_TRIGGER */
- writel(0x00, MIPI_DSI_BASE + 0x0528);
+ writel(0x00, ctl_base + 0x0528);
- cal_busy = readl(MIPI_DSI_BASE + 0x550);
+ cal_busy = readl(ctl_base + 0x550);
while (cal_busy & 0x10) {
i++;
if (i > term_cnt) {
@@ -87,10 +96,11 @@
"exceeded polling TIMEOUT!\n");
break;
}
- cal_busy = readl(MIPI_DSI_BASE + 0x550);
+ cal_busy = readl(ctl_base + 0x550);
}
}
+#if (DISPLAY_TYPE_MDSS == 0)
int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo)
{
struct mipi_dsi_phy_ctrl *pd;
@@ -176,7 +186,7 @@
writel(pd->regulator[i], MIPI_DSI_BASE + off);
off += 4;
}
- mipi_dsi_calibration();
+ mipi_dsi_calibration(MIPI_DSI_BASE);
off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
for (i = 1; i < 20; i++) {
@@ -202,6 +212,7 @@
}
return 0;
}
+#endif
void mdss_dsi_phy_sw_reset(uint32_t ctl_base)
{
@@ -214,10 +225,36 @@
udelay(100);
}
-int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, uint32_t phy_base)
+static void mdss_dsi_20nm_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd,
+ uint32_t phy_base, uint32_t reg_base)
{
/* DSI0 and DSI1 have a common regulator */
+ if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) {
+ /* LDO ctrl */
+ writel(0x1d, phy_base + MMSS_DSI_PHY_LDO_CTRL);
+ } else {
+ /* Regulator ctrl 1 */
+ writel(pd->regulator[1], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_1);
+ /* Regulator ctrl 2 */
+ writel(pd->regulator[2], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_2);
+ /* Regulator ctrl 3 */
+ writel(pd->regulator[3], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_3);
+ /* Regulator ctrl 4 */
+ writel(pd->regulator[4], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_4);
+ /* Regulator ctrl - CAL_PWR_CFG */
+ writel(pd->regulator[6], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG);
+ /* LDO ctrl */
+ writel(0x00, phy_base + MMSS_DSI_PHY_LDO_CTRL);
+ /* Regulator ctrl 0 */
+ writel(pd->regulator[0], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_0);
+ dmb();
+ }
+}
+static void mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd,
+ uint32_t phy_base)
+{
+ /* DSI0 and DSI1 have a common regulator */
uint32_t off = 0x0280; /* phy regulator ctrl settings */
if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) {
@@ -268,12 +305,12 @@
}
}
-int mdss_dsi_v2_phy_init(struct mipi_dsi_panel_config *pinfo, uint32_t ctl_base)
+int mdss_dsi_v2_phy_init(struct mipi_panel_info *mipi, uint32_t ctl_base)
{
struct mdss_dsi_phy_ctrl *pd;
uint32_t i, ln, off = 0, offset;
- pd = pinfo->mdss_dsi_phy_config;
+ pd = mipi->mdss_dsi_phy_db;
/* DSI PHY configuration */
off = 0x480;
writel(pd->strength[0], ctl_base + off + (4 * 0));
@@ -289,7 +326,7 @@
for (i = 0; i < 5; i++)
writel(pd->regulator[i], ctl_base + off + (4 * i));
- mipi_dsi_calibration();
+ mipi_dsi_calibration(ctl_base);
/* 4 lanes + clk lane configuration */
/* lane config n * (0 - 4) & DataPath setup */
@@ -307,12 +344,12 @@
for (i = 0; i < 12; i++)
writel(pd->timing[i], ctl_base + off + (4 * i));
- if (1 == pinfo->num_of_lanes)
+ if (1 == mipi->num_of_lanes)
writel(0x8, ctl_base + 0x200 + (4 * 11));
- if (pinfo->lane_swap)
- writel(pinfo->lane_swap, ctl_base + 0x0ac);
+ if (mipi->lane_swap)
+ writel(mipi->lane_swap, ctl_base + 0x0ac);
/* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing
length should > data lane HS timing length */
@@ -320,16 +357,16 @@
return 0;
}
-static int mdss_dsi_phy_28nm_init(struct mipi_dsi_panel_config *pinfo,
+static int mdss_dsi_phy_28nm_init(struct mipi_panel_info *mipi,
uint32_t ctl_base, uint32_t phy_base)
{
struct mdss_dsi_phy_ctrl *pd;
uint32_t i, off = 0, ln, offset;
if (mdp_get_revision() == MDP_REV_304)
- return mdss_dsi_v2_phy_init(pinfo, ctl_base);
+ return mdss_dsi_v2_phy_init(mipi, ctl_base);
- pd = (pinfo->mdss_dsi_phy_config);
+ pd = (mipi->mdss_dsi_phy_db);
/* Strength ctrl 0 */
writel(pd->strength[0], phy_base + 0x0184);
@@ -366,7 +403,7 @@
/* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */
if (phy_base == DSI0_PHY_BASE ||
- (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1))
+ (readl(mipi->ctl_base) == DSI_HW_REV_103_1))
writel(0x01, phy_base + 0x01d4);
else
writel(0x00, phy_base + 0x01d4);
@@ -383,11 +420,12 @@
/* DSI_0_CLKOUT_TIMING_CTRL */
writel(0x41b, ctl_base + 0x0c4);
dmb();
+ return 0;
}
void mdss_dsi_phy_contention_detection(
- struct mipi_dsi_panel_config *pinfo,
+ struct mipi_panel_info *mipi,
uint32_t phy_base)
{
struct mdss_dsi_phy_ctrl *pd;
@@ -395,48 +433,23 @@
if (mdp_get_revision() == MDP_REV_304)
return;
- pd = (pinfo->mdss_dsi_phy_config);
- writel(pd->strength[1], phy_base + 0x0188);
+ pd = (mipi->mdss_dsi_phy_db);
+ writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
dmb();
}
-static int mdss_dsi_phy_20nm_init(struct mipi_dsi_panel_config *pinfo,
- uint32_t ctl_base, uint32_t phy_base)
+static int mdss_dsi_phy_20nm_init(struct mipi_panel_info *mipi,
+ uint32_t ctl_base, uint32_t phy_base, uint32_t reg_base)
{
- struct mdss_dsi_phy_ctrl *pd = pinfo->mdss_dsi_phy_config;
+ struct mdss_dsi_phy_ctrl *pd = mipi->mdss_dsi_phy_db;
uint32_t i, off = 0, ln, offset;
+ mdss_dsi_20nm_phy_regulator_init(pd, phy_base, reg_base);
+
/* Strength ctrl 0 */
writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0);
- mdss_dsi_phy_regulator_init(pd, phy_base);
-
- off = MMSS_DSI_PHY_TIMING_CTRL_0;
- for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) {
- writel(pd->timing[i], phy_base + off);
- dmb();
- }
-
- /* Currently the Phy settings for the DSI 0 is done in clk prepare*/
- if (phy_base == DSI1_PHY_BASE) {
- writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1);
- writel(0x05, phy_base + MMSS_DSI_PHY_CTRL_0);
- dmb();
-
- writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0);
- dmb();
-
- /* BITCLK_HS_SEL should be set to 0 for left */
- writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL);
-
- writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_2);
- writel(0x02, phy_base + MMSS_DSI_PHY_CTRL_2);
- writel(0x03, phy_base + MMSS_DSI_PHY_CTRL_2);
- dmb();
- }
-
- writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
- dmb();
+ writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL);
for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) {
off = (ln * 0x40);
@@ -447,27 +460,36 @@
}
}
- dmb();
-
- off = MMSS_DSI_PHY_BIST_CTRL_0;
- for (i = 0; i < TOTAL_BIST_CTRL_CONFIG; i++, off +=4) {
- writel(pd->bistCtrl[i], phy_base + off);
+ off = MMSS_DSI_PHY_TIMING_CTRL_0;
+ for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) {
+ writel(pd->timing[i], phy_base + off);
+ dmb();
}
- dmb();
- writel(0x41b, ctl_base + MMSS_DSI_CLKOUT_TIMING_CTRL);
+ writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1);
dmb();
+ writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0);
+ dmb();
+ return 0;
}
-int mdss_dsi_phy_init (struct mipi_dsi_panel_config *pinfo,
- uint32_t ctl_base, uint32_t phy_base)
+int mdss_dsi_phy_init(struct mipi_panel_info *mipi)
{
int ret;
- if (pinfo->mdss_dsi_phy_config->is_pll_20nm)
- ret = mdss_dsi_phy_20nm_init(pinfo, ctl_base, phy_base);
- else
- ret = mdss_dsi_phy_28nm_init(pinfo, ctl_base, phy_base);
+ if (mipi->mdss_dsi_phy_db->is_pll_20nm) {
+ ret = mdss_dsi_phy_20nm_init(mipi, mipi->ctl_base,
+ mipi->phy_base, mipi->reg_base);
+ if (mipi->dual_dsi)
+ ret = mdss_dsi_phy_20nm_init(mipi, mipi->sctl_base,
+ mipi->sphy_base, mipi->reg_base);
+ } else {
+ ret = mdss_dsi_phy_28nm_init(mipi,
+ mipi->ctl_base, mipi->phy_base);
+ if (mipi->dual_dsi)
+ ret = mdss_dsi_phy_28nm_init(mipi, mipi->sctl_base,
+ mipi->sphy_base);
+ }
return ret;
}
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index fd77583..350c40a 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -3146,13 +3146,6 @@
/* Wait for the MMC_BOOT_MCI_CLK write to go through. */
mmc_mclk_reg_wr_delay();
-
- /* Enable power save */
- reg |= MMC_BOOT_MCI_CLK_PWRSAVE;
- writel(reg, MMC_BOOT_MCI_CLK);
-
- /* Wait for the MMC_BOOT_MCI_CLK write to go through. */
- mmc_mclk_reg_wr_delay();
}
#if MMC_BOOT_BAM
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index 76145eb..2632961 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -36,6 +36,7 @@
#include <partition_parser.h>
#include <platform/iomap.h>
#include <platform/timer.h>
+#include <platform.h>
extern void clock_init_mmc(uint32_t);
extern void clock_config_mmc(uint32_t, uint32_t);
@@ -1082,6 +1083,7 @@
host->base = cfg->sdhc_base;
host->sdhc_event = &sdhc_event;
+ host->caps.hs200_support = cfg->hs200_support;
host->caps.hs400_support = cfg->hs400_support;
data = (struct sdhci_msm_data *) malloc(sizeof(struct sdhci_msm_data));
@@ -1135,7 +1137,6 @@
static uint32_t mmc_identify_card(struct sdhci_host *host, struct mmc_card *card)
{
uint32_t mmc_return = 0;
- uint32_t raw_csd[4];
/* Ask card to send its unique card identification (CID) number (CMD2) */
mmc_return = mmc_all_send_cid(host, card);
@@ -1227,7 +1228,6 @@
uint32_t mmc_sd_card_init(struct sdhci_host *host, struct mmc_card *card)
{
uint8_t i;
- uint32_t mmc_ret;
struct mmc_command cmd;
memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
@@ -1472,7 +1472,6 @@
static uint32_t mmc_card_init(struct mmc_device *dev)
{
uint32_t mmc_return = 0;
- uint32_t status;
uint8_t bus_width = 0;
struct sdhci_host *host;
@@ -1601,7 +1600,11 @@
return mmc_return;
}
}
+#if USE_TARGET_HS200_CAPS
+ else if (host->caps.hs200_support && host->caps.sdr104_support && mmc_card_supports_hs200_mode(card))
+#else
else if (host->caps.sdr104_support && mmc_card_supports_hs200_mode(card))
+#endif
{
dprintf(INFO, "SDHC Running in HS200 mode\n");
mmc_return = mmc_set_hs200_mode(host, card, bus_width);
@@ -2103,7 +2106,6 @@
uint32_t blk_end;
uint32_t num_erase_grps;
uint64_t erase_timeout = 0;
- uint32_t *out;
struct mmc_card *card;
@@ -2171,9 +2173,9 @@
/*
* As per emmc 4.5 spec section 7.4.27, calculate the erase timeout
- * erase_timeout = 300 * ERASE_TIMEOUT_MULT * num_erase_grps
+ * erase_timeout = 300ms * ERASE_TIMEOUT_MULT * num_erase_grps
*/
- erase_timeout = (300 * card->ext_csd[MMC_ERASE_TIMEOUT_MULT] * num_erase_grps);
+ erase_timeout = (300 * 1000 * card->ext_csd[MMC_ERASE_TIMEOUT_MULT] * num_erase_grps);
/* Send CMD38 to perform erase */
if (mmc_send_erase(dev, erase_timeout))
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index 0a7d5b4..bcec0ad 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -35,6 +35,7 @@
#include <target.h>
#include <string.h>
#include <partition_parser.h>
+#include <boot_device.h>
#include <dme.h>
/*
* Weak function for UFS.
@@ -134,7 +135,7 @@
val = mmc_sdhci_write((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (write_size / block_size));
if (val)
{
- dprintf(CRITICAL, "Failed Writing block @ %x\n", (data_addr / block_size));
+ dprintf(CRITICAL, "Failed Writing block @ %x\n",(unsigned int)(data_addr / block_size));
return val;
}
sptr += write_size;
@@ -146,7 +147,7 @@
val = mmc_sdhci_write((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (data_len / block_size));
if (val)
- dprintf(CRITICAL, "Failed Writing block @ %x\n", (data_addr / block_size));
+ dprintf(CRITICAL, "Failed Writing block @ %x\n",(unsigned int)(data_addr / block_size));
}
else
{
@@ -196,7 +197,7 @@
ret = mmc_sdhci_read((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (read_size / block_size));
if (ret)
{
- dprintf(CRITICAL, "Failed Reading block @ %x\n", (data_addr / block_size));
+ dprintf(CRITICAL, "Failed Reading block @ %x\n",(unsigned int) (data_addr / block_size));
return ret;
}
sptr += read_size;
@@ -208,7 +209,7 @@
ret = mmc_sdhci_read((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (data_len / block_size));
if (ret)
- dprintf(CRITICAL, "Failed Reading block @ %x\n", (data_addr / block_size));
+ dprintf(CRITICAL, "Failed Reading block @ %x\n",(unsigned int) (data_addr / block_size));
}
else
{
@@ -289,7 +290,7 @@
}
else
{
- dprintf(CRITICAL, "Erase Fail: Erase size: %u is bigger than scratch region:%u\n", scratch_size);
+ dprintf(CRITICAL, "Erase Fail: Erase size: %u is bigger than scratch region\n", scratch_size);
return 1;
}
@@ -372,7 +373,7 @@
unaligned_blks = blk_count % erase_unit_sz;
blks_to_erase = blk_count - unaligned_blks;
- dprintf(SPEW, "Performing SDHCI erase: 0x%x:0x%x\n", blk_addr, blks_to_erase);
+ dprintf(SPEW, "Performing SDHCI erase: 0x%x:0x%x\n", blk_addr,(unsigned int)blks_to_erase);
if (mmc_sdhci_erase((struct mmc_device *)dev, blk_addr, blks_to_erase * block_size))
{
dprintf(CRITICAL, "MMC erase failed\n");
diff --git a/platform/msm_shared/partial_goods.c b/platform/msm_shared/partial_goods.c
new file mode 100644
index 0000000..d2c3ab6
--- /dev/null
+++ b/platform/msm_shared/partial_goods.c
@@ -0,0 +1,150 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <platform/partial_goods.h>
+#include <libfdt.h>
+#include <reg.h>
+#include <debug.h>
+
+void update_partial_goods_dtb_nodes(void *fdt)
+{
+ int i;
+ int tbl_sz = sizeof(table) / sizeof(struct partial_goods);
+ int parent_offset = 0;
+ int subnode_offset = 0;
+ int ret = 0;
+ int prop_len = 0;
+ uint32_t reg = readl(QFPROM_PTE_PART_ADDR);
+ uint32_t prop_type = 0;
+ struct subnode_list *subnode_lst = NULL;
+ const struct fdt_property *prop = NULL;
+ const char *replace_str = NULL;
+
+ /*
+ * The PTE register bits 23 to 27 have the partial goods
+ * info, extract the partial goods value before using
+ */
+ reg = (reg & 0x0f800000) >> 23;
+
+ /* If none of the DTB needs update */
+ if (!reg)
+ return;
+
+ ret = fdt_open_into(fdt, fdt, fdt_totalsize(fdt));
+ if (ret != 0)
+ {
+ dprintf(CRITICAL, "Failed to move/resize dtb buffer: %d\n", ret);
+ ASSERT(0);
+ }
+
+ for (i = 0; i < tbl_sz; i++)
+ {
+ if (reg == table[i].val)
+ {
+ /* Find the Parent node */
+ ret = fdt_path_offset(fdt, table[i].parent_node);
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed to get parent node: %s\terrno:%d\n", table[i].parent_node, ret);
+ ASSERT(0);
+ }
+ parent_offset = ret;
+
+ /* Find the subnode */
+ subnode_lst = table[i].subnode;
+
+ while (subnode_lst->subnode)
+ {
+ ret = fdt_subnode_offset(fdt, parent_offset, subnode_lst->subnode);
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed to get subnode: %s\terrno:%d\n", subnode_lst->subnode, ret);
+ ASSERT(0);
+ }
+ subnode_offset = ret;
+
+ /* Find the property node and its length */
+ prop = fdt_get_property(fdt, subnode_offset, subnode_lst->property, &prop_len);
+ if (!prop)
+ {
+ dprintf(CRITICAL, "Failed to get property: %s\terrno: %d\n", subnode_lst->property, prop_len);
+ ASSERT(0);
+ }
+
+ /*
+ * Replace the property value based on the property
+ * length and type
+ */
+ if (!(strncmp(subnode_lst->property, "device_type", sizeof(subnode_lst->property))))
+ prop_type = DEVICE_TYPE;
+ else if ((!strncmp(subnode_lst->property, "status", sizeof(subnode_lst->property))))
+ prop_type = STATUS_TYPE;
+ else
+ {
+ dprintf(CRITICAL, "%s: Property type is not supported\n", subnode_lst->property);
+ ASSERT(0);
+ }
+
+ switch (prop_type)
+ {
+ case DEVICE_TYPE:
+ replace_str = "nak";
+ break;
+ case STATUS_TYPE:
+ if (prop_len == sizeof("ok"))
+ replace_str = "no";
+ else if (prop_len == sizeof("okay"))
+ replace_str = "dsbl";
+ else
+ {
+ dprintf(CRITICAL, "Property value length: %u is invalid for property: %s\n", prop_len, subnode_lst->property);
+ ASSERT(0);
+ }
+ break;
+ default:
+ /* Control would not come here, as this gets taken care while setting property type */
+ break;
+ };
+
+ /* Replace the property with new value */
+ ret = fdt_setprop_inplace(fdt, subnode_offset, subnode_lst->property, (const void *)replace_str, prop_len);
+ if (!ret)
+ dprintf(INFO, "Updated device tree property: %s @ %s node\n", subnode_lst->property, subnode_lst->subnode);
+ else
+ {
+ dprintf(CRITICAL, "Failed to update property: %s: error no: %d\n", subnode_lst->property, ret);
+ ASSERT(0);
+ }
+
+ subnode_lst++;
+ }
+ }
+ }
+
+ fdt_pack(fdt);
+}
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index d40fb8a..2338060 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -605,12 +605,12 @@
array_size, (long long)(card_size_sec - 34));
/* Updating CRC of the Partition entry array in both headers */
- partition_entry_array_start = primary_gpt_header + block_size;
- crc_value = calculate_crc32(partition_entry_array_start,
+ partition_entry_array_start = (unsigned int)primary_gpt_header + block_size;
+ crc_value = calculate_crc32((unsigned char *)partition_entry_array_start,
max_part_count * part_entry_size);
PUT_LONG(primary_gpt_header + PARTITION_CRC_OFFSET, crc_value);
- crc_value = calculate_crc32(partition_entry_array_start + array_size,
+ crc_value = calculate_crc32((unsigned char *)partition_entry_array_start + array_size,
max_part_count * part_entry_size);
PUT_LONG(secondary_gpt_header + PARTITION_CRC_OFFSET, crc_value);
@@ -715,7 +715,7 @@
}
/* Writing the partition entries array for the primary header */
- partition_entry_array_start = primary_gpt_header + block_size;
+ partition_entry_array_start = (unsigned int)primary_gpt_header + block_size;
ret = write_gpt_partition_array(primary_gpt_header,
partition_entry_array_start,
partition_entry_array_size, block_size);
@@ -726,7 +726,7 @@
}
/*Writing the partition entries array for the backup header */
- partition_entry_array_start = primary_gpt_header + block_size +
+ partition_entry_array_start = (unsigned int)primary_gpt_header + block_size +
partition_entry_array_size;
ret = write_gpt_partition_array(secondary_gpt_header,
partition_entry_array_start,
@@ -872,10 +872,8 @@
return INVALID_PTN;
}
for (n = 0; n < partition_count; n++) {
- if (!memcmp
- (name, &partition_entries[n].name, input_string_length)
- && input_string_length ==
- strlen((const char *)&partition_entries[n].name)) {
+ if ((input_string_length == strlen((const char *)&partition_entries[n].name))
+ && !memcmp(name, &partition_entries[n].name, input_string_length)) {
return n;
}
}
diff --git a/platform/msm_shared/qgic.c b/platform/msm_shared/qgic.c
index 7250c62..a0a822a 100644
--- a/platform/msm_shared/qgic.c
+++ b/platform/msm_shared/qgic.c
@@ -35,8 +35,6 @@
#include <arch/arm.h>
#include <qgic.h>
-static struct ihandler handler[NR_IRQS];
-
static uint8_t qgic_get_cpumask()
{
uint32_t mask=0, i;
diff --git a/platform/msm_shared/qgic_v3.c b/platform/msm_shared/qgic_v3.c
index 1177a23..692801b 100644
--- a/platform/msm_shared/qgic_v3.c
+++ b/platform/msm_shared/qgic_v3.c
@@ -32,6 +32,7 @@
#include <debug.h>
#include <arch/arm.h>
#include <arch/defines.h>
+#include <qtimer.h>
#include <qgic_v3.h>
#define GIC_WAKER_PROCESSORSLEEP BIT(1)
@@ -70,7 +71,6 @@
void qgic_cpu_init()
{
- uint32_t waker = 0;
uint32_t retry = 1000;
uint32_t sre = 0;
uint32_t pmr = 0xff;
diff --git a/platform/msm_shared/qmp_usb30_phy.c b/platform/msm_shared/qmp_usb30_phy.c
index b3b3477..a2c21cf 100644
--- a/platform/msm_shared/qmp_usb30_phy.c
+++ b/platform/msm_shared/qmp_usb30_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -35,6 +35,7 @@
#include <bits.h>
#include <clock.h>
#include <debug.h>
+#include <qtimer.h>
#define HS_PHY_COMMON_CTRL 0xEC
#define USE_CORECLK BIT(14)
@@ -44,13 +45,87 @@
#define QMP_PHY_MAX_TIMEOUT 1000
#define PHYSTATUS BIT(6)
+static bool hsonly_mode;
+
+struct qmp_reg qmp_settings[] =
+{
+ {0xAC, 0x14}, /* QSERDES_COM_SYSCLK_EN_SEL */
+ {0x34, 0x08}, /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
+ {0x174, 0x30}, /* QSERDES_COM_CLK_SELECT */
+ {0x3C, 0x06}, /* QSERDES_COM_SYS_CLK_CTRL */
+ {0xb4, 0x00}, /* QSERDES_COM_RESETSM_CNTRL */
+ {0xb8, 0x08}, /* QSERDES_COM_RESETSM_CNTRL2 */
+ {0x194, 0x06}, /* QSERDES_COM_CMN_CONFIG */
+ {0x19c, 0x01}, /* QSERDES_COM_SVS_MODE_CLK_SEL */
+ {0x178, 0x01}, /* QSERDES_COM_HSCLK_SEL */
+ {0xd0, 0x82}, /* QSERDES_COM_DEC_START_MODE0 */
+ {0xdc, 0x55}, /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
+ {0xe0, 0x55}, /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
+ {0xe4, 0x03}, /* QSERDES_COM_DIV_FRAC_START3_MODE0 */
+ {0x78, 0x0b}, /* QSERDES_COM_CP_CTRL_MODE0 */
+ {0x84, 0x16}, /* QSERDES_COM_PLL_RCTRL_MODE0 */
+ {0x90, 0x28}, /* QSERDES_COM_PLL_CCTRL_MODE0 */
+ {0x108, 0x80}, /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
+ {0x10c, 0x00}, /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
+ {0x124, 0x1c}, /* QSERDES_COM_VCO_TUNE_CTRL */
+ {0x12c, 0x3f}, /* QSERDES_COM_VCO_TUNE1_MODE0 */
+ {0x130, 0x01}, /* QSERDES_COM_VCO_TUNE2_MODE0 */
+ {0x184, 0x0a}, /* QSERDES_COM_CORECLK_DIV */
+ {0x4c, 0x15}, /* QSERDES_COM_LOCK_CMP1_MODE0 */
+ {0x50, 0x34}, /* QSERDES_COM_LOCK_CMP2_MODE0 */
+ {0x54, 0x00}, /* QSERDES_COM_LOCK_CMP3_MODE0 */
+ {0xc8, 0x00}, /* QSERDES_COM_LOCK_CMP_EN */
+ {0x18c, 0x00}, /* QSERDES_COM_CORE_CLK_EN */
+ {0xc4, 0x15}, /*QSERDES_COM_RESCODE_DIV_NUM */
+ {0xcc, 0x00}, /* QSERDES_COM_LOCK_CMP_CFG */
+ {0x128, 0x00}, /* QSERDES_COM_VCO_TUNE_MAP */
+ {0xc, 0x0a}, /* QSERDES_COM_BG_TIMER */
+ {0x10, 0x01}, /* QSERDES_COM_SSC_EN_CENTER */
+ {0x1c, 0x31}, /* QSERDES_COM_SSC_PER1 */
+ {0x20, 0x01}, /* QSERDES_COM_SSC_PER2 */
+ {0x14, 0x00}, /* QSERDES_COM_SSC_ADJ_PER1 */
+ {0x18, 0x00}, /* QSERDES_COM_SSC_ADJ_PER2 */
+ {0x24, 0xde}, /* QSERDES_COM_SSC_STEP_SIZE1 */
+ {0x28, 0x07}, /* QSERDES_COM_SSC_STEP_SIZE2 */
+ {0x440, 0x0b}, /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
+ {0x4d8, 0x03}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
+ {0x4dc, 0x6c}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
+ {0x70, 0xf}, /* QSERDES_COM_BG_TRIM */
+ {0x48, 0xf}, /* QSERDES_COM_PLL_IVCO */
+ {0x4e0, 0xb8}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
+ {0x508, 0x77}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
+ {0x50c, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */
+ {0x514, 0x04}, /* QSERDES_RX_SIGDET_CNTRL */
+ {0x518, 0x1b}, /* QSERDES_RX_SIGDET_LVL */
+ {0x51c, 0x16}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+ {0x268, 0x45}, /* QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN */
+ {0x2ac, 0x12}, /* QSERDES_TX_RCV_DETECT_LVL_2 */
+ {0x6c4, 0x03}, /* USB3_PHY_FLL_CNTRL2 */
+ {0x6c0, 0x02}, /* USB3_PHY_FLL_CNTRL1 */
+ {0x6c8, 0x09}, /* USB3_PHY_FLL_CNT_VAL_L */
+ {0x6cc, 0x42}, /* USB3_PHY_FLL_CNT_VAL_H_TOL */
+ {0x6d0, 0x85}, /* USB3_PHY_FLL_MAN_CODE */
+ {0x294, 0x02}, /* QSERDES_TX_LANE_MODE */
+ {0x680, 0xd1}, /* USB3_PHY_LOCK_DETECT_CONFIG1 */
+ {0x684, 0x1f}, /* USB3_PHY_LOCK_DETECT_CONFIG2 */
+ {0x688, 0x47}, /* USB3_PHY_LOCK_DETECT_CONFIG3 */
+ {0x664, 0x08}, /* USB3_PHY_POWER_STATE_CONFIG2 */
+ {0x600, 0x00}, /* USB3_PHY_SW_RESET */
+ {0x608, 0x03}, /* USB3_PHY_START_CONTROL */
+};
+
__WEAK uint32_t target_override_pll()
{
return 0;
}
+__WEAK uint32_t platform_get_qmp_rev()
+{
+ return 0x10000000;
+}
+
/* USB3.0 QMP phy reset */
-void usb30_qmp_phy_reset(void)
+static void qmp_phy_qmp_reset(void)
{
int ret = 0;
uint32_t val;
@@ -61,9 +136,6 @@
struct clk *phy_com_clk = NULL;
struct clk *phy_clk = NULL;
-#if USB_RESET_FROM_CLK
- clock_reset_usb_phy();
-#else
/* Look if phy com clock is present */
phy_com_clk = clk_get("usb30_phy_com_reset");
if (phy_com_clk)
@@ -134,7 +206,6 @@
ret = clk_reset(usb2b_clk, CLK_RESET_DEASSERT);
if (ret)
dprintf(CRITICAL, "Failed to deassert usb2b_phy_clk\n");
-#endif
/* Override the phy common control values */
val = readl(MSM_USB30_QSCRATCH_BASE + HS_PHY_COMMON_CTRL);
@@ -144,79 +215,115 @@
writel(val, MSM_USB30_QSCRATCH_BASE + HS_PHY_COMMON_CTRL);
}
+/* USB3.0 QMP phy reset */
+void usb30_qmp_phy_reset(void)
+{
+#if USB_RESET_FROM_CLK
+ clock_reset_usb_phy();
+#else
+ qmp_phy_qmp_reset();
+#endif
+}
+
/* USB 3.0 phy init: HPG for QMP phy*/
void usb30_qmp_phy_init()
{
int timeout = QMP_PHY_MAX_TIMEOUT;
+ uint32_t rev_id = 0;
+ uint32_t phy_status = 0;
+ uint32_t qmp_reg_size;
+ uint32_t i;
+
+ rev_id = platform_get_qmp_rev();
/* Sequence as per HPG */
-
writel(0x01, QMP_PHY_BASE + PCIE_USB3_PHY_POWER_DOWN_CONTROL);
- writel(0x08, QMP_PHY_BASE + QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
- if (target_override_pll())
- writel(0xE1, QMP_PHY_BASE + QSERDES_COM_PLL_VCOTAIL_EN);
-
- writel(0x82, QMP_PHY_BASE + QSERDES_COM_DEC_START1);
- writel(0x03, QMP_PHY_BASE + QSERDES_COM_DEC_START2);
- writel(0xD5, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START1);
- writel(0xAA, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START2);
- writel(0x4D, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START3);
- writel(0x01, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP_EN);
- writel(0x2B, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP1);
- writel(0x68, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP2);
- writel(0x7C, QMP_PHY_BASE + QSERDES_COM_PLL_CRCTRL);
- writel(0x02, QMP_PHY_BASE + QSERDES_COM_PLL_CP_SETI);
- writel(0x1F, QMP_PHY_BASE + QSERDES_COM_PLL_IP_SETP);
- writel(0x0F, QMP_PHY_BASE + QSERDES_COM_PLL_CP_SETP);
- writel(0x01, QMP_PHY_BASE + QSERDES_COM_PLL_IP_SETI);
- writel(0x0F, QMP_PHY_BASE + QSERDES_COM_IE_TRIM);
- writel(0x0F, QMP_PHY_BASE + QSERDES_COM_IP_TRIM);
- writel(0x46, QMP_PHY_BASE + QSERDES_COM_PLL_CNTRL);
-
- /* CDR Settings */
- writel(0xDA, QMP_PHY_BASE + QSERDES_RX_CDR_CONTROL1);
- writel(0x42, QMP_PHY_BASE + QSERDES_RX_CDR_CONTROL2);
-
- /* Calibration Settings */
- writel(0x90, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL);
- if (target_override_pll())
- writel(0x07, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL2);
+ if (rev_id >= 0x20000000)
+ {
+ qmp_reg_size = sizeof(qmp_settings) / sizeof(struct qmp_reg);
+ for (i = 0 ; i < qmp_reg_size; i++)
+ writel(qmp_settings[i].val, QMP_PHY_BASE + qmp_settings[i].off);
+ }
else
- writel(0x05, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL2);
+ {
+ writel(0x08, QMP_PHY_BASE + QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
- writel(0x20, QMP_PHY_BASE + QSERDES_COM_RES_CODE_START_SEG1);
- writel(0x77, QMP_PHY_BASE + QSERDES_COM_RES_CODE_CAL_CSR);
- writel(0x15, QMP_PHY_BASE + QSERDES_COM_RES_TRIM_CONTROL);
- writel(0x03, QMP_PHY_BASE + QSERDES_TX_RCV_DETECT_LVL);
- writel(0x02, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2);
- writel(0x6C, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3);
- writel(0xC7, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4);
- writel(0x40, QMP_PHY_BASE + QSERDES_RX_SIGDET_ENABLES);
- writel(0x73, QMP_PHY_BASE + QSERDES_RX_SIGDET_CNTRL);
- writel(0x06, QMP_PHY_BASE + QSERDES_RX_SIGDET_DEGLITCH_CNTRL);
- writel(0x48, QMP_PHY_BASE + PCIE_USB3_PHY_RX_IDLE_DTCT_CNTRL);
- writel(0x01, QMP_PHY_BASE + QSERDES_COM_SSC_EN_CENTER);
- writel(0x02, QMP_PHY_BASE + QSERDES_COM_SSC_ADJ_PER1);
- writel(0x31, QMP_PHY_BASE + QSERDES_COM_SSC_PER1);
- writel(0x01, QMP_PHY_BASE + QSERDES_COM_SSC_PER2);
- writel(0x19, QMP_PHY_BASE + QSERDES_COM_SSC_STEP_SIZE1);
- writel(0x19, QMP_PHY_BASE + QSERDES_COM_SSC_STEP_SIZE2);
- writel(0x08, QMP_PHY_BASE + PCIE_USB3_PHY_POWER_STATE_CONFIG2);
+ if (target_override_pll())
+ writel(0xE1, QMP_PHY_BASE + QSERDES_COM_PLL_VCOTAIL_EN);
- writel(0x00, QMP_PHY_BASE + PCIE_USB3_PHY_SW_RESET);
- writel(0x03, QMP_PHY_BASE + PCIE_USB3_PHY_START);
+ writel(0x82, QMP_PHY_BASE + QSERDES_COM_DEC_START1);
+ writel(0x03, QMP_PHY_BASE + QSERDES_COM_DEC_START2);
+ writel(0xD5, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START1);
+ writel(0xAA, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START2);
+ writel(0x4D, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START3);
+ writel(0x01, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP_EN);
+ writel(0x2B, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP1);
+ writel(0x68, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP2);
+ writel(0x7C, QMP_PHY_BASE + QSERDES_COM_PLL_CRCTRL);
+ writel(0x02, QMP_PHY_BASE + QSERDES_COM_PLL_CP_SETI);
+ writel(0x1F, QMP_PHY_BASE + QSERDES_COM_PLL_IP_SETP);
+ writel(0x0F, QMP_PHY_BASE + QSERDES_COM_PLL_CP_SETP);
+ writel(0x01, QMP_PHY_BASE + QSERDES_COM_PLL_IP_SETI);
+ writel(0x0F, QMP_PHY_BASE + QSERDES_COM_IE_TRIM);
+ writel(0x0F, QMP_PHY_BASE + QSERDES_COM_IP_TRIM);
+ writel(0x46, QMP_PHY_BASE + QSERDES_COM_PLL_CNTRL);
- clock_bumpup_pipe3_clk();
+ /* CDR Settings */
+ writel(0xDA, QMP_PHY_BASE + QSERDES_RX_CDR_CONTROL1);
+ writel(0x42, QMP_PHY_BASE + QSERDES_RX_CDR_CONTROL2);
- while ((readl(QMP_PHY_BASE + PCIE_USB3_PHY_PCS_STATUS) & PHYSTATUS))
+ /* Calibration Settings */
+ writel(0x90, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL);
+ if (target_override_pll())
+ writel(0x07, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL2);
+ else
+ writel(0x05, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL2);
+
+ writel(0x20, QMP_PHY_BASE + QSERDES_COM_RES_CODE_START_SEG1);
+ writel(0x77, QMP_PHY_BASE + QSERDES_COM_RES_CODE_CAL_CSR);
+ writel(0x15, QMP_PHY_BASE + QSERDES_COM_RES_TRIM_CONTROL);
+ writel(0x03, QMP_PHY_BASE + QSERDES_TX_RCV_DETECT_LVL);
+ writel(0x02, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2);
+ writel(0x6C, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3);
+ writel(0xC7, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4);
+ writel(0x40, QMP_PHY_BASE + QSERDES_RX_SIGDET_ENABLES);
+ writel(0x73, QMP_PHY_BASE + QSERDES_RX_SIGDET_CNTRL);
+ writel(0x06, QMP_PHY_BASE + QSERDES_RX_SIGDET_DEGLITCH_CNTRL);
+ writel(0x48, QMP_PHY_BASE + PCIE_USB3_PHY_RX_IDLE_DTCT_CNTRL);
+ writel(0x01, QMP_PHY_BASE + QSERDES_COM_SSC_EN_CENTER);
+ writel(0x02, QMP_PHY_BASE + QSERDES_COM_SSC_ADJ_PER1);
+ writel(0x31, QMP_PHY_BASE + QSERDES_COM_SSC_PER1);
+ writel(0x01, QMP_PHY_BASE + QSERDES_COM_SSC_PER2);
+ writel(0x19, QMP_PHY_BASE + QSERDES_COM_SSC_STEP_SIZE1);
+ writel(0x19, QMP_PHY_BASE + QSERDES_COM_SSC_STEP_SIZE2);
+ writel(0x08, QMP_PHY_BASE + PCIE_USB3_PHY_POWER_STATE_CONFIG2);
+
+ writel(0x00, QMP_PHY_BASE + PCIE_USB3_PHY_SW_RESET);
+ writel(0x03, QMP_PHY_BASE + PCIE_USB3_PHY_START);
+ }
+
+ if (rev_id >= 0x20000000)
+ phy_status = 0x77c;
+ else
+ phy_status = 0x728;
+
+ while ((readl(QMP_PHY_BASE + phy_status) & PHYSTATUS))
{
udelay(1);
timeout--;
if (!timeout)
{
- dprintf(CRITICAL, "QMP phy initialization failed\n");
+ dprintf(CRITICAL, "QMP phy initialization failed, fallback to HighSpeed only mode\n");
+ hsonly_mode = true;
return;
}
}
+
+ clock_bumpup_pipe3_clk();
+}
+
+bool use_hsonly_mode()
+{
+ return hsonly_mode;
}
diff --git a/platform/msm_shared/qpic.c b/platform/msm_shared/qpic.c
index 8c9e47d..1bdc81f 100644
--- a/platform/msm_shared/qpic.c
+++ b/platform/msm_shared/qpic.c
@@ -31,7 +31,9 @@
#include <err.h>
#include <msm_panel.h>
#include <platform/iomap.h>
+#include <platform/timer.h>
#include <reg.h>
+#include <target.h>
#include "qpic.h"
#include "qpic_panel.h"
@@ -44,7 +46,6 @@
/* for debugging */
static uint32_t use_bam = false;
-static uint32_t use_irq = false;
static uint32_t use_vsync;
/* For compilation */
@@ -76,9 +77,9 @@
uint32_t fb_offset, size;
if (use_bam)
- fb_offset = qpic_res->fb_phys + qpic_res->base;
+ fb_offset = qpic_res->fb_phys + (uint32_t) qpic_res->base;
else
- fb_offset = qpic_res->fb_virt + qpic_res->base;
+ fb_offset = (uint32_t) qpic_res->fb_virt + (uint32_t) qpic_res->base;
size = qpic_res->fb_xres * qpic_res->fb_yres * qpic_res->fb_bpp;
@@ -207,7 +208,8 @@
static int qpic_send_pkt_sw(uint32_t cmd, uint32_t len, uint8_t *param)
{
uint32_t bytes_left, space, data, cfg2;
- int i, ret = 0;
+ int ret = 0;
+ uint32_t i;
if (len && !param) {
dprintf(CRITICAL, "Null Pointer!\n");
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index ecb5bbb..ae1cba0 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
- * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -33,6 +33,7 @@
#include <debug.h>
#include <string.h>
#include <malloc.h>
+#include <bits.h>
#include <sys/types.h>
#include <platform.h>
#include <platform/clock.h>
@@ -48,7 +49,8 @@
static uint32_t cfg1_raw;
static uint32_t ecc_bch_cfg;
-struct cmd_element ce_array[100];
+struct cmd_element ce_array[100] __attribute__ ((aligned(16)));
+struct cmd_element ce_read_array[20] __attribute__ ((aligned(16)));
#define QPIC_BAM_DATA_FIFO_SIZE 64
#define QPIC_BAM_CMD_FIFO_SIZE 64
@@ -62,16 +64,19 @@
static uint8_t* rdwr_buf;
static struct flash_id supported_flash[] = {
- /* Flash ID ID Mask Density(MB) Wid Pgsz Blksz oobsz 8-bit ECCf */
- {0x1590AC2C, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 0},
- {0x1590AA2C, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0xE0, 1},
- {0x2690AC2C, 0xFFFFFFFF, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
- {0x1590ACAD, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x80, 0},
- {0x9590DC2C, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0x40, 0},
- {0x1590aa98, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0x80, 1},
+ /* Flash ID Flash ID2 ID Mask ID Mask2 Density(MB) Wid Pgsz Blksz oobsz 8-bit ECCf */
+ {0x1590AC2C, 0x56, 0xFFFFFFFF, 0xFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 0},
+ {0x1590AC2C, 0x57, 0xFFFFFFFF, 0xFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 1},
+ {0x1590AA2C, 0x06, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0xE0, 1},
+ {0x2690AC2C, 0x54, 0xFFFFFFFF, 0x0, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
+ {0x1590ACAD, 0, 0xFFFFFFFF, 0x0, 0x20000000, 0, 2048, 0x00020000, 0x80, 0},
+ {0x9590DC2C, 0x56, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0x40, 0},
+ {0x1590aa98, 0x76, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0x80, 1},
/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
};
+static int qpic_nand_mark_badblock(uint32_t page);
+
static void
qpic_nand_wait_for_cmd_exec(uint32_t num_desc)
{
@@ -97,17 +102,17 @@
static uint32_t
qpic_nand_read_reg(uint32_t reg_addr,
- uint8_t flags,
- struct cmd_element *cmd_list_ptr)
+ uint8_t flags)
{
uint32_t val;
+ struct cmd_element *cmd_list_read_ptr = ce_read_array;
- bam_add_cmd_element(cmd_list_ptr, reg_addr, (uint32_t)PA((addr_t)&val), CE_READ_TYPE);
+ bam_add_cmd_element(cmd_list_read_ptr, reg_addr, (uint32_t)PA((addr_t)&val), CE_READ_TYPE);
/* Enqueue the desc for the above command */
bam_add_one_desc(&bam,
CMD_PIPE_INDEX,
- (unsigned char*)PA((addr_t)cmd_list_ptr),
+ (unsigned char*)PA((addr_t)cmd_list_read_ptr),
BAM_CE_SIZE,
BAM_DESC_CMD_FLAG| BAM_DESC_INT_FLAG | flags);
@@ -165,7 +170,7 @@
/* Check if this is an ECC error on an erased page. */
if (status & NAND_FLASH_OP_ERR)
{
- erase_sts = qpic_nand_read_reg(NAND_ERASED_CW_DETECT_STATUS, 0, ce_array);
+ erase_sts = qpic_nand_read_reg(NAND_ERASED_CW_DETECT_STATUS, 0);
if ((erase_sts & (1 << NAND_ERASED_CW_DETECT_STATUS_PAGE_ALL_ERASED)))
{
/* Mask the OP ERROR. */
@@ -198,8 +203,8 @@
struct cmd_element *cmd_list_ptr_start = ce_array;
int num_desc = 0;
uint32_t status;
- uint32_t id;
- uint32_t flash_cmd = NAND_CMD_FETCH_ID;
+ uint32_t id, id2;
+ uint32_t flash_cmd = NAND_CMD_FETCH_ID | BIT(19); //bit 19 needs to be set to get extended NAND ID
uint32_t exec_cmd = 1;
int nand_ret = NANDC_RESULT_SUCCESS;
@@ -227,7 +232,7 @@
cmd_list_ptr = ce_array;
/* Read the status register */
- status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr);
+ status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0);
/* Check for errors */
nand_ret = qpic_nand_check_status(status);
@@ -238,9 +243,11 @@
}
/* Read the id */
- id = qpic_nand_read_reg(NAND_READ_ID, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr);
+ id = qpic_nand_read_reg(NAND_READ_ID, 0);
+ id2 = qpic_nand_read_reg(NAND_READ_ID2, BAM_DESC_UNLOCK_FLAG);
flash->id = id;
+ flash->id2 = id2;
flash->vendor = id & 0xff;
flash->device = (id >> 8) & 0xff;
flash->dev_cfg = (id >> 24) & 0xFF;
@@ -433,7 +440,7 @@
qpic_nand_wait_for_cmd_exec(num_desc);
/* Read buffer status and check for errors. */
- status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr++);
+ status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0);
if (qpic_nand_check_status(status))
{
@@ -613,8 +620,8 @@
ASSERT(buffer != NULL);
/* Read the vld and dev_cmd1 registers before modifying */
- vld = qpic_nand_read_reg(NAND_DEV_CMD_VLD, 0, ce_array);
- dev_cmd1 = qpic_nand_read_reg(NAND_DEV_CMD1, 0, ce_array);
+ vld = qpic_nand_read_reg(NAND_DEV_CMD_VLD, 0);
+ dev_cmd1 = qpic_nand_read_reg(NAND_DEV_CMD1, 0);
/* Initialize flash cmd */
params.cfg.cmd = NAND_CMD_PAGE_READ;
@@ -724,11 +731,21 @@
return cmd_list_ptr;
}
-/* Reads nand_flash_status and resets nand_flash_status and nand_read_status */
+/* Reads nand_flash_status */
struct cmd_element*
-qpic_nand_add_read_n_reset_status_ce(struct cmd_element *start,
- uint32_t *flash_status_read,
- uint32_t read_status)
+qpic_nand_add_read_ce(struct cmd_element *start, uint32_t *flash_status_read)
+{
+ struct cmd_element *cmd_list_ptr = start;
+
+ bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)flash_status_read), CE_READ_TYPE);
+ cmd_list_ptr++;
+
+ return cmd_list_ptr;
+}
+
+/* Resets nand_flash_status and nand_read_status */
+struct cmd_element*
+qpic_nand_reset_status_ce(struct cmd_element *start, uint32_t read_status)
{
struct cmd_element *cmd_list_ptr = start;
uint32_t flash_status_reset;
@@ -738,8 +755,6 @@
flash_status_reset = NAND_FLASH_STATUS_RESET;
read_status_reset = NAND_READ_STATUS_RESET;
- bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)flash_status_read), CE_READ_TYPE);
- cmd_list_ptr++;
bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)flash_status_reset, CE_WRITE_TYPE);
cmd_list_ptr++;
@@ -802,12 +817,12 @@
qpic_nand_wait_for_cmd_exec(num_desc);
- status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr);
+ status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0);
nand_ret = qpic_nand_check_status(status);
/* Dummy read to unlock pipe. */
- status = qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr);
+ status = qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG);
if (nand_ret)
return NANDC_RESULT_FAILURE;
@@ -817,8 +832,13 @@
return nand_ret;
}
-static int
-qpic_nand_block_isbad(unsigned page)
+/**
+ * qpic_nand_block_isbad() - Checks is given block is bad
+ * @page - number of page the block starts at
+ *
+ * Returns nand_result_t
+ */
+nand_result_t qpic_nand_block_isbad(unsigned page)
{
unsigned cwperpage;
struct cfg_params params;
@@ -886,16 +906,16 @@
/* Function to erase a block on the nand.
* page: Starting page address for the block.
*/
-static int
-qpic_nand_blk_erase(uint32_t page)
+nand_result_t qpic_nand_blk_erase(uint32_t page)
{
struct cfg_params cfg;
struct cmd_element *cmd_list_ptr = ce_array;
+ struct cmd_element *cmd_list_read_ptr = ce_read_array;
struct cmd_element *cmd_list_ptr_start = ce_array;
+ struct cmd_element *cmd_list_read_ptr_start = ce_read_array;
uint32_t status;
int num_desc = 0;
uint32_t blk_addr = page / flash.num_pages_per_blk;
- int nand_ret;
/* Erase only if the block is not bad */
if (qpic_nand_block_isbad(page))
@@ -929,32 +949,40 @@
qpic_nand_wait_for_cmd_exec(num_desc);
- status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr);
+ status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0);
- cmd_list_ptr++;
cmd_list_ptr_start = cmd_list_ptr;
+ cmd_list_read_ptr_start = cmd_list_read_ptr;
/* QPIC controller automatically sends
* GET_STATUS cmd to the nand card because
* of the configuration programmed.
* Read the result of GET_STATUS cmd.
*/
- cmd_list_ptr = qpic_nand_add_read_n_reset_status_ce(cmd_list_ptr, &status, 1);
+ cmd_list_read_ptr = qpic_nand_add_read_ce(cmd_list_read_ptr, &status);
- /* Enqueue the desc for the above commands */
+ /* Enqueue the desc for the NAND_FLASH_STATUS read command */
+ bam_add_one_desc(&bam,
+ CMD_PIPE_INDEX,
+ (unsigned char*)cmd_list_read_ptr_start,
+ PA((uint32_t)cmd_list_read_ptr - (uint32_t)cmd_list_read_ptr_start),
+ BAM_DESC_CMD_FLAG) ;
+
+ cmd_list_ptr = qpic_nand_reset_status_ce(cmd_list_ptr, 1);
+
+ /* Enqueue the desc for NAND_FLASH_STATUS and NAND_READ_STATUS write commands */
bam_add_one_desc(&bam,
CMD_PIPE_INDEX,
(unsigned char*)cmd_list_ptr_start,
PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start),
BAM_DESC_INT_FLAG | BAM_DESC_CMD_FLAG) ;
-
- num_desc = 1;
+ num_desc = 2;
qpic_nand_wait_for_cmd_exec(num_desc);
status = qpic_nand_check_status(status);
/* Dummy read to unlock pipe. */
- nand_ret = qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr);
+ qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG);
/* Check for status errors*/
if (status)
@@ -962,6 +990,7 @@
dprintf(CRITICAL,
"NAND Erase error: Block address belongs to bad block: %d\n",
blk_addr);
+ qpic_nand_mark_badblock(page);
return NANDC_RESULT_FAILURE;
}
@@ -969,6 +998,7 @@
if (!(status & PROG_ERASE_OP_RESULT))
return NANDC_RESULT_SUCCESS;
+ qpic_nand_mark_badblock(page);
return NANDC_RESULT_FAILURE;
}
@@ -979,7 +1009,9 @@
enum nand_cfg_value cfg_mode)
{
struct cmd_element *cmd_list_ptr = ce_array;
+ struct cmd_element *cmd_list_read_ptr = ce_read_array;
struct cmd_element *cmd_list_ptr_start = ce_array;
+ struct cmd_element *cmd_list_read_ptr_start = ce_read_array;
uint32_t ecc;
int num_desc = 0;
int int_flag = 0;
@@ -1026,26 +1058,29 @@
num_desc++;
cmd_list_ptr_start = cmd_list_ptr;
+ cmd_list_read_ptr_start = cmd_list_read_ptr;
+
+ cmd_list_read_ptr = qpic_nand_add_read_ce(cmd_list_read_ptr_start, &status[i]);
+ /* Enqueue the desc for the NAND_FLASH_STATUS read command */
+ bam_add_one_desc(&bam,
+ CMD_PIPE_INDEX,
+ (unsigned char*)cmd_list_read_ptr_start,
+ PA((uint32_t)cmd_list_read_ptr - (uint32_t)cmd_list_read_ptr_start),
+ BAM_DESC_CMD_FLAG);
/* Set interrupt bit only for the last CW */
if (i == flash.cws_per_page - 1)
- {
- cmd_list_ptr = qpic_nand_add_read_n_reset_status_ce(cmd_list_ptr,
- &status[i],
- 1);
- }
+ cmd_list_ptr = qpic_nand_reset_status_ce(cmd_list_ptr, 1);
else
- cmd_list_ptr = qpic_nand_add_read_n_reset_status_ce(cmd_list_ptr,
- &status[i],
- 0);
+ cmd_list_ptr = qpic_nand_reset_status_ce(cmd_list_ptr, 0);
- /* Enqueue the desc for the above commands */
+ /* Enqueue the desc for NAND_FLASH_STATUS and NAND_READ_STATUS write commands */
bam_add_one_desc(&bam,
CMD_PIPE_INDEX,
(unsigned char*)cmd_list_ptr_start,
PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start),
int_flag | BAM_DESC_CMD_FLAG);
- num_desc++;
+ num_desc += 2;
qpic_nand_wait_for_cmd_exec(num_desc);
@@ -1190,8 +1225,10 @@
/* Check if we support the device */
for (index = 0; index < (ARRAY_SIZE(supported_flash)); index++)
{
- if ((flash->id & supported_flash[index].mask) ==
- (supported_flash[index].flash_id & (supported_flash[index].mask)))
+ if (((flash->id & supported_flash[index].mask) ==
+ (supported_flash[index].flash_id & (supported_flash[index].mask))) &&
+ ((flash->id2 & supported_flash[index].mask2) ==
+ (supported_flash[index].flash_id2 & (supported_flash[index].mask2))))
{
dev_found = 1;
break;
@@ -1253,7 +1290,6 @@
qpic_nand_init(struct qpic_nand_init_config *config)
{
uint32_t i;
- int nand_ret;
nand_base = config->nand_base;
@@ -1318,6 +1354,12 @@
return flash.num_blocks;
}
+unsigned
+flash_spare_size(void)
+{
+ return flash.spare_size;
+}
+
struct ptable *
flash_get_ptable(void)
{
@@ -1359,7 +1401,6 @@
uint8_t flags = 0;
uint32_t *cmd_list_temp = NULL;
- uint32_t temp_status = 0;
/* UD bytes in last CW is 512 - cws_per_page *4.
* Since each of the CW read earlier reads 4 spare bytes.
*/
@@ -1474,7 +1515,7 @@
bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)&(flash_sts[i])), CE_READ_TYPE);
- cmd_list_temp = cmd_list_ptr;
+ cmd_list_temp = (uint32_t *)cmd_list_ptr;
cmd_list_ptr++;
@@ -1519,6 +1560,105 @@
return nand_ret;
}
+/**
+ * qpic_nand_read() - read data
+ * @start_page: number of page to begin reading from
+ * @num_pages: number of pages to read
+ * @buffer: buffer where to store the read data
+ * @spareaddr: buffer where to store spare data.
+ * If null, spare data wont be read
+ *
+ * This function reads @num_pages starting from @start_page and stores the
+ * read data in buffer. Note that it's in the caller responsibility to make
+ * sure the read pages are all from same partition.
+ *
+ * Returns nand_result_t
+ */
+nand_result_t qpic_nand_read(uint32_t start_page, uint32_t num_pages,
+ unsigned char* buffer, unsigned char* spareaddr)
+{
+ unsigned i = 0, ret = 0;
+
+ if (!buffer) {
+ dprintf(CRITICAL, "qpic_nand_read: buffer = null\n");
+ return NANDC_RESULT_PARAM_INVALID;
+ }
+ while (i < num_pages) {
+ ret = qpic_nand_read_page(start_page + i, buffer + flash.page_size * i,
+ spareaddr);
+ i++;
+ if (ret == NANDC_RESULT_BAD_PAGE)
+ qpic_nand_mark_badblock(start_page + i);
+ if (ret) {
+ dprintf(CRITICAL,
+ "qpic_nand_read: reading page %d failed with %d err\n",
+ start_page + i, ret);
+ return ret;
+ }
+ }
+ return NANDC_RESULT_SUCCESS;
+}
+
+/**
+ * qpic_nand_write() - read data
+ * @start_page: number of page to begin writing to
+ * @num_pages: number of pages to write
+ * @buffer: buffer to be written
+ * @write_extra_bytes: true if spare data (ox 0xff) to be written
+ *
+ * This function writes @num_pages starting from @start_page. Note that it's
+ * in the caller responsibility to make sure the written pages are all from
+ * same partition.
+ *
+ * Returns nand_result_t
+ */
+nand_result_t qpic_nand_write(uint32_t start_page, uint32_t num_pages,
+ unsigned char* buffer, unsigned write_extra_bytes)
+{
+ int i = 0, ret = NANDC_RESULT_SUCCESS;
+ uint32_t *spare = (unsigned *)flash_spare_bytes;
+ uint32_t wsize;
+ uint32_t spare_byte_count = 0;
+
+ if (!buffer) {
+ dprintf(CRITICAL, "qpic_nand_write: buffer = null\n");
+ return NANDC_RESULT_PARAM_INVALID;
+ }
+ spare_byte_count = ((flash.cw_size * flash.cws_per_page)- flash.page_size);
+
+ if (write_extra_bytes)
+ wsize = flash.page_size + spare_byte_count;
+ else
+ wsize = flash.page_size;
+
+ memset(spare, 0xff, (spare_byte_count / flash.cws_per_page));
+
+ for (i = 0; i < (int)num_pages; i++) {
+ memcpy(rdwr_buf, buffer, flash.page_size);
+ if (write_extra_bytes) {
+ memcpy(rdwr_buf + flash.page_size,
+ buffer + flash.page_size, spare_byte_count);
+ ret = qpic_nand_write_page(start_page + i,
+ NAND_CFG, rdwr_buf, rdwr_buf + flash.page_size);
+ } else {
+ ret = qpic_nand_write_page(start_page + i,
+ NAND_CFG, rdwr_buf, spare);
+ }
+ if (ret) {
+ dprintf(CRITICAL,
+ "flash_write: write failure @ page %d, block %d\n",
+ start_page + i,
+ (start_page + i) / flash.num_pages_per_blk);
+ if (ret == NANDC_RESULT_BAD_PAGE)
+ qpic_nand_mark_badblock(start_page + i);
+ goto out;
+ }
+ buffer += wsize;
+ }
+out:
+ return ret;
+}
+
/* Function to read a flash partition.
* ptn : Partition to read.
* extra_per_page : Spare data to be read.
@@ -1630,13 +1770,14 @@
int
flash_erase(struct ptentry *ptn)
{
- int ret = 0;
+ int ret = 0, i;
- ret = qpic_nand_blk_erase(ptn->start * flash.num_pages_per_blk);
-
- if (ret)
- dprintf(CRITICAL, "Erase operation failed \n");
-
+ for (i = 0; i < (int)ptn->length; i++) {
+ ret = qpic_nand_blk_erase((ptn->start + i) * flash.num_pages_per_blk);
+ if (ret)
+ dprintf(CRITICAL, "Erase operation failed @ page #%d\n",
+ ptn->start + i);
+ }
return ret;
}
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index fce33f2..4f2ad47 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -30,6 +30,7 @@
#include <reg.h>
#include <bits.h>
#include <debug.h>
+#include <qtimer.h>
__WEAK int platform_is_msm8994()
{
diff --git a/platform/msm_shared/rpm-smd.c b/platform/msm_shared/rpm-smd.c
index d623542..693d369 100644
--- a/platform/msm_shared/rpm-smd.c
+++ b/platform/msm_shared/rpm-smd.c
@@ -34,6 +34,7 @@
#include <arch/defines.h>
#include <debug.h>
#include <stdlib.h>
+#include <platform/timer.h>
#define RPM_REQ_MAGIC 0x00716572
#define RPM_CMD_MAGIC 0x00646d63
@@ -56,8 +57,6 @@
static void fill_kvp_object(kvp_data **kdata, uint32_t *data, uint32_t len)
{
- uint32_t i =0;
-
*kdata = (kvp_data *) memalign(CACHE_LINE, ROUNDUP(len, CACHE_LINE));
ASSERT(*kdata);
@@ -133,8 +132,12 @@
rpm_ack_msg *resp;
msg_type type;
uint32_t ret = 0;
+ /* As per the current design rpm response does not exceed 20 bytes */
+ uint32_t response[5];
- resp = (rpm_ack_msg*)smd_read(&ch, len, SMD_APPS_RPM);
+ smd_read(&ch, len, SMD_APPS_RPM, response);
+
+ resp = (rpm_ack_msg *)response;
arch_invalidate_cache_range((addr_t)resp, sizeof(rpm_gen_hdr));
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index c905e23..793b88c 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -38,7 +38,7 @@
$(LOCAL_DIR)/mmc.o
endif
-ifeq ($(ENABLE_VERIFIED_BOOT),1)
+ifeq ($(VERIFIED_BOOT),1)
OBJS += \
$(LOCAL_DIR)/boot_verifier.o
endif
@@ -241,12 +241,6 @@
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/scm.o \
- $(LOCAL_DIR)/ufs.o \
- $(LOCAL_DIR)/utp.o \
- $(LOCAL_DIR)/uic.o \
- $(LOCAL_DIR)/ucs.o \
- $(LOCAL_DIR)/ufs_hci.o \
- $(LOCAL_DIR)/dme.o \
$(LOCAL_DIR)/certificate.o \
$(LOCAL_DIR)/image_verify.o \
$(LOCAL_DIR)/crypto_hash.o \
@@ -336,6 +330,7 @@
$(LOCAL_DIR)/board.o \
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/flash-ubi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/scm.o \
$(LOCAL_DIR)/dev_tree.o \
@@ -348,7 +343,8 @@
$(LOCAL_DIR)/qpic_panel.o
endif
-ifeq ($(PLATFORM),msmzirc)
+ifeq ($(PLATFORM),mdm9640)
+DEFINES += DISPLAY_TYPE_QPIC=1
OBJS += $(LOCAL_DIR)/qgic.o \
$(LOCAL_DIR)/uart_dm.o \
$(LOCAL_DIR)/interrupts.o \
@@ -357,6 +353,7 @@
$(LOCAL_DIR)/board.o \
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/flash-ubi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/clock.o \
@@ -365,7 +362,10 @@
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/scm.o \
$(LOCAL_DIR)/qmp_usb30_phy.o \
- $(LOCAL_DIR)/qusb2_phy.o
+ $(LOCAL_DIR)/qusb2_phy.o \
+ $(LOCAL_DIR)/display.o \
+ $(LOCAL_DIR)/qpic.o \
+ $(LOCAL_DIR)/qpic_panel.o
endif
ifeq ($(PLATFORM),fsm9900)
@@ -415,6 +415,7 @@
$(LOCAL_DIR)/crypto5_wrapper.o \
$(LOCAL_DIR)/i2c_qup.o \
$(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/qmp_usb30_phy.o \
$(LOCAL_DIR)/dload_util.o
endif
@@ -435,12 +436,6 @@
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/scm.o \
- $(LOCAL_DIR)/ufs.o \
- $(LOCAL_DIR)/utp.o \
- $(LOCAL_DIR)/uic.o \
- $(LOCAL_DIR)/ucs.o \
- $(LOCAL_DIR)/ufs_hci.o \
- $(LOCAL_DIR)/dme.o \
$(LOCAL_DIR)/qmp_usb30_phy.o \
$(LOCAL_DIR)/certificate.o \
$(LOCAL_DIR)/image_verify.o \
@@ -503,14 +498,23 @@
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/scm.o \
+ $(LOCAL_DIR)/qmp_usb30_phy.o \
+ $(LOCAL_DIR)/qusb2_phy.o \
+ $(LOCAL_DIR)/certificate.o \
+ $(LOCAL_DIR)/image_verify.o \
+ $(LOCAL_DIR)/crypto_hash.o \
+ $(LOCAL_DIR)/crypto5_eng.o \
+ $(LOCAL_DIR)/crypto5_wrapper.o
+endif
+
+ifeq ($(ENABLE_UFS_SUPPORT), 1)
+ OBJS += \
$(LOCAL_DIR)/ufs.o \
$(LOCAL_DIR)/utp.o \
$(LOCAL_DIR)/uic.o \
$(LOCAL_DIR)/ucs.o \
$(LOCAL_DIR)/ufs_hci.o \
- $(LOCAL_DIR)/dme.o \
- $(LOCAL_DIR)/qmp_usb30_phy.o \
- $(LOCAL_DIR)/qusb2_phy.o
+ $(LOCAL_DIR)/dme.o
endif
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
@@ -525,3 +529,7 @@
$(LOCAL_DIR)/usb30_udc.o \
$(LOCAL_DIR)/usb30_wrapper.o
endif
+
+ifeq ($(ENABLE_PARTIAL_GOODS_SUPPORT), 1)
+ OBJS += $(LOCAL_DIR)/partial_goods.o
+endif
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index c7ff1b8..b45fd3d 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -32,6 +32,8 @@
#include <asm.h>
#include <bits.h>
#include <arch/ops.h>
+#include <rand.h>
+#include <image_verify.h>
#include "scm.h"
#pragma GCC optimize ("O0")
@@ -57,7 +59,7 @@
{
uint32_t ret;
scmcall_arg scm_arg = {0};
- scmcall_arg scm_ret = {0};
+ scmcall_ret scm_ret = {0};
/* Make a call to check if SCM call available using new interface,
* if this returns 0 then scm implementation as per arm spec
* otherwise use the old interface for scm calls
@@ -170,7 +172,7 @@
{
uint32_t context_id;
register uint32_t r0 __asm__("r0") = SCM_ATOMIC(svc, cmd, 1);
- register uint32_t r1 __asm__("r1") = &context_id;
+ register uint32_t r1 __asm__("r1") = (uint32_t)&context_id;
register uint32_t r2 __asm__("r2") = arg1;
__asm__ volatile(
@@ -199,7 +201,7 @@
{
int context_id;
register uint32_t r0 __asm__("r0") = SCM_ATOMIC(svc, cmd, 2);
- register uint32_t r1 __asm__("r1") = &context_id;
+ register uint32_t r1 __asm__("r1") = (uint32_t)&context_id;
register uint32_t r2 __asm__("r2") = arg1;
register uint32_t r3 __asm__("r3") = arg2;
@@ -331,9 +333,9 @@
else
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD,SSD_ENCRYPT_ID);
- scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
- scm_arg.x2 = cmd.img_ptr;
- scm_arg.x3 = cmd.img_len_ptr;
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_BUFFER_READWRITE);
+ scm_arg.x2 = (uint32_t) cmd.img_ptr;
+ scm_arg.x3 = (uint32_t) cmd.img_len_ptr;
ret = scm_call2(&scm_arg, NULL);
}
@@ -421,7 +423,8 @@
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD, SSD_PARSE_MD_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_VALUE,SMC_PARAM_TYPE_BUFFER_READWRITE);
scm_arg.x2 = parse_req.md_len;
- scm_arg.x3 = parse_req.md;
+ scm_arg.x3 = (uint32_t) parse_req.md;
+ scm_arg.atomic = true;
ret = scm_call2(&scm_arg, &scm_ret);
parse_rsp.status = scm_ret.x1;
@@ -506,7 +509,7 @@
scm_arg.x2 = decrypt_req.md_ctx_id;
scm_arg.x3 = decrypt_req.last_frag;
scm_arg.x4 = decrypt_req.frag_len;
- scm_arg.x5[0] = decrypt_req.frag;
+ scm_arg.x5[0] = (uint32_t) decrypt_req.frag;
ret = scm_call2(&scm_arg, &scm_ret);
decrypt_rsp.status = scm_ret.x1;
@@ -581,6 +584,48 @@
return ret;
}
+int scm_svc_get_secure_state(uint32_t *state_low, uint32_t *state_high)
+{
+ get_secure_state_req req;
+ get_secure_state_rsp rsp;
+
+ int ret = 0;
+
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ if (!scm_arm_support)
+ {
+ req.status_ptr = (uint32_t*)&rsp;
+ req.status_len = sizeof(rsp);
+
+ ret = scm_call(TZBSP_SVC_INFO,
+ TZ_INFO_GET_SECURE_STATE,
+ &req,
+ sizeof(req),
+ NULL,
+ 0);
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(TZBSP_SVC_INFO, TZ_INFO_GET_SECURE_STATE);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x0);
+
+ ret = scm_call2(&scm_arg, &scm_ret);
+
+ rsp.status_low = scm_ret.x1;
+ rsp.status_high = scm_ret.x2;
+ }
+
+ if(!ret)
+ {
+ *state_low = rsp.status_low;
+ *state_high = rsp.status_high;
+ }
+
+ return ret;
+}
+
int scm_protect_keystore(uint32_t * img_ptr, uint32_t img_len)
{
int ret=0;
@@ -607,7 +652,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD, SSD_PROTECT_KEYSTORE_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
- scm_arg.x2 = protect_req.keystore_ptr;
+ scm_arg.x2 = (uint32_t) protect_req.keystore_ptr;
scm_arg.x3 = protect_req.keystore_len;
ret = scm_call2(&scm_arg, &scm_ret);
@@ -658,7 +703,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_FUSE, SCM_BLOW_SW_FUSE_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
- scm_arg.x2 = cmd_buf;
+ scm_arg.x2 = (uint32_t) cmd_buf;
scm_arg.x3 = cmd_len;
scm_call2(&scm_arg, NULL);
@@ -698,7 +743,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_FUSE, SCM_IS_SW_FUSE_BLOWN_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
- scm_arg.x2 = cmd_buf;
+ scm_arg.x2 = (uint32_t) cmd_buf;
scm_arg.x3 = cmd_len;
scm_call2(&scm_arg, &scm_ret);
@@ -706,7 +751,6 @@
}
}
-#define SHA256_DIGEST_LENGTH (256/8)
/*
* struct qseecom_save_partition_hash_req
* @partition_id - partition id.
@@ -750,7 +794,7 @@
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_ES, SCM_SAVE_PARTITION_HASH_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x3, 0, SMC_PARAM_TYPE_BUFFER_READWRITE);
scm_arg.x2 = req.partition_id;
- scm_arg.x3 = (uint8_t *)&req.digest;
+ scm_arg.x3 = (uint32_t) &req.digest;
scm_arg.x4 = sizeof(req.digest);
if (scm_call2(&scm_arg, NULL))
@@ -758,6 +802,119 @@
}
}
+int mdtp_cipher_dip_cmd(uint8_t *in_buf, uint32_t in_buf_size, uint8_t *out_buf,
+ uint32_t out_buf_size, uint32_t direction)
+{
+ uint32_t svc_id;
+ uint32_t cmd_id;
+ void *cmd_buf;
+ void *rsp_buf;
+ size_t cmd_len;
+ size_t rsp_len;
+ mdtp_cipher_dip_req req;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ ASSERT(in_buf != NULL);
+ ASSERT(out_buf != NULL);
+
+ req.in_buf = in_buf;
+ req.in_buf_size = in_buf_size;
+ req.out_buf = out_buf;
+ req.out_buf_size = out_buf_size;
+ req.direction = direction;
+
+ if (!scm_arm_support)
+ {
+ svc_id = SCM_SVC_MDTP;
+ cmd_id = SCM_MDTP_CIPHER_DIP;
+ cmd_buf = (void *)&req;
+ cmd_len = sizeof(req);
+ rsp_buf = NULL;
+ rsp_len = 0;
+
+ if (scm_call(svc_id, cmd_id, cmd_buf, cmd_len, rsp_buf, rsp_len))
+ {
+ dprintf(CRITICAL, "Failed to call Cipher DIP SCM\n");
+ return -1;
+ }
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_MDTP, SCM_MDTP_CIPHER_DIP);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x5, SMC_PARAM_TYPE_BUFFER_READ, SMC_PARAM_TYPE_VALUE,
+ SMC_PARAM_TYPE_BUFFER_READWRITE, SMC_PARAM_TYPE_VALUE, SMC_PARAM_TYPE_VALUE);
+ scm_arg.x2 = (uint32_t)req.in_buf;
+ scm_arg.x3 = req.in_buf_size;
+ scm_arg.x4 = (uint32_t)req.out_buf;
+ scm_arg.x5[0] = req.out_buf_size;
+ scm_arg.x5[1] = req.direction;
+
+ if (scm_call2(&scm_arg, &scm_ret))
+ {
+ dprintf(CRITICAL, "Failed in Cipher DIP SCM call\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+int qfprom_read_row_cmd(uint32_t row_address,
+ uint32_t addr_type,
+ uint32_t *row_data,
+ uint32_t *qfprom_api_status)
+{
+ uint32_t svc_id;
+ uint32_t cmd_id;
+ void *cmd_buf;
+ void *rsp_buf;
+ size_t cmd_len;
+ size_t rsp_len;
+ qfprom_read_row_req req;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ req.row_address = row_address;
+ req.addr_type = addr_type;
+ req.row_data = row_data;
+ req.qfprom_api_status = qfprom_api_status;
+
+ if (!scm_arm_support)
+ {
+ svc_id = SCM_SVC_FUSE;
+ cmd_id = SCM_QFPROM_READ_ROW_ID;
+ cmd_buf = (void *)&req;
+ cmd_len = sizeof(req);
+ rsp_buf = NULL;
+ rsp_len = 0;
+
+ if (scm_call(svc_id, cmd_id, cmd_buf, cmd_len, rsp_buf, rsp_len))
+ {
+ dprintf(CRITICAL, "Failed to call SCM_SVC_FUSE.SCM_QFPROM_READ_ROW_ID SCM\n");
+ return -1;
+ }
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_FUSE, SCM_QFPROM_READ_ROW_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x4, SMC_PARAM_TYPE_VALUE, SMC_PARAM_TYPE_VALUE,
+ SMC_PARAM_TYPE_BUFFER_READWRITE, SMC_PARAM_TYPE_BUFFER_READWRITE);
+ scm_arg.x2 = req.row_address;
+ scm_arg.x3 = req.addr_type;
+ scm_arg.x4 = (uint32_t)req.row_data;
+ scm_arg.x5[0] = (uint32_t)req.qfprom_api_status;
+
+ if (scm_call2(&scm_arg, &scm_ret))
+ {
+ dprintf(CRITICAL, "Failed to call SCM_SVC_FUSE.SCM_QFPROM_READ_ROW_ID SCM\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
/*
* Switches the CE1 channel between ADM and register usage.
* channel : AP_CE_REGISTER_USE, CE1 uses register interface
@@ -853,7 +1010,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_MILESTONE_32_64_ID, SCM_SVC_MILESTONE_CMD_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2, SMC_PARAM_TYPE_BUFFER_READ);
- scm_arg.x2 = (void *)¶m;
+ scm_arg.x2 = (uint32_t ) ¶m;
scm_arg.x3 = sizeof(el1_system_param);
scm_call2(&scm_arg, NULL);
@@ -890,7 +1047,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(TZ_SVC_CRYPTO, PRNG_CMD_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE);
- scm_arg.x2 = (uint8_t *) rbuf;
+ scm_arg.x2 = (uint32_t) rbuf;
scm_arg.x3 = r_len;
ret = scm_call2(&scm_arg, NULL);
@@ -906,7 +1063,7 @@
void * get_canary()
{
void * canary;
- if(scm_random(&canary, sizeof(canary))) {
+ if(scm_random((uint32_t *)&canary, sizeof(canary))) {
dprintf(CRITICAL,"scm_call for random failed !!!");
/*
* fall back to use lib rand API if scm call failed.
@@ -995,7 +1152,7 @@
arg->x0 = arg->atomic ? (arg->x0 | SCM_ATOMIC_BIT) : arg->x0;
x5 = arg->x5[0];
- if ((arg->x1 & 0xF) > SCM_MAX_ARG_LEN)
+ if ((arg->x1 & 0xF) > SCM_MAX_ARG_LEN - 1)
{
indir_arg = memalign(CACHE_LINE, (SCM_INDIR_MAX_LEN * sizeof(uint32_t)));
ASSERT(indir_arg);
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 8f6a86e..c898a81 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -430,7 +430,7 @@
uint8_t i;
uint8_t ret = 0;
uint8_t need_reset = 0;
- uint32_t retry = 0;
+ uint64_t retry = 0;
uint32_t int_status;
uint32_t trans_complete = 0;
uint32_t err_status;
@@ -504,7 +504,13 @@
trans_complete = 1;
break;
}
- else if (int_status & SDHCI_ERR_INT_STAT_MASK && !host->tuning_in_progress)
+ /*
+ * Some controllers set the data timout first on issuing an erase & take time
+ * to set data complete interrupt. We need to wait hoping the controller would
+ * set data complete
+ */
+ else if (int_status & SDHCI_ERR_INT_STAT_MASK && !host->tuning_in_progress &&
+ !((REG_READ16(host, SDHCI_ERR_INT_STS_REG) & SDHCI_DAT_TIMEOUT_MASK)))
goto err;
/*
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index d721110..4e83a55 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -191,7 +191,7 @@
/*
* Register the interrupt handler for pwr irq
*/
- register_int_handler(config->pwr_irq, sdhci_int_handler, (void *)config);
+ register_int_handler(config->pwr_irq, (int_handler)sdhci_int_handler, (void *)config);
unmask_interrupt(config->pwr_irq);
@@ -294,14 +294,36 @@
REG_RMW32(host, SDCC_DLL_CONFIG_REG, SDCC_DLL_CONFIG_MCLK_START, SDCC_DLL_CONFIG_MCLK_WIDTH, reg_val);
}
+static void sdhci_dll_clk_enable(struct sdhci_host *host, int enable)
+{
+ if (enable)
+ {
+ REG_WRITE32(host, (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) & ~SDCC_DLL_CLOCK_DISABLE), SDCC_HC_REG_DLL_CONFIG_2);
+ }
+ else
+ {
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_CLK_OUT_EN), SDCC_DLL_CONFIG_REG);
+ REG_WRITE32(host, (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) | SDCC_DLL_CLOCK_DISABLE), SDCC_HC_REG_DLL_CONFIG_2);
+ }
+}
+
/* Initialize DLL (Programmable Delay Line) */
static uint32_t sdhci_msm_init_dll(struct sdhci_host *host)
{
uint32_t pwr_save = 0;
uint32_t timeout = SDHCI_DLL_TIMEOUT;
+ uint32_t dll_cfg2;
+ uint32_t mclk_clk_freq = 0;
pwr_save = REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & SDCC_DLL_PWR_SAVE_EN;
+ /* Dll sequence needs additional steps for sdcc core version 42 */
+ if (host->major == 1 && host->minor >= 0x42)
+ {
+ /* Disable DLL clock before configuring */
+ sdhci_dll_clk_enable(host, 0);
+ }
+
/* PWR SAVE to 0 */
if (pwr_save)
REG_WRITE32(host, (REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & ~SDCC_DLL_PWR_SAVE_EN), SDCC_VENDOR_SPECIFIC_FUNC);
@@ -313,10 +335,33 @@
/* Set frequency field in DLL_CONFIG */
msm_set_dll_freq(host);
+ /* Configure the mclk freq based on the current clock rate
+ * and fll cycle count as per hpg section 15.2.2
+ */
+ if (host->major == 1 && host->minor >= 0x42)
+ {
+ dll_cfg2 = REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2);
+ if (dll_cfg2 & SDCC_FLL_CYCLE_CNT)
+ mclk_clk_freq = (host->cur_clk_rate / TCXO_FREQ) * 8;
+ else
+ mclk_clk_freq = (host->cur_clk_rate / TCXO_FREQ) * 4;
+
+ REG_WRITE32(host, ((REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) & ~(0xFF << 10)) | (mclk_clk_freq << 10)), SDCC_HC_REG_DLL_CONFIG_2);
+
+ udelay(5);
+ }
+
/* Write 0 to DLL_RST */
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_RESET_EN), SDCC_DLL_CONFIG_REG);
/* Write 0 to DLL_PDN */
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_PDN_EN), SDCC_DLL_CONFIG_REG);
+
+ /* Set the mclk clock and enable the dll clock */
+ if (host->major == 1 && host->minor >= 0x42)
+ {
+ msm_set_dll_freq(host);
+ sdhci_dll_clk_enable(host, 1);
+ }
/* Write 1 to DLL_EN */
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_EN), SDCC_DLL_CONFIG_REG);
/* Write 1 to CLK_OUT_EN */
@@ -418,7 +463,7 @@
uint32_t total_phases)
{
int sub_phases[MAX_PHASES][MAX_PHASES]={{0}};
- int phases_per_row[MAX_PHASES] = {0};
+ uint32_t phases_per_row[MAX_PHASES] = {0};
uint32_t i,j;
int selected_phase = 0;
uint32_t row_index = 0;
@@ -660,14 +705,14 @@
{
uint32_t *tuning_block;
uint32_t *tuning_data;
- uint32_t tuned_phases[MAX_PHASES] = {{0}};
+ uint32_t tuned_phases[MAX_PHASES] = {0};
uint32_t size;
uint32_t phase = 0;
uint32_t tuned_phase_cnt = 0;
uint8_t drv_type = 0;
bool drv_type_changed = false;
int ret = 0;
- int i;
+ uint32_t i;
struct sdhci_msm_data *msm_host;
msm_host = host->msm_host;
@@ -686,12 +731,12 @@
if (bus_width == DATA_BUS_WIDTH_8BIT)
{
- tuning_block = tuning_block_128;
+ tuning_block = (uint32_t *)tuning_block_128;
size = sizeof(tuning_block_128);
}
else
{
- tuning_block = tuning_block_64;
+ tuning_block = (uint32_t *)tuning_block_64;
size = sizeof(tuning_block_64);
}
diff --git a/platform/msm_shared/shutdown_detect.c b/platform/msm_shared/shutdown_detect.c
index a51c9ae..633dbac 100644
--- a/platform/msm_shared/shutdown_detect.c
+++ b/platform/msm_shared/shutdown_detect.c
@@ -34,6 +34,8 @@
#include <kernel/timer.h>
#include <platform/timer.h>
#include <shutdown_detect.h>
+#include <platform.h>
+#include <target.h>
/* sleep clock is 32.768 khz, 0x8000 count per second */
#define MPM_SLEEP_TIMETICK_COUNT 0x8000
@@ -102,7 +104,7 @@
* for software to be safely detect if there is a key release action.
*/
timer_set_oneshot(p_timer, PWRKEY_DETECT_FREQUENCY,
- long_press_pwrkey_timer_func, NULL);
+ (timer_callback)long_press_pwrkey_timer_func, NULL);
} else {
shutdown_device();
}
@@ -146,7 +148,7 @@
*/
if (is_pwrkey_pon_reason() && is_pwrkey_time_expired()) {
timer_initialize(&pon_timer);
- timer_set_oneshot(&pon_timer, 0, long_press_pwrkey_timer_func, NULL);
+ timer_set_oneshot(&pon_timer, 0,(timer_callback)long_press_pwrkey_timer_func, NULL);
/*
* Wait until long press power key timeout
diff --git a/platform/msm_shared/smd.c b/platform/msm_shared/smd.c
index 6d99088..61d8f1f 100644
--- a/platform/msm_shared/smd.c
+++ b/platform/msm_shared/smd.c
@@ -30,15 +30,19 @@
#include <smd.h>
#include <smem.h>
#include <debug.h>
+#include <kernel/event.h>
#include <platform/irqs.h>
#include <platform/iomap.h>
#include <platform/interrupts.h>
+#include <platform/timer.h>
#include <reg.h>
#include <malloc.h>
#include <bits.h>
-smd_channel_alloc_entry_t *smd_channel_alloc_entry;
+#define SMD_CHANNEL_ACCESS_RETRY 1000000
+smd_channel_alloc_entry_t *smd_channel_alloc_entry;
+static event_t smd_closed;
static void smd_write_state(smd_channel_info_t *ch, uint32_t state)
{
@@ -63,7 +67,7 @@
ch->port_info->ch0.state_updated = flag;
}
-void smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type)
+int smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type)
{
int i = 0;
@@ -76,12 +80,14 @@
}
}
- /* Channel not found */
+ /* Channel not found, retry again */
if(i == SMEM_NUM_SMD_STREAM_CHANNELS)
{
- dprintf(CRITICAL, "smd channel type %x not found\n", ch_type);
- ASSERT(0);
+ dprintf(SPEW, "Channel not found, wait and retry for the update\n");
+ return -1;
}
+
+ return 0;
}
int smd_get_channel_info(smd_channel_info_t *ch, uint32_t ch_type)
@@ -91,8 +97,10 @@
uint32_t fifo_buf_size = 0;
uint32_t size = 0;
- smd_get_channel_entry(ch, ch_type);
+ ret = smd_get_channel_entry(ch, ch_type);
+ if (ret)
+ return ret;
ch->port_info = smem_get_alloc_entry(SMEM_SMD_BASE_ID + ch->alloc_entry.cid,
&size);
@@ -111,36 +119,55 @@
int smd_init(smd_channel_info_t *ch, uint32_t ch_type)
{
unsigned ret = 0;
+ int chnl_found = 0;
+ uint64_t timeout = SMD_CHANNEL_ACCESS_RETRY;
smd_channel_alloc_entry = (smd_channel_alloc_entry_t*)memalign(CACHE_LINE, SMD_CHANNEL_ALLOC_MAX);
ASSERT(smd_channel_alloc_entry);
- ret = smem_read_alloc_entry(SMEM_CHANNEL_ALLOC_TBL,
- (void*)smd_channel_alloc_entry,
- SMD_CHANNEL_ALLOC_MAX);
- if(ret)
+ dprintf(INFO, "Waiting for the RPM to populate smd channel table\n");
+
+ do
{
- dprintf(CRITICAL,"ERROR reading smem channel alloc tbl\n");
- return -1;
+ ret = smem_read_alloc_entry(SMEM_CHANNEL_ALLOC_TBL,
+ (void*)smd_channel_alloc_entry,
+ SMD_CHANNEL_ALLOC_MAX);
+ if(ret)
+ {
+ dprintf(CRITICAL,"ERROR reading smem channel alloc tbl\n");
+ return -1;
+ }
+
+ chnl_found = smd_get_channel_info(ch, ch_type);
+ timeout--;
+ udelay(10);
+ } while(timeout && chnl_found);
+
+ if (!timeout)
+ {
+ dprintf(CRITICAL, "Apps timed out waiting for RPM-->APPS channel entry\n");
+ ASSERT(0);
}
- smd_get_channel_info(ch, ch_type);
-
register_int_handler(SMD_IRQ, smd_irq_handler, ch);
- unmask_interrupt(SMD_IRQ);
smd_set_state(ch, SMD_SS_OPENING, 1);
smd_notify_rpm();
+ unmask_interrupt(SMD_IRQ);
+
return 0;
}
void smd_uninit(smd_channel_info_t *ch)
{
+ event_init(&smd_closed, false, EVENT_FLAG_AUTOUNSIGNAL);
smd_set_state(ch, SMD_SS_CLOSING, 1);
smd_notify_rpm();
+ /* Wait for the SMD-RPM channel to be closed */
+ event_wait(&smd_closed);
}
bool is_channel_open(smd_channel_info_t *ch)
@@ -204,12 +231,10 @@
ch_ptr->port_info->ch1.read_index = read_index;
}
-uint8_t* smd_read(smd_channel_info_t *ch, uint32_t *len, int ch_type)
+void smd_read(smd_channel_info_t *ch, uint32_t *len, int ch_type, uint32_t *response)
{
smd_pkt_hdr smd_hdr;
uint32_t size = 0;
- /* Response as per the current design does not exceed 20 bytes */
- uint32_t response[5];
/* Read the indices from smem */
ch->port_info = smem_get_alloc_entry(SMEM_SMD_BASE_ID + ch->alloc_entry.cid,
@@ -217,7 +242,7 @@
if(!ch->port_info->ch1.DTR_DSR)
{
dprintf(CRITICAL,"%s: DTR is off\n", __func__);
- return -1;
+ ASSERT(0);
}
/* Wait until the data updated in the smd buffer is equal to smd packet header*/
@@ -228,7 +253,7 @@
}
/* Copy the smd buffer to local buf */
- memcpy_from_fifo(ch, &smd_hdr, sizeof(smd_hdr));
+ memcpy_from_fifo(ch, (uint32_t *)&smd_hdr, sizeof(smd_hdr));
arch_invalidate_cache_range((addr_t)&smd_hdr, sizeof(smd_hdr));
@@ -242,11 +267,10 @@
}
/* We are good to return the response now */
- memcpy_from_fifo(ch, response, sizeof(response));
+ memcpy_from_fifo(ch, response, smd_hdr.pkt_size);
- arch_invalidate_cache_range((addr_t)response, sizeof(response));
+ arch_invalidate_cache_range((addr_t)response, smd_hdr.pkt_size);
- return response;
}
void smd_signal_read_complete(smd_channel_info_t *ch, uint32_t len)
@@ -389,6 +413,7 @@
if(ch->current_state == SMD_SS_CLOSED)
{
free(smd_channel_alloc_entry);
+ event_signal(&smd_closed, false);
return INT_NO_RESCHEDULE;
}
diff --git a/platform/msm_shared/smem.c b/platform/msm_shared/smem.c
index 25628d3..0dc3c24 100644
--- a/platform/msm_shared/smem.c
+++ b/platform/msm_shared/smem.c
@@ -104,7 +104,7 @@
uint32_t smem_addr = 0;
uint32_t base_ext = 0;
uint32_t offset = 0;
- void *ret = 0;
+ void *ret = NULL;
#if DYNAMIC_SMEM
smem_addr = smem_get_base_addr();
@@ -114,11 +114,11 @@
smem = (struct smem *)smem_addr;
if (type < SMEM_FIRST_VALID_TYPE || type > SMEM_LAST_VALID_TYPE)
- return 1;
+ return ret;
ainfo = &smem->alloc_info[type];
if (readl(&ainfo->allocated) == 0)
- return 1;
+ return ret;
*size = readl(&ainfo->size);
base_ext = readl(&ainfo->base_ext);
@@ -126,7 +126,7 @@
if(base_ext)
{
- ret = base_ext + offset;
+ ret = (void*)base_ext + offset;
}
else
{
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 7760e69..db186d4 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -2,7 +2,7 @@
* Copyright (c) 2009, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -32,6 +32,7 @@
#define __PLATFORM_MSM_SHARED_SMEM_H
#include <sys/types.h>
+#include <platform.h>
#define SMEM_V7_SMEM_MAX_PMIC_DEVICES 1
#define SMEM_V8_SMEM_MAX_PMIC_DEVICES 3
@@ -184,10 +185,23 @@
unsigned fused_chip;
unsigned platform_subtype;
struct smem_pmic_info pmic_info[SMEM_V8_SMEM_MAX_PMIC_DEVICES];
- /*
- * Need for 8 bytes alignment
- * while reading from shared memory
- */
+};
+
+struct smem_board_info_v9 {
+ struct smem_board_info_v3 board_info_v3;
+ unsigned platform_version;
+ unsigned fused_chip;
+ unsigned platform_subtype;
+ struct smem_pmic_info pmic_info[SMEM_V8_SMEM_MAX_PMIC_DEVICES];
+ uint32_t foundry_id; /* Used as foundry_id only for v9 */
+};
+
+struct smem_board_info_v10 {
+ struct smem_board_info_v3 board_info_v3;
+ unsigned platform_version;
+ unsigned fused_chip;
+ unsigned platform_subtype;
+ struct smem_pmic_info pmic_info[SMEM_V8_SMEM_MAX_PMIC_DEVICES];
uint32_t foundry_id; /* Used as foundry_id only for v9 */
uint32_t chip_serial; /* Used as serial number for v10 */
};
@@ -360,7 +374,7 @@
MSM8510 = 225,
MSM8512 = 226,
MSM8936 = 233,
- MSMZIRC = 234,
+ MDM9640 = 234,
MSM8939 = 239,
APQ8036 = 240,
APQ8039 = 241,
@@ -385,6 +399,15 @@
MDM9309 = 261,
MDM9609 = 262,
MSM8239 = 263,
+ APQ8009 = 265,
+ MSMTELLURIUM = 264,
+ MSMTERBIUM = 266,
+ MSM8929 = 268,
+ MSM8629 = 269,
+ MSM8229 = 270,
+ APQ8029 = 271,
+ MSM8609 = 275,
+ FSM9916 = 276,
};
enum platform {
diff --git a/platform/msm_shared/smem_ptable.c b/platform/msm_shared/smem_ptable.c
index 6ec563a..fd27e10 100644
--- a/platform/msm_shared/smem_ptable.c
+++ b/platform/msm_shared/smem_ptable.c
@@ -61,7 +61,7 @@
{
unsigned i;
unsigned ret;
- unsigned len;
+ unsigned len = 0;
/* Read only the header portion of ptable */
ret = smem_read_alloc_entry_offset(SMEM_AARM_PARTITION_TABLE,
@@ -220,7 +220,7 @@
uint32_t i;
uint32_t ret;
uint32_t version;
- uint32_t smem_ram_ptable_size;
+ uint32_t smem_ram_ptable_size = 0;
struct smem_ram_ptable_hdr *ram_ptable_hdr;
/* Check smem ram partition table version and decide on length of ram_ptable */
diff --git a/platform/msm_shared/spmi.c b/platform/msm_shared/spmi.c
index 6d486b7..d82fbb9 100644
--- a/platform/msm_shared/spmi.c
+++ b/platform/msm_shared/spmi.c
@@ -33,6 +33,7 @@
#include <platform/iomap.h>
#include <platform/irqs.h>
#include <platform/interrupts.h>
+#include <malloc.h>
#define PMIC_ARB_V2 0x20010000
#define CHNL_IDX(sid, pid) ((sid << 8) | pid)
@@ -47,8 +48,8 @@
static void spmi_lookup_chnl_number()
{
int i;
- uint8_t slave_id;
- uint8_t ppid_address;
+ uint8_t slave_id = 0;
+ uint8_t ppid_address = 0;
/* We need a max of sid (4 bits) + pid (8bits) of uint8_t's */
uint32_t chnl_tbl_sz = BIT(12) * sizeof(uint8_t);
@@ -95,7 +96,6 @@
{
uint32_t shift_value[] = {0, 8, 16, 24};
int i;
- int j;
uint32_t val = 0;
/* Write to WDATA */
@@ -154,12 +154,12 @@
*/
/* Write first 4 bytes to WDATA0 */
- write_wdata_from_array(param->buffer, 0, param->size, &bytes_written);
+ write_wdata_from_array(param->buffer, 0, param->size,(uint8_t *)&bytes_written);
if (bytes_written < param->size)
{
/* Write next 4 bytes to WDATA1 */
- write_wdata_from_array(param->buffer, 1, param->size, &bytes_written);
+ write_wdata_from_array(param->buffer, 1, param->size, (uint8_t *)&bytes_written);
}
/* Fill in the byte count for the command
@@ -241,7 +241,6 @@
{
uint32_t val = 0;
uint32_t error;
- uint32_t addr;
uint8_t bytes_read = 0;
/* Look up for pmic channel only for V2 hardware
@@ -382,7 +381,7 @@
{
pmic_irq_perph_id = periph_id;
- register_int_handler(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ , spmi_irq, 0);
+ register_int_handler(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ ,(int_handler)spmi_irq, 0);
unmask_interrupt(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ);
}
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
index 0a2eca0..2d74aa6 100644
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -119,11 +119,11 @@
*/
static unsigned int
msm_boot_uart_calculate_num_chars_to_write(char *data_in,
- uint32_t *num_of_chars)
+ uint32_t *num_of_chars)
{
- int i = 0, j = 0;
+ uint32_t i = 0, j = 0;
- if ((data_in == NULL) || (*num_of_chars < 0)) {
+ if ((data_in == NULL)) {
return MSM_BOOT_UART_DM_E_INVAL;
}
@@ -357,7 +357,7 @@
for (i = 0; i < (int)tx_word_count; i++) {
tx_char = (tx_char_left < 4) ? tx_char_left : 4;
- num_chars_written = pack_chars_into_words(tx_data, tx_char, &tx_word);
+ num_chars_written = pack_chars_into_words((uint8_t *)tx_data, tx_char, &tx_word);
/* Wait till TX FIFO has space */
while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXRDY)) {
diff --git a/platform/msm_shared/ucs.c b/platform/msm_shared/ucs.c
index 49ecf1b..3e7563a 100644
--- a/platform/msm_shared/ucs.c
+++ b/platform/msm_shared/ucs.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -37,8 +37,7 @@
int ucs_do_scsi_cmd(struct ufs_dev *dev, struct scsi_req_build_type *req)
{
struct upiu_req_build_type req_upiu;
- struct upiu_basic_hdr resp_upiu;
- int ret;
+ struct upiu_basic_resp_hdr resp_upiu;
memset(&req_upiu, 0 , sizeof(struct upiu_req_build_type));
@@ -68,9 +67,14 @@
{
if (resp_upiu.status == SCSI_STATUS_CHK_COND && (*((uint8_t *)(req->cdb)) != SCSI_CMD_SENSE_REQ))
{
- ret = ucs_do_request_sense(dev);
- if (ret)
- dprintf(CRITICAL, "SCSI request sense failed.\n");
+ dprintf(CRITICAL, "Data segment length: %x\n", BE16(resp_upiu.data_seg_len));
+ if (BE16(resp_upiu.data_seg_len))
+ {
+ dprintf(CRITICAL, "SCSI Request failed and we have sense data\n");
+ dprintf(CRITICAL, "Sense Data Length/Response Code: 0x%x/0x%x\n", BE16(resp_upiu.sense_length), BE16(resp_upiu.sense_response_code));
+ parse_sense_key(resp_upiu.sense_data[0]);
+ dprintf(CRITICAL, "Sense Buffer (HEX): 0x%x 0x%x 0x%x 0x%x\n", BE32(resp_upiu.sense_data[0]), BE32(resp_upiu.sense_data[1]), BE32(resp_upiu.sense_data[2]), BE32(resp_upiu.sense_data[3]));
+ }
}
dprintf(CRITICAL, "ucs_do_scsi_cmd failed status = %x\n", resp_upiu.status);
@@ -80,6 +84,57 @@
return UFS_SUCCESS;
}
+int parse_sense_key(uint32_t sense_data)
+{
+ uint32_t key = BE32(sense_data) >> 24;
+ dprintf(CRITICAL, "Sense Key: 0x%x\n", key);
+ switch(key)
+ {
+ case 0x0:
+ dprintf(INFO, "NO SENSE: No information available to be reported\n");
+ break;
+ case 0x1:
+ dprintf(INFO, "RECOVERED ERROR: Additional sense buffer bytes indicate further details\n");
+ break;
+ case 0x2:
+ dprintf(INFO, "NOT READY: Logical Unit Not Ready and cannot be accessed at this time\n");
+ break;
+ case 0x3:
+ dprintf(INFO, "MEDIUM ERROR: Last command unsuccessful due to non-recoverable error condition\n");
+ break;
+ case 0x4:
+ dprintf(INFO, "HARDWARE ERROR: Target detected a non-recoverable hardware error\n");
+ break;
+ case 0x5:
+ dprintf(INFO, "ILLEGAL REQUEST: Illegal parameter in the command descriptor block in the command sent\n");
+ break;
+ case 0x6:
+ dprintf(INFO, "UNIT ATTENTION: Unit has been reset/unexpectedly power on/removable media has changed\n");
+ break;
+ case 0x7:
+ dprintf(INFO, "DATA PROTECT: Read/Write operation attempted on a block that is protected from this operation\n");
+ break;
+ case 0x8:
+ dprintf(INFO, "BLANK CHECK: Target encountered blank or unformatted media while reading or writing\n");
+ break;
+ case 0x9:
+ dprintf(INFO, "VENDOR SPECIFIC: Vendor specific error or exceptional conditions\n");
+ break;
+ case 0xB:
+ dprintf(INFO, "ABORTED COMMAND: Target aborted the execution of the command\n");
+ break;
+ case 0xD:
+ dprintf(INFO, "VOLUME OVERFLOW: Buffered peripheral device has reached the end of partition\n");
+ break;
+ case 0xE:
+ dprintf(INFO, "MISCOMPARE: Source data did not match the data read from the media\n");
+ break;
+ default:
+ dprintf(INFO, "INVALID sense key\n");
+ }
+ return key;
+}
+
int ucs_do_scsi_rpmb_read(struct ufs_dev *dev, uint32_t *req_buf, uint32_t blk_cnt,
uint32_t *resp_buf, uint32_t *resp_len)
{
@@ -316,7 +371,9 @@
struct unmap_blk_desc *blk_desc;
param_list = (struct unmap_param_list *)param;
- param_list->data_len = (sizeof(struct unmap_param_list) - 1) << 0x8; /* n-1 */
+
+ // data length = size of unmap block descriptor struct (n-1) - size of data length field.
+ param_list->data_len = ((sizeof(struct unmap_param_list) - 1) - 1) << 0x8;
param_list->blk_desc_data_len = sizeof(struct unmap_blk_desc) << 0x8;
@@ -337,6 +394,7 @@
/* Flush cdb to memory. */
dsb();
arch_invalidate_cache_range((addr_t) cdb_param, SCSI_CDB_PARAM_LEN);
+ arch_invalidate_cache_range((addr_t) param, sizeof(struct unmap_param_list));
memset((void*)&req_upiu, 0 , sizeof(struct scsi_req_build_type));
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
index d8858b9..6f419cd 100644
--- a/platform/msm_shared/usb30_dwc.c
+++ b/platform/msm_shared/usb30_dwc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -879,8 +879,8 @@
{
case DWC_EVENT_EP_CMD_COMPLETE:
{
- dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
- DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ DBG("\n cmd = %s has no action. ignored.",
+ cmd_lookup[DWC_EVENT_EP_EVENT_CMD_TYPE(*event)]);
}
break;
case DWC_EVENT_EP_XFER_NOT_READY:
@@ -944,8 +944,8 @@
{
case DWC_EVENT_EP_CMD_COMPLETE:
{
- dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
- DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ DBG("\n cmd = %s has no action. ignored.",
+ cmd_lookup[DWC_EVENT_EP_EVENT_CMD_TYPE(*event)]);
}
break;
case DWC_EVENT_EP_XFER_NOT_READY:
@@ -1208,15 +1208,14 @@
static void dwc_event_handler_ep_bulk_state_inactive(dwc_dev_t *dev,
uint32_t *event)
{
- uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
- dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
switch (event_id)
{
case DWC_EVENT_EP_CMD_COMPLETE:
{
- DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ DBG("\n cmd = %s has no action. ignored.",
+ cmd_lookup[DWC_EVENT_EP_EVENT_CMD_TYPE(*event)]);
}
break;
case DWC_EVENT_EP_XFER_NOT_READY:
@@ -1584,6 +1583,7 @@
/* enable device event generation */
dwc_event_device_enable(dev, BIT(DWC_EVENT_DEVICE_EVENT_ID_DISCONNECT) |
BIT(DWC_EVENT_DEVICE_EVENT_ID_USB_RESET) |
+ BIT(DWC_EVENT_DEVICE_EVENT_ID_SUSPEND_ENTRY) |
BIT(DWC_EVENT_DEVICE_EVENT_ID_CONNECT_DONE));
/* 18.e initialize control end point
diff --git a/platform/msm_shared/usb30_dwc.h b/platform/msm_shared/usb30_dwc.h
index 5a43696..1a69a61 100644
--- a/platform/msm_shared/usb30_dwc.h
+++ b/platform/msm_shared/usb30_dwc.h
@@ -493,6 +493,7 @@
static enum handler_return dwc_irq_handler_ee1(void* arg);
static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index);
+void dwc_ep_cmd_clear_stall(dwc_dev_t *dev, uint8_t ep_phy_num);
static int dwc_request_queue(dwc_dev_t *dev, uint8_t ep_phy_num, dwc_request_t *req);
#endif
diff --git a/platform/msm_shared/usb30_dwc_hw.c b/platform/msm_shared/usb30_dwc_hw.c
index 86a10a9..7b69bbb 100644
--- a/platform/msm_shared/usb30_dwc_hw.c
+++ b/platform/msm_shared/usb30_dwc_hw.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013,2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -41,6 +41,7 @@
#include <usb30_dwc_hw.h>
#include <smem.h>
#include <board.h>
+#include <qmp_phy.h>
extern char* ss_link_state_lookup[20];
extern char* hs_link_state_lookup[20];
@@ -512,13 +513,15 @@
void dwc_phy_digital_reset(dwc_dev_t *dev)
{
REG_WRITE_FIELDI(dev, GUSB2PHYCFG, 0, PHYSOFTRST, 1);
- REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 1);
+ if (!use_hsonly_mode())
+ REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 1);
/* per HPG */
udelay(100);
REG_WRITE_FIELDI(dev, GUSB2PHYCFG, 0, PHYSOFTRST, 0);
- REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 0);
+ if (!use_hsonly_mode())
+ REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 0);
/* per HPG */
udelay(100);
diff --git a/platform/msm_shared/usb30_udc.c b/platform/msm_shared/usb30_udc.c
index cf27db9..0e5e1b0 100644
--- a/platform/msm_shared/usb30_udc.c
+++ b/platform/msm_shared/usb30_udc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -46,6 +46,7 @@
#include <smem.h>
#include <board.h>
#include <platform/timer.h>
+#include <qmp_phy.h>
//#define DEBUG_USB
@@ -232,13 +233,15 @@
/* 2. Put controller in reset */
dwc_reset(dwc, 1);
+
/* Steps 3 - 7 must be done while dwc is in reset condition */
/* 3. Reset PHY */
phy_reset(wrapper, dev_info);
/* 4. SS phy config */
- usb_wrapper_ss_phy_configure(wrapper);
+ if (!use_hsonly_mode())
+ usb_wrapper_ss_phy_configure(wrapper);
/* 5. HS phy init */
usb_wrapper_hs_phy_init(wrapper);
@@ -259,6 +262,10 @@
if (dev_info->t_usb_if->phy_init)
dev_info->t_usb_if->phy_init();
+ /* HS only mode support */
+ if (use_hsonly_mode())
+ usb_wrapper_hsonly_mode(wrapper);
+
/* 10. */
usb_wrapper_workaround_10(wrapper);
@@ -636,7 +643,7 @@
* |______|_____________|_____________|
*/
usb_epnum = (s.index & USB_EP_NUM_MASK);
- dir = (s.index & USB_EP_DIR_MASK == USB_EP_DIR_IN) ? 0x1 : 0x0;
+ dir = ((s.index & USB_EP_DIR_MASK) == USB_EP_DIR_IN) ? 0x1 : 0x0;
/*
* Convert the logical ep number to physical before
diff --git a/platform/msm_shared/usb30_wrapper.c b/platform/msm_shared/usb30_wrapper.c
index 7a83c2e..b6ca7ea 100644
--- a/platform/msm_shared/usb30_wrapper.c
+++ b/platform/msm_shared/usb30_wrapper.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -49,6 +49,7 @@
#include <platform/clock.h>
#include <usb30_wrapper.h>
#include <usb30_wrapper_hwio.h>
+#include <qmp_phy.h>
/* Configure DBM mode: by-pass or DBM */
@@ -166,7 +167,8 @@
REG_WRITE_FIELD(dev, HS_PHY_CTRL, SW_SESSVLD_SEL, 0x1);
/* Indicate power present to SS phy */
- REG_WRITE_FIELD(dev, SS_PHY_CTRL, LANE0_PWR_PRESENT, 0x1);
+ if (!use_hsonly_mode())
+ REG_WRITE_FIELD(dev, SS_PHY_CTRL, LANE0_PWR_PRESENT, 0x1);
}
/* API to read SS PHY registers */
@@ -252,3 +254,13 @@
{
REG_WRITE(dev, HS_PHY_CTRL_COMMON, 0x00001CB8);
}
+
+void usb_wrapper_hsonly_mode(usb_wrapper_dev_t *dev)
+{
+ REG_WRITE_FIELD(dev, GENERAL_CFG, PIPE_UTMI_CLK_DIS, 0x1);
+ udelay(1);
+ REG_WRITE_FIELD(dev, GENERAL_CFG, PIPE_UTMI_CLK_SEL, 0x1);
+ REG_WRITE_FIELD(dev, GENERAL_CFG, PIPE3_PHYSTATUS_SW, 0x1);
+ udelay(1);
+ REG_WRITE_FIELD(dev, GENERAL_CFG, PIPE_UTMI_CLK_DIS, 0x0);
+}
diff --git a/platform/msm_shared/usb30_wrapper.h b/platform/msm_shared/usb30_wrapper.h
index 5433e6f..25a3afa 100644
--- a/platform/msm_shared/usb30_wrapper.h
+++ b/platform/msm_shared/usb30_wrapper.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013,2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -65,5 +65,5 @@
void usb_wrapper_workaround_11(usb_wrapper_dev_t *dev);
void usb_wrapper_workaround_13(usb_wrapper_dev_t *dev);
void usb_wrapper_hs_phy_ctrl_force_write(usb_wrapper_dev_t *dev);
-
+void usb_wrapper_hsonly_mode(usb_wrapper_dev_t *dev);
#endif
diff --git a/platform/msm_shared/usb30_wrapper_hwio.h b/platform/msm_shared/usb30_wrapper_hwio.h
index 1b5c9f7..6afab35 100644
--- a/platform/msm_shared/usb30_wrapper_hwio.h
+++ b/platform/msm_shared/usb30_wrapper_hwio.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013,2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -120,6 +120,12 @@
#define HWIO_GENERAL_CFG_XHCI_REV_SHFT 0x2
#define HWIO_GENERAL_CFG_DBM_EN_BMSK 0x2
#define HWIO_GENERAL_CFG_DBM_EN_SHFT 0x1
+#define HWIO_GENERAL_CFG_PIPE_UTMI_CLK_DIS_BMSK 0x100
+#define HWIO_GENERAL_CFG_PIPE_UTMI_CLK_DIS_SHFT 0x8
+#define HWIO_GENERAL_CFG_PIPE_UTMI_CLK_SEL_BMSK 0x1
+#define HWIO_GENERAL_CFG_PIPE_UTMI_CLK_SEL_SHFT 0x0
+#define HWIO_GENERAL_CFG_PIPE3_PHYSTATUS_SW_BMSK 0x8
+#define HWIO_GENERAL_CFG_PIPE3_PHYSTATUS_SW_SHFT 0x3
#define HWIO_RAM1_REG_ADDR(x) ((x) + 0x0000000c)
#define HWIO_RAM1_REG_RMSK 0x7
diff --git a/platform/thulium/acpuclock.c b/platform/thulium/acpuclock.c
index 3b76b91..e2ee7d5 100644
--- a/platform/thulium/acpuclock.c
+++ b/platform/thulium/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -70,12 +70,16 @@
}
else if(freq == MMC_CLK_96MHZ)
{
- ret = clk_get_set_enable(clk_name, 100000000, true);
+ ret = clk_get_set_enable(clk_name, 96000000, true);
}
else if(freq == MMC_CLK_192MHZ)
{
ret = clk_get_set_enable(clk_name, 192000000, true);
}
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
else
{
dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
@@ -168,13 +172,20 @@
clock_usb30_gdsc_enable();
- ret = clk_get_set_enable("usb30_master_clk", 125000000, true);
+ ret = clk_get_set_enable("usb30_master_clk", 150000000, true);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
ASSERT(0);
}
+ ret = clk_get_set_enable("gcc_aggre2_usb3_axi_clk", 150000000, true);
+ if (ret)
+ {
+ dprintf(CRITICAL, "failed to set aggre2_usb3_axi_clk, ret = %d\n", ret);
+ ASSERT(0);
+ }
+
ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, true);
if(ret)
{
@@ -202,8 +213,6 @@
dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
ASSERT(0);
}
-
- pm8x41_lnbb_clock_ctrl(1);
}
void clock_bumpup_pipe3_clk()
diff --git a/platform/thulium/include/platform/iomap.h b/platform/thulium/include/platform/iomap.h
index a11db96..276841d 100644
--- a/platform/thulium/include/platform/iomap.h
+++ b/platform/thulium/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -38,6 +38,7 @@
#define MSM_SHARED_IMEM_BASE 0x066BF000
#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + 0x6B0)
#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
@@ -45,6 +46,12 @@
#define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000)
#define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS 0x00068000
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE 0x00006000
+
+#define APCS_HLOS_IPC_INTERRUPT_0 0x9820010
+
#define PERIPH_SS_BASE 0x07400000
#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000)
@@ -87,36 +94,37 @@
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
/* UART Clocks */
-#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x17004)
-#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x1C004)
-#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x1C00C)
-#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x1C010)
-#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x1C014)
-#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x1C018)
-#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x1C01C)
+#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x25004)
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29004)
+#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C)
+#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010)
+#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014)
+#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0x29018)
+#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0x2901C)
/* USB3 clocks */
#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
+#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008)
+#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
+#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014)
#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018)
#define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C)
#define USB30_MASTER_N (CLK_CTL_BASE + 0xF020)
#define USB30_MASTER_D (CLK_CTL_BASE + 0xF024)
+#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF028)
+#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF02C)
#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C)
-#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF014)
-#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF018)
-#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
-#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C)
#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010)
#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000)
#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004)
#define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020)
#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024)
-#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004)
+#define GCC_AGGRE2_USB3_AXI_CBCR (CLK_CTL_BASE + 0x83018)
/* SDCC */
#define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */
@@ -157,7 +165,7 @@
#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
/* DRV strength for sdcc */
-#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0003C000)
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0012C000)
/* SDHCI - power control registers */
#define SDCC_MCI_HC_MODE (0x00000078)
@@ -171,7 +179,13 @@
#define BOOT_CONFIG_OFFSET 0x00006044
#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
-/* Fix This */
-#define PLATFORM_QMP_OFFSET 0x8
+/* QMP rev registers */
+#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x788)
+#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x78C)
+#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x790)
+#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x794)
+
+/* Dummy macro needed for compilation only */
+#define PLATFORM_QMP_OFFSET 0x0
#endif
diff --git a/platform/thulium/include/platform/irqs.h b/platform/thulium/include/platform/irqs.h
index dd0f31a..696c83f 100644
--- a/platform/thulium/include/platform/irqs.h
+++ b/platform/thulium/include/platform/irqs.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -47,6 +47,8 @@
#define USB30_EE1_IRQ (GIC_SPI_START + 131)
+#define GLINK_IPC_IRQ (GIC_SPI_START + 168)
+
/* Retrofit universal macro names */
#define INT_USB_HS USB30_EE1_IRQ
diff --git a/platform/thulium/include/platform/partial_goods.h b/platform/thulium/include/platform/partial_goods.h
new file mode 100644
index 0000000..03c16ec
--- /dev/null
+++ b/platform/thulium/include/platform/partial_goods.h
@@ -0,0 +1,46 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <partial_goods.h>
+
+#define QFPROM_PTE_PART_ADDR 0x0007013C
+
+/* Look up table for partial goods */
+struct partial_goods table[] =
+{
+ {0x1, "/cpus", {{"cpu@100", "device_type"},}},
+ {0x2, "/cpus", {{"cpu@101", "device_type"},}},
+ {0x3, "/cpus", {{"cpu@100", "device_type"},
+ {"cpu@101","device_type"},}},
+ {0x4, "/cpus", {{"cpu@100", "device_type"},
+ {"cpu@101", "device_type"},
+ {"cpu@1", "device_type"},}},
+ {0x10, "/soc", {{"qcom,kgsl-3d0", "status"},}},
+ {0x11, "/soc", {{"qcom,vidc", "status"},}},
+ {0x12, "/soc", {{"qcom,msm-adsp-loader", "status"},}},
+};
diff --git a/platform/thulium/platform.c b/platform/thulium/platform.c
index 1dad8cc..be0678c 100644
--- a/platform/thulium/platform.c
+++ b/platform/thulium/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -130,3 +130,14 @@
{
return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
}
+
+addr_t get_bs_info_addr()
+{
+ return BS_INFO_ADDR;
+}
+
+uint32_t platform_get_qmp_rev()
+{
+ return readl(USB3_PHY_REVISION_ID3) << 24 | readl(USB3_PHY_REVISION_ID2) << 16 |
+ readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
+}
diff --git a/platform/thulium/thulium-clock.c b/platform/thulium/thulium-clock.c
index b02bec4..d0a23ed 100644
--- a/platform/thulium/thulium-clock.c
+++ b/platform/thulium/thulium-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -156,42 +156,42 @@
F_END
};
-static struct rcg_clk blsp1_uart2_apps_clk_src =
+static struct rcg_clk blsp2_uart2_apps_clk_src =
{
- .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+ .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "blsp1_uart2_apps_clk",
+ .dbg_name = "blsp2_uart2_apps_clk",
.ops = &clk_ops_rcg_mnd,
},
};
-static struct branch_clk gcc_blsp1_uart2_apps_clk =
+static struct branch_clk gcc_blsp2_uart2_apps_clk =
{
- .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
+ .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
+ .parent = &blsp2_uart2_apps_clk_src.c,
.c = {
- .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .dbg_name = "gcc_blsp2_uart2_apps_clk",
.ops = &clk_ops_branch,
},
};
-static struct vote_clk gcc_blsp1_ahb_clk = {
- .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+static struct vote_clk gcc_blsp2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
- .en_mask = BIT(17),
+ .en_mask = BIT(15),
.c = {
- .dbg_name = "gcc_blsp1_ahb_clk",
+ .dbg_name = "gcc_blsp2_ahb_clk",
.ops = &clk_ops_vote,
},
};
@@ -204,9 +204,9 @@
F( 20000000, gpll0, 15, 1, 2),
F( 25000000, gpll0, 12, 1, 2),
F( 50000000, gpll0, 12, 0, 0),
- F( 96000000, gpll4, 16, 0, 0),
- F(192000000, gpll4, 8, 0, 0),
- F(384000000, gpll4, 4, 0, 0),
+ F( 96000000, gpll4, 4, 0, 0),
+ F(192000000, gpll4, 2, 0, 0),
+ F(384000000, gpll4, 1, 0, 0),
F_END
};
@@ -261,7 +261,9 @@
};
static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = {
- F( 125000000, gpll0, 1, 5, 24),
+ F( 19200000, cxo, 1, 0, 0),
+ F( 120000000, gpll0, 5, 0, 0),
+ F( 150000000, gpll0, 4, 0, 0),
F_END
};
@@ -293,6 +295,16 @@
},
};
+static struct branch_clk gcc_aggre2_usb3_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_AGGRE2_USB3_AXI_CBCR,
+ .parent = &usb30_master_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_aggre2_usb3_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
F( 60000000, gpll0, 10, 0, 0),
F_END
@@ -398,11 +410,12 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
- CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
- CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+ CLK_LOOKUP("uart8_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart8_core_clk", gcc_blsp2_uart2_apps_clk.c),
/* USB30 clocks */
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("gcc_aggre2_usb3_axi_clk", gcc_aggre2_usb3_axi_clk.c),
CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
diff --git a/project/apq8064.mk b/project/apq8064.mk
index 1c483dd..7a105a1 100644
--- a/project/apq8064.mk
+++ b/project/apq8064.mk
@@ -6,7 +6,11 @@
MODULES += app/aboot
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
diff --git a/project/apq8084.mk b/project/apq8084.mk
index fb61eea..4ca01bd 100644
--- a/project/apq8084.mk
+++ b/project/apq8084.mk
@@ -32,6 +32,8 @@
DEFINES += ABOOT_FORCE_TAGS_ADDR=0x01e00000
DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x00080000
+DEFINES += USE_BOOTDEV_CMDLINE=1
+
ifeq ($(EMMC_BOOT),1)
DEFINES += _EMMC_BOOT=1
endif
diff --git a/project/fsm9010.mk b/project/fsm9010.mk
index 1fa0a02..7759f73 100644
--- a/project/fsm9010.mk
+++ b/project/fsm9010.mk
@@ -6,9 +6,15 @@
MODULES += app/aboot
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
+
EMMC_BOOT := 1
-ENABLE_SDHCI_SUPPORT := 0
+ENABLE_SDHCI_SUPPORT := 1
+ENABLE_USB30_SUPPORT := 1
DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
@@ -28,3 +34,7 @@
ifeq ($(ENABLE_SDHCI_SUPPORT),1)
DEFINES += MMC_SDHCI_SUPPORT=1
endif
+
+ifeq ($(ENABLE_USB30_SUPPORT),1)
+DEFINES += USB30_SUPPORT=1
+endif
diff --git a/project/fsm9900.mk b/project/fsm9900.mk
index 993b34a..0f91c53 100644
--- a/project/fsm9900.mk
+++ b/project/fsm9900.mk
@@ -6,7 +6,12 @@
MODULES += app/aboot
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
+
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
diff --git a/project/mdm9625.mk b/project/mdm9625.mk
index b9b72aa..f0c4821 100644
--- a/project/mdm9625.mk
+++ b/project/mdm9625.mk
@@ -6,7 +6,11 @@
MODULES += app/aboot
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
diff --git a/project/mdm9635.mk b/project/mdm9635.mk
index e83f0c1..1be7653 100644
--- a/project/mdm9635.mk
+++ b/project/mdm9635.mk
@@ -6,7 +6,11 @@
MODULES += app/aboot
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
diff --git a/project/msmzirc.mk b/project/mdm9640.mk
similarity index 70%
rename from project/msmzirc.mk
rename to project/mdm9640.mk
index 3cec784..24addd8 100644
--- a/project/msmzirc.mk
+++ b/project/mdm9640.mk
@@ -1,10 +1,15 @@
-# top level project rules for the msmzirc project
+# top level project rules for the mdm9640 project
#
LOCAL_DIR := $(GET_LOCAL_DIR)
-TARGET := msmzirc
+TARGET := mdm9640
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
+
ENABLE_USB30_SUPPORT := 1
ENABLE_SDHCI_SUPPORT := 1
ENABLE_BOOT_CONFIG_SUPPORT := 1
@@ -19,6 +24,7 @@
DEFINES += BAM_V170=1
DEFINES += USE_BOOTDEV_CMDLINE=1
DEFINES += USE_MDM_BOOT_CFG=1
+DEFINES += USE_TARGET_HS200_CAPS=1
ifeq ($(ENABLE_USB30_SUPPORT),1)
DEFINES += USB30_SUPPORT=1
@@ -33,3 +39,11 @@
#Override linker for mdm targets
LD := $(TOOLCHAIN_PREFIX)ld.bfd
+
+ENABLE_SMD_SUPPORT := 1
+ifeq ($(ENABLE_SMD_SUPPORT),1)
+DEFINES += SMD_SUPPORT=1
+endif
+
+# Turn on Werror
+CFLAGS += -Werror
diff --git a/project/msm8909.mk b/project/msm8909.mk
index 410e13a..afc40f6 100644
--- a/project/msm8909.mk
+++ b/project/msm8909.mk
@@ -14,13 +14,13 @@
EMMC_BOOT := 1
-#ENABLE_SMD_SUPPORT := 1
-ENABLE_BOOT_CONFIG_SUPPORT := 1
+ENABLE_SMD_SUPPORT := 1
ENABLE_PWM_SUPPORT := true
+#ENABLE_BOOT_CONFIG_SUPPORT := 1
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_LOG_BUF=1
-DEFINES += WITH_DEBUG_UART=1
+DEFINES += WITH_DEBUG_UART=0
#DEFINES += WITH_DEBUG_FBCON=1
DEFINES += DEVICE_TREE=1
#DEFINES += MMC_BOOT_BAM=1
@@ -61,3 +61,7 @@
ifeq ($(ENABLE_SMD_SUPPORT),1)
DEFINES += SMD_SUPPORT=1
endif
+
+ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT),1)
+DEFINES += BOOT_CONFIG_SUPPORT=1
+endif
diff --git a/project/msm8994.mk b/project/msm8994.mk
index 26b097e..f797e77 100644
--- a/project/msm8994.mk
+++ b/project/msm8994.mk
@@ -34,6 +34,7 @@
DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x00080000
DEFINES += ENABLE_XPU_VIOLATION=1
+DEFINES += USE_BOOTDEV_CMDLINE=1
#Disable thumb mode
ENABLE_THUMB := false
@@ -61,3 +62,12 @@
ifeq ($(ENABLE_SMD_SUPPORT),1)
DEFINES += SMD_SUPPORT=1
endif
+
+ifeq ($(ENABLE_MDTP_SUPPORT),1)
+DEFINES += MDTP_SUPPORT=1
+DEFINES += MDTP_EFUSE_ADDRESS=0xFC4B81F8 # QFPROM_RAW_SPARE_REG19_LSB
+DEFINES += MDTP_EFUSE_START=17
+endif
+
+# Turn on Werror
+CFLAGS += -Werror
diff --git a/project/thulium.mk b/project/thulium.mk
index d1ece21..05e764f 100644
--- a/project/thulium.mk
+++ b/project/thulium.mk
@@ -6,13 +6,19 @@
MODULES += app/aboot
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
DEBUG := 1
+endif
+
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
ENABLE_UFS_SUPPORT := 1
ENABLE_BOOT_CONFIG_SUPPORT := 1
ENABLE_USB30_SUPPORT := 1
ENABLE_QGIC3 := 1
+ENABLE_PARTIAL_GOODS_SUPPORT := 1
DEFINES +=VIRTIO=1
@@ -24,11 +30,12 @@
DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
-DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x00008000
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80008000
DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82200000
DEFINES += ABOOT_FORCE_TAGS_ADDR=0x82000000
DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x80080000
DEFINES += USB_RESET_FROM_CLK=1
+DEFINES += USE_BOOTDEV_CMDLINE=1
#Disable thumb mode
ENABLE_THUMB := false
@@ -48,3 +55,9 @@
ifeq ($(ENABLE_USB30_SUPPORT),1)
DEFINES += USB30_SUPPORT=1
endif
+
+ifeq ($(ENABLE_PARTIAL_GOODS_SUPPORT),1)
+DEFINES += ENABLE_PARTIAL_GOODS_SUPPORT=1
+endif
+
+CFLAGS += -Werror
diff --git a/scripts/buildall b/scripts/buildall
index 906ee0c..c355387 100755
--- a/scripts/buildall
+++ b/scripts/buildall
@@ -1,6 +1,6 @@
#!/bin/sh
-PROJECTS="armemu-test sam7ex256-test osk5912-test qemu-arm-test beagle-test surf-test"
+PROJECTS="msm8226 msm8974 apq8084 msm8994 mdm9630 mdm9640 msm8610 msm8916 thulium"
FAILED=""
for p in $PROJECTS; do
diff --git a/target/apq8084/include/target/display.h b/target/apq8084/include/target/display.h
index c1d78f0..d4cf4bd 100644
--- a/target/apq8084/include/target/display.h
+++ b/target/apq8084/include/target/display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -119,9 +119,9 @@
static const char panel_lane_config[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
};
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index 6aa3b33..543951e 100755
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -285,13 +285,17 @@
platform_read_boot_config();
+#ifdef MMC_SDHCI_SUPPORT
if (platform_boot_dev_isemmc())
target_sdc_init();
- else
+#endif
+#ifdef UFS_SUPPORT
+ if(!platform_boot_dev_isemmc())
{
ufs_device.base = UFS_BASE;
ufs_init(&ufs_device);
}
+#endif
/* Storage initialization is complete, read the partition table info */
if (partition_read_table())
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index b077038..b46ef08 100755
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -44,6 +44,7 @@
#include <target/display.h>
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define HFPLL_LDO_ID 12
@@ -177,9 +178,9 @@
mdp_gdsc_ctrl(0);
return ret;
}
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(DSI0_PLL_BASE);
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ dsi_pll_enable_seq(pinfo->mipi.pll_0_base);
mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
@@ -506,7 +507,9 @@
void target_display_init(const char *panel_name)
{
uint32_t ret = 0;
+ char cont_splash = '\0';
+ set_panel_cmd_string(panel_name, &cont_splash);
panel_name += strspn(panel_name, " ");
if (!strcmp(panel_name, NO_PANEL_CONFIG)
@@ -528,6 +531,11 @@
target_force_cont_splash_disable(true);
msm_display_off();
}
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/fsm9010/init.c b/target/fsm9010/init.c
index 8f3da01..7e47d47 100644
--- a/target/fsm9010/init.c
+++ b/target/fsm9010/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -50,6 +50,8 @@
#include <platform/gpio.h>
#include <platform/timer.h>
#include <stdlib.h>
+#include <string.h>
+#include <sdhci_msm.h>
extern bool target_use_signed_kernel(void);
static void set_sdc_power_ctrl();
@@ -91,7 +93,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(2, 0, BLSP1_UART2_BASE);
+ uart_dm_init(3, 0, BLSP1_UART3_BASE);
#endif
}
@@ -155,31 +157,39 @@
}
#if MMC_SDHCI_SUPPORT
+
static void target_mmc_sdhci_init()
{
- struct mmc_config_data config = {0};
+ static uint32_t mmc_clks[] = {
+ MMC_CLK_200MHZ, MMC_CLK_96MHZ, MMC_CLK_50MHZ };
+ struct mmc_config_data config;
+ unsigned int i;
+
+ memset(&config, 0, sizeof config);
config.bus_width = DATA_BUS_WIDTH_8BIT;
- config.max_clk_rate = MMC_CLK_96MHZ;
/* Trying Slot 1*/
config.slot = 1;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.hs400_support = 0;
- if (!(dev = mmc_init(&config))) {
+ for (i = 0; i < ARRAY_SIZE(mmc_clks); ++i) {
+ config.max_clk_rate = mmc_clks[i];
+ dprintf(INFO, "SDHC Running at %u MHz\n",
+ config.max_clk_rate / 1000000);
+ dev = mmc_init(&config);
+ if (dev && partition_read_table() == 0)
+ return;
+ }
+
+ if (dev == NULL)
dprintf(CRITICAL, "mmc init failed!");
- ASSERT(0);
- }
-
- /*
- * MMC initialization is complete, read the partition table info
- */
- if (partition_read_table()) {
+ else
dprintf(CRITICAL, "Error reading the partition table info\n");
- ASSERT(0);
- }
+ ASSERT(0);
}
void *target_mmc_device()
@@ -347,34 +357,6 @@
return 0;
}
-/* Check if MSM needs VBUS mimic for USB */
-static int target_needs_vbus_mimic()
-{
- return 1;
-}
-
-/* Do target specific usb initialization */
-void target_usb_init(void)
-{
- uint32_t val;
-
- extern void ulpi_write(unsigned val, unsigned reg);
-
- if (target_needs_vbus_mimic()) {
- /* Select and enable external configuration with USB PHY */
- ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
-
- /* Enable sess_vld */
- val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
- writel(val, USB_GENCONFIG_2);
-
- /* Enable external vbus configuration in the LINK */
- val = readl(USB_USBCMD);
- val |= SESS_VLD_CTRL;
- writel(val, USB_USBCMD);
- }
-}
-
/* Returns 1 if target supports continuous splash screen. */
int target_cont_splash_screen()
{
@@ -390,6 +372,7 @@
{
#if MMC_SDHCI_SUPPORT
mmc_put_card_to_sleep(dev);
+ sdhci_mode_disable(&dev->host);
#else
mmc_put_card_to_sleep();
#endif
@@ -412,17 +395,41 @@
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
- { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ {
+ off: SDC1_CLK_HDRV_CTL_OFF,
+ val: TLMM_CUR_VAL_10MA,
+ mask: TLMM_HDRV_MASK
+ },
+ {
+ off: SDC1_CMD_HDRV_CTL_OFF,
+ val: TLMM_CUR_VAL_10MA,
+ mask: TLMM_HDRV_MASK
+ },
+ {
+ off: SDC1_DATA_HDRV_CTL_OFF,
+ val: TLMM_CUR_VAL_10MA,
+ mask: TLMM_HDRV_MASK
+ },
};
/* Pull configs for sdc pins */
struct tlmm_cfgs sdc1_pull_cfg[] =
{
- { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
- { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
- { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ {
+ off: SDC1_CLK_PULL_CTL_OFF,
+ val: TLMM_NO_PULL,
+ mask: TLMM_PULL_MASK
+ },
+ {
+ off: SDC1_CMD_PULL_CTL_OFF,
+ val: TLMM_PULL_UP,
+ mask: TLMM_PULL_MASK
+ },
+ {
+ off: SDC1_DATA_PULL_CTL_OFF,
+ val: TLMM_PULL_UP,
+ mask: TLMM_PULL_MASK
+ },
};
/* Set the drive strength & pull control values */
@@ -437,6 +444,92 @@
return _emmc_recovery_init();
}
+#define USB30_QSCRATCH_GENERAL_CFG (MSM_USB30_QSCRATCH_BASE + 0x08)
+#define USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_SEL (1 << 0)
+#define USB30_QSCRATCH_GENERAL_CFG_PIPE3_PHYSTATUS_SW (1 << 3)
+#define USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_DIS (1 << 8)
+
+#define CM_DWC_USB2_USB_PHY_UTMI_CTRL5 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x74)
+#define CM_DWC_USB2_USB_PHY_HS_PHY_CTRL_COMMON0 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x78)
+#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X0 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x98)
+#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X1 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x9c)
+#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X2 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0xa0)
+#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X3 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0xa4)
+#define CM_DWC_USB2_USB_PHY_REFCLK_CTRL (CM_DWC_USB2_CM_DWC_USB2_BASE + 0xe8)
+
+void target_usb_phy_mux_configure(void)
+{
+}
+
+void target_usb_phy_init(void)
+{
+ uint32_t val;
+
+ /* Disable clock */
+ val = readl(USB30_QSCRATCH_GENERAL_CFG);
+ val |= USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_DIS;
+ writel(val, USB30_QSCRATCH_GENERAL_CFG);
+ mdelay(1);
+
+ /* Select UTMI instead of PIPE3 */
+ val |= USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_SEL;
+ writel(val, USB30_QSCRATCH_GENERAL_CFG);
+ val |= USB30_QSCRATCH_GENERAL_CFG_PIPE3_PHYSTATUS_SW;
+ writel(val, USB30_QSCRATCH_GENERAL_CFG);
+ mdelay(1);
+
+ /* Enable clock */
+ val &= ~USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_DIS;
+ writel(val, USB30_QSCRATCH_GENERAL_CFG);
+
+ /* Initialize HS PICO PHY */
+ writel(0xc4, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X0);
+ writel(0x88, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X1);
+ writel(0x11, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X2);
+ writel(0x03, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X3);
+
+ writel(0x02, CM_DWC_USB2_USB_PHY_UTMI_CTRL5);
+ mdelay(1);
+ writel(0x00, CM_DWC_USB2_USB_PHY_UTMI_CTRL5);
+
+ val = readl(CM_DWC_USB2_USB_PHY_REFCLK_CTRL);
+ val &= ~(7 << 1);
+ val |= (6 << 1);
+ writel(val, CM_DWC_USB2_USB_PHY_REFCLK_CTRL);
+
+ val = readl(CM_DWC_USB2_USB_PHY_HS_PHY_CTRL_COMMON0);
+ val &= ~(7 << 4);
+ val |= (7 << 4);
+ writel(val, CM_DWC_USB2_USB_PHY_HS_PHY_CTRL_COMMON0);
+}
+
+void target_usb_phy_reset(void)
+{
+}
+
+target_usb_iface_t* target_usb30_init()
+{
+ target_usb_iface_t *t_usb_iface;
+
+ t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
+ ASSERT(t_usb_iface);
+
+ t_usb_iface->mux_config = target_usb_phy_mux_configure;
+ t_usb_iface->phy_init = target_usb_phy_init;
+ t_usb_iface->phy_reset = target_usb_phy_reset;
+ t_usb_iface->clock_init = clock_usb30_init;
+ t_usb_iface->vbus_override = 1;
+
+ return t_usb_iface;
+}
+
+/* identify the usb controller to be used for the target */
+const char * target_usb_controller()
+{
+ return "dwc";
+}
+
+/* configure hs phy mux if using dwc controller */
void target_usb_stop(void)
{
}
diff --git a/target/fsm9010/meminfo.c b/target/fsm9010/meminfo.c
index c6dd53e..fa0f96a 100644
--- a/target/fsm9010/meminfo.c
+++ b/target/fsm9010/meminfo.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -90,6 +90,6 @@
unsigned target_get_max_flash_size(void)
{
- return (512 * 1024 * 1024);
+ return (86 * 1024 * 1024);
}
#endif /* DEVICE_TREE */
diff --git a/target/fsm9010/rules.mk b/target/fsm9010/rules.mk
index 36cdc57..17a1b1d 100644
--- a/target/fsm9010/rules.mk
+++ b/target/fsm9010/rules.mk
@@ -4,7 +4,7 @@
PLATFORM := fsm9010
-MEMBASE := 0x0F900000 # SDRAM
+MEMBASE := 0x18a00000 # SDRAM
MEMSIZE := 0x00100000 # 1MB
BASE_ADDR := 0x0b600000
@@ -12,12 +12,13 @@
TAGS_ADDR := BASE_ADDR+0x01e00000
KERNEL_ADDR := BASE_ADDR+0x00008000
RAMDISK_ADDR := BASE_ADDR+0x02000000
-SCRATCH_ADDR := 0x0ff00000
+SCRATCH_ADDR := 0x0e000000
MODULES += \
dev/keys \
- lib/ptable \
- lib/libfdt
+ lib/ptable \
+ lib/libfdt \
+ dev/pmic/pm8x41
DEFINES += \
MEMSIZE=$(MEMSIZE) \
diff --git a/target/fsm9900/init.c b/target/fsm9900/init.c
index aff6aa6..cc06e0e 100644
--- a/target/fsm9900/init.c
+++ b/target/fsm9900/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -342,6 +342,7 @@
case FSM9915:
case FSM9950:
case FSM9955:
+ case FSM9916:
board->baseband = BASEBAND_MSM;
break;
default:
@@ -369,7 +370,7 @@
uint32_t restart_reason = 0;
uint32_t restart_reason_addr;
- restart_reason_addr = RESTART_REASON_ADDR;
+ restart_reason_addr = RESTART_REASON_ADDR_V2;
/* Read reboot reason and scrub it */
restart_reason = readl(restart_reason_addr);
@@ -381,7 +382,7 @@
void reboot_device(unsigned reboot_reason)
{
/* Write the reboot reason */
- writel(reboot_reason, RESTART_REASON_ADDR);
+ writel(reboot_reason, RESTART_REASON_ADDR_V2);
/* Disable Watchdog Debug.
* Required becuase of a H/W bug which causes the system to
diff --git a/target/fsm9900/rules.mk b/target/fsm9900/rules.mk
index 0416f39..e4909eb 100644
--- a/target/fsm9900/rules.mk
+++ b/target/fsm9900/rules.mk
@@ -4,15 +4,15 @@
PLATFORM := fsm9900
-MEMBASE := 0x0F900000 # SDRAM
+MEMBASE := 0x1e000000 # SDRAM
MEMSIZE := 0x00100000 # 1MB
-BASE_ADDR := 0x00000
+BASE_ADDR := 0x0b600000
TAGS_ADDR := BASE_ADDR+0x00000100
KERNEL_ADDR := BASE_ADDR+0x00008000
RAMDISK_ADDR := BASE_ADDR+0x01000000
-SCRATCH_ADDR := 0x11000000
+SCRATCH_ADDR := 0x0c000000
MODULES += \
dev/keys \
diff --git a/target/init.c b/target/init.c
index 79e0466..97809cc 100644
--- a/target/init.c
+++ b/target/init.c
@@ -1,6 +1,8 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
@@ -52,6 +54,11 @@
return (120 * 1024 * 1024);
}
+__WEAK int flash_ubi_img(void)
+{
+ return 0;
+}
+
__WEAK int target_is_emmc_boot(void)
{
#if _EMMC_BOOT
@@ -66,6 +73,11 @@
return 0;
}
+__WEAK unsigned check_hard_reboot_mode(void)
+{
+ return 0;
+}
+
__WEAK void reboot_device(unsigned reboot_reason)
{
}
@@ -204,3 +216,13 @@
{
return DDR_CONFIG_VAL;
}
+
+/* Return Build variant */
+__WEAK bool target_build_variant_user()
+{
+#if USER_BUILD_VARIANT
+ return true;
+#else
+ return false;
+#endif
+}
diff --git a/target/msmzirc/init.c b/target/mdm9640/init.c
similarity index 89%
rename from target/msmzirc/init.c
rename to target/mdm9640/init.c
index c96ac33..91c61ef 100644
--- a/target/msmzirc/init.c
+++ b/target/mdm9640/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -34,6 +34,7 @@
#include <baseband.h>
#include <lib/ptable.h>
#include <qpic_nand.h>
+#include <malloc.h>
#include <ctype.h>
#include <string.h>
#include <pm8x41.h>
@@ -46,6 +47,13 @@
#include <platform/clock.h>
#include <qmp_phy.h>
#include <qusb2_phy.h>
+#include <rpm-smd.h>
+#include <scm.h>
+#include <spmi.h>
+#include <partition_parser.h>
+#include <sdhci_msm.h>
+#include <uart_dm.h>
+#include <boot_device.h>
extern void smem_ptable_init(void);
extern void smem_add_modem_partitions(struct ptable *flash_ptable);
@@ -75,7 +83,7 @@
#define LAST_NAND_PTN_LEN_PATTERN 0xFFFFFFFF
-#define EXT4_CMDLINE " rootfstype=ext4 root=/dev/mmcblk0p"
+#define EXT4_CMDLINE " rootwait rootfstype=ext4 root=/dev/mmcblk0p"
#define UBI_CMDLINE " rootfstype=ubifs rootflags=bulk_read ubi.fm_autoconvert=1"
struct qpic_nand_init_config config;
@@ -84,7 +92,6 @@
{
uint32_t ptn_index;
struct ptentry *ptentry_ptr = flash_ptable.parts;
- struct ptentry *boot_ptn;
unsigned i;
uint32_t len;
@@ -261,9 +268,8 @@
}
snprintf(buf, buflen, EXT4_CMDLINE"%d", system_ptn_index);
}
-
- return 0;
}
+ return 0;
}
const char * target_usb_controller()
@@ -276,17 +282,17 @@
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
- { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
- { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, 0 },
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, 0 },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK, 0 },
};
/* Pull configs for sdc pins */
struct tlmm_cfgs sdc1_pull_cfg[] =
{
- { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
- { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
- { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, 0 },
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0 },
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0 },
};
/* Set the drive strength & pull control values */
@@ -309,12 +315,13 @@
set_sdc_power_ctrl();
config.slot = 1;
- config.bus_width = DATA_BUS_WIDTH_4BIT;
+ config.bus_width = DATA_BUS_WIDTH_8BIT;
config.max_clk_rate = MMC_CLK_200MHZ;
config.sdhc_base = MSM_SDC1_SDHCI_BASE;
config.pwrctl_base = MSM_SDC1_BASE;
config.pwr_irq = SDCC1_PWRCTL_IRQ;
config.hs400_support = 0;
+ config.hs200_support = 0;
config.use_io_switch = 1;
if (!(dev = mmc_init(&config))) {
@@ -323,6 +330,12 @@
}
}
+int target_cont_splash_screen()
+{
+ /* FOR OEMs - Set cont_splash_screen to keep the splash enable after LK.*/
+ return false;
+}
+
void target_uninit(void)
{
if (platform_boot_dev_isemmc())
@@ -342,7 +355,7 @@
{
target_usb_iface_t *t_usb_iface;
- t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
+ t_usb_iface = (target_usb_iface_t *) calloc(1, sizeof(target_usb_iface_t));
ASSERT(t_usb_iface);
t_usb_iface->mux_config = NULL;
diff --git a/target/msmzirc/keypad.c b/target/mdm9640/keypad.c
similarity index 100%
rename from target/msmzirc/keypad.c
rename to target/mdm9640/keypad.c
diff --git a/target/msmzirc/meminfo.c b/target/mdm9640/meminfo.c
similarity index 100%
rename from target/msmzirc/meminfo.c
rename to target/mdm9640/meminfo.c
diff --git a/target/mdm9640/qpic_panel_drv.c b/target/mdm9640/qpic_panel_drv.c
new file mode 100755
index 0000000..2c1f776
--- /dev/null
+++ b/target/mdm9640/qpic_panel_drv.c
@@ -0,0 +1,183 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <endian.h>
+#include <platform/gpio.h>
+#include <platform/clock.h>
+#include <regulator.h>
+#include <rpm-smd.h>
+#include <platform/timer.h>
+
+#include "qpic.h"
+#include "qpic_panel.h"
+
+#define GPIOMUX_FUNC_2 2
+#define GPIOMUX_FUNC_GPIO 0
+
+#define RST_GPIO_ID 23
+#define CS_GPIO_ID 21
+#define AD8_GPIO_ID 20
+#define TE_GPIO_ID 22
+#define BL_GPIO_ID 68
+
+#define MEM_ACCESS_MODE 0x48
+#define MEM_ACCESS_FORMAT 0x66
+
+static uint32_t ldo6[][11] = {
+ {
+ LDOA_RES_TYPE, 6,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+ KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+ KEY_MICRO_VOLT, 4, 0,
+ },
+ {
+ LDOA_RES_TYPE, 6,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+ KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+ KEY_MICRO_VOLT, 4, 1800000,
+ },
+};
+
+static uint32_t ldo12[][11] = {
+ {
+ LDOA_RES_TYPE, 12,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+ KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+ KEY_MICRO_VOLT, 4, 0,
+ },
+ {
+ LDOA_RES_TYPE, 12,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+ KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+ KEY_MICRO_VOLT, 4, 2700000,
+ },
+};
+
+static void panel_io_off(struct qpic_panel_io_desc *qpic_panel_io)
+{
+ /* Turning off all gpios */
+ gpio_tlmm_config(RST_GPIO_ID, GPIOMUX_FUNC_2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_tlmm_config(CS_GPIO_ID, GPIOMUX_FUNC_2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_tlmm_config(AD8_GPIO_ID, GPIOMUX_FUNC_2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_tlmm_config(TE_GPIO_ID, GPIOMUX_FUNC_2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_tlmm_config(BL_GPIO_ID, GPIOMUX_FUNC_GPIO, GPIO_INPUT,GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_set(BL_GPIO_ID, 0x0);
+
+ /* Disabling vdd & avdd voltage */
+ rpm_send_data(&ldo6[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE);
+ rpm_send_data(&ldo12[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE);
+
+ return;
+}
+
+static int panel_io_on(struct qpic_panel_io_desc *qpic_panel_io)
+{
+ int rc = 0;
+
+ /* Setting vdd & avdd voltage */
+ rpm_send_data(&ldo6[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+ rpm_send_data(&ldo12[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+
+ /* Turning on all gpios */
+ gpio_tlmm_config(RST_GPIO_ID, GPIOMUX_FUNC_2, GPIO_INPUT,GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_tlmm_config(CS_GPIO_ID, GPIOMUX_FUNC_2, GPIO_INPUT,GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_tlmm_config(AD8_GPIO_ID, GPIOMUX_FUNC_2, GPIO_INPUT,GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_tlmm_config(TE_GPIO_ID, GPIOMUX_FUNC_2, GPIO_INPUT,GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_tlmm_config(BL_GPIO_ID, GPIOMUX_FUNC_GPIO, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_set(BL_GPIO_ID, 0x2);
+ mdelay(20);
+ return rc;
+}
+
+void ili9341_off(struct qpic_panel_io_desc *qpic_panel_io)
+{
+ panel_io_off(qpic_panel_io);
+}
+
+int ili9341_on(struct qpic_panel_io_desc *qpic_panel_io)
+{
+ uint8_t param[4];
+ int ret;
+
+ ret = panel_io_on(qpic_panel_io);
+ if (ret)
+ return ret;
+ qpic_send_pkt(OP_SOFT_RESET, NULL, 0);
+ /* wait for 120 ms after reset as panel spec suggests */
+ mdelay(120);
+ qpic_send_pkt(OP_SET_DISPLAY_OFF, NULL, 0);
+ /* wait for 20 ms after disply off */
+ mdelay(20);
+
+ /* set memory access control */
+ param[0] = MEM_ACCESS_MODE;
+ qpic_send_pkt(OP_SET_ADDRESS_MODE, param, 1);
+ /* wait for 20 ms after command sent as panel spec suggests */
+ mdelay(20);
+
+ param[0] = MEM_ACCESS_FORMAT;
+ qpic_send_pkt(OP_SET_PIXEL_FORMAT, param, 1);
+ mdelay(20);
+
+ /* set interface */
+ param[0] = 1;
+ param[1] = 0;
+ param[2] = 0;
+ qpic_send_pkt(OP_ILI9341_INTERFACE_CONTROL, param, 3);
+ mdelay(20);
+
+ qpic_send_pkt(OP_EXIT_SLEEP_MODE, NULL, 0);
+ mdelay(20);
+
+ qpic_send_pkt(OP_ENTER_NORMAL_MODE, NULL, 0);
+ mdelay(20);
+
+ qpic_send_pkt(OP_SET_DISPLAY_ON, NULL, 0);
+ mdelay(20);
+
+ param[0] = 0;
+ qpic_send_pkt(OP_ILI9341_TEARING_EFFECT_LINE_ON, param, 1);
+
+ param[0] = qpic_read_data(OP_GET_PIXEL_FORMAT, 1);
+
+ return 0;
+}
+
diff --git a/target/msmzirc/rules.mk b/target/mdm9640/rules.mk
similarity index 84%
rename from target/msmzirc/rules.mk
rename to target/mdm9640/rules.mk
index 7a19970..84d1417 100644
--- a/target/msmzirc/rules.mk
+++ b/target/mdm9640/rules.mk
@@ -2,9 +2,9 @@
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
-PLATFORM := msmzirc
+PLATFORM := mdm9640
-MEMBASE := 0x81200000
+MEMBASE := 0x87C00000
MEMSIZE := 0x00100000 # 1MB
BASE_ADDR := 0x80000000
SCRATCH_ADDR := 0x80000000
@@ -15,15 +15,17 @@
KERNEL_REGION := 0x80000000
KERNEL_REGION_SIZE := 0x01200000 # 18MB
-
+DEFINES += DISPLAY_SPLASH_SCREEN=0
DEFINES += NO_KEYPAD_DRIVER=1
DEFINES += PERIPH_BLK_BLSP=1
+DEVS += fbcon
MODULES += \
dev/keys \
lib/ptable \
dev/pmic/pm8x41 \
- lib/libfdt
+ lib/libfdt \
+ dev/fbcon
DEFINES += \
MEMBASE=$(MEMBASE) \
@@ -41,4 +43,6 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/qpic_panel_drv.o \
$(LOCAL_DIR)/keypad.o
diff --git a/target/mdm9640/target_display.c b/target/mdm9640/target_display.c
new file mode 100644
index 0000000..1c2ee68
--- /dev/null
+++ b/target/mdm9640/target_display.c
@@ -0,0 +1,76 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <msm_panel.h>
+#include <rpm-smd.h>
+
+/* PANEL INFO */
+#define HVGA_PANEL_XRES 320
+#define HVGA_PANEL_YRES 480
+#define BPP_16 16
+
+/* FB Base Address */
+#define QPIC_FB_ADDR 0x80000000
+
+static struct msm_fb_panel_data panel;
+extern int msm_display_init(struct msm_fb_panel_data *pdata);
+extern int msm_display_off();
+
+void target_display_init(const char *panel_name)
+{
+ uint32_t ret = 0;
+ dprintf(SPEW, "%s: Panel name = %s\n", __func__, panel_name);
+
+ /* Setting panel info */
+ panel.panel_info.xres = HVGA_PANEL_XRES;
+ panel.panel_info.yres = HVGA_PANEL_YRES;
+ panel.panel_info.bpp = BPP_16;
+ panel.panel_info.type = QPIC_PANEL;
+
+ /* Setting FB info */
+ panel.fb.width = panel.panel_info.xres;
+ panel.fb.height = panel.panel_info.yres;
+ panel.fb.stride = panel.panel_info.xres;
+ panel.fb.bpp = panel.panel_info.bpp;
+ panel.fb.format = FB_FORMAT_RGB565;
+ panel.fb.base = (void *) QPIC_FB_ADDR;
+
+ rpm_smd_init();
+ ret = msm_display_init(&panel);
+ if (ret)
+ dprintf(CRITICAL, "%s: ERROR: Display init failed\n", __func__);
+}
+
+void target_display_shutdown(void)
+{
+ msm_display_off();
+ rpm_smd_uninit();
+}
diff --git a/target/msmzirc/tools/makefile b/target/mdm9640/tools/makefile
similarity index 100%
rename from target/msmzirc/tools/makefile
rename to target/mdm9640/tools/makefile
diff --git a/target/msm8226/include/target/display.h b/target/msm8226/include/target/display.h
index 91d1e57..08531a1 100755
--- a/target/msm8226/include/target/display.h
+++ b/target/msm8226/include/target/display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -82,9 +82,9 @@
static const char panel_lane_config[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
};
diff --git a/target/msm8226/oem_panel.c b/target/msm8226/oem_panel.c
index 3d944b6..354c08e 100755
--- a/target/msm8226/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -95,16 +95,16 @@
int ret = NO_ERROR;
switch (panel_id) {
case TOSHIBA_720P_VIDEO_PANEL:
- ret = mipi_dsi_cmds_tx(toshiba_720p_video_rotation,
- TOSHIBA_720P_VIDEO_ROTATION);
+ ret = mdss_dsi_cmds_tx(NULL, toshiba_720p_video_rotation,
+ TOSHIBA_720P_VIDEO_ROTATION, 0);
break;
case NT35590_720P_CMD_PANEL:
- ret = mipi_dsi_cmds_tx(nt35590_720p_cmd_rotation,
- NT35590_720P_CMD_ROTATION);
+ ret = mdss_dsi_cmds_tx(NULL, nt35590_720p_cmd_rotation,
+ NT35590_720P_CMD_ROTATION, 0);
break;
case NT35590_720P_VIDEO_PANEL:
- ret = mipi_dsi_cmds_tx(nt35590_720p_video_rotation,
- NT35590_720P_VIDEO_ROTATION);
+ ret = mdss_dsi_cmds_tx(NULL, nt35590_720p_video_rotation,
+ NT35590_720P_VIDEO_ROTATION, 0);
break;
}
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index ca4623c..4ac9b37 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,6 +43,7 @@
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define HFPLL_LDO_ID 8
@@ -305,9 +306,9 @@
mdp_gdsc_ctrl(0);
return ret;
}
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(DSI0_PLL_BASE);
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ dsi_pll_enable_seq(pinfo->mipi.pll_0_base);
mmss_dsi_clocks_enable(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
@@ -397,6 +398,9 @@
uint32_t panel_loop = 0;
uint32_t ret = 0;
uint32_t fb_addr = MIPI_FB_ADDR;
+ char cont_splash = '\0';
+
+ set_panel_cmd_string(panel_name, &cont_splash);
if (!strcmp(panel_name, NO_PANEL_CONFIG)
|| !strcmp(panel_name, SIM_VIDEO_PANEL)
@@ -420,6 +424,10 @@
}
} while (++panel_loop <= oem_panel_max_auto_detect_panels());
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8610/include/target/display.h b/target/msm8610/include/target/display.h
index 1d7f963..e3d3ce0 100644
--- a/target/msm8610/include/target/display.h
+++ b/target/msm8610/include/target/display.h
@@ -34,38 +34,6 @@
/*---------------------------------------------------------------------------*/
#include <display_resource.h>
-/*---------------------------------------------------------------------------*/
-/* GPIO configuration */
-/*---------------------------------------------------------------------------*/
-static struct gpio_pin reset_gpio = {
- "msmgpio", 41, 3, 1, 0, 1
-};
-
-static struct gpio_pin enable_gpio = {
- 0, 0, 0, 0, 0, 0
-};
-
-static struct gpio_pin te_gpio = {
- "msmgpio", 12, 0, 2, 0, 1
-};
-
-static struct gpio_pin pwm_gpio = {
- 0, 0, 0, 0, 0, 0
-};
-
-static struct gpio_pin mode_gpio = {
- "msmgpio", 7, 3, 1, 0, 1
-};
-
-
-/*---------------------------------------------------------------------------*/
-/* Supply configuration */
-/*---------------------------------------------------------------------------*/
-static struct ldo_entry ldo_entry_array[] = {
-{ "vddio", 14, 0, 1800000, 100000, 100, 0, 0, 0, 0},
-{ "vdda", 19, 0, 2850000, 100000, 100, 0, 0, 0, 0},
-};
-
#define TOTAL_LDO_DEFINED 2
/*---------------------------------------------------------------------------*/
@@ -111,4 +79,9 @@
#define MIPI_VSYNC_BACK_PORCH_LINES 10
#define MIPI_VSYNC_FRONT_PORCH_LINES 12
+int target_cont_splash_screen();
+void target_force_cont_splash_disable(uint8_t override);
+uint32_t oem_panel_max_auto_detect_panels();
+uint8_t target_panel_auto_detect_enabled();
+uint8_t target_panel_auto_detect_enabled();
#endif
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index c0f5f96..46f5f7e 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -97,6 +97,8 @@
struct mmc_device *dev;
+void target_crypto_init_params();
+
void target_early_init(void)
{
#if WITH_DEBUG_UART
@@ -473,8 +475,6 @@
static void set_sdc_power_ctrl()
{
- uint8_t data_hdrv = 0;
- uint32_t platform = board_platform_id();
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
diff --git a/target/msm8610/oem_panel.c b/target/msm8610/oem_panel.c
index 18733a0..9b59866 100644
--- a/target/msm8610/oem_panel.c
+++ b/target/msm8610/oem_panel.c
@@ -29,10 +29,12 @@
#include <debug.h>
#include <err.h>
+#include <string.h>
#include <smem.h>
#include <msm_panel.h>
#include <board.h>
#include <mipi_dsi.h>
+#include <target/display.h>
#include "include/panel.h"
#include "panel_display.h"
diff --git a/target/msm8610/rules.mk b/target/msm8610/rules.mk
index 9e1c05c..45a7864 100644
--- a/target/msm8610/rules.mk
+++ b/target/msm8610/rules.mk
@@ -1,6 +1,6 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
-INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared -I$(LK_TOP_DIR)/platform/msm8610/include
INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8610
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index 7866acc..f87b2ed 100755
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -30,6 +30,8 @@
#include <debug.h>
#include <smem.h>
#include <err.h>
+#include <string.h>
+#include <qtimer.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <pm8x41.h>
@@ -37,8 +39,10 @@
#include <board.h>
#include <platform/gpio.h>
#include <platform/iomap.h>
+#include <platform/clock.h>
#include <pm_pwm.h>
#include <target/display.h>
+#include <gcdb_display.h>
#include "include/panel.h"
#include "include/display_resource.h"
@@ -53,6 +57,23 @@
#define PWM_DUTY_US 13
#define PWM_PERIOD_US 27
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 41, 3, 1, 0, 1
+};
+
+static struct gpio_pin mode_gpio = {
+ "msmgpio", 7, 3, 1, 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Supply configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+{ "vddio", 14, 0, 1800000, 100000, 100, 0, 0, 0, 0},
+{ "vdda", 19, 0, 2850000, 100000, 100, 0, 0, 0, 0},
+};
+
+
int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
{
struct pm8x41_mpp mpp;
@@ -145,7 +166,7 @@
0x100 * ldo_entry_array[ldocounter].ldo_id),
ldo_entry_array[ldocounter].ldo_type);
- dprintf(SPEW, "Setting %s\n",
+ dprintf(SPEW, "Setting %u\n",
ldo_entry_array[ldocounter].ldo_id);
/* Set voltage during power on */
@@ -171,6 +192,9 @@
{
uint32_t panel_loop = 0;
uint32_t ret = 0;
+ char cont_splash = '\0';
+
+ set_panel_cmd_string(panel_name, &cont_splash);
if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
dprintf(INFO, "Skip panel configuration\n");
@@ -179,7 +203,7 @@
do {
target_force_cont_splash_disable(false);
- ret = gcdb_display_init(panel_name, MDP_REV_304, MIPI_FB_ADDR);
+ ret = gcdb_display_init(panel_name, MDP_REV_304,(void *)MIPI_FB_ADDR);
if (ret) {
/*Panel signature did not match, turn off the display*/
target_force_cont_splash_disable(true);
@@ -187,8 +211,12 @@
} else {
break;
}
- } while (++panel_loop <= oem_panel_max_auto_detect_panels());
+ } while (++panel_loop <= (uint32_t)oem_panel_max_auto_detect_panels());
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8909/include/target/display.h b/target/msm8909/include/target/display.h
index cc2b4c2..0e3a1bc 100644
--- a/target/msm8909/include/target/display.h
+++ b/target/msm8909/include/target/display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -83,9 +83,9 @@
static const char panel_lane_config[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
};
@@ -96,7 +96,7 @@
/*---------------------------------------------------------------------------*/
/* Other Configuration */
/*---------------------------------------------------------------------------*/
-#define DISPLAY_CMDLINE_PREFIX " mdss_mdp.panel="
+#define DISPLAY_CMDLINE_PREFIX " mdss_mdp3.panel="
#define MIPI_FB_ADDR 0x83200000
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 37736cd..96232fe 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -240,7 +240,7 @@
{
{ SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
};
/* Pull configs for sdc pins */
@@ -298,7 +298,7 @@
target_keystatus();
-#if ENABLE_BOOT_CONFIG_SUPPORT
+#if BOOT_CONFIG_SUPPORT
platform_read_boot_config();
#endif
@@ -348,7 +348,7 @@
if (target_use_signed_kernel())
target_crypto_init_params();
-#if ENABLE_SMD_SUPPORT
+#if SMD_SUPPORT
rpm_smd_init();
#endif
}
@@ -471,6 +471,7 @@
case MSM8909:
case MSM8209:
case MSM8208:
+ case MSM8609:
board->baseband = BASEBAND_MSM;
break;
@@ -480,6 +481,10 @@
board->baseband = BASEBAND_MDM;
break;
+ case APQ8009:
+ board->baseband = BASEBAND_APQ;
+ break;
+
default:
dprintf(CRITICAL, "Platform type: %u is not supported\n", platform);
ASSERT(0);
@@ -506,6 +511,8 @@
switch (board_hardware_id()) {
case HW_PLATFORM_SURF:
case HW_PLATFORM_MTP:
+ case HW_PLATFORM_QRD:
+ case HW_PLATFORM_RCM:
splash_screen = 1;
break;
default:
@@ -636,7 +643,7 @@
if (target_is_ssd_enabled())
clock_ce_disable(CE1_INSTANCE);
-#if ENABLE_SMD_SUPPORT
+#if SMD_SUPPORT
rpm_smd_uninit();
#endif
}
diff --git a/target/msm8909/oem_panel.c b/target/msm8909/oem_panel.c
index 6d5e586..f7b5717 100644
--- a/target/msm8909/oem_panel.c
+++ b/target/msm8909/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -39,8 +39,14 @@
#include "include/panel_hx8394d_720p_video.h"
#include "include/panel_hx8379a_fwvga_skua_video.h"
+#include "include/panel_sharp_qhd_video.h"
+#include "include/panel_truly_wvga_cmd.h"
+#include "include/panel_ili9806e_fwvga_video.h"
+#include "include/panel_hx8379c_fwvga_video.h"
+#include "include/panel_hx8394d_qhd_video.h"
#define DISPLAY_MAX_PANEL_DETECTION 0
+#define ILI9806E_FWVGA_VIDEO_PANEL_POST_INIT_DELAY 68
enum {
QRD_SKUA = 0x00,
@@ -56,6 +62,11 @@
enum {
HX8394D_720P_VIDEO_PANEL,
HX8379A_FWVGA_SKUA_VIDEO_PANEL,
+ SHARP_QHD_VIDEO_PANEL,
+ TRULY_WVGA_CMD_PANEL,
+ ILI9806E_FWVGA_VIDEO_PANEL,
+ HX8379C_FWVGA_VIDEO_PANEL,
+ HX8394D_QHD_VIDEO_PANEL,
UNKNOWN_PANEL
};
@@ -66,6 +77,11 @@
static struct panel_list supp_panels[] = {
{"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL},
{"hx8379a_fwvga_skua_video", HX8379A_FWVGA_SKUA_VIDEO_PANEL},
+ {"sharp_qhd_video", SHARP_QHD_VIDEO_PANEL},
+ {"truly_wvga_cmd", TRULY_WVGA_CMD_PANEL},
+ {"ili9806e_fwvga_video",ILI9806E_FWVGA_VIDEO_PANEL},
+ {"hx8379c_fwvga_video",HX8379C_FWVGA_VIDEO_PANEL},
+ {"hx8394d_qhd_video", HX8394D_QHD_VIDEO_PANEL}
};
static uint32_t panel_id;
@@ -81,6 +97,9 @@
* OEM can keep there panel specific on instructions in this
* function
*/
+ if (panel_id == ILI9806E_FWVGA_VIDEO_PANEL)
+ mdelay(ILI9806E_FWVGA_VIDEO_PANEL_POST_INIT_DELAY);
+
return NO_ERROR;
}
@@ -138,15 +157,140 @@
panelstruct->panelresetseq
= &hx8379a_fwvga_skua_video_reset_seq;
panelstruct->backlightinfo = &hx8379a_fwvga_skua_video_backlight;
- pinfo->mipi.panel_cmds
+ pinfo->mipi.panel_on_cmds
= hx8379a_fwvga_skua_video_on_command;
- pinfo->mipi.num_of_panel_cmds
+ pinfo->mipi.num_of_panel_on_cmds
= HX8379A_FWVGA_SKUA_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = hx8379a_fwvga_skua_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = HX8379A_FWVGA_SKUA_VIDEO_OFF_COMMAND;
memcpy(phy_db->timing,
hx8379a_fwvga_skua_video_timings, TIMING_SIZE);
pinfo->mipi.signature = HX8379A_FWVGA_SKUA_VIDEO_SIGNATURE;
break;
-
+ case SHARP_QHD_VIDEO_PANEL:
+ panelstruct->paneldata = &sharp_qhd_video_panel_data;
+ panelstruct->panelres = &sharp_qhd_video_panel_res;
+ panelstruct->color = &sharp_qhd_video_color;
+ panelstruct->videopanel = &sharp_qhd_video_video_panel;
+ panelstruct->commandpanel = &sharp_qhd_video_command_panel;
+ panelstruct->state = &sharp_qhd_video_state;
+ panelstruct->laneconfig = &sharp_qhd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &sharp_qhd_video_timing_info;
+ panelstruct->panelresetseq
+ = &sharp_qhd_video_panel_reset_seq;
+ panelstruct->backlightinfo = &sharp_qhd_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = sharp_qhd_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = SHARP_QHD_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = sharp_qhd_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = SHARP_QHD_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing, sharp_qhd_video_timings, TIMING_SIZE);
+ break;
+ case TRULY_WVGA_CMD_PANEL:
+ panelstruct->paneldata = &truly_wvga_cmd_panel_data;
+ panelstruct->panelres = &truly_wvga_cmd_panel_res;
+ panelstruct->color = &truly_wvga_cmd_color;
+ panelstruct->videopanel = &truly_wvga_cmd_video_panel;
+ panelstruct->commandpanel = &truly_wvga_cmd_command_panel;
+ panelstruct->state = &truly_wvga_cmd_state;
+ panelstruct->laneconfig = &truly_wvga_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &truly_wvga_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &truly_wvga_cmd_reset_seq;
+ panelstruct->backlightinfo = &truly_wvga_cmd_backlight;
+ pinfo->mipi.panel_on_cmds
+ = truly_wvga_cmd_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = TRULY_WVGA_CMD_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = truly_wvga_cmd_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = TRULY_WVGA_CMD_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ truly_wvga_cmd_timings, TIMING_SIZE);
+ break;
+ case ILI9806E_FWVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &ili9806e_fwvga_video_panel_data;
+ panelstruct->panelres = &ili9806e_fwvga_video_panel_res;
+ panelstruct->color = &ili9806e_fwvga_video_color;
+ panelstruct->videopanel = &ili9806e_fwvga_video_video_panel;
+ panelstruct->commandpanel = &ili9806e_fwvga_video_command_panel;
+ panelstruct->state = &ili9806e_fwvga_video_state;
+ panelstruct->laneconfig = &ili9806e_fwvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &ili9806e_fwvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &ili9806e_fwvga_video_reset_seq;
+ panelstruct->backlightinfo = &ili9806e_fwvga_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = ili9806e_fwvga_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = ILI9806E_FWVGA_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = ili9806e_fwvga_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = ILI9806E_FWVGA_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ ili9806e_fwvga_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = ILI9806E_FWVGA_VIDEO_SIGNATURE;
+ break;
+ case HX8379C_FWVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8379c_fwvga_video_panel_data;
+ panelstruct->panelres = &hx8379c_fwvga_video_panel_res;
+ panelstruct->color = &hx8379c_fwvga_video_color;
+ panelstruct->videopanel = &hx8379c_fwvga_video_video_panel;
+ panelstruct->commandpanel = &hx8379c_fwvga_video_command_panel;
+ panelstruct->state = &hx8379c_fwvga_video_state;
+ panelstruct->laneconfig = &hx8379c_fwvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8379c_fwvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8379c_fwvga_video_reset_seq;
+ panelstruct->backlightinfo = &hx8379c_fwvga_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = hx8379c_fwvga_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = HX8379C_FWVGA_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = hx8379c_fwvga_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = HX8379C_FWVGA_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ hx8379c_fwvga_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = HX8379C_FWVGA_VIDEO_SIGNATURE;
+ break;
+ case HX8394D_QHD_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8394d_qhd_video_panel_data;
+ panelstruct->panelres = &hx8394d_qhd_video_panel_res;
+ panelstruct->color = &hx8394d_qhd_video_color;
+ panelstruct->videopanel = &hx8394d_qhd_video_video_panel;
+ panelstruct->commandpanel = &hx8394d_qhd_video_command_panel;
+ panelstruct->state = &hx8394d_qhd_video_state;
+ panelstruct->laneconfig = &hx8394d_qhd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8394d_qhd_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8394d_qhd_video_panel_reset_seq;
+ panelstruct->backlightinfo = &hx8394d_qhd_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = hx8394d_qhd_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = HX8394D_QHD_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = hx8394d_qhd_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = HX8394D_QHD_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ hx8394d_qhd_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = HX8394D_QHD_VIDEO_SIGNATURE;
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -196,6 +340,7 @@
switch (hw_id) {
case HW_PLATFORM_SURF:
case HW_PLATFORM_MTP:
+ case HW_PLATFORM_RCM:
panel_id = HX8394D_720P_VIDEO_PANEL;
break;
case HW_PLATFORM_QRD:
@@ -204,7 +349,11 @@
panel_id = HX8379A_FWVGA_SKUA_VIDEO_PANEL;
break;
case QRD_SKUC:
+ panel_id = ILI9806E_FWVGA_VIDEO_PANEL;
+ break;
case QRD_SKUE:
+ panel_id = HX8379C_FWVGA_VIDEO_PANEL;
+ break;
default:
dprintf(CRITICAL, "QRD Display not enabled for %d type\n",
platform_subtype);
diff --git a/target/msm8909/regulator.c b/target/msm8909/regulator.c
new file mode 100644
index 0000000..e421b42
--- /dev/null
+++ b/target/msm8909/regulator.c
@@ -0,0 +1,94 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Fundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <regulator.h>
+#include <rpm-smd.h>
+#include <debug.h>
+
+static uint32_t ldo2[][11]=
+{
+ {
+ LDOA_RES_TYPE, 2,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+ KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
+ },
+
+ {
+ LDOA_RES_TYPE, 2,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+ KEY_MICRO_VOLT, 4, 1200000,
+ KEY_CURRENT, 4, 40,
+ },
+};
+
+static uint32_t ldo6[][11]=
+{
+ {
+ LDOA_RES_TYPE, 6,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+ KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
+ },
+
+ {
+ LDOA_RES_TYPE, 6,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+ KEY_MICRO_VOLT, 4, 1800000,
+ KEY_CURRENT, 4, 150,
+ },
+};
+
+
+static uint32_t ldo17[][11]=
+{
+ {
+ LDOA_RES_TYPE, 17,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+ KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
+ },
+
+ {
+ LDOA_RES_TYPE, 17,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+ KEY_MICRO_VOLT, 4, 2850000,
+ KEY_CURRENT, 4, 40,
+ },
+};
+
+void regulator_enable()
+{
+ rpm_send_data(&ldo2[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+
+ rpm_send_data(&ldo17[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+
+ rpm_send_data(&ldo6[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+
+}
diff --git a/target/msm8909/rules.mk b/target/msm8909/rules.mk
index b076247..5753859 100644
--- a/target/msm8909/rules.mk
+++ b/target/msm8909/rules.mk
@@ -35,3 +35,8 @@
$(LOCAL_DIR)/meminfo.o \
$(LOCAL_DIR)/target_display.o \
$(LOCAL_DIR)/oem_panel.o
+
+ifeq ($(ENABLE_SMD_SUPPORT),1)
+OBJS += \
+ $(LOCAL_DIR)/regulator.o
+endif
diff --git a/target/msm8909/target_display.c b/target/msm8909/target_display.c
index 93837f9..7b7aea7 100755
--- a/target/msm8909/target_display.c
+++ b/target/msm8909/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,6 +43,7 @@
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define VCO_DELAY_USEC 1000
#define GPIO_STATE_LOW 0
@@ -50,6 +51,7 @@
#define RESET_GPIO_SEQ_LEN 3
#define PWM_DUTY_US 13
#define PWM_PERIOD_US 27
+#define PM8916_VER 0x20000
static void mdss_dsi_uniphy_pll_sw_reset_8909(uint32_t pll_base)
{
@@ -93,12 +95,19 @@
int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
{
struct pm8x41_mpp mpp;
+ uint32_t hw_id = board_hardware_id();
+ struct board_pmic_data pmic_info;
int rc;
if (bl->bl_interface_type == BL_DCS)
return 0;
- mpp.base = PM8x41_MMP2_BASE;
+ board_pmic_info(&pmic_info, 1);
+ if (pmic_info.pmic_version == PM8916_VER)
+ mpp.base = PM8x41_MMP4_BASE;
+ else
+ mpp.base = PM8x41_MMP2_BASE;
+
mpp.vin = MPP_VIN0;
if (enable) {
pm_pwm_enable(false);
@@ -116,6 +125,14 @@
pm8x41_enable_mpp(&mpp, MPP_DISABLE);
}
mdelay(20);
+
+ if (enable) {
+ gpio_tlmm_config(bkl_gpio.pin_id, 0,
+ bkl_gpio.pin_direction, bkl_gpio.pin_pull,
+ bkl_gpio.pin_strength, bkl_gpio.pin_state);
+ gpio_set(bkl_gpio.pin_id, 2);
+ }
+
return 0;
}
@@ -149,9 +166,9 @@
return ret;
}
mdss_dsi_uniphy_pll_sw_reset_8909(DSI0_PLL_BASE);
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- if (!dsi_pll_enable_seq_8909(DSI0_PLL_BASE))
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ if (!dsi_pll_enable_seq_8909(pinfo->mipi.pll_0_base))
dprintf(CRITICAL, "Not able to enable the pll\n");
gcc_dsi_clocks_enable(pll_data->pclk_m,
pll_data->pclk_n,
@@ -183,14 +200,6 @@
gpio_set(enable_gpio.pin_id, 2);
}
- if (hw_id == HW_PLATFORM_SURF || (hw_id == HW_PLATFORM_MTP)) {
- /* configure backlight gpio for CDP and MTP */
- gpio_tlmm_config(bkl_gpio.pin_id, 0,
- bkl_gpio.pin_direction, bkl_gpio.pin_pull,
- bkl_gpio.pin_strength, bkl_gpio.pin_state);
- gpio_set(bkl_gpio.pin_id, 2);
- }
-
gpio_tlmm_config(reset_gpio.pin_id, 0,
reset_gpio.pin_direction, reset_gpio.pin_pull,
reset_gpio.pin_strength, reset_gpio.pin_state);
@@ -214,12 +223,11 @@
return ret;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
- /*
- * The PMIC regulators needed for display are enabled in SBL.
- * There is no access to the regulators is LK.
- */
+ if (enable)
+ regulator_enable(); /* L2, L6, and L17 */
+
return NO_ERROR;
}
@@ -232,9 +240,16 @@
{
uint32_t panel_loop = 0;
uint32_t ret = 0;
+ char cont_splash = '\0';
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ set_panel_cmd_string(panel_name, &cont_splash);
+
+ panel_name += strspn(panel_name, " ");
+ if (!strcmp(panel_name, NO_PANEL_CONFIG)
+ || !strcmp(panel_name, SIM_VIDEO_PANEL)
+ || !strcmp(panel_name, SIM_CMD_PANEL)) {
+ dprintf(INFO, "Selected %s: Skip panel configuration\n",
+ panel_name);
return;
}
@@ -248,6 +263,11 @@
msm_display_off();
}
} while (++panel_loop <= oem_panel_max_auto_detect_panels());
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8916/include/target/display.h b/target/msm8916/include/target/display.h
old mode 100755
new mode 100644
index 5b90130..27b4a5d
--- a/target/msm8916/include/target/display.h
+++ b/target/msm8916/include/target/display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -41,6 +41,10 @@
"msmgpio", 25, 3, 1, 0, 1
};
+static struct gpio_pin ts_reset_gpio = {
+ "msmgpio", 12, 3, 1, 0, 1
+};
+
static struct gpio_pin enable_gpio = {
"msmgpio", 97, 3, 1, 0, 1
};
@@ -49,6 +53,11 @@
"msmgpio", 98, 3, 1, 0, 1
};
+/*Use GPIO 75 for incell panel setup*/
+static struct gpio_pin enable_gpio_1 = {
+ "msmgpio", 75, 3, 1, 0, 1
+};
+
static struct gpio_pin enp_gpio = {
"msmgpio", 97, 3, 1, 0, 1
};
@@ -57,6 +66,11 @@
"msmgpio", 32, 3, 1, 0, 1
};
+/*Use GPIO 77 for incell panel setup*/
+static struct gpio_pin enn_gpio_1 = {
+ "msmgpio", 77, 3, 1, 0, 1
+};
+
static struct gpio_pin te_gpio = {
0, 0, 0, 0, 0, 0
};
@@ -81,6 +95,10 @@
"msmgpio", 8, 3, 1, 0, 1
};
+static struct gpio_pin enable_gpio_skut2 = {
+ "msmgpio", 22, 3, 1, 0, 1
+};
+
/*---------------------------------------------------------------------------*/
/* Target Physical configuration */
/*---------------------------------------------------------------------------*/
@@ -105,9 +123,9 @@
static const char panel_lane_config[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
};
@@ -133,10 +151,35 @@
enum qrd_subtype
{
HW_PLATFORM_SUBTYPE_DEFAULT = 0,
+ HW_PLATFORM_SUBTYPE_CDP_1 = 1,
+ HW_PLATFORM_SUBTYPE_CDP_2 = 2,
+ HW_PLATFORM_SUBTYPE_MTP_3 = 3,
HW_PLATFORM_SUBTYPE_SKUH = 4,
HW_PLATFORM_SUBTYPE_SKUI = 5, /* msm8916 */
HW_PLATFORM_SUBTYPE_SKUK = 5, /* msm8939 */
HW_PLATFORM_SUBTYPE_SKUT1 = 0x40, /* msm8916 */
};
+
+enum {
+ JDI_1080P_VIDEO_PANEL,
+ NT35590_720P_VIDEO_PANEL,
+ NT35590_720P_CMD_PANEL,
+ INNOLUX_720P_VIDEO_PANEL,
+ OTM8019A_FWVGA_VIDEO_PANEL,
+ OTM1283A_720P_VIDEO_PANEL,
+ NT35596_1080P_VIDEO_PANEL,
+ SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
+ JDI_FHD_VIDEO_PANEL,
+ HX8379A_FWVGA_VIDEO_PANEL,
+ HX8394D_720P_VIDEO_PANEL,
+ NT35521_WXGA_VIDEO_PANEL,
+ SAMSUNG_WXGA_VIDEO_PANEL,
+ HX8279A_WSVGA_VIDEO_PANEL,
+ R61318_HD_VIDEO_PANEL,
+ R63417_1080P_VIDEO_PANEL,
+ JDI_A216_FHD_VIDEO_PANEL,
+ UNKNOWN_PANEL
+};
+
#endif
diff --git a/target/msm8916/init.c b/target/msm8916/init.c
index 8e0d26f..fbc45e4 100644
--- a/target/msm8916/init.c
+++ b/target/msm8916/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -66,6 +66,7 @@
#endif
#define FASTBOOT_MODE 0x77665500
+#define PON_SOFT_RB_SPARE 0x88F
#define CE1_INSTANCE 1
#define CE_EE 1
@@ -241,6 +242,21 @@
return restart_reason;
}
+unsigned check_hard_reboot_mode(void)
+{
+ uint8_t hard_restart_reason = 0;
+ uint8_t value = 0;
+
+ /* Read reboot reason and scrub it
+ * Bit-5, bit-6 and bit-7 of SOFT_RB_SPARE for hard reset reason
+ */
+ value = pm8x41_reg_read(PON_SOFT_RB_SPARE);
+ hard_restart_reason = value >> 5;
+ pm8x41_reg_write(PON_SOFT_RB_SPARE, value & 0x1f);
+
+ return hard_restart_reason;
+}
+
static int scm_dload_mode(int mode)
{
int ret = 0;
@@ -341,11 +357,15 @@
case MSM8636:
case MSM8936:
case MSM8239:
+ case MSM8929:
+ case MSM8629:
+ case MSM8229:
board->baseband = BASEBAND_MSM;
break;
case APQ8016:
case APQ8039:
case APQ8036:
+ case APQ8029:
board->baseband = BASEBAND_APQ;
break;
default:
@@ -369,17 +389,17 @@
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
- { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
- { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, 0},
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, 0},
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK , 0},
};
/* Pull configs for sdc pins */
struct tlmm_cfgs sdc1_pull_cfg[] =
{
- { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
- { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
- { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, 0},
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0},
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0},
};
/* Set the drive strength & pull control values */
@@ -411,6 +431,7 @@
switch(board_hardware_id()) {
case HW_PLATFORM_SURF:
+ case HW_PLATFORM_MTP:
ret = 1;
break;
default:
@@ -460,7 +481,7 @@
if (is_cold_boot &&
(!(pon_reason & HARD_RST)) &&
(!(pon_reason & KPDPWR_N)) &&
- ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG) || (pon_reason & CBLPWR_N)))
return 1;
else
return 0;
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
old mode 100755
new mode 100644
index 44abdf7..ae2725d
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -53,10 +53,16 @@
#include "include/panel_hx8379a_fwvga_video.h"
#include "include/panel_hx8394d_720p_video.h"
#include "include/panel_nt35521_wxga_video.h"
+#include "include/panel_samsung_wxga_video.h"
+#include "include/panel_hx8279a_wsvga_video.h"
+#include "include/panel_r61318_hd_video.h"
+#include "include/panel_r63417_1080p_video.h"
+#include "include/panel_jdi_a216_fhd_video.h"
#define DISPLAY_MAX_PANEL_DETECTION 2
#define OTM8019A_FWVGA_VIDEO_PANEL_ON_DELAY 50
#define NT35590_720P_CMD_PANEL_ON_DELAY 40
+#define SAMSUNG_WXGA_VIDEO_PANEL_ON_DELAY 100
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -67,22 +73,6 @@
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
-enum {
-JDI_1080P_VIDEO_PANEL,
-NT35590_720P_VIDEO_PANEL,
-NT35590_720P_CMD_PANEL,
-INNOLUX_720P_VIDEO_PANEL,
-OTM8019A_FWVGA_VIDEO_PANEL,
-OTM1283A_720P_VIDEO_PANEL,
-NT35596_1080P_VIDEO_PANEL,
-SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
-JDI_FHD_VIDEO_PANEL,
-HX8379A_FWVGA_VIDEO_PANEL,
-HX8394D_720P_VIDEO_PANEL,
-NT35521_WXGA_VIDEO_PANEL,
-UNKNOWN_PANEL
-};
-
/*
* The list of panels that are supported on this target.
* Any panel in this list can be selected using fastboot oem command.
@@ -99,7 +89,12 @@
{"jdi_fhd_video", JDI_FHD_VIDEO_PANEL},
{"hx8379a_wvga_video", HX8379A_FWVGA_VIDEO_PANEL},
{"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL},
- {"nt35521_wxga_video", NT35521_WXGA_VIDEO_PANEL}
+ {"nt35521_wxga_video", NT35521_WXGA_VIDEO_PANEL},
+ {"samsung_wxga_video", SAMSUNG_WXGA_VIDEO_PANEL},
+ {"hx8279a_wsvga_video", HX8279A_WSVGA_VIDEO_PANEL},
+ {"r61318_hd_video", R61318_HD_VIDEO_PANEL},
+ {"r63417_1080p_video", R63417_1080P_VIDEO_PANEL},
+ {"jdi_a216_fhd_video", JDI_A216_FHD_VIDEO_PANEL},
};
static uint32_t panel_id;
@@ -121,6 +116,9 @@
} else if (panel_id == NT35590_720P_CMD_PANEL) {
/* needs extra delay to avoid snow screen artifacts */
mdelay(NT35590_720P_CMD_PANEL_ON_DELAY);
+ } else if (panel_id == SAMSUNG_WXGA_VIDEO_PANEL) {
+ /* needs extra delay to avoid unexpected artifacts */
+ mdelay(SAMSUNG_WXGA_VIDEO_PANEL_ON_DELAY);
}
return NO_ERROR;
@@ -434,6 +432,126 @@
memcpy(phy_db->timing,
nt35521_wxga_video_timings, TIMING_SIZE);
break;
+ case SAMSUNG_WXGA_VIDEO_PANEL:
+ panelstruct->paneldata = &samsung_wxga_video_panel_data;
+ panelstruct->panelres = &samsung_wxga_video_panel_res;
+ panelstruct->color = &samsung_wxga_video_color;
+ panelstruct->videopanel = &samsung_wxga_video_video_panel;
+ panelstruct->commandpanel = &samsung_wxga_video_command_panel;
+ panelstruct->state = &samsung_wxga_video_state;
+ panelstruct->laneconfig = &samsung_wxga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &samsung_wxga_video_timing_info;
+ panelstruct->panelresetseq
+ = &samsung_wxga_video_reset_seq;
+ panelstruct->backlightinfo = &samsung_wxga_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = samsung_wxga_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = SAMSUNG_WXGA_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = samsung_wxga_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = SAMSUNG_WXGA_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ samsung_wxga_video_timings, TIMING_SIZE);
+ break;
+ case HX8279A_WSVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8279a_wsvga_video_panel_data;
+ panelstruct->panelres = &hx8279a_wsvga_video_panel_res;
+ panelstruct->color = &hx8279a_wsvga_video_color;
+ panelstruct->videopanel = &hx8279a_wsvga_video_video_panel;
+ panelstruct->commandpanel = &hx8279a_wsvga_video_command_panel;
+ panelstruct->state = &hx8279a_wsvga_video_state;
+ panelstruct->laneconfig = &hx8279a_wsvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8279a_wsvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8279a_wsvga_video_reset_seq;
+ panelstruct->backlightinfo = &hx8279a_wsvga_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = hx8279a_wsvga_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = HX8279A_WSVGA_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = hx8279a_wsvga_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = HX8279A_WSVGA_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ hx8279a_wsvga_video_timings, TIMING_SIZE);
+ break;
+ case R61318_HD_VIDEO_PANEL:
+ panelstruct->paneldata = & r61318_hd_video_panel_data;
+ panelstruct->panelres = & r61318_hd_video_panel_res;
+ panelstruct->color = & r61318_hd_video_color;
+ panelstruct->videopanel = & r61318_hd_video_video_panel;
+ panelstruct->commandpanel = & r61318_hd_video_command_panel;
+ panelstruct->state = & r61318_hd_video_state;
+ panelstruct->laneconfig = & r61318_hd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = & r61318_hd_video_timing_info;
+ panelstruct->panelresetseq
+ = & r61318_hd_video_reset_seq;
+ panelstruct->backlightinfo = & r61318_hd_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = r61318_hd_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = R61318_HD_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = r61318_hd_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = R61318_HD_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ r61318_hd_video_timings, TIMING_SIZE);
+ break;
+ case R63417_1080P_VIDEO_PANEL:
+ panelstruct->paneldata = & r63417_1080p_video_panel_data;
+ panelstruct->panelres = & r63417_1080p_video_panel_res;
+ panelstruct->color = & r63417_1080p_video_color;
+ panelstruct->videopanel = & r63417_1080p_video_video_panel;
+ panelstruct->commandpanel = & r63417_1080p_video_command_panel;
+ panelstruct->state = & r63417_1080p_video_state;
+ panelstruct->laneconfig = & r63417_1080p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = & r63417_1080p_video_timing_info;
+ panelstruct->panelresetseq
+ = & r63417_1080p_video_reset_seq;
+ panelstruct->backlightinfo = & r63417_1080p_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = r63417_1080p_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = R63417_1080P_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = r63417_1080p_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = R63417_1080P_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ r63417_1080p_video_timings, TIMING_SIZE);
+ break;
+ case JDI_A216_FHD_VIDEO_PANEL:
+ panelstruct->paneldata = &jdi_a216_fhd_video_panel_data;
+ panelstruct->panelres = &jdi_a216_fhd_video_panel_res;
+ panelstruct->color = &jdi_a216_fhd_video_color;
+ panelstruct->videopanel = &jdi_a216_fhd_video_video_panel;
+ panelstruct->commandpanel = &jdi_a216_fhd_video_command_panel;
+ panelstruct->state = &jdi_a216_fhd_video_state;
+ panelstruct->laneconfig = &jdi_a216_fhd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_a216_fhd_video_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_a216_fhd_video_reset_seq;
+ panelstruct->backlightinfo = &jdi_a216_fhd_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = jdi_a216_fhd_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = JDI_A216_FHD_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = jdi_a216_fhd_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = JDI_A216_FHD_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_a216_fhd_video_timings, TIMING_SIZE);
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -484,32 +602,61 @@
switch (hw_id) {
case HW_PLATFORM_MTP:
- panel_id = JDI_1080P_VIDEO_PANEL;
+ if (platform_is_msm8939() &&
+ hw_subtype == HW_PLATFORM_SUBTYPE_MTP_3) {
+ panel_id = JDI_FHD_VIDEO_PANEL;
+ } else {
+ panel_id = JDI_1080P_VIDEO_PANEL;
+ switch (auto_pan_loop) {
+ case 0:
+ panel_id = JDI_1080P_VIDEO_PANEL;
+ break;
+ case 1:
+ panel_id = HX8394D_720P_VIDEO_PANEL;
+ break;
+ default:
+ panel_id = UNKNOWN_PANEL;
+ dprintf(CRITICAL, "Unknown panel\n");
+ return PANEL_TYPE_UNKNOWN;
+ }
+ auto_pan_loop++;
+ }
break;
case HW_PLATFORM_SURF:
- panel_id = JDI_1080P_VIDEO_PANEL;
- switch (auto_pan_loop) {
- case 0:
+ if (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_1) {
+ panel_id = JDI_FHD_VIDEO_PANEL;
+ } else if (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_2) {
+ panel_id = JDI_A216_FHD_VIDEO_PANEL;
+ } else {
panel_id = JDI_1080P_VIDEO_PANEL;
- break;
- case 1:
- panel_id = NT35590_720P_VIDEO_PANEL;
- break;
- default:
- panel_id = UNKNOWN_PANEL;
- dprintf(CRITICAL, "Unknown panel\n");
- return PANEL_TYPE_UNKNOWN;
+ switch (auto_pan_loop) {
+ case 0:
+ panel_id = JDI_1080P_VIDEO_PANEL;
+ break;
+ case 1:
+ panel_id = NT35590_720P_VIDEO_PANEL;
+ break;
+ default:
+ panel_id = UNKNOWN_PANEL;
+ dprintf(CRITICAL, "Unknown panel\n");
+ return PANEL_TYPE_UNKNOWN;
+ }
+ auto_pan_loop++;
}
- auto_pan_loop++;
break;
case HW_PLATFORM_QRD:
target_id = board_target_id();
plat_hw_ver_major = ((target_id >> 16) & 0xFF);
- if (platform_is_msm8939()) {
+ if (platform_is_msm8939() || platform_is_msm8929()) {
switch (hw_subtype) {
case HW_PLATFORM_SUBTYPE_SKUK:
- panel_id = NT35596_1080P_VIDEO_PANEL;
+ if ((plat_hw_ver_major >> 4) == 0x1)
+ panel_id = R61318_HD_VIDEO_PANEL;
+ else if ((plat_hw_ver_major >> 4) == 0x2)
+ panel_id = R63417_1080P_VIDEO_PANEL;
+ else
+ panel_id = NT35596_1080P_VIDEO_PANEL;
break;
default:
dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
@@ -533,8 +680,15 @@
panel_id = HX8379A_FWVGA_VIDEO_PANEL;
break;
case HW_PLATFORM_SUBTYPE_SKUT1:
- /* qrd SKUT1 */
- panel_id = NT35521_WXGA_VIDEO_PANEL;
+ if ((plat_hw_ver_major & 0x0F) == 0x1)
+ /* qrd SKUT1 */
+ panel_id = NT35521_WXGA_VIDEO_PANEL;
+ else if ((plat_hw_ver_major & 0x0F) == 0x2)
+ /* qrd SKUT2 */
+ panel_id = SAMSUNG_WXGA_VIDEO_PANEL;
+ else if ((plat_hw_ver_major & 0x0F) == 0x3)
+ /* qrd SKUT3 */
+ panel_id = HX8279A_WSVGA_VIDEO_PANEL;
break;
default:
dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
@@ -554,7 +708,7 @@
* Update all data structures after 'panel_init' label. Only panel
* selection is supposed to happen before that.
*/
- if (platform_is_msm8939() || (hw_id == HW_PLATFORM_QRD)) {
+ if (platform_is_msm8939() || platform_is_msm8929() || (hw_id == HW_PLATFORM_QRD)) {
phy_db->regulator_mode = DSI_PHY_REGULATOR_LDO_MODE;
memcpy(panel_regulator_settings,
ldo_regulator_settings, REGULATOR_SIZE);
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
old mode 100755
new mode 100644
index ea69e86..0ddaec1
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +45,7 @@
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define VCO_DELAY_USEC 1000
#define GPIO_STATE_LOW 0
@@ -145,9 +146,9 @@
return ret;
}
mdss_dsi_uniphy_pll_sw_reset_8916(DSI0_PLL_BASE);
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- if (!dsi_pll_enable_seq_8916(DSI0_PLL_BASE))
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ if (!dsi_pll_enable_seq_8916(pinfo->mipi.pll_0_base))
dprintf(CRITICAL, "Not able to enable the pll\n");
gcc_dsi_clocks_enable(pinfo->mipi.dual_dsi, pll_data->pclk_m,
pll_data->pclk_n,
@@ -284,19 +285,64 @@
return 0;
}
+int target_panel_reset_incell(uint8_t enable)
+{
+ /*Enable the gpios in 75->97->77 order for incell panel*/
+ if (enable) {
+ gpio_tlmm_config(enable_gpio_1.pin_id, 0,
+ enable_gpio_1.pin_direction, enable_gpio_1.pin_pull,
+ enable_gpio_1.pin_strength, enable_gpio_1.pin_state);
+ gpio_set_dir(enable_gpio_1.pin_id, 2);
+
+ gpio_tlmm_config(enp_gpio.pin_id, 0,
+ enp_gpio.pin_direction, enp_gpio.pin_pull,
+ enp_gpio.pin_strength, enp_gpio.pin_state);
+ gpio_set_dir(enp_gpio.pin_id, 2);
+
+ gpio_tlmm_config(enn_gpio_1.pin_id, 0,
+ enn_gpio_1.pin_direction, enn_gpio_1.pin_pull,
+ enn_gpio_1.pin_strength, enn_gpio_1.pin_state);
+ gpio_set_dir(enn_gpio_1.pin_id, 2);
+ }
+ else {
+ gpio_set_dir(enable_gpio_1.pin_id, 0);
+ gpio_set_dir(enp_gpio.pin_id, 0); /* ENP */
+ gpio_set_dir(enn_gpio_1.pin_id, 0); /* ENN */
+ }
+}
+
+int target_panel_reset_jdi_a216(uint8_t enable)
+{
+ if (enable) {
+ gpio_tlmm_config(ts_reset_gpio.pin_id, 0,
+ ts_reset_gpio.pin_direction, ts_reset_gpio.pin_pull,
+ ts_reset_gpio.pin_strength, ts_reset_gpio.pin_state);
+ gpio_set_dir(ts_reset_gpio.pin_id, GPIO_STATE_HIGH);
+ } else {
+ gpio_set_dir(ts_reset_gpio.pin_id, GPIO_STATE_LOW);
+ }
+}
+
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo)
{
int ret = NO_ERROR;
uint32_t hw_id = board_hardware_id();
uint32_t hw_subtype = board_hardware_subtype();
+ uint32_t target_id, plat_hw_ver_major;
if (enable) {
if (pinfo->mipi.use_enable_gpio) {
/* set enable gpio pin for SKUT1 */
if ((hw_id == HW_PLATFORM_QRD) &&
- (hw_subtype == HW_PLATFORM_SUBTYPE_SKUT1))
- enable_gpio = enable_gpio_skut1;
+ (hw_subtype == HW_PLATFORM_SUBTYPE_SKUT1)) {
+ target_id = board_target_id();
+ plat_hw_ver_major = ((target_id >> 16) & 0xFF);
+ if ((plat_hw_ver_major & 0x0F) == 0x1)
+ enable_gpio = enable_gpio_skut1;
+ else
+ enable_gpio = enable_gpio_skut2;
+ }
gpio_tlmm_config(enable_gpio.pin_id, 0,
enable_gpio.pin_direction, enable_gpio.pin_pull,
enable_gpio.pin_strength,
@@ -305,10 +351,18 @@
gpio_set_dir(enable_gpio.pin_id, 2);
}
- if (platform_is_msm8939()) {
+ if (platform_is_msm8939() || platform_is_msm8929()) {
if ((hw_id == HW_PLATFORM_QRD) &&
(hw_subtype == HW_PLATFORM_SUBTYPE_SKUK))
target_panel_reset_skuk(enable);
+ if (((hw_id == HW_PLATFORM_SURF) &&
+ (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_1)) ||
+ ((hw_id == HW_PLATFORM_MTP) &&
+ (hw_subtype == HW_PLATFORM_SUBTYPE_MTP_3)))
+ target_panel_reset_incell(enable);
+ if ((hw_id == HW_PLATFORM_SURF) &&
+ (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_2))
+ target_panel_reset_jdi_a216(enable);
} else { /* msm8916 */
if ((hw_id == HW_PLATFORM_QRD) &&
(hw_subtype == HW_PLATFORM_SUBTYPE_SKUH))
@@ -342,7 +396,7 @@
if (pinfo->mipi.use_enable_gpio)
gpio_set_dir(enable_gpio.pin_id, 0);
- if (platform_is_msm8939()) {
+ if (platform_is_msm8939() || platform_is_msm8929()) {
if ((hw_id == HW_PLATFORM_QRD) &&
(hw_subtype == HW_PLATFORM_SUBTYPE_SKUK))
target_panel_reset_skuk(enable);
@@ -374,7 +428,9 @@
{
uint32_t panel_loop = 0;
uint32_t ret = 0;
+ char cont_splash = '\0';
+ set_panel_cmd_string(panel_name, &cont_splash);
panel_name += strspn(panel_name, " ");
if (!strcmp(panel_name, NO_PANEL_CONFIG)
@@ -395,6 +451,11 @@
msm_display_off();
}
} while (++panel_loop <= oem_panel_max_auto_detect_panels());
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8974/include/target/display.h b/target/msm8974/include/target/display.h
index 953a1af..6821fd3 100644
--- a/target/msm8974/include/target/display.h
+++ b/target/msm8974/include/target/display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -34,30 +34,6 @@
/*---------------------------------------------------------------------------*/
#include <display_resource.h>
-/*---------------------------------------------------------------------------*/
-/* GPIO configuration */
-/*---------------------------------------------------------------------------*/
-static struct gpio_pin reset_gpio = {
- "pm8941_gpios", 19, 2, 1, 0, 1
-};
-
-static struct gpio_pin enable_gpio = {
- "msmgpio", 58, 3, 1, 0, 1
-};
-
-static struct gpio_pin pwm_gpio = {
- "pm8941_gpios", 36, 3, 1, 0, 1
-};
-
-/*---------------------------------------------------------------------------*/
-/* LDO configuration */
-/*---------------------------------------------------------------------------*/
-static struct ldo_entry ldo_entry_array[] = {
- { "vdd", 22, 0, 3000000, 100000, 100, 0, 20, 0, 0},
-{ "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
-{ "vdda", 2, 1, 1200000, 100000, 100, 0, 0, 0, 0},
-};
-
#define TOTAL_LDO_DEFINED 3
/*---------------------------------------------------------------------------*/
@@ -78,9 +54,9 @@
static const char panel_lane_config[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
};
@@ -109,4 +85,9 @@
#define HDMI_PANEL_NAME "hdmi"
#define HDMI_CONTROLLER_STRING "hdmi:0"
+int target_cont_splash_screen();
+uint8_t target_panel_auto_detect_enabled();
+uint32_t target_hw_interposer();
+void target_force_cont_splash_disable(uint8_t override);
+uint32_t oem_panel_max_auto_detect_panels();
#endif
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index 59f7ffd..a7e0ca8 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -31,6 +31,7 @@
#include <platform/irqs.h>
#include <platform/gpio.h>
#include <reg.h>
+#include <string.h>
#include <target.h>
#include <platform.h>
#include <dload_util.h>
@@ -46,6 +47,8 @@
#include <hsusb.h>
#include <clock.h>
#include <partition_parser.h>
+#include <sdhci_msm.h>
+#include <qtimer.h>
#include <scm.h>
#include <platform/clock.h>
#include <platform/gpio.h>
@@ -53,6 +56,8 @@
#define HW_PLATFORM_8994_INTERPOSER 0x3
+extern int platform_is_8974();
+extern int platform_is_8974ac();
extern bool target_use_signed_kernel(void);
static void set_sdc_power_ctrl();
@@ -384,7 +389,7 @@
ret = scm_protect_keystore((uint32_t *)&buffer[0],size);
if(ret != 0)
- dprintf(CRITICAL,"ERROR: scm_protect_keystore Failed");
+ dprintf(CRITICAL,"ERROR: scm_protect_keystore Failed\n");
free(buffer);
}
@@ -663,7 +668,6 @@
unsigned target_pause_for_battery_charge(void)
{
- uint8_t pon_reason = pm8x41_get_pon_reason();
/* This function will always return 0 to facilitate
* automated testing/reboot with usb connected.
@@ -772,7 +776,6 @@
void target_usb_stop(void)
{
- uint32_t platform = board_platform_id();
/* Disable VBUS mimicing in the controller. */
if (target_needs_vbus_mimic())
diff --git a/target/msm8974/oem_panel.c b/target/msm8974/oem_panel.c
index 34cdd1b..45b00d9 100755
--- a/target/msm8974/oem_panel.c
+++ b/target/msm8974/oem_panel.c
@@ -33,6 +33,8 @@
#include <msm_panel.h>
#include <board.h>
#include <mipi_dsi.h>
+#include <string.h>
+#include <target/display.h>
#include "include/panel.h"
#include "panel_display.h"
@@ -283,7 +285,6 @@
struct mdss_dsi_phy_ctrl *phy_db)
{
uint32_t hw_id = board_hardware_id();
- uint32_t target_id = board_target_id();
int32_t panel_override_id;
if (panel_name) {
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index fbfaeb8..6224f31 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -30,16 +30,20 @@
#include <debug.h>
#include <smem.h>
#include <err.h>
+#include <qtimer.h>
+#include <string.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <pm8x41.h>
#include <pm8x41_wled.h>
#include <board.h>
#include <mdp5.h>
+#include <edp.h>
#include <platform/gpio.h>
#include <platform/clock.h>
#include <platform/iomap.h>
#include <target/display.h>
+#include <gcdb_display.h>
#include "include/panel.h"
#include "include/display_resource.h"
@@ -48,6 +52,30 @@
#define HFPLL_LDO_ID 12
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "pm8941_gpios", 19, 2, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {
+ "msmgpio", 58, 3, 1, 0, 1
+};
+
+static struct gpio_pin pwm_gpio = {
+ "pm8941_gpios", 36, 3, 1, 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* LDO configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+ { "vdd", 22, 0, 3000000, 100000, 100, 0, 20, 0, 0},
+ { "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+ { "vdda", 2, 1, 1200000, 100000, 100, 0, 0, 0, 0},
+};
+
static struct pm8x41_wled_data wled_ctrl = {
.mod_scheme = 0x00,
.led1_brightness = (0x0F << 8) | 0xEF,
@@ -219,9 +247,9 @@
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(DSI0_PLL_BASE);
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ dsi_pll_enable_seq(pinfo->mipi.pll_0_base);
mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
@@ -289,7 +317,7 @@
0x100 * ldo_entry_array[ldocounter].ldo_id),
ldo_entry_array[ldocounter].ldo_type);
- dprintf(SPEW, "Setting %s\n",
+ dprintf(SPEW, "Setting %u\n",
ldo_entry_array[ldocounter].ldo_id);
/* Set voltage during power on */
@@ -306,8 +334,9 @@
return NO_ERROR;
}
-static int msm8974_mdss_edp_panel_clock(int enable)
+static uint32_t msm8974_mdss_edp_panel_clock(uint8_t enable , struct msm_panel_info *pinfo)
{
+ uint32_t dual_dsi = pinfo->mipi.dual_dsi;
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
@@ -315,24 +344,15 @@
} else if (!target_cont_splash_screen()) {
/* Add here for continuous splash */
edp_clk_disable();
- mdp_clock_disable();
+ mdp_clock_disable(dual_dsi);
mdp_gdsc_ctrl(enable);
}
return 0;
}
-static int msm8974_edp_panel_power(int enable)
+static int msm8974_edp_panel_power(uint8_t enable)
{
- struct pm8x41_gpio gpio36_param = {
- .direction = PM_GPIO_DIR_OUT,
- .function = PM_GPIO_FUNC_2,
- .vin_sel = 2, /* VIN_2 */
- .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
- .output_buffer = PM_GPIO_OUT_CMOS,
- .out_strength = PM_GPIO_OUT_DRIVE_HIGH,
- };
-
struct pm8x41_ldo ldo12 = LDO(PM8x41_LDO12, PLDO_TYPE);
if (enable) {
@@ -371,7 +391,7 @@
if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
if (buf_size < (prefix_string_len + LK_OVERRIDE_PANEL_LEN +
- HDMI_CONTROLLER_STRING)) {
+ strlen(HDMI_CONTROLLER_STRING))) {
dprintf(CRITICAL, "command line argument is greater than buffer size\n");
return false;
}
@@ -392,11 +412,13 @@
{
uint32_t hw_id = board_hardware_id();
uint32_t panel_loop = 0;
- uint32_t ret = 0;
+ int ret = 0;
+ char cont_splash = '\0';
if (target_hw_interposer())
return;
+ set_panel_cmd_string(panel_name, &cont_splash);
panel_name += strspn(panel_name, " ");
if (!strcmp(panel_name, NO_PANEL_CONFIG)
@@ -411,6 +433,7 @@
dprintf(INFO, "%s: HDMI is primary\n", __func__);
return;
}
+
switch (hw_id) {
case HW_PLATFORM_LIQUID:
edp_panel_init(&(panel.panel_info));
@@ -431,16 +454,21 @@
do {
target_force_cont_splash_disable(false);
ret = gcdb_display_init(panel_name, MDP_REV_50,
- MIPI_FB_ADDR);
+ (void *)MIPI_FB_ADDR);
if (!ret || ret == ERR_NOT_SUPPORTED) {
break;
} else {
target_force_cont_splash_disable(true);
msm_display_off();
}
- } while (++panel_loop <= oem_panel_max_auto_detect_panels());
+ } while (++panel_loop <= (uint32_t)oem_panel_max_auto_detect_panels());
break;
}
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8994/include/target/display.h b/target/msm8994/include/target/display.h
index b9d5dfe..c426ee2 100644
--- a/target/msm8994/include/target/display.h
+++ b/target/msm8994/include/target/display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -34,31 +34,6 @@
/*---------------------------------------------------------------------------*/
#include <display_resource.h>
-/*---------------------------------------------------------------------------*/
-/* GPIO configuration */
-/*---------------------------------------------------------------------------*/
-static struct gpio_pin reset_gpio = {
- "msmgpio", 78, 3, 1, 0, 1
-};
-
-static struct gpio_pin lcd_reg_en = { /* boost regulator */
- "pm8994_gpios", 14, 3, 1, 0, 1
-};
-
-static struct gpio_pin bklt_gpio = { /* lcd_bklt_reg_en */
- "pmi8994_gpios", 2, 3, 1, 0, 1
-};
-
-/*---------------------------------------------------------------------------*/
-/* LDO configuration */
-/*---------------------------------------------------------------------------*/
-static struct ldo_entry ldo_entry_array[] = {
- { "vdd", 14, 0, 1800000, 100000, 100, 0, 20, 0, 0},
- { "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
- { "vdda", 2, 1, 1250000, 100000, 100, 0, 0, 0, 0},
- { "vcca", 28, 1, 1000000, 10000, 100, 0, 0, 0, 0},
-};
-
#define TOTAL_LDO_DEFINED 3
/*---------------------------------------------------------------------------*/
@@ -74,15 +49,15 @@
};
static const uint32_t panel_regulator_settings[] = {
- 0x03, 0x05, 0x03, 0x00, 0x20, 0x07, 0x01
+ 0x03, 0x03, 0x03, 0x00, 0x20, 0x07, 0x01
};
static const char panel_lane_config[] = {
-0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x88,
-0x02, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x01, 0x88,
-0x02, 0x00, 0x00, 0x40, 0x20, 0x00, 0x00, 0x01, 0x88,
-0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x88,
-0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x88
+0x02, 0xa0, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x46,
+0x02, 0xa0, 0x00, 0x00, 0x40, 0x00, 0x00, 0x01, 0x46,
+0x02, 0xa0, 0x00, 0x40, 0x20, 0x00, 0x00, 0x01, 0x46,
+0x02, 0xa0, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x46,
+0x00, 0xa0, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x46
};
static const uint32_t panel_physical_ctrl[] = {
@@ -106,4 +81,21 @@
#define PWM_BL_LPG_CHAN_ID 4 /* lpg_out<3> */
+#define HDMI_PANEL_NAME "hdmi"
+#define HDMI_CONTROLLER_STRING "hdmi:0"
+
#endif
+
+/*---------------------------------------------------------------------------*/
+/* Functions */
+/*---------------------------------------------------------------------------*/
+int target_display_pre_on();
+int target_display_pre_off();
+int target_display_post_on();
+int target_display_post_off();
+int target_cont_splash_screen();
+int target_display_get_base_offset(uint32_t base);
+void target_force_cont_splash_disable(uint8_t override);
+uint8_t target_panel_auto_detect_enabled();
+
+
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index bb3198e..5df2874 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -59,7 +59,9 @@
#include <rpm-smd.h>
#include <sdhci_msm.h>
#include <pm8x41_wled.h>
-#include <qpnp_wled.h>
+#include <qpnp_led.h>
+
+#include "target/display.h"
#define CE_INSTANCE 2
#define CE_EE 1
@@ -75,9 +77,10 @@
#define FASTBOOT_MODE 0x77665500
-#define PMIC_WLED_SLAVE_ID 3
+#define PMIC_LED_SLAVE_ID 3
#define DDR_CFG_DLY_VAL 0x80040870
+void target_crypto_init_params(void);
static void set_sdc_power_ctrl(uint8_t slot);
static uint32_t mmc_pwrctl_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE };
@@ -151,7 +154,10 @@
}
if (crypto_initialized())
+ {
crypto_eng_cleanup();
+ clock_ce_disable(CE_INSTANCE);
+ }
rpm_smd_uninit();
}
@@ -212,7 +218,7 @@
if (slot == 0x1)
{
- clk = TLMM_CUR_VAL_16MA;
+ clk = TLMM_CUR_VAL_10MA;
cmd = TLMM_CUR_VAL_8MA;
dat = TLMM_CUR_VAL_8MA;
reg = SDC1_HDRV_PULL_CTL;
@@ -316,24 +322,31 @@
platform_read_boot_config();
+#ifdef MMC_SDHCI_SUPPORT
if (platform_boot_dev_isemmc())
{
target_sdc_init();
}
- else
+#endif
+#ifdef UFS_SUPPORT
+ if(!platform_boot_dev_isemmc())
{
ufs_device.base = UFS_BASE;
ufs_init(&ufs_device);
}
-
+#endif
/* Storage initialization is complete, read the partition table info */
mmc_read_partition_table(0);
rpm_smd_init();
- /* QPNP WLED init for display backlight */
- pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID);
- qpnp_wled_init();
+ /* QPNP LED init for boot process notification */
+ if (board_hardware_id() == HW_PLATFORM_LIQUID){
+ pm8x41_wled_config_slave_id(PMIC_LED_SLAVE_ID);
+ qpnp_led_init(QPNP_LED_BLUE, QPNP_LED_CTRL_BASE,
+ QPNP_BLUE_LPG_CTRL_BASE);
+ }
+
}
unsigned board_machtype(void)
@@ -442,7 +455,7 @@
else
reset_type = PON_PSHOLD_HARD_RESET;
- pm8x41_reset_configure(reset_type);
+ pm8994_reset_configure(reset_type);
/* Drop PS_HOLD for MSM */
writel(0x00, MPM2_MPM_PS_HOLD);
@@ -543,7 +556,7 @@
dprintf(CRITICAL, "Going down for shutdown.\n");
/* Configure PMIC for shutdown. */
- pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
+ pm8994_reset_configure(PON_PSHOLD_SHUTDOWN);
/* Drop PS_HOLD for MSM */
writel(0x00, MPM2_MPM_PS_HOLD);
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
index f658fc6..de292b5 100644
--- a/target/msm8994/oem_panel.c
+++ b/target/msm8994/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -28,11 +28,14 @@
*/
#include <debug.h>
+#include <string.h>
#include <err.h>
#include <smem.h>
#include <msm_panel.h>
#include <board.h>
#include <mipi_dsi.h>
+#include <qtimer.h>
+#include <platform.h>
#include "include/panel.h"
#include "panel_display.h"
@@ -44,6 +47,10 @@
#include "include/panel_jdi_qhd_dualdsi_video.h"
#include "include/panel_jdi_qhd_dualdsi_cmd.h"
#include "include/panel_jdi_4k_dualdsi_video.h"
+#include "include/panel_jdi_1080p_video.h"
+#include "include/panel_hx8379a_truly_fwvga_video.h"
+#include "include/panel_nt35597_wqxga_video.h"
+#include "include/panel_nt35597_wqxga_cmd.h"
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -53,6 +60,10 @@
JDI_QHD_DUALDSI_VIDEO_PANEL,
JDI_QHD_DUALDSI_CMD_PANEL,
JDI_4K_DUALDSI_VIDEO_PANEL,
+JDI_1080P_VIDEO_PANEL,
+HX8379A_TRULY_FWVGA_VIDEO_PANEL,
+NOVATEK_WQXGA_VIDEO_PANEL,
+NOVATEK_WQXGA_CMD_PANEL,
UNKNOWN_PANEL
};
@@ -65,6 +76,10 @@
{"jdi_qhd_dualdsi_video", JDI_QHD_DUALDSI_VIDEO_PANEL},
{"jdi_qhd_dualdsi_cmd", JDI_QHD_DUALDSI_CMD_PANEL},
{"jdi_4k_dualdsi_video", JDI_4K_DUALDSI_VIDEO_PANEL},
+ {"jdi_1080p_video", JDI_1080P_VIDEO_PANEL},
+ {"hx8379a_truly_fwvga_video", HX8379A_TRULY_FWVGA_VIDEO_PANEL},
+ {"nt35597_wqxga_video", NOVATEK_WQXGA_VIDEO_PANEL},
+ {"nt35597_wqxga_cmd", NOVATEK_WQXGA_CMD_PANEL},
};
static uint32_t panel_id;
@@ -110,6 +125,14 @@
panelstruct->paneldata = &sharp_wqxga_dualdsi_video_panel_data;
panelstruct->paneldata->panel_operating_mode = 11;
panelstruct->paneldata->panel_with_enable_gpio = 0;
+
+ /*
+ * Even though this panel can be supported with a single pipe,
+ * enable ping-pong split and use two pipes for simplicity sake.
+ */
+ if (platform_is_msm8992())
+ panelstruct->paneldata->panel_operating_mode |= DST_SPLIT_FLAG;
+
panelstruct->panelres = &sharp_wqxga_dualdsi_video_panel_res;
panelstruct->color = &sharp_wqxga_dualdsi_video_color;
panelstruct->videopanel = &sharp_wqxga_dualdsi_video_video_panel;
@@ -121,6 +144,9 @@
panelstruct->panelresetseq
= &sharp_wqxga_dualdsi_video_reset_seq;
panelstruct->backlightinfo = &sharp_wqxga_dualdsi_video_backlight;
+
+ pinfo->labibb = &sharp_wqxga_dualdsi_video_labibb;
+
pinfo->mipi.panel_on_cmds
= sharp_wqxga_dualdsi_video_on_command;
pinfo->mipi.num_of_panel_on_cmds
@@ -131,11 +157,16 @@
= SHARP_WQXGA_DUALDSI_VIDEO_OFF_COMMAND;
memcpy(phy_db->timing,
sharp_wqxga_dualdsi_video_timings, TIMING_SIZE);
+ pinfo->dfps.panel_dfps = sharp_wqxga_dualdsi_video_dfps;
break;
case JDI_QHD_DUALDSI_VIDEO_PANEL:
pan_type = PANEL_TYPE_DSI;
pinfo->lcd_reg_en = 1;
panelstruct->paneldata = &jdi_qhd_dualdsi_video_panel_data;
+
+ if (platform_is_msm8992())
+ panelstruct->paneldata->panel_operating_mode |= DST_SPLIT_FLAG;
+
panelstruct->panelres = &jdi_qhd_dualdsi_video_panel_res;
panelstruct->color = &jdi_qhd_dualdsi_video_color;
panelstruct->videopanel = &jdi_qhd_dualdsi_video_video_panel;
@@ -162,6 +193,10 @@
pan_type = PANEL_TYPE_DSI;
pinfo->lcd_reg_en = 1;
panelstruct->paneldata = &jdi_qhd_dualdsi_cmd_panel_data;
+
+ if (platform_is_msm8992())
+ panelstruct->paneldata->panel_operating_mode |= DST_SPLIT_FLAG;
+
panelstruct->panelres = &jdi_qhd_dualdsi_cmd_panel_res;
panelstruct->color = &jdi_qhd_dualdsi_cmd_color;
panelstruct->videopanel = &jdi_qhd_dualdsi_cmd_video_panel;
@@ -189,6 +224,10 @@
pinfo->lcd_reg_en = 1;
pinfo->mipi.cmds_post_tg = 1;
panelstruct->paneldata = &jdi_4k_dualdsi_video_panel_data;
+
+ if (platform_is_msm8992())
+ panelstruct->paneldata->panel_operating_mode |= DST_SPLIT_FLAG;
+
panelstruct->panelres = &jdi_4k_dualdsi_video_panel_res;
panelstruct->color = &jdi_4k_dualdsi_video_color;
panelstruct->videopanel = &jdi_4k_dualdsi_video_video_panel;
@@ -213,6 +252,118 @@
memcpy(&panelstruct->fbcinfo, &jdi_4k_dualdsi_video_fbc,
sizeof(struct fb_compression));
break;
+ case JDI_1080P_VIDEO_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 1;
+ panelstruct->paneldata = &jdi_1080p_video_panel_data;
+ panelstruct->panelres = &jdi_1080p_video_panel_res;
+ panelstruct->color = &jdi_1080p_video_color;
+ panelstruct->videopanel = &jdi_1080p_video_video_panel;
+ panelstruct->commandpanel = &jdi_1080p_video_command_panel;
+ panelstruct->state = &jdi_1080p_video_state;
+ panelstruct->laneconfig = &jdi_1080p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_1080p_video_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_1080p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &jdi_1080p_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = jdi_1080p_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = JDI_1080P_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = jdi_1080p_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = JDI_1080P_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_1080p_video_timings, TIMING_SIZE);
+ break;
+ case HX8379A_TRULY_FWVGA_VIDEO_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 1;
+ panelstruct->paneldata = &hx8379a_truly_fwvga_video_panel_data;
+ panelstruct->panelres = &hx8379a_truly_fwvga_video_panel_res;
+ panelstruct->color = &hx8379a_truly_fwvga_video_color;
+ panelstruct->videopanel = &hx8379a_truly_fwvga_video_video_panel;
+ panelstruct->commandpanel = &hx8379a_truly_fwvga_video_command_panel;
+ panelstruct->state = &hx8379a_truly_fwvga_video_state;
+ panelstruct->laneconfig = &hx8379a_truly_fwvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8379a_truly_fwvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8379a_truly_fwvga_video_reset_seq;
+ panelstruct->backlightinfo = &hx8379a_truly_fwvga_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = hx8379a_truly_fwvga_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = HX8379A_TRULY_FWVGA_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = hx8379a_truly_fwvga_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = HX8379A_TRULY_FWVGA_VIDEO_OFF_COMMAND;
+ pinfo->mipi.broadcast = 0;
+ memcpy(phy_db->timing,
+ hx8379a_truly_fwvga_video_timings, TIMING_SIZE);
+ case NOVATEK_WQXGA_VIDEO_PANEL:
+ dprintf(ALWAYS, " Novatek 35597 panel selected\n");
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 0;
+ panelstruct->paneldata = &nt35597_wqxga_video_panel_data;
+ panelstruct->paneldata->panel_with_enable_gpio = 0;
+ panelstruct->panelres = &nt35597_wqxga_video_panel_res;
+ panelstruct->color = &nt35597_wqxga_video_color;
+ panelstruct->videopanel = &nt35597_wqxga_video_video_panel;
+ panelstruct->commandpanel = &nt35597_wqxga_video_command_panel;
+ panelstruct->state = &nt35597_wqxga_video_state;
+ panelstruct->laneconfig = &nt35597_wqxga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35597_wqxga_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35597_wqxga_video_reset_seq;
+ panelstruct->backlightinfo = &nt35597_wqxga_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = nt35597_wqxga_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = NT35597_WQXGA_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = nt35597_wqxga_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = NT35597_WQXGA_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ nt35597_wqxga_video_timings, TIMING_SIZE);
+ memcpy(&panelstruct->fbcinfo, &nt35597_wqxga_video_fbc,
+ sizeof(struct fb_compression));
+ break;
+ case NOVATEK_WQXGA_CMD_PANEL:
+ dprintf(ALWAYS, " Novatek 35597 command mode panel selected\n");
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 1;
+ panelstruct->paneldata = &nt35597_wqxga_cmd_panel_data;
+ panelstruct->paneldata->panel_with_enable_gpio = 0;
+ panelstruct->panelres = &nt35597_wqxga_cmd_panel_res;
+ panelstruct->color = &nt35597_wqxga_cmd_color;
+ panelstruct->videopanel = &nt35597_wqxga_cmd_video_panel;
+ panelstruct->commandpanel = &nt35597_wqxga_cmd_command_panel;
+ panelstruct->state = &nt35597_wqxga_cmd_state;
+ panelstruct->laneconfig = &nt35597_wqxga_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35597_wqxga_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &nt35597_wqxga_cmd_reset_seq;
+ panelstruct->backlightinfo = &nt35597_wqxga_cmd_backlight;
+ pinfo->mipi.panel_on_cmds
+ = nt35597_wqxga_cmd_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = NT35597_WQXGA_CMD_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = nt35597_wqxga_cmd_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = NT35597_WQXGA_CMD_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ nt35597_wqxga_cmd_timings, TIMING_SIZE);
+ memcpy(&panelstruct->fbcinfo, &nt35597_wqxga_cmd_fbc,
+ sizeof(struct fb_compression));
+ break;
default:
case UNKNOWN_PANEL:
pan_type = PANEL_TYPE_UNKNOWN;
@@ -221,7 +372,7 @@
return pan_type;
}
-bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
struct msm_panel_info *pinfo,
struct mdss_dsi_phy_ctrl *phy_db)
{
@@ -261,7 +412,7 @@
}
panel_init:
- if (panel_id == JDI_4K_DUALDSI_VIDEO_PANEL)
+ if (panel_id == JDI_4K_DUALDSI_VIDEO_PANEL || panel_id == HX8379A_TRULY_FWVGA_VIDEO_PANEL)
phy_db->regulator_mode = DSI_PHY_REGULATOR_LDO_MODE;
return init_panel_data(panelstruct, pinfo, phy_db);
}
diff --git a/target/msm8994/rules.mk b/target/msm8994/rules.mk
index ec35e53..9c02201 100644
--- a/target/msm8994/rules.mk
+++ b/target/msm8994/rules.mk
@@ -16,10 +16,13 @@
DEFINES += DISPLAY_TYPE_MIPI=1
DEFINES += DISPLAY_TYPE_DSI6G=1
+DEFINES += DISPLAY_EN_20NM_PLL_90_PHASE
+
MODULES += \
dev/keys \
dev/pmic/pm8x41 \
dev/qpnp_wled \
+ dev/qpnp_led \
lib/ptable \
dev/gcdb/display \
lib/libfdt
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index bb22fa4..6cf3653 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -28,6 +28,7 @@
*/
#include <debug.h>
+#include <string.h>
#include <smem.h>
#include <err.h>
#include <msm_panel.h>
@@ -39,12 +40,16 @@
#include <mdp5.h>
#include <scm.h>
#include <endian.h>
+#include <regulator.h>
+#include <qtimer.h>
+#include <arch/defines.h>
#include <platform/gpio.h>
#include <platform/clock.h>
#include <platform/iomap.h>
#include <target/display.h>
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define HFPLL_LDO_ID 12
@@ -57,51 +62,38 @@
#define PMIC_WLED_SLAVE_ID 3
#define PMIC_MPP_SLAVE_ID 2
-static void dsi_pll_20nm_phy_init( uint32_t pll_base, int off)
-{
- mdss_dsi_pll_20nm_sw_reset_st_machine(pll_base);
+#define DSI0_BASE_ADJUST -0x4000
+#define DSI1_BASE_ADJUST -0xA000
- dmb();
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 78, 3, 1, 0, 1
+};
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
- writel(0x80, pll_base + off + 0x0174);
+static struct gpio_pin lcd_reg_en = { /* boost regulator */
+ "pm8994_gpios", 14, 3, 1, 0, 1
+};
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
- writel(0x00, pll_base + off + 0x0174);
- udelay(5000);
- /* Strength ctrl 0 */
- writel(0x77, pll_base + off + 0x0184);
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
- writel(0x7f, pll_base + off + 0x0170);
-
- /* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */
- writel(0x00, pll_base + off + 0x01d4);
-
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_2 */
- writel(0x00, pll_base + off + 0x0178);
-}
+static struct gpio_pin bklt_gpio = { /* lcd_bklt_reg_en */
+ "pmi8994_gpios", 2, 3, 1, 0, 1
+};
static uint32_t dsi_pll_20nm_enable_seq(uint32_t pll_base)
{
uint32_t pll_locked;
-
- /*
- * PLL power up sequence.
- * Add necessary delays recommeded by hardware.
- */
- writel(0x01, pll_base + 0x9c); /* MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN */
- writel(0x07, pll_base + 0x14); /* MMSS_DSI_PHY_PLL_PLL_CNTRL */
- writel(0x00, pll_base + 0x2c); /* MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN */
- udelay(500);
-
- dsi_pll_20nm_phy_init(pll_base, 0x200); /* Ctrl 0 */
+ /* MDSS_DSI_0_PHY_DSIPHY_CTRL_1 */
+ writel(0x00, pll_base + 0x374);
dmb();
-
- pll_locked = mdss_dsi_pll_20nm_lock_status(pll_base);
- if (!pll_locked)
- dprintf(INFO, "%s: DSI PLL lock failed\n", __func__);
- else
- dprintf(INFO, "%s: DSI PLL lock Success\n", __func__);
+ /* MDSS_DSI_0_PHY_DSIPHY_CTRL_0 */
+ writel(0x7f, pll_base + 0x370);
+ dmb();
+ pll_locked = mdss_dsi_pll_20nm_lock_status(pll_base);
+ if (!pll_locked)
+ dprintf(INFO, "%s: DSI PLL lock failed\n", __func__);
+ else
+ dprintf(INFO, "%s: DSI PLL lock Success\n", __func__);
return pll_locked;
}
@@ -110,10 +102,8 @@
{
uint8_t slave_id = 3; /* pmi */
- if (enable) {
- pm8x41_wled_config_slave_id(slave_id);
- qpnp_wled_enable_backlight(enable);
- }
+ pm8x41_wled_config_slave_id(slave_id);
+ qpnp_wled_enable_backlight(enable);
qpnp_ibb_enable(enable);
return NO_ERROR;
}
@@ -266,41 +256,69 @@
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
- uint32_t ret;
+ uint32_t ret = NO_ERROR;
struct mdss_dsi_pll_config *pll_data;
- uint32_t dual_dsi = pinfo->mipi.dual_dsi;
+ uint32_t flags;
+ struct dfps_pll_codes *pll_codes = &pinfo->mipi.pll_codes;
- pll_data = pinfo->mipi.dsi_pll_config;
- if (enable) {
- mdp_gdsc_ctrl(enable);
- mmss_bus_clock_enable();
- mdp_clock_enable();
- ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
- if (ret) {
- dprintf(CRITICAL,
- "%s: Failed to restore MDP security configs",
- __func__);
- mdp_clock_disable();
- mmss_bus_clock_disable();
- mdp_gdsc_ctrl(0);
- return ret;
- }
- mdss_dsi_auto_pll_20nm_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- dsi_pll_20nm_enable_seq(DSI0_PLL_BASE);
- mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
- pll_data->pclk_m,
- pll_data->pclk_n,
- pll_data->pclk_d);
- } else if(!target_cont_splash_screen()) {
- /* Disable clocks if continuous splash off */
- mmss_dsi_clock_disable(dual_dsi);
- mdp_clock_disable();
- mmss_bus_clock_disable();
- mdp_gdsc_ctrl(enable);
+ if (pinfo->dest == DISPLAY_2) {
+ flags = MMSS_DSI_CLKS_FLAG_DSI1;
+ if (pinfo->mipi.dual_dsi)
+ flags |= MMSS_DSI_CLKS_FLAG_DSI0;
+ } else {
+ flags = MMSS_DSI_CLKS_FLAG_DSI0;
+ if (pinfo->mipi.dual_dsi)
+ flags |= MMSS_DSI_CLKS_FLAG_DSI1;
}
+ pll_data = pinfo->mipi.dsi_pll_config;
+
+ if (!enable) {
+ mmss_dsi_clock_disable(flags);
+ goto clks_disable;
+ }
+
+ mdp_gdsc_ctrl(enable);
+ mmss_bus_clock_enable();
+ mdp_clock_enable();
+
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ goto clks_disable;
+ }
+
+ mdss_dsi_auto_pll_20nm_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.pll_1_base, pll_data);
+
+ if (!dsi_pll_20nm_enable_seq(pinfo->mipi.pll_0_base)) {
+ ret = ERROR;
+ dprintf(CRITICAL, "PLL failed to lock!\n");
+ goto clks_disable;
+ }
+
+ pll_codes->codes[0] = readl_relaxed(pinfo->mipi.pll_0_base +
+ MMSS_DSI_PHY_PLL_CORE_KVCO_CODE);
+ pll_codes->codes[1] = readl_relaxed(pinfo->mipi.pll_0_base +
+ MMSS_DSI_PHY_PLL_CORE_VCO_TUNE);
+ dprintf(SPEW, "codes %d %d\n", pll_codes->codes[0],
+ pll_codes->codes[1]);
+
+ mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, flags,
+ pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
+
return NO_ERROR;
+
+clks_disable:
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(0);
+
+ return ret;
}
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
@@ -329,11 +347,68 @@
return NO_ERROR;
}
+static void wled_init(struct msm_panel_info *pinfo)
+{
+ struct qpnp_wled_config_data config = {0};
+ struct labibb_desc *labibb;
+ int display_type = 0;
+
+ labibb = pinfo->labibb;
+
+ if (labibb)
+ display_type = labibb->amoled_panel;
+
+ config.display_type = display_type;
+ config.lab_init_volt = 4600000; /* fixed, see pmi register */
+ config.ibb_init_volt = 1400000; /* fixed, see pmi register */
+
+ if (labibb && labibb->force_config) {
+ config.lab_min_volt = labibb->lab_min_volt;
+ config.lab_max_volt = labibb->lab_max_volt;
+ config.ibb_min_volt = labibb->ibb_min_volt;
+ config.ibb_max_volt = labibb->ibb_max_volt;
+ config.pwr_up_delay = labibb->pwr_up_delay;
+ config.pwr_down_delay = labibb->pwr_down_delay;
+ config.ibb_discharge_en = labibb->ibb_discharge_en;
+ } else {
+ /* default */
+ config.pwr_up_delay = 3;
+ config.pwr_down_delay = 3;
+ config.ibb_discharge_en = 1;
+ if (display_type) { /* amoled */
+ config.lab_min_volt = 4600000;
+ config.lab_max_volt = 4600000;
+ config.ibb_min_volt = 4000000;
+ config.ibb_max_volt = 4000000;
+ } else { /* lcd */
+ config.lab_min_volt = 5500000;
+ config.lab_max_volt = 5500000;
+ config.ibb_min_volt = 5500000;
+ config.ibb_max_volt = 5500000;
+ }
+ }
+
+ dprintf(SPEW, "%s: %d %d %d %d %d %d %d %d %d %d\n", __func__,
+ config.display_type,
+ config.lab_min_volt, config.lab_max_volt,
+ config.ibb_min_volt, config.ibb_max_volt,
+ config.lab_init_volt, config.ibb_init_volt,
+ config.pwr_up_delay, config.pwr_down_delay,
+ config.ibb_discharge_en);
+
+
+ /* QPNP WLED init for display backlight */
+ pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID);
+
+ qpnp_wled_init(&config);
+}
+
int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
if (enable) {
regulator_enable(); /* L2, L12, L14, and L28 */
mdelay(10);
+ wled_init(pinfo);
qpnp_ibb_enable(true); /* +5V and -5V */
mdelay(50);
@@ -363,20 +438,50 @@
return NO_ERROR;
}
+int target_display_get_base_offset(uint32_t base)
+{
+ if(platform_is_msm8992()) {
+ if (base == MIPI_DSI0_BASE)
+ return DSI0_BASE_ADJUST;
+ else if (base == MIPI_DSI1_BASE)
+ return DSI1_BASE_ADJUST;
+ }
+
+ return 0;
+}
+
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
bool ret = true;
- ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
+ panel_name += strspn(panel_name, " ");
+
+ if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+ if (buf_size < (prefix_string_len + LK_OVERRIDE_PANEL_LEN +
+ strlen(HDMI_CONTROLLER_STRING))) {
+ dprintf(CRITICAL, "command line argument is greater than buffer size\n");
+ return false;
+ }
+
+ strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+ buf_size -= prefix_string_len;
+ strlcat(pbuf, LK_OVERRIDE_PANEL, buf_size);
+ buf_size -= LK_OVERRIDE_PANEL_LEN;
+ strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
+ } else {
+ ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
+ }
return ret;
}
void target_display_init(const char *panel_name)
{
- panel_name += strspn(panel_name, " ");
+ char cont_splash = '\0';
+ set_panel_cmd_string(panel_name, &cont_splash);
+ panel_name += strspn(panel_name, " ");
if (!strcmp(panel_name, NO_PANEL_CONFIG)
|| !strcmp(panel_name, SIM_VIDEO_PANEL)
|| !strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL)
@@ -385,11 +490,19 @@
dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
panel_name);
return;
+ } else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+ return;
}
- if (gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR)) {
+
+ if (gcdb_display_init(panel_name, MDP_REV_50, (void *)MIPI_FB_ADDR)) {
target_force_cont_splash_disable(true);
msm_display_off();
}
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/target_display.c b/target/target_display.c
index 4b07cc8..ae014e1 100644
--- a/target/target_display.c
+++ b/target/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -30,6 +30,8 @@
#include <debug.h>
#include <platform.h>
+#include "include/msm_panel.h"
+
__WEAK int mdp_lcdc_config(void)
{
return 0;
@@ -62,6 +64,10 @@
{
return 0;
}
+__WEAK int target_display_get_base_offset(uint32_t base)
+{
+ return 0;
+}
__WEAK int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
return 0;
diff --git a/target/thulium/init.c b/target/thulium/init.c
index c1b13bb..28c6b2c 100644
--- a/target/thulium/init.c
+++ b/target/thulium/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -53,6 +53,17 @@
#include <ufs.h>
#include <boot_device.h>
#include <qmp_phy.h>
+#include <sdhci_msm.h>
+#include <qusb2_phy.h>
+
+#define CE_INSTANCE 1
+#define CE_EE 1
+#define CE_FIFO_SIZE 64
+#define CE_READ_PIPE 3
+#define CE_WRITE_PIPE 2
+#define CE_READ_PIPE_LOCK_GRP 0
+#define CE_WRITE_PIPE_LOCK_GRP 0
+#define CE_ARRAY_SIZE 20
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
@@ -70,12 +81,10 @@
struct mmc_device *dev;
struct ufs_dev ufs_device;
-extern void ulpi_write(unsigned val, unsigned reg);
-
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(2, 0, BLSP1_UART1_BASE);
+ uart_dm_init(8, 0, BLSP2_UART1_BASE);
#endif
}
@@ -97,7 +106,7 @@
thread_sleep(1);
/* Get status of P_GPIO_5 */
- pm8x41_gpio_get(3, &status);
+ pm8x41_gpio_get(2, &status);
return !status; /* active low */
}
@@ -167,6 +176,7 @@
config.bus_width = DATA_BUS_WIDTH_8BIT;
config.max_clk_rate = MMC_CLK_192MHZ;
+ config.hs400_support = 1;
/* Try slot 1*/
config.slot = 1;
@@ -212,22 +222,22 @@
platform_read_boot_config();
+#ifdef MMC_SDHCI_SUPPORT
if (platform_boot_dev_isemmc())
{
target_sdc_init();
}
- else
+#endif
+#ifdef UFS_SUPPORT
+ if (!platform_boot_dev_isemmc())
{
ufs_device.base = UFS_BASE;
ufs_init(&ufs_device);
}
+#endif
/* Storage initialization is complete, read the partition table info */
- if (partition_read_table())
- {
- dprintf(CRITICAL, "Error reading the partition table info\n");
- ASSERT(0);
- }
+ mmc_read_partition_table(0);
}
unsigned board_machtype(void)
@@ -250,7 +260,10 @@
switch(platform) {
case MSMTHULIUM:
- board->baseband = BASEBAND_MSM;
+ if (board->platform_version == 0x10000)
+ board->baseband = BASEBAND_APQ;
+ else
+ board->baseband = BASEBAND_MSM;
break;
default:
dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
@@ -344,8 +357,38 @@
return 1;
}
-void target_fastboot_init(void)
+crypto_engine_type board_ce_type(void)
{
- /* We are entering fastboot mode, so read partition table */
- mmc_read_partition_table(1);
+ return CRYPTO_ENGINE_TYPE_SW;
+}
+
+/* Set up params for h/w CE. */
+void target_crypto_init_params()
+{
+ struct crypto_init_params ce_params;
+
+ /* Set up base addresses and instance. */
+ ce_params.crypto_instance = CE_INSTANCE;
+ ce_params.crypto_base = MSM_CE_BASE;
+ ce_params.bam_base = MSM_CE_BAM_BASE;
+
+ /* Set up BAM config. */
+ ce_params.bam_ee = CE_EE;
+ ce_params.pipes.read_pipe = CE_READ_PIPE;
+ ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
+
+ /* Assign buffer sizes. */
+ ce_params.num_ce = CE_ARRAY_SIZE;
+ ce_params.read_fifo_size = CE_FIFO_SIZE;
+ ce_params.write_fifo_size = CE_FIFO_SIZE;
+
+ /* BAM is initialized by TZ for this platform.
+ * Do not do it again as the initialization address space
+ * is locked.
+ */
+ ce_params.do_bam_init = 0;
+
+ crypto_init_params(&ce_params);
}