| commit | 88cbd4198f751db318c089ed0f2f74086fc2f8a6 | [log] [tgz] |
|---|---|---|
| author | Linux Build Service Account <lnxbuild@localhost> | Wed Feb 25 08:40:33 2015 -0800 |
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | Wed Feb 25 08:40:33 2015 -0800 |
| tree | fc80052b6d68c15c2829dd3c3dca175c8e5e8aea | |
| parent | d382d0b05e678da3171a5158cceb0a278eb690c4 [diff] | |
| parent | fed864d5470e7fb14cac7e60a15349421de8a71e [diff] |
Merge "arch: arm: Add DSB instruction before cache invalidate"
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S index 22d9a2b..cfcbaa4 100644 --- a/arch/arm/cache-ops.S +++ b/arch/arm/cache-ops.S
@@ -328,6 +328,7 @@ /* void arch_flush_invalidate_cache_range(addr_t start, size_t len); */ FUNCTION(arch_clean_invalidate_cache_range) + dsb add r2, r0, r1 // Calculate the end address bic r0,#(CACHE_LINE-1) // Align start with cache line 0: