| commit | 8cd82cb0753f80f887b6327adf477361ede67e00 | [log] [tgz] |
|---|---|---|
| author | Channagoud Kadabi <ckadabi@codeaurora.org> | Wed Feb 04 21:04:19 2015 -0800 |
| committer | Channagoud Kadabi <ckadabi@codeaurora.org> | Thu Feb 05 12:10:40 2015 -0800 |
| tree | 4c72db0760390b9fb92162bb50e4fce1ee6d6856 | |
| parent | 95f66f600ad07561643c71ed3056cb7ecd3f6097 [diff] |
arch:arm: Fix undefined instruction for vfp VFP enable bit needs CP10 & CP11 in CPACR (Co Processor access control register) to be enabled, otherwise floating point exception enable (FPEX.EN) would fail with undefined instruction. Use isb to make sure CP10 & CP11 are enabled in CPACR before enabling FPEX.EN bit. Change-Id: Ie33edc8c96ae2264acd51a53c2b9a302815b29d8