arch:arm: Fix undefined instruction for vfp
VFP enable bit needs CP10 & CP11 in CPACR (Co Processor access
control register) to be enabled, otherwise floating point exception
enable (FPEX.EN) would fail with undefined instruction. Use isb to
make sure CP10 & CP11 are enabled in CPACR before enabling FPEX.EN
bit.
Change-Id: Ie33edc8c96ae2264acd51a53c2b9a302815b29d8
diff --git a/arch/arm/arch.c b/arch/arm/arch.c
index dc171b4..6b5cf72 100644
--- a/arch/arm/arch.c
+++ b/arch/arm/arch.c
@@ -25,6 +25,7 @@
#include <arch/ops.h>
#include <arch/arm.h>
#include <arch/arm/mmu.h>
+#include <arch/defines.h>
#include <platform.h>
#if ARM_CPU_CORTEX_A8
@@ -59,6 +60,8 @@
val |= (3<<22)|(3<<20);
__asm__ volatile("mcr p15, 0, %0, c1, c0, 2" :: "r" (val));
+ isb();
+
/* set enable bit in fpexc */
__asm__ volatile("mrc p10, 7, %0, c8, c0, 0" : "=r" (val));
val |= (1<<30);