Merge "platform: msm_shared: Rename tellurium / terbium to MSM8952/MSM8956."
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index b51d450..35373d8 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -68,6 +68,7 @@
#include "bootimg.h"
#include "fastboot.h"
#include "sparse_format.h"
+#include "meta_format.h"
#include "mmc.h"
#include "devinfo.h"
#include "board.h"
@@ -1904,24 +1905,25 @@
lun = partition_get_lun(index);
mmc_set_lun(lun);
-#if MMC_SDHCI_SUPPORT
- if (mmc_erase_card(ptn, size)) {
- fastboot_fail("failed to erase partition\n");
- return;
- }
-#else
- BUF_DMA_ALIGN(out, DEFAULT_ERASE_SIZE);
- size = partition_get_size(index);
- if (size > DEFAULT_ERASE_SIZE)
- size = DEFAULT_ERASE_SIZE;
+ if (platform_boot_dev_isemmc())
+ {
+ if (mmc_erase_card(ptn, size)) {
+ fastboot_fail("failed to erase partition\n");
+ return;
+ }
+ } else {
+ BUF_DMA_ALIGN(out, DEFAULT_ERASE_SIZE);
+ size = partition_get_size(index);
+ if (size > DEFAULT_ERASE_SIZE)
+ size = DEFAULT_ERASE_SIZE;
- /* Simple inefficient version of erase. Just writing
- 0 in first several blocks */
- if (mmc_write(ptn , size, (unsigned int *)out)) {
- fastboot_fail("failed to erase partition");
- return;
+ /* Simple inefficient version of erase. Just writing
+ 0 in first several blocks */
+ if (mmc_write(ptn , size, (unsigned int *)out)) {
+ fastboot_fail("failed to erase partition");
+ return;
+ }
}
-#endif
fastboot_okay("");
}
@@ -2015,6 +2017,33 @@
return;
}
+void cmd_flash_meta_img(const char *arg, void *data, unsigned sz)
+{
+ int i, images;
+ meta_header_t *meta_header;
+ img_header_entry_t *img_header_entry;
+
+ meta_header = (meta_header_t*) data;
+ img_header_entry = (img_header_entry_t*) (data+sizeof(meta_header_t));
+
+ images = meta_header->img_hdr_sz / sizeof(img_header_entry_t);
+
+ for (i=0; i<images; i++) {
+
+ if((img_header_entry[i].ptn_name == NULL) ||
+ (img_header_entry[i].start_offset == 0) ||
+ (img_header_entry[i].size == 0))
+ break;
+
+ cmd_flash_mmc_img(img_header_entry[i].ptn_name,
+ (void *) data + img_header_entry[i].start_offset,
+ img_header_entry[i].size);
+ }
+
+ fastboot_okay("");
+ return;
+}
+
void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz)
{
unsigned int chunk;
@@ -2192,6 +2221,7 @@
void cmd_flash_mmc(const char *arg, void *data, unsigned sz)
{
sparse_header_t *sparse_header;
+ meta_header_t *meta_header;
#ifdef SSD_ENABLE
/* 8 Byte Magic + 2048 Byte xml + Encrypted Data */
@@ -2278,10 +2308,13 @@
#endif
sparse_header = (sparse_header_t *) data;
- if (sparse_header->magic != SPARSE_HEADER_MAGIC)
- cmd_flash_mmc_img(arg, data, sz);
- else
+ meta_header = (meta_header_t *) data;
+ if (sparse_header->magic == SPARSE_HEADER_MAGIC)
cmd_flash_mmc_sparse_img(arg, data, sz);
+ else if (meta_header->magic == META_HEADER_MAGIC)
+ cmd_flash_meta_img(arg, data, sz);
+ else
+ cmd_flash_mmc_img(arg, data, sz);
return;
}
diff --git a/app/aboot/fastboot.c b/app/aboot/fastboot.c
index 9dac985..4dc955d 100644
--- a/app/aboot/fastboot.c
+++ b/app/aboot/fastboot.c
@@ -456,6 +456,10 @@
snprintf((char *)response, MAX_RSP_SIZE, "DATA%08x", len);
if (usb_if.usb_write(response, strlen((const char *)response)) < 0)
return;
+ /*
+ * Discard the cache contents before starting the download
+ */
+ arch_invalidate_cache_range((addr_t) download_base, sz);
r = usb_if.usb_read(download_base, len);
if ((r < 0) || ((unsigned) r != len)) {
diff --git a/app/aboot/meta_format.h b/app/aboot/meta_format.h
new file mode 100644
index 0000000..7bf6812
--- /dev/null
+++ b/app/aboot/meta_format.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of The Linux Foundation nor
+ * the names of its contributors may be used to endorse or promote
+ * products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _META_FORMAT_H_
+#define _META_FORMAT_H_
+
+#define META_HEADER_MAGIC 0xce1ad63c
+#define MAX_GPT_NAME_SIZE 72
+typedef unsigned int u32;
+typedef unsigned short int u16;
+
+typedef struct meta_header {
+ u32 magic; /* 0xce1ad63c */
+ u16 major_version; /* (0x1) - reject images with higher major versions */
+ u16 minor_version; /* (0x0) - allow images with higer minor versions */
+ char img_version[64]; /* Top level version for images in this meta */
+ u16 meta_hdr_sz; /* size of this header */
+ u16 img_hdr_sz; /* size of img_header_entry list */
+} meta_header_t;
+
+typedef struct img_header_entry {
+ char ptn_name[MAX_GPT_NAME_SIZE];
+ u32 start_offset;
+ u32 size;
+} img_header_entry_t;
+
+#endif
diff --git a/dev/gcdb/display/include/panel_auo_qvga_cmd.h b/dev/gcdb/display/include/panel_auo_qvga_cmd.h
new file mode 100644
index 0000000..4215108
--- /dev/null
+++ b/dev/gcdb/display/include/panel_auo_qvga_cmd.h
@@ -0,0 +1,310 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_AUO_QVGA_CMD_H_
+#define _PANEL_AUO_QVGA_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config auo_qvga_cmd_panel_data = {
+ "qcom,mdss_dsi_auo_qvga_cmd", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 1, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ""
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution auo_qvga_cmd_panel_res = {
+ 320, 320, 4, 4, 4, 0, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info auo_qvga_cmd_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char auo_qvga_cmd_on_cmd0[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x00, 0xFF, 0xFF,
+};
+
+static char auo_qvga_cmd_on_cmd1[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xBD, 0x01, 0x90, 0x14,
+ 0x14, 0x00, 0xFF, 0xFF,
+};
+
+static char auo_qvga_cmd_on_cmd2[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xBE, 0x01, 0x90, 0x14,
+ 0x14, 0x01, 0xFF, 0xFF,
+};
+
+static char auo_qvga_cmd_on_cmd3[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xBF, 0x01, 0x90, 0x14,
+ 0x14, 0x00, 0xFF, 0xFF,
+};
+
+static char auo_qvga_cmd_on_cmd4[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xBB, 0x07, 0x07, 0x07,
+};
+
+static char auo_qvga_cmd_on_cmd5[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xC7, 0x40, 0xFF, 0xFF,
+};
+
+static char auo_qvga_cmd_on_cmd6[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x02, 0xFF, 0xFF,
+};
+
+static char auo_qvga_cmd_on_cmd7[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xFE, 0x08, 0x50, 0xFF,
+};
+
+static char auo_qvga_cmd_on_cmd8[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xC3, 0xF2, 0x95, 0x04,
+};
+
+static char auo_qvga_cmd_on_cmd9[] = {
+ 0x04, 0x00, 0x15, 0x80,
+};
+
+static char auo_qvga_cmd_on_cmd10[] = {
+ 0x06, 0x00, 0x39, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x01, 0xFF, 0xFF,
+};
+
+static char auo_qvga_cmd_on_cmd11[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB0, 0x03, 0x03, 0x03,
+};
+
+static char auo_qvga_cmd_on_cmd12[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB1, 0x05, 0x05, 0x05,
+};
+
+static char auo_qvga_cmd_on_cmd13[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB2, 0x01, 0x01, 0x01,
+};
+
+static char auo_qvga_cmd_on_cmd14[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB4, 0x07, 0x07, 0x07,
+};
+
+static char auo_qvga_cmd_on_cmd15[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB5, 0x03, 0x03, 0x03,
+};
+
+static char auo_qvga_cmd_on_cmd16[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB6, 0x53, 0x53, 0x53,
+};
+
+static char auo_qvga_cmd_on_cmd17[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB7, 0x33, 0x33, 0x33,
+};
+
+static char auo_qvga_cmd_on_cmd18[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB8, 0x23, 0x23, 0x23,
+};
+
+static char auo_qvga_cmd_on_cmd19[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB9, 0x03, 0x03, 0x03,
+};
+
+static char auo_qvga_cmd_on_cmd20[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xBA, 0x03, 0x03, 0x03,
+};
+
+static char auo_qvga_cmd_on_cmd21[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xBE, 0x32, 0x30, 0x70,
+};
+
+static char auo_qvga_cmd_on_cmd22[] = {
+ 0x08, 0x00, 0x39, 0xC0,
+ 0xCF, 0xFF, 0xD4, 0x95,
+ 0xEF, 0x4F, 0x00, 0x04,
+};
+
+static char auo_qvga_cmd_on_cmd23[] = {
+ 0x35, 0x01, 0x15, 0x80,
+};
+
+static char auo_qvga_cmd_on_cmd24[] = {
+ 0x36, 0x01, 0x15, 0x80,
+};
+
+static char auo_qvga_cmd_on_cmd25[] = {
+ 0xC0, 0x20, 0x15, 0x80,
+};
+
+static char auo_qvga_cmd_on_cmd26[] = {
+ 0x07, 0x00, 0x39, 0xC0,
+ 0xC2, 0x17, 0x17, 0x17,
+ 0x17, 0x17, 0x0B, 0xFF,
+};
+
+static char auo_qvga_cmd_on_cmd27[] = {
+ 0x00, 0x00, 0x32, 0x80,
+};
+
+static char auo_qvga_cmd_on_cmd28[] = {
+ 0x11, 0x00, 0x05, 0x80,
+};
+
+static char auo_qvga_cmd_on_cmd29[] = {
+ 0x29, 0x00, 0x05, 0x80,
+};
+
+static struct mipi_dsi_cmd auo_qvga_cmd_on_command[] = {
+ {0xc, auo_qvga_cmd_on_cmd0, 0x00},
+ {0xc, auo_qvga_cmd_on_cmd1, 0x00},
+ {0xc, auo_qvga_cmd_on_cmd2, 0x00},
+ {0xc, auo_qvga_cmd_on_cmd3, 0x10},
+ {0x8, auo_qvga_cmd_on_cmd4, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd5, 0x00},
+ {0xc, auo_qvga_cmd_on_cmd6, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd7, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd8, 0x00},
+ {0x4, auo_qvga_cmd_on_cmd9, 0x00},
+ {0xc, auo_qvga_cmd_on_cmd10, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd11, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd12, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd13, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd14, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd15, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd16, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd17, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd18, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd19, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd20, 0x00},
+ {0x8, auo_qvga_cmd_on_cmd21, 0x00},
+ {0xc, auo_qvga_cmd_on_cmd22, 0x00},
+ {0x4, auo_qvga_cmd_on_cmd23, 0x00},
+ {0x4, auo_qvga_cmd_on_cmd24, 0x00},
+ {0x4, auo_qvga_cmd_on_cmd25, 0x00},
+ {0xc, auo_qvga_cmd_on_cmd26, 0x00},
+ {0x4, auo_qvga_cmd_on_cmd27, 0x00},
+ {0x4, auo_qvga_cmd_on_cmd28, 0xFF},
+ {0x4, auo_qvga_cmd_on_cmd29, 0x00}
+};
+
+#define auo_QVGA_CMD_ON_COMMAND 30
+
+static char auo_qvga_cmdoff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char auo_qvga_cmdoff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd auo_qvga_cmd_off_command[] = {
+ {0x4, auo_qvga_cmdoff_cmd0, 0x32},
+ {0x4, auo_qvga_cmdoff_cmd1, 0x78}
+};
+
+#define auo_QVGA_CMD_OFF_COMMAND 2
+
+static struct command_state auo_qvga_cmd_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info auo_qvga_cmd_command_panel = {
+ 1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info auo_qvga_cmd_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration auo_qvga_cmd_lane_config = {
+ 1, 0, 1, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t auo_qvga_cmd_timings[] = {
+ 0x5F, 0x12, 0x0A, 0x00, 0x32, 0x34, 0x10, 0x16, 0x0F, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing auo_qvga_cmd_timing_info = {
+ 0, 4, 0x05, 0x15
+};
+
+static struct panel_reset_sequence auo_qvga_cmd_panel_reset_seq = {
+ { 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight auo_qvga_cmd_backlight = {
+ 2, 1, 255, 100, 1, "PMIC_8941"
+};
+
+#endif /*_PANEL_AUO_QVGA_CMD_H_*/
diff --git a/dev/gcdb/display/include/panel_hx8394d_720p_video.h b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
index 3ab32f8..ac4806f 100644
--- a/dev/gcdb/display/include/panel_hx8394d_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
@@ -283,6 +283,6 @@
1, 1, 4095, 100, 1, "PMIC_8941"
};
-#define HX8394D_720P_VIDEO_SIGNATURE 0xFFFF
+#define HX8394D_720P_VIDEO_SIGNATURE 0xa0087
#endif /*_HX8394D_720P_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_r61318_hd_video.h b/dev/gcdb/display/include/panel_r61318_hd_video.h
index 72c27c2..7662312 100644
--- a/dev/gcdb/display/include/panel_r61318_hd_video.h
+++ b/dev/gcdb/display/include/panel_r61318_hd_video.h
@@ -181,20 +181,25 @@
};
static char r61318_hd_video_on_cmd19[] = {
- 0x02, 0x00, 0x39, 0xC0,
- 0x53, 0x24, 0xFF, 0xFF,
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBB, 0x2E, 0xFF, 0xFF
};
static char r61318_hd_video_on_cmd20[] = {
0x02, 0x00, 0x39, 0xC0,
- 0x51, 0xff, 0xFF, 0xFF,
+ 0x53, 0x2C, 0xFF, 0xFF
};
static char r61318_hd_video_on_cmd21[] = {
- 0x11, 0x00, 0x05, 0x80
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x51, 0xff, 0xFF, 0xFF,
};
static char r61318_hd_video_on_cmd22[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char r61318_hd_video_on_cmd23[] = {
0x29, 0x00, 0x05, 0x80
};
@@ -220,11 +225,12 @@
{0x8, r61318_hd_video_on_cmd18, 0x00},
{0x8, r61318_hd_video_on_cmd19, 0x00},
{0x8, r61318_hd_video_on_cmd20, 0x00},
- {0x4, r61318_hd_video_on_cmd21, 0x78},
- {0x4, r61318_hd_video_on_cmd22, 0x32}
+ {0x8, r61318_hd_video_on_cmd21, 0x00},
+ {0x4, r61318_hd_video_on_cmd22, 0x78},
+ {0x4, r61318_hd_video_on_cmd23, 0x32}
};
-#define R61318_HD_VIDEO_ON_COMMAND 23
+#define R61318_HD_VIDEO_ON_COMMAND 24
static char r61318_hd_videooff_cmd0[] = {
diff --git a/dev/gcdb/display/include/panel_sharp_1080p_cmd.h b/dev/gcdb/display/include/panel_sharp_1080p_cmd.h
new file mode 100644
index 0000000..353cbc3
--- /dev/null
+++ b/dev/gcdb/display/include/panel_sharp_1080p_cmd.h
@@ -0,0 +1,200 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_SHARP_1080P_CMD_H_
+#define _PANEL_SHARP_1080P_CMD_H_
+
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config sharp_1080p_cmd_panel_data = {
+ "qcom,mdss_dsi_sharp_1080p_cmd", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 1, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution sharp_1080p_cmd_panel_res = {
+ 1080, 1920, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info sharp_1080p_cmd_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char sharp_1080p_cmd_on_cmd0[] = {
+ 0xbb, 0x10, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd1[] = {
+ 0xb0, 0x03, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd2[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd3[] = {
+ 0x51, 0xff, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd4[] = {
+ 0x53, 0x24, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd5[] = {
+ 0xff, 0x23, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd6[] = {
+ 0x08, 0x05, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd7[] = {
+ 0x46, 0x90, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd8[] = {
+ 0xff, 0x10, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd9[] = {
+ 0xff, 0xf0, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd10[] = {
+ 0x92, 0x01, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd11[] = {
+ 0xff, 0x10, 0x15, 0x80
+};
+
+static char sharp_1080p_cmd_on_cmd12[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd sharp_1080p_cmd_on_command[] = {
+ {0x4 , sharp_1080p_cmd_on_cmd0, 0x00},
+ {0x4 , sharp_1080p_cmd_on_cmd1, 0x00},
+ {0x3 , sharp_1080p_cmd_on_cmd2, 0x78},
+ {0x4 , sharp_1080p_cmd_on_cmd3, 0x00},
+ {0x4 , sharp_1080p_cmd_on_cmd4, 0x00},
+ {0x4 , sharp_1080p_cmd_on_cmd5, 0x00},
+ {0x4 , sharp_1080p_cmd_on_cmd6, 0x00},
+ {0x4 , sharp_1080p_cmd_on_cmd7, 0x00},
+ {0x4 , sharp_1080p_cmd_on_cmd8, 0x00},
+ {0x4 , sharp_1080p_cmd_on_cmd9, 0x00},
+ {0x4 , sharp_1080p_cmd_on_cmd10, 0x00},
+ {0x4 , sharp_1080p_cmd_on_cmd11, 0x00},
+ {0x3 , sharp_1080p_cmd_on_cmd12, 0x28}
+};
+
+#define SHARP_1080P_CMD_ON_COMMAND 13
+
+
+static char sharp_1080p_cmdoff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char sharp_1080p_cmdoff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd sharp_1080p_cmd_off_command[] = {
+ {0x4 , sharp_1080p_cmdoff_cmd0, 0},
+ {0x4 , sharp_1080p_cmdoff_cmd1, 0}
+};
+
+#define SHARP_1080P_CMD_OFF_COMMAND 2
+
+
+static struct command_state sharp_1080p_cmd_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info sharp_1080p_cmd_command_panel = {
+ 1, 1, 1, 0, 0, 0x2c, 0x3c, 0, 0, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info sharp_1080p_cmd_video_panel = {
+ 0, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration sharp_1080p_cmd_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t sharp_1080p_cmd_timings[] = {
+ 0xe7, 0x36, 0x24, 0x00, 0x66, 0x6a, 0x2a, 0x3a, 0x2d, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing sharp_1080p_cmd_timing_info = {
+ 0x0, 0x04, 0x04, 0x1b
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence sharp_1080p_cmd_panel_reset_seq = {
+ { 1, 0, 1, }, { 10, 10, 10, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+static struct backlight sharp_1080p_cmd_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#endif /*_PANEL_sharp_1080P_CMD_H_*/
diff --git a/lib/libc/malloc.c b/lib/libc/malloc.c
index 6f05f63..9cec44c 100644
--- a/lib/libc/malloc.c
+++ b/lib/libc/malloc.c
@@ -24,6 +24,7 @@
#include <malloc.h>
#include <string.h>
#include <lib/heap.h>
+#include <arch/ops.h>
void *malloc(size_t size)
{
@@ -32,7 +33,11 @@
void *memalign(size_t boundary, size_t size)
{
- return heap_alloc(size, boundary);
+ void *ptr;
+ ptr = heap_alloc(size, boundary);
+ /* Clean the cache before giving the memory */
+ arch_invalidate_cache_range((addr_t) ptr, size);
+ return ptr;
}
void *calloc(size_t count, size_t size)
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index e2a66fe..bca7c54 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -280,4 +280,5 @@
#define SECURITY_CONTROL_CORE_FEATURE_CONFIG0 0x0005E004
/* EBI2 */
#define TLMM_EBI2_EMMC_GPIO_CFG (TLMM_BASE_ADDR + 0x00111000)
+#define TCSR_BOOT_MISC_DETECT 0x193D100
#endif
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index fd56c0e..d98bbdf 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -265,4 +265,5 @@
#define HS_TIMER_CTRL 0x0BC
#define TCSR_TZ_WONCE 0x193D000
+#define TCSR_BOOT_MISC_DETECT 0x193D100
#endif
diff --git a/platform/msm8994/platform.c b/platform/msm8994/platform.c
index 507158b..eaaadc0 100644
--- a/platform/msm8994/platform.c
+++ b/platform/msm8994/platform.c
@@ -40,7 +40,7 @@
#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
/* LK memory - cacheable, write through */
-#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
MMU_MEMORY_AP_READ_WRITE)
/* Peripherals - non-shared device */
@@ -123,7 +123,7 @@
sections * MB,
ptn_entry.start +
sections * MB,
- (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
}
}
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index 1612e61..95d636e 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -101,6 +101,7 @@
#define MMC_USR_WP 171
#define MMC_ERASE_TIMEOUT_MULT 223
#define MMC_HC_ERASE_GRP_SIZE 224
+#define MMC_PARTITION_CONFIG 179
/* Values for ext csd fields */
#define MMC_HS_TIMING 0x1
@@ -117,6 +118,13 @@
#define MMC_HC_ERASE_MULT (512 * 1024)
#define RST_N_FUNC_ENABLE BIT(0)
+/* RPMB Related */
+#define RPMB_PART_MIN_SIZE (128 * 2014)
+#define RPMB_SIZE_MULT 168
+#define REL_WR_SEC_C 222
+#define PARTITION_ACCESS_MASK 0x7
+#define MAX_RPMB_CMDS 0x3
+
/* Command related */
#define MMC_MAX_COMMAND_RETRY 1000
#define MMC_MAX_CARD_STAT_RETRY 10000
@@ -226,6 +234,12 @@
#define MMC_CARD_MMC(card) ((card->type == MMC_TYPE_STD_MMC) || \
(card->type == MMC_TYPE_MMCHC))
+enum part_access_type
+{
+ PART_ACCESS_DEFAULT = 0x0,
+ PART_ACCESS_RPMB = 0x3,
+};
+
/* CSD Register.
* Note: not all the fields have been defined here
*/
@@ -292,6 +306,8 @@
uint8_t *ext_csd; /* Ext CSD for the card info */
uint32_t raw_csd[4]; /* Raw CSD for the card */
uint32_t raw_scr[2]; /* SCR for SD card */
+ uint32_t rpmb_size; /* Size of rpmb partition */
+ uint32_t rel_wr_count; /* Reliable write count */
struct mmc_cid cid; /* CID structure */
struct mmc_csd csd; /* CSD structure */
struct mmc_sd_scr scr; /* SCR structure */
@@ -337,4 +353,6 @@
void mmc_put_card_to_sleep(struct mmc_device *dev);
/* API: Change the driver type of the card */
bool mmc_set_drv_type(struct sdhci_host *host, struct mmc_card *card, uint8_t drv_type);
+/* API: Send the read & write command sequence to rpmb */
+uint32_t mmc_sdhci_rpmb_send(struct mmc_device *dev, struct mmc_command *cmd);
#endif
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index 283f1cc..83685d5 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -256,6 +256,7 @@
#define PRNG_CMD_ID 0x01
#define IS_CALL_AVAIL_CMD 0x01
+#define IS_SECURE_BOOT_ENABLED 0x04
/* Download Mode specific arguments to be passed to TZ */
#define SCM_EDLOAD_MODE 0x01
@@ -337,6 +338,7 @@
#define SCM_SVC_PWR 0x9
#define SCM_IO_DISABLE_PMIC_ARBITER 0x1
+#define SCM_IO_DISABLE_PMIC_ARBITER1 0x2
#define SCM_SVC_MILESTONE_32_64_ID 0x1
#define SCM_SVC_MILESTONE_CMD_ID 0xf
@@ -349,6 +351,11 @@
/* Apps CE resource. */
#define TZ_RESOURCE_CE_AP 2
+/* Secure IO Service IDs */
+#define SCM_IO_READ 0x1
+#define SCM_IO_WRITE 0x2
+#define SCM_SVC_IO 0x5
+
uint8_t switch_ce_chn_cmd(enum ap_ce_channel_type channel);
/**
@@ -443,4 +450,5 @@
* Used for checking if armv8 SCM support present
*/
void scm_init();
+bool is_secure_boot_enable();
#endif
diff --git a/platform/msm_shared/include/sdhci.h b/platform/msm_shared/include/sdhci.h
index 604ac81..c0b484d 100644
--- a/platform/msm_shared/include/sdhci.h
+++ b/platform/msm_shared/include/sdhci.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -100,6 +100,7 @@
uint32_t cmd_retry; /* Retry the command, if card is busy */
uint32_t cmd23_support; /* If card supports cmd23 */
uint64_t cmd_timeout; /* Command timeout in us */
+ bool write_flag; /* Write flag, for reliable write cases */
struct mmc_data data; /* Data pointer */
};
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index f8ff3bb..66f95c6 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -414,6 +414,10 @@
tmp |= BIT(28);
writel(tmp, mipi->ctl_base + LANE_CTL);
}
+
+ if ((mipi->mode == DSI_VIDEO_MODE) && mipi->tx_eot_append)
+ writel(0x1, mipi->ctl_base + EOT_PACKET_CTRL);
+
#endif
return 0;
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index 2632961..3bc7110 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -240,6 +240,9 @@
card->wp_grp_size = (card->csd.wp_grp_size + 1) * (card->csd.erase_grp_size + 1) \
* (card->csd.erase_grp_mult + 1);
+ card->rpmb_size = RPMB_PART_MIN_SIZE * card->ext_csd[RPMB_SIZE_MULT];
+ card->rel_wr_count = card->ext_csd[REL_WR_SEC_C];
+
dprintf(SPEW, "Decoded CSD fields:\n");
dprintf(SPEW, "cmmc_structure: %u\n", mmc_csd.cmmc_structure);
dprintf(SPEW, "card_cmd_class: %x\n", mmc_csd.card_cmd_class);
@@ -2366,3 +2369,107 @@
if(sdhci_send_command(&dev->host, &cmd))
dprintf(CRITICAL, "card sleep error: %s\n", __func__);
}
+
+/*
+ * Switch the partition access type to rpmb or default
+ */
+static uint32_t mmc_sdhci_switch_part(struct mmc_device *dev, uint32_t type)
+{
+ uint32_t part_access;
+ uint32_t ret;
+
+ /* Clear the partition access */
+ part_access = dev->card.ext_csd[MMC_PARTITION_CONFIG] & ~PARTITION_ACCESS_MASK;
+ part_access |= type;
+
+ ret = mmc_switch_cmd(&dev->host, &dev->card, MMC_ACCESS_WRITE, MMC_PARTITION_CONFIG, part_access);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to switch partition to type: %u\n", type);
+ return 1;
+ }
+
+ dev->card.ext_csd[MMC_PARTITION_CONFIG] = part_access;
+ return 0;
+}
+
+static uint32_t mmc_sdhci_set_blk_cnt(struct mmc_device *dev, uint32_t blk_cnt, uint32_t rel_write)
+{
+ struct mmc_command cmd = {0};
+
+ cmd.cmd_index = CMD23_SET_BLOCK_COUNT;
+ cmd.argument = blk_cnt & 0x0000ffff;
+ cmd.argument |= rel_write;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R1;
+
+ if (sdhci_send_command(&dev->host, &cmd))
+ {
+ dprintf(CRITICAL, "Set block count failed: %s\n", __func__);
+ return 1;
+ }
+
+ return 0;
+}
+
+uint32_t mmc_sdhci_rpmb_send(struct mmc_device *dev, struct mmc_command *cmd)
+{
+ int i;
+ uint32_t retry = 5;
+ uint32_t status;
+ uint32_t rel_write = 0;
+ uint32_t ret = 1;
+
+ ASSERT(cmd);
+
+ /* 1. Set the partition type to rpmb */
+ if (mmc_sdhci_switch_part(dev, PART_ACCESS_RPMB))
+ return 1;
+
+ for (i = 0; i < MAX_RPMB_CMDS; i++)
+ {
+ if (!cmd[i].cmd_index)
+ break;
+
+ if (cmd[i].write_flag == true)
+ rel_write = BIT(31);
+ else
+ rel_write = 0;
+
+ /* 2. Set the block count using cmd23 */
+ if (mmc_sdhci_set_blk_cnt(dev, cmd[i].data.num_blocks, rel_write))
+ goto err;
+
+ /* 3. Send the command */
+ if (sdhci_send_command(&dev->host, &cmd[i]))
+ goto err;
+ do
+ {
+ /* 4. Poll for card status to ensure rpmb operation completeness */
+ if (mmc_get_card_status(&dev->host, &dev->card, &status))
+ {
+ dprintf(CRITICAL, "Failed to get card status after rpmb operations\n");
+ goto err;
+ }
+
+ retry--;
+ udelay(500);
+ if (!retry)
+ {
+ dprintf(CRITICAL, "Card status check timed out after rpmb operations\n");
+ goto err;
+ }
+ } while(!(status & MMC_READY_FOR_DATA) || (MMC_CARD_STATUS(status) == MMC_PROG_STATE));
+ }
+
+ /* If we reach here, that means success */
+ ret = 0;
+
+err:
+ /* 5. Switch the partition back to default type */
+ if (mmc_sdhci_switch_part(dev, PART_ACCESS_DEFAULT))
+ ret = 1;
+
+ return ret;
+}
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index bcec0ad..11d50cf 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -124,6 +124,12 @@
if (data_len % block_size)
data_len = ROUNDUP(data_len, block_size);
+ /*
+ * Flush the cache before handing over the data to
+ * storage driver
+ */
+ arch_clean_invalidate_cache_range((addr_t)in, data_len);
+
if (platform_boot_dev_isemmc())
{
/* TODO: This function is aware of max data that can be
@@ -151,8 +157,6 @@
}
else
{
- arch_clean_invalidate_cache_range((addr_t)in, data_len);
-
ret = ufs_write((struct ufs_dev *)dev, data_addr, (addr_t)in, (data_len / block_size));
if (ret)
@@ -296,6 +300,9 @@
memset((void *)out, 0, erase_size);
+ /* Flush the data to memory before writing to storage */
+ arch_clean_invalidate_cache_range((addr_t) out , erase_size);
+
if (mmc_sdhci_write(dev, out, blk_addr, num_blks))
{
dprintf(CRITICAL, "failed to erase the partition: %x\n", blk_addr);
@@ -597,7 +604,9 @@
unsigned long long ptn = 0;
uint64_t size;
int index = -1;
+#ifdef UFS_SUPPORT
int ret = 0;
+#endif
dev = target_mmc_device();
block_size = mmc_get_device_blocksize();
@@ -614,7 +623,8 @@
return 1;
}
- size = partition_get_size(index);
+ /* Convert the size to blocks */
+ size = partition_get_size(index) / block_size;
/*
* For read only partitions the minimum size allocated on the disk is
@@ -623,6 +633,7 @@
*/
if (partition_read_only(index) && size < card->wp_grp_size)
{
+ /* Write protect api takes the size in bytes, convert size to bytes */
size = card->wp_grp_size * block_size;
}
/* Set the power on WP bit */
@@ -630,6 +641,7 @@
}
else
{
+#ifdef UFS_SUPPORT
/* Enable the power on WP fo all LUNs which have WP bit is enabled */
ret = dme_set_fpoweronwpen((struct ufs_dev*) dev);
if (ret < 0)
@@ -637,6 +649,7 @@
dprintf(CRITICAL, "Failure to WP UFS partition\n");
return 1;
}
+#endif
}
return 0;
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index 38b2a80..2338060 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -872,10 +872,8 @@
return INVALID_PTN;
}
for (n = 0; n < partition_count; n++) {
- if (!memcmp
- (name, &partition_entries[n].name, input_string_length)
- && input_string_length ==
- strlen((const char *)&partition_entries[n].name)) {
+ if ((input_string_length == strlen((const char *)&partition_entries[n].name))
+ && !memcmp(name, &partition_entries[n].name, input_string_length)) {
return n;
}
}
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index b45fd3d..681b238 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -34,6 +34,8 @@
#include <arch/ops.h>
#include <rand.h>
#include <image_verify.h>
+#include <dload_util.h>
+#include <platform/iomap.h>
#include "scm.h"
#pragma GCC optimize ("O0")
@@ -54,6 +56,7 @@
/* SCM interface as per ARM spec present? */
bool scm_arm_support;
+static uint32_t scm_io_write(uint32_t address, uint32_t val);
static void scm_arm_support_available(uint32_t svc_id, uint32_t cmd_id)
{
@@ -958,14 +961,29 @@
int scm_halt_pmic_arbiter()
{
int ret = 0;
+ scmcall_arg scm_arg = {0};
- if (scm_arm_support)
- {
- dprintf(INFO, "%s:SCM call is not supported\n",__func__);
- return -1;
+ if (scm_arm_support) {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x1);
+ scm_arg.x2 = 0;
+ scm_arg.atomic = true;
+ ret = scm_call2(&scm_arg, NULL);
+ } else {
+ ret = scm_call_atomic(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER, 0);
}
- ret = scm_call_atomic(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER, 0);
+ /* Retry with the SCM_IO_DISABLE_PMIC_ARBITER1 func ID if the above Func ID fails*/
+ if(ret) {
+ if (scm_arm_support) {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER1);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x1);
+ scm_arg.x2 = 0;
+ scm_arg.atomic = true;
+ ret = scm_call2(&scm_arg, NULL);
+ } else
+ ret = scm_call_atomic(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER1, 0);
+ }
return ret;
}
@@ -1178,3 +1196,133 @@
return 0;
}
+
+static bool secure_boot_enable = false;
+static bool wdog_debug_fuse_disable = false;
+
+void scm_check_boot_fuses()
+{
+ uint32_t ret = 0;
+ uint32_t resp;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ if (!scm_arm_support) {
+ ret = scm_call(TZBSP_SVC_INFO, IS_SECURE_BOOT_ENABLED, NULL, 0, &resp, sizeof(resp));
+ } else {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(TZBSP_SVC_INFO, IS_SECURE_BOOT_ENABLED);
+ ret = scm_call2(&scm_arg, &scm_ret);
+ resp = scm_ret.x1;
+ }
+
+ /* Parse Bit 0 and Bit 2 of the response */
+ if(!ret) {
+ /* Bit 0 - SECBOOT_ENABLE_CHECK */
+ if(resp & 0x1)
+ secure_boot_enable = true;
+ /* Bit 2 - DEBUG_DISABLE_CHECK */
+ if(resp & 0x4)
+ wdog_debug_fuse_disable = true;
+ } else
+ dprintf(CRITICAL, "scm call to check secure boot fuses failed\n");
+}
+
+bool is_secure_boot_enable()
+{
+ scm_check_boot_fuses();
+ return secure_boot_enable;
+}
+
+static uint32_t scm_io_read(addr_t address)
+{
+ uint32_t ret;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ if (!scm_arm_support) {
+ ret = scm_call_atomic(SCM_SVC_IO, SCM_IO_READ, address);
+ } else {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_IO, SCM_IO_READ);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x1);
+ scm_arg.x2 = address;
+ scm_arg.atomic = true;
+ ret = scm_call2(&scm_arg, &scm_ret);
+ }
+ return ret;
+}
+
+static uint32_t scm_io_write(uint32_t address, uint32_t val)
+{
+ uint32_t ret;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ if (!scm_arm_support) {
+ ret = scm_call_atomic2(SCM_SVC_IO, SCM_IO_WRITE, address, val);
+ } else {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_IO, SCM_IO_WRITE);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2);
+ scm_arg.x2 = address;
+ scm_arg.x3 = val;
+ scm_arg.atomic = true;
+ ret = scm_call2(&scm_arg, &scm_ret);
+ }
+ return ret;
+}
+
+static int scm_call2_atomic(uint32_t svc, uint32_t cmd, uint32_t arg1, uint32_t arg2)
+{
+ uint32_t ret = 0;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ if (!scm_arm_support)
+ {
+ ret = scm_call_atomic2(svc, cmd, arg1, arg2);
+ } else {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(svc, cmd);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2);
+ scm_arg.x2 = arg1;
+ scm_arg.x3 = arg2;
+ ret = scm_call2(&scm_arg, &scm_ret);
+ }
+ return ret;
+}
+
+#if PLATFORM_USE_SCM_DLOAD
+int scm_dload_mode(int mode)
+{
+ int ret = 0;
+ uint32_t dload_type;
+
+ dprintf(SPEW, "DLOAD mode: %d\n", mode);
+ if (mode == NORMAL_DLOAD)
+ dload_type = SCM_DLOAD_MODE;
+ else if(mode == EMERGENCY_DLOAD)
+ dload_type = SCM_EDLOAD_MODE;
+ else
+ dload_type = 0;
+
+ /* Write to the Boot MISC register */
+ ret = scm_call2_atomic(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0);
+
+ if (ret) {
+ ret = scm_io_write(TCSR_BOOT_MISC_DETECT,dload_type);
+ if(ret) {
+ dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret);
+ return ret;
+ }
+ }
+
+ scm_check_boot_fuses();
+
+ /* Make WDOG_DEBUG DISABLE scm call only in non-secure boot */
+ if(!(secure_boot_enable || wdog_debug_fuse_disable)) {
+ ret = scm_call2_atomic(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
+ if(ret)
+ dprintf(CRITICAL, "Failed to disable the wdog debug \n");
+ }
+
+ return ret;
+}
+#endif
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index 4e83a55..f6d66da 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -802,6 +802,9 @@
if (drv_type_changed)
mmc_set_drv_type(host, card, 0);
+ if (tuned_phase_cnt == MAX_PHASES)
+ dprintf(CRITICAL, "WARNING: All phase passed.The selected phase may not be optimal\n");
+
/* Find the appropriate tuned phase */
if (tuned_phase_cnt)
{
diff --git a/platform/thulium/acpuclock.c b/platform/thulium/acpuclock.c
index e2ee7d5..15ebd30 100644
--- a/platform/thulium/acpuclock.c
+++ b/platform/thulium/acpuclock.c
@@ -123,6 +123,20 @@
*/
static void ce_async_reset(uint8_t instance)
{
+ if (instance == 1)
+ {
+ /* Start the block reset for CE */
+ writel(1, GCC_CE1_BCR);
+ udelay(2);
+ /* Take CE block out of reset */
+ writel(0, GCC_CE1_BCR);
+ udelay(2);
+ }
+ else
+ {
+ dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance);
+ ASSERT(0);
+ }
}
void clock_ce_enable(uint8_t instance)
diff --git a/platform/thulium/include/platform/iomap.h b/platform/thulium/include/platform/iomap.h
index 276841d..ef58cfe 100644
--- a/platform/thulium/include/platform/iomap.h
+++ b/platform/thulium/include/platform/iomap.h
@@ -153,8 +153,9 @@
#define SPMI_PIC_BASE (SPMI_BASE + 0x1800000)
#define PMIC_ARB_CORE 0x400F000
-#define MSM_CE_BAM_BASE 0x67A000
-#define MSM_CE_BASE 0x644000
+#define MSM_CE_BAM_BASE 0x644000
+#define MSM_CE_BASE 0x67A000
+#define GCC_CE1_BCR (CLK_CTL_BASE + 0x00041000)
#define TLMM_BASE_ADDR 0x1010000
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
diff --git a/project/msm8909.mk b/project/msm8909.mk
index afc40f6..3eea90b 100644
--- a/project/msm8909.mk
+++ b/project/msm8909.mk
@@ -65,3 +65,6 @@
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT),1)
DEFINES += BOOT_CONFIG_SUPPORT=1
endif
+
+#SCM call before entering DLOAD mode
+DEFINES += PLATFORM_USE_SCM_DLOAD=1
diff --git a/project/msm8916.mk b/project/msm8916.mk
index 5f51f80..2dff5df 100644
--- a/project/msm8916.mk
+++ b/project/msm8916.mk
@@ -51,3 +51,6 @@
#enable user force reset feature
DEFINES += USER_FORCE_RESET_SUPPORT=1
+
+#SCM call before entering DLOAD mode
+DEFINES += PLATFORM_USE_SCM_DLOAD=1
diff --git a/project/thulium.mk b/project/thulium.mk
index 05e764f..4bce478 100644
--- a/project/thulium.mk
+++ b/project/thulium.mk
@@ -27,6 +27,7 @@
#DEFINES += WITH_DEBUG_FBCON=1
DEFINES += DEVICE_TREE=1
DEFINES += SPMI_CORE_V2=1
+DEFINES += BAM_V170=1
DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
diff --git a/target/fsm9010/init.c b/target/fsm9010/init.c
index 7e47d47..e5c50bb 100644
--- a/target/fsm9010/init.c
+++ b/target/fsm9010/init.c
@@ -288,7 +288,10 @@
};
switch (platform) {
+ case FSM9008:
case FSM9010:
+ case FSM9016:
+ case FSM9055:
board->baseband = BASEBAND_MSM;
break;
default:
diff --git a/target/fsm9010/meminfo.c b/target/fsm9010/meminfo.c
index fa0f96a..3c1fc98 100644
--- a/target/fsm9010/meminfo.c
+++ b/target/fsm9010/meminfo.c
@@ -90,6 +90,6 @@
unsigned target_get_max_flash_size(void)
{
- return (86 * 1024 * 1024);
+ return (222 * 1024 * 1024);
}
#endif /* DEVICE_TREE */
diff --git a/target/fsm9010/rules.mk b/target/fsm9010/rules.mk
index 17a1b1d..8e7fd48 100644
--- a/target/fsm9010/rules.mk
+++ b/target/fsm9010/rules.mk
@@ -12,7 +12,7 @@
TAGS_ADDR := BASE_ADDR+0x01e00000
KERNEL_ADDR := BASE_ADDR+0x00008000
RAMDISK_ADDR := BASE_ADDR+0x02000000
-SCRATCH_ADDR := 0x0e000000
+SCRATCH_ADDR := 0x32200000
MODULES += \
dev/keys \
diff --git a/target/msm8226/oem_panel.c b/target/msm8226/oem_panel.c
index 354c08e..442fa29 100755
--- a/target/msm8226/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -50,6 +50,7 @@
#include "include/panel_ssd2080m_720p_video.h"
#include "include/panel_jdi_1080p_video.h"
#include "include/panel_nt35590_qvga_cmd.h"
+#include "include/panel_auo_qvga_cmd.h"
#define DISPLAY_MAX_PANEL_DETECTION 2
@@ -69,6 +70,7 @@
SSD2080M_720P_VIDEO_PANEL,
JDI_1080P_VIDEO_PANEL,
NT35590_QVGA_CMD_PANEL,
+AUO_QVGA_CMD_PANEL,
UNKNOWN_PANEL
};
@@ -86,6 +88,7 @@
{"ssd2080m_720p_video", SSD2080M_720P_VIDEO_PANEL},
{"jdi_1080p_video", JDI_1080P_VIDEO_PANEL},
{"nt35590_qvga_cmd", NT35590_QVGA_CMD_PANEL},
+ {"auo_qvga_cmd", AUO_QVGA_CMD_PANEL},
};
static uint32_t panel_id;
@@ -355,6 +358,29 @@
memcpy(phy_db->timing,
nt35590_qvga_cmd_timings, TIMING_SIZE);
break;
+ case AUO_QVGA_CMD_PANEL:
+ panelstruct->paneldata = &auo_qvga_cmd_panel_data;
+ panelstruct->panelres = &auo_qvga_cmd_panel_res;
+ panelstruct->color = &auo_qvga_cmd_color;
+ panelstruct->videopanel = &auo_qvga_cmd_video_panel;
+ panelstruct->commandpanel = &auo_qvga_cmd_command_panel;
+ panelstruct->state = &auo_qvga_cmd_state;
+ panelstruct->laneconfig = &auo_qvga_cmd_lane_config;
+ panelstruct->paneltiminginfo = &auo_qvga_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &auo_qvga_cmd_panel_reset_seq;
+ panelstruct->backlightinfo = &auo_qvga_cmd_backlight;
+ pinfo->mipi.panel_on_cmds
+ = auo_qvga_cmd_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = auo_QVGA_CMD_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = auo_qvga_cmd_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = auo_QVGA_CMD_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ auo_qvga_cmd_timings, TIMING_SIZE);
+ break;
case UNKNOWN_PANEL:
memset(panelstruct, 0, sizeof(struct panel_struct));
memset(pinfo->mipi.panel_on_cmds, 0,
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 4ac9b37..77ca16e 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -262,6 +262,8 @@
PWM_BL_LPG_CHAN_ID,
enable);
break;
+ case BL_DCS:
+ break;
default:
dprintf(CRITICAL, "backlight type:%d not supported\n",
bl->bl_interface_type);
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 96232fe..7b055a5 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -378,30 +378,6 @@
return restart_reason;
}
-static int scm_dload_mode(int mode)
-{
- int ret = 0;
- uint32_t dload_type;
-
- dprintf(SPEW, "DLOAD mode: %d\n", mode);
- if (mode == NORMAL_DLOAD)
- dload_type = SCM_DLOAD_MODE;
- else if(mode == EMERGENCY_DLOAD)
- dload_type = SCM_EDLOAD_MODE;
- else
- dload_type = 0;
-
- ret = scm_call_atomic2(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0);
- if (ret)
- dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret);
-
- ret = scm_call_atomic2(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
- if (ret)
- dprintf(CRITICAL, "Failed to disable the wdog debug \n");
-
- return ret;
-}
-
/* Configure PMIC and Drop PS_HOLD for shutdown */
void shutdown_device()
{
diff --git a/target/msm8916/init.c b/target/msm8916/init.c
index fbc45e4..3bdd5ac 100644
--- a/target/msm8916/init.c
+++ b/target/msm8916/init.c
@@ -257,29 +257,6 @@
return hard_restart_reason;
}
-static int scm_dload_mode(int mode)
-{
- int ret = 0;
- uint32_t dload_type;
-
- dprintf(SPEW, "DLOAD mode: %d\n", mode);
- if (mode == NORMAL_DLOAD)
- dload_type = SCM_DLOAD_MODE;
- else if(mode == EMERGENCY_DLOAD)
- dload_type = SCM_EDLOAD_MODE;
- else
- dload_type = 0;
-
- ret = scm_call_atomic2(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0);
- if (ret)
- dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret);
-
- ret = scm_call_atomic2(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
- if (ret)
- dprintf(CRITICAL, "Failed to disable the wdog debug \n");
-
- return ret;
-}
/* Configure PMIC and Drop PS_HOLD for shutdown */
void shutdown_device()
{
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
index ae2725d..9e4349d 100644
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -634,6 +634,9 @@
panel_id = JDI_1080P_VIDEO_PANEL;
break;
case 1:
+ panel_id = HX8394D_720P_VIDEO_PANEL;
+ break;
+ case 2:
panel_id = NT35590_720P_VIDEO_PANEL;
break;
default:
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index 0ddaec1..43a2903 100644
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -62,33 +62,124 @@
mdelay(1);
}
-static uint32_t dsi_pll_enable_seq_8916(uint32_t pll_base)
+static void dsi_pll_toggle_lock_detect_8916(uint32_t pll_base)
{
- uint32_t pll_locked = 0;
+ writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */
+ udelay(1);
+ writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
+ udelay(512);
+}
+static void dsi_pll_sw_reset_8916(uint32_t pll_base)
+{
writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
udelay(1);
writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
+}
+
+static uint32_t gf_1_dsi_pll_enable_sequence_8916(uint32_t pll_base)
+{
+ uint32_t rc;
+
+ dsi_pll_sw_reset_8916(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x34, pll_base + 0x0070); /* CAL CFG1*/
- udelay(1);
+ writel(0x14, pll_base + 0x0070); /* CAL CFG1*/
writel(0x01, pll_base + 0x0020); /* GLB CFG */
- udelay(1);
writel(0x05, pll_base + 0x0020); /* GLB CFG */
- udelay(1);
+ udelay(3);
writel(0x0f, pll_base + 0x0020); /* GLB CFG */
- udelay(1);
+ udelay(500);
- writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */
- udelay(1);
- writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
- udelay(512);
- pll_locked = readl(pll_base + 0x00c0) & 0x01;
+ dsi_pll_toggle_lock_detect_8916(pll_base);
+ rc = readl(pll_base + 0x00c0) & 0x01;
+
+ return rc;
+}
+
+static uint32_t gf_2_dsi_pll_enable_sequence_8916(uint32_t pll_base)
+{
+ uint32_t rc;
+
+ dsi_pll_sw_reset_8916(pll_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x04, pll_base + 0x0070); /* CAL CFG1*/
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ udelay(3);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(500);
+
+ dsi_pll_toggle_lock_detect_8916(pll_base);
+ rc = readl(pll_base + 0x00c0) & 0x01;
+
+ return rc;
+}
+
+static uint32_t tsmc_dsi_pll_enable_sequence_8916(uint32_t pll_base)
+{
+ uint32_t rc;
+
+ dsi_pll_sw_reset_8916(pll_base);
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+
+ writel(0x34, pll_base + 0x0070); /* CAL CFG1*/
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(500);
+
+ dsi_pll_toggle_lock_detect_8916(pll_base);
+ rc = readl(pll_base + 0x00c0) & 0x01;
+
+ return rc;
+}
+
+
+static uint32_t dsi_pll_enable_seq_8916(uint32_t pll_base)
+{
+ uint32_t pll_locked = 0;
+ uint32_t counter = 0;
+
+ do {
+ pll_locked = tsmc_dsi_pll_enable_sequence_8916(pll_base);
+
+ dprintf(SPEW, "TSMC pll locked status is %d\n", pll_locked);
+ ++counter;
+ } while (!pll_locked && (counter < 3));
+
+ if(!pll_locked) {
+ counter = 0;
+ do {
+ pll_locked = gf_1_dsi_pll_enable_sequence_8916(pll_base);
+
+ dprintf(SPEW, "GF P1 pll locked status is %d\n", pll_locked);
+ ++counter;
+ } while (!pll_locked && (counter < 3));
+ }
+
+ if(!pll_locked) {
+ counter = 0;
+ do {
+ pll_locked = gf_2_dsi_pll_enable_sequence_8916(pll_base);
+
+ dprintf(SPEW, "GF P2 pll locked status is %d\n", pll_locked);
+ ++counter;
+ } while (!pll_locked && (counter < 3));
+ }
return pll_locked;
}
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 5df2874..6dc9ce9 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -446,9 +446,15 @@
void reboot_device(unsigned reboot_reason)
{
uint8_t reset_type = 0;
+ uint32_t restart_reason_addr;
+
+ if (platform_is_msm8994())
+ restart_reason_addr = RESTART_REASON_ADDR;
+ else
+ restart_reason_addr = RESTART_REASON_ADDR2;
/* Write the reboot reason */
- writel(reboot_reason, RESTART_REASON_ADDR);
+ writel(reboot_reason, restart_reason_addr);
if(reboot_reason == FASTBOOT_MODE)
reset_type = PON_PSHOLD_WARM_RESET;
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
index de292b5..62795ad 100644
--- a/target/msm8994/oem_panel.c
+++ b/target/msm8994/oem_panel.c
@@ -48,6 +48,7 @@
#include "include/panel_jdi_qhd_dualdsi_cmd.h"
#include "include/panel_jdi_4k_dualdsi_video.h"
#include "include/panel_jdi_1080p_video.h"
+#include "include/panel_sharp_1080p_cmd.h"
#include "include/panel_hx8379a_truly_fwvga_video.h"
#include "include/panel_nt35597_wqxga_video.h"
#include "include/panel_nt35597_wqxga_cmd.h"
@@ -61,6 +62,7 @@
JDI_QHD_DUALDSI_CMD_PANEL,
JDI_4K_DUALDSI_VIDEO_PANEL,
JDI_1080P_VIDEO_PANEL,
+SHARP_1080P_CMD_PANEL,
HX8379A_TRULY_FWVGA_VIDEO_PANEL,
NOVATEK_WQXGA_VIDEO_PANEL,
NOVATEK_WQXGA_CMD_PANEL,
@@ -77,6 +79,7 @@
{"jdi_qhd_dualdsi_cmd", JDI_QHD_DUALDSI_CMD_PANEL},
{"jdi_4k_dualdsi_video", JDI_4K_DUALDSI_VIDEO_PANEL},
{"jdi_1080p_video", JDI_1080P_VIDEO_PANEL},
+ {"sharp_1080p_cmd", SHARP_1080P_CMD_PANEL},
{"hx8379a_truly_fwvga_video", HX8379A_TRULY_FWVGA_VIDEO_PANEL},
{"nt35597_wqxga_video", NOVATEK_WQXGA_VIDEO_PANEL},
{"nt35597_wqxga_cmd", NOVATEK_WQXGA_CMD_PANEL},
@@ -158,6 +161,7 @@
memcpy(phy_db->timing,
sharp_wqxga_dualdsi_video_timings, TIMING_SIZE);
pinfo->dfps.panel_dfps = sharp_wqxga_dualdsi_video_dfps;
+ pinfo->mipi.tx_eot_append = true;
break;
case JDI_QHD_DUALDSI_VIDEO_PANEL:
pan_type = PANEL_TYPE_DSI;
@@ -278,6 +282,32 @@
memcpy(phy_db->timing,
jdi_1080p_video_timings, TIMING_SIZE);
break;
+ case SHARP_1080P_CMD_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 0;
+ panelstruct->paneldata = &sharp_1080p_cmd_panel_data;
+ panelstruct->panelres = &sharp_1080p_cmd_panel_res;
+ panelstruct->color = &sharp_1080p_cmd_color;
+ panelstruct->videopanel = &sharp_1080p_cmd_video_panel;
+ panelstruct->commandpanel = &sharp_1080p_cmd_command_panel;
+ panelstruct->state = &sharp_1080p_cmd_state;
+ panelstruct->laneconfig = &sharp_1080p_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &sharp_1080p_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &sharp_1080p_cmd_panel_reset_seq;
+ panelstruct->backlightinfo = &sharp_1080p_cmd_backlight;
+ pinfo->mipi.panel_on_cmds
+ = sharp_1080p_cmd_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = SHARP_1080P_CMD_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = sharp_1080p_cmd_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = SHARP_1080P_CMD_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ sharp_1080p_cmd_timings, TIMING_SIZE);
+ break;
case HX8379A_TRULY_FWVGA_VIDEO_PANEL:
pan_type = PANEL_TYPE_DSI;
pinfo->lcd_reg_en = 1;
diff --git a/target/msm8994/regulator.c b/target/msm8994/regulator.c
index 8a8d1e1..c28afa2 100644
--- a/target/msm8994/regulator.c
+++ b/target/msm8994/regulator.c
@@ -35,15 +35,15 @@
{
LDOA_RES_TYPE, 2,
KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
},
{
LDOA_RES_TYPE, 2,
KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 1250000,
+ KEY_CURRENT, 4, 16,
},
};
@@ -52,15 +52,15 @@
{
LDOA_RES_TYPE, 12,
KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
},
{
LDOA_RES_TYPE, 12,
KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 1800000,
+ KEY_CURRENT, 4, 11,
},
};
@@ -69,32 +69,32 @@
{
LDOA_RES_TYPE, 14,
KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
},
{
LDOA_RES_TYPE, 14,
KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 1800000,
+ KEY_CURRENT, 4, 52,
},
};
-static uint32_t ldo28[][11]=
+static uint32_t ldo28[][14]=
{
{
LDOA_RES_TYPE, 28,
KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
},
{
LDOA_RES_TYPE, 28,
KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 1000000,
+ KEY_CURRENT, 4, 72,
},
};