Merge "target: msm8952: handle display ldo enable failures properly"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 99dca48..09ba226 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -176,6 +176,7 @@
static const char *baseband_dsda2 = " androidboot.baseband=dsda2";
static const char *baseband_sglte2 = " androidboot.baseband=sglte2";
static const char *warmboot_cmdline = " qpnp-power-on.warm_boot=1";
+static const char *baseband_apq_nowgr = " androidboot.baseband=baseband_apq_nowgr";
#if VERIFIED_BOOT
#if !VBOOT_MOTA
@@ -442,6 +443,9 @@
case BASEBAND_DSDA2:
cmdline_len += strlen(baseband_dsda2);
break;
+ case BASEBAND_APQ_NOWGR:
+ cmdline_len += strlen(baseband_apq_nowgr);
+ break;
}
if (cmdline) {
@@ -631,6 +635,11 @@
if (have_cmdline) --dst;
while ((*dst++ = *src++));
break;
+ case BASEBAND_APQ_NOWGR:
+ src = baseband_apq_nowgr;
+ if (have_cmdline) --dst;
+ while ((*dst++ = *src++));
+ break;
}
if (strlen(display_panel_buf)) {
@@ -3836,7 +3845,6 @@
page_size = flash_page_size();
page_mask = page_size - 1;
}
-
ASSERT((MEMBASE + MEMSIZE) > MEMBASE);
read_device_info(&device);
diff --git a/platform/msm_shared/include/baseband.h b/platform/msm_shared/include/baseband.h
index 64dde97..a1ed9ca 100644
--- a/platform/msm_shared/include/baseband.h
+++ b/platform/msm_shared/include/baseband.h
@@ -41,6 +41,7 @@
BASEBAND_DSDA2 = 8,
BASEBAND_SGLTE2 = 9,
BASEBAND_MDM2 = 10,
+ BASEBAND_APQ_NOWGR = 11,
BASEBAND_32BITS = 0x7FFFFFFF
};
diff --git a/platform/msm_shared/include/mipi_dsi_autopll_thulium.h b/platform/msm_shared/include/mipi_dsi_autopll_thulium.h
index 9467853..622dba0 100644
--- a/platform/msm_shared/include/mipi_dsi_autopll_thulium.h
+++ b/platform/msm_shared/include/mipi_dsi_autopll_thulium.h
@@ -71,6 +71,13 @@
#define DSIPHY_PLL_PLLLOCK_CMP_EN 0x0488
#define DSIPHY_PLL_DEC_START 0x0490
+#define DSIPHY_PLL_SSC_EN_CENTER 0x0494
+#define DSIPHY_PLL_SSC_ADJ_PER1 0x0498
+#define DSIPHY_PLL_SSC_ADJ_PER2 0x049c
+#define DSIPHY_PLL_SSC_PER1 0x04a0
+#define DSIPHY_PLL_SSC_PER2 0x04a4
+#define DSIPHY_PLL_SSC_STEP_SIZE1 0x04a8
+#define DSIPHY_PLL_SSC_STEP_SIZE2 0x04ac
#define DSIPHY_PLL_DIV_FRAC_START1 0x04b4
#define DSIPHY_PLL_DIV_FRAC_START2 0x04b8
#define DSIPHY_PLL_DIV_FRAC_START3 0x04bc
diff --git a/platform/msm_shared/mipi_dsi_autopll_thulium.c b/platform/msm_shared/mipi_dsi_autopll_thulium.c
index 8531730..4b2bfb0 100644
--- a/platform/msm_shared/mipi_dsi_autopll_thulium.c
+++ b/platform/msm_shared/mipi_dsi_autopll_thulium.c
@@ -44,12 +44,14 @@
#define VCO_REF_CLK_RATE 19200000
+#define CEIL(x, y) (((x) + ((y)-1)) / (y))
+
static void mdss_mdp_pll_input_init(struct dsi_pll_db *pdb)
{
pdb->in.fref = 19200000; /* 19.2 Mhz*/
pdb->in.fdata = 0; /* bit clock rate */
pdb->in.dsiclk_sel = 1; /* 1, reg: 0x0014 */
- pdb->in.ssc_en = 0; /* 1, reg: 0x0494, bit 0 */
+ pdb->in.ssc_en = 1; /* 1, reg: 0x0494, bit 0 */
pdb->in.ldo_en = 0; /* 0, reg: 0x004c, bit 0 */
/* fixed input */
@@ -119,6 +121,39 @@
pdb->out.cmn_ldo_cntrl = 0x3c;
}
+static void mdss_mdp_pll_ssc_calc(struct dsi_pll_db *pdb,
+ uint32_t vco_clk_rate, uint32_t fref)
+{
+ uint32_t period, ssc_period;
+ uint32_t ref, rem;
+ uint64_t step_size;
+
+ ssc_period = pdb->in.ssc_freq / 500;
+ period = (unsigned long)fref / 1000;
+ ssc_period = CEIL(period, ssc_period);
+ ssc_period -= 1;
+ pdb->out.ssc_per = ssc_period;
+
+ step_size = vco_clk_rate;
+ ref = fref;
+
+ ref /= 1000;
+ step_size /= ref;
+ step_size <<= 20;
+ step_size /= 1000;
+ step_size *= pdb->in.ssc_spread;
+ step_size /= 1000;
+ step_size *= (pdb->in.ssc_adj_per + 1);
+
+ rem = 0;
+ rem = step_size % (ssc_period + 1);
+ if (rem)
+ step_size++;
+
+ step_size &= 0x0ffff; /* take lower 16 bits */
+ pdb->out.ssc_step_size = step_size;
+}
+
static uint32_t mdss_mdp_pll_kvco_slop(uint32_t vrate)
{
uint32_t slop = 0;
@@ -330,6 +365,37 @@
dmb(); /* make sure register committed */
}
+static void mdss_mdp_pll_ssc_config(uint32_t phy_base, struct dsi_pll_db *pdb)
+{
+ uint32_t data;
+
+ data = pdb->in.ssc_adj_per;
+ data &= 0x0ff;
+ writel(data, phy_base + DSIPHY_PLL_SSC_ADJ_PER1);
+ data = (pdb->in.ssc_adj_per >> 8);
+ data &= 0x03;
+ writel(data, phy_base + DSIPHY_PLL_SSC_ADJ_PER2);
+
+ data = pdb->out.ssc_per;
+ data &= 0x0ff;
+ writel(data, phy_base + DSIPHY_PLL_SSC_PER1);
+ data = (pdb->out.ssc_per >> 8);
+ data &= 0x0ff;
+ writel(data, phy_base + DSIPHY_PLL_SSC_PER2);
+
+ data = pdb->out.ssc_step_size;
+ data &= 0x0ff;
+ writel(data, phy_base + DSIPHY_PLL_SSC_STEP_SIZE1);
+ data = (pdb->out.ssc_step_size >> 8);
+ data &= 0x0ff;
+ writel(data, phy_base + DSIPHY_PLL_SSC_STEP_SIZE2);
+
+ data = (pdb->in.ssc_center_spread & 0x01);
+ data <<= 1;
+ data |= 0x01; /* enable */
+ writel(data, phy_base + DSIPHY_PLL_SSC_EN_CENTER);
+}
+
static int mdss_dsi_phy_14nm_init(struct msm_panel_info *pinfo,
uint32_t phy_base)
{
@@ -436,6 +502,9 @@
pdb.out.pll_n2div = pll_data->n2div;
mdss_mdp_pll_dec_frac_calc(&pdb, pll_data->vco_clock, VCO_REF_CLK_RATE);
+ if (pdb.in.ssc_en)
+ mdss_mdp_pll_ssc_calc(&pdb, pll_data->vco_clock,
+ VCO_REF_CLK_RATE);
mdss_mdp_pll_calc_vco_count(&pdb, pll_data->vco_clock, VCO_REF_CLK_RATE);
/* de-assert pll and start */
@@ -447,9 +516,13 @@
/* configure frequence */
mdss_mdp_pll_nonfreq_config(phy_base, &pdb);
mdss_mdp_pll_freq_config(phy_base, &pdb);
+ if (pdb.in.ssc_en)
+ mdss_mdp_pll_ssc_config(phy_base, &pdb);
if (pinfo->lcdc.split_display) {
mdss_mdp_pll_nonfreq_config(phy_1_base, &pdb);
mdss_mdp_pll_freq_config(phy_1_base, &pdb);
+ if (pdb.in.ssc_en)
+ mdss_mdp_pll_ssc_config(phy_1_base, &pdb);
}
}
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 67aadfd..525d4c4 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -67,6 +67,7 @@
#if PON_VIB_SUPPORT
#define VIBRATE_TIME 250
#endif
+#define HW_SUBTYPE_APQ_NOWGR 0xA
#define CE1_INSTANCE 1
#define CE_EE 1
@@ -425,7 +426,11 @@
break;
case APQ8009:
- board->baseband = BASEBAND_APQ;
+ if ((board->platform_hw == HW_PLATFORM_MTP) &&
+ (board->platform_subtype == HW_SUBTYPE_APQ_NOWGR))
+ board->baseband = BASEBAND_APQ_NOWGR;
+ else
+ board->baseband = BASEBAND_APQ;
break;
default:
@@ -472,40 +477,41 @@
splash_override = override;
}
+/*Update this command line only for LE based builds*/
int get_target_boot_params(const char *cmdline, const char *part, char **buf)
{
struct ptable *ptable;
int system_ptn_index = -1;
- uint32_t buflen;
+ int le_based = -1;
- if (!target_is_emmc_boot()) {
- if (!cmdline || !part || !buf || buflen < 0) {
- dprintf(CRITICAL, "WARN: Invalid input param\n");
- return -1;
- }
- buflen = strlen(" root=/dev/mtdblock") + sizeof(int) + 1; /*1 character for null termination*/
- *buf = (char *)malloc(buflen);
- if(!(*buf)) {
- dprintf(CRITICAL,"Unable to allocate memory for boot params\n");
- return -1;
- }
+ /*LE partition.xml will have recoveryfs partition*/
+ if (target_is_emmc_boot())
+ le_based = partition_get_index("recoveryfs");
+ else
+ /*Nand targets by default have this*/
+ le_based = 1;
- ptable = flash_get_ptable();
- if (!ptable) {
- dprintf(CRITICAL,
- "WARN: Cannot get flash partition table\n");
- free(*buf);
- return -1;
+ if (le_based != -1)
+ {
+ if (!target_is_emmc_boot())
+ {
+ ptable = flash_get_ptable();
+ if (!ptable)
+ {
+ dprintf(CRITICAL,
+ "WARN: Cannot get flash partition table\n");
+ return -1;
+ }
+ system_ptn_index = ptable_get_index(ptable, part);
}
-
- system_ptn_index = ptable_get_index(ptable, part);
+ else
+ system_ptn_index = partition_get_index(part);
if (system_ptn_index < 0) {
dprintf(CRITICAL,
"WARN: Cannot get partition index for %s\n", part);
free(*buf);
return -1;
}
-
/*
* check if cmdline contains "root=" at the beginning of buffer or
* " root=" in the middle of buffer.
@@ -514,11 +520,15 @@
(strstr(cmdline, " root="))))
dprintf(DEBUG, "DEBUG: cmdline has root=\n");
else
- snprintf(*buf, buflen, " root=/dev/mtdblock%d",
- system_ptn_index);
/*in success case buf will be freed in the calling function of this*/
+ {
+ if (!target_is_emmc_boot())
+ snprintf(buf, buflen, " root=/dev/mtdblock%d",system_ptn_index);
+ else
+ /*For Emmc case increase the ptn_index by 1*/
+ snprintf(buf, buflen, " root=/dev/mmcblk0p%d",system_ptn_index + 1);
+ }
}
-
return 0;
}