Merge "app: aboot: check for input image size for overflow"
diff --git a/include/platform.h b/include/platform.h
index 07b1c04..5bc065a 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -88,4 +88,5 @@
bool platform_is_mdmcalifornium();
bool platform_is_sdxhedgehog();
uint64_t platform_get_ddr_start();
+bool platform_is_glink_enabled();
#endif
diff --git a/platform/init.c b/platform/init.c
index 8280ffb..f429527 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -162,3 +162,14 @@
{
return SIGNATURE_SIZE;
}
+
+/* Check if glink is supported or not */
+__WEAK bool platform_is_glink_enabled()
+{
+#if GLINK_SUPPORT
+ return 1;
+#else
+ return 0;
+#endif
+}
+
diff --git a/platform/mdm9640/include/platform/iomap.h b/platform/mdm9640/include/platform/iomap.h
index a55687c..6981256 100644
--- a/platform/mdm9640/include/platform/iomap.h
+++ b/platform/mdm9640/include/platform/iomap.h
@@ -219,4 +219,11 @@
/* Register for finding out if single ended or differential clock enablement */
#define TCSR_PHY_CLK_SCHEME_SEL 0x01956044
+/* RPM MSG RAM */
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS 0x00060000
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE 0x00006000
+/* notify RPM via IPC interrupt*/
+#define APCS_HLOS_IPC_INTERRUPT_0 APCS_ALIAS0_IPC_INTERRUPT
+
#endif
diff --git a/platform/mdm9640/include/platform/irqs.h b/platform/mdm9640/include/platform/irqs.h
index a9e8fc5..b1d958b 100644
--- a/platform/mdm9640/include/platform/irqs.h
+++ b/platform/mdm9640/include/platform/irqs.h
@@ -47,6 +47,7 @@
#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define GLINK_IPC_IRQ (GIC_SPI_START + 168)
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
diff --git a/platform/mdm9640/platform.c b/platform/mdm9640/platform.c
index db301ee..3cfced4 100644
--- a/platform/mdm9640/platform.c
+++ b/platform/mdm9640/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -183,7 +183,8 @@
switch(platform_id)
{
- case SDXHEDGEHOG:
+ case SDXHEDGEHOG1:
+ case SDXHEDGEHOG2:
ret = true;
break;
default:
@@ -214,3 +215,10 @@
readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
}
+bool platform_is_glink_enabled()
+{
+ if (platform_is_sdxhedgehog())
+ return 1;
+ else
+ return 0;
+}
diff --git a/platform/msm_shared/include/qusb2_phy.h b/platform/msm_shared/include/qusb2_phy.h
index b8e8689..d446add 100644
--- a/platform/msm_shared/include/qusb2_phy.h
+++ b/platform/msm_shared/include/qusb2_phy.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -53,6 +53,7 @@
/* QUSB2 PHY SDXHEDGEHOG */
#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x4)
+#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO_SDXHEDGEHOG (QUSB2_PHY_BASE + 0xb4)
#define QUSB2PHY_PLL_CLOCK_INVERTERS_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x18c)
#define QUSB2PHY_PLL_CMODE_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x02c)
#define QUSB2PHY_PLL_LOCK_DELAY_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x90)
@@ -63,4 +64,6 @@
#define QUSB2PHY_DEBUG_CTRL2_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x278)
#define QUSB2PHY_DEBUG_STAT5_SDXHEDGEHOG (QUSB2_PHY_BASE + 0x298)
+#define USB30_GENERAL_CFG_PIPE 0x08af8808
+
#endif
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index e13e441..ab64209 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -89,8 +89,18 @@
dmb();
/* set CLAMP_N_EN and stay with disabled USB PHY */
- writel(0x23, QUSB2PHY_PORT_POWERDOWN);
+ if(platform_is_sdxhedgehog())
+ writel(0x23, QUSB2PHY_PWR_CTRL1_SDXHEDGEHOG);
+ else
+ writel(0x23, QUSB2PHY_PORT_POWERDOWN);
+ /* TCSR register bit 0 indicates whether single ended clock
+ * or differential clock configuration is enabled. Based on the
+ * configuration set the PLL_TEST register.
+ */
+#if TCSR_PHY_CLK_SCHEME_SEL
+ se_clock = readl(TCSR_PHY_CLK_SCHEME_SEL) & 0x1;
+#endif
if (platform_is_msm8996() || platform_is_mdmcalifornium() || platform_is_msm8953())
{
if(platform_is_msm8996sg())
@@ -123,10 +133,16 @@
}
else if (platform_is_sdxhedgehog())
{
- writel(0x13, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDXHEDGEHOG);
+ /* HPG init sequence 0x13 for CML and 0x03 for CMOS */
+ if (se_clock)
+ writel(0x03, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDXHEDGEHOG);
+ else
+ writel(0x13, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDXHEDGEHOG);
+
writel(0x7C, QUSB2PHY_PLL_CLOCK_INVERTERS_SDXHEDGEHOG);
writel(0x80, QUSB2PHY_PLL_CMODE_SDXHEDGEHOG);
writel(0x0a, QUSB2PHY_PLL_LOCK_DELAY_SDXHEDGEHOG);
+ writel(0x19, QUSB2PHY_PLL_DIGITAL_TIMERS_TWO_SDXHEDGEHOG);
writel(0xa5, QUSB2PHY_TUNE1_SDXHEDGEHOG);
writel(0x09, QUSB2PHY_TUNE2_SDXHEDGEHOG);
writel(0x00, QUSB2PHY_IMP_CTRL1_SDXHEDGEHOG);
@@ -161,19 +177,15 @@
writel(0x22, QUSB2PHY_PORT_POWERDOWN);
udelay(150);
}
- /* TCSR register bit 0 indicates whether single ended clock
- * or differential clock configuration is enabled. Based on the
- * configuration set the PLL_TEST register.
- */
-#if TCSR_PHY_CLK_SCHEME_SEL
- se_clock = readl(TCSR_PHY_CLK_SCHEME_SEL) & 0x1;
-#endif
+
/* By default consider differential clock configuration and if TCSR
* register bit 0 is not set then use single ended setting
*/
if (se_clock)
{
- writel(0x80, QUSB2PHY_PLL_TEST);
+ /* PLL TEST is not valid for sdxhedgehog */
+ if(!platform_is_sdxhedgehog())
+ writel(0x80, QUSB2PHY_PLL_TEST);
}
else
{
diff --git a/platform/msm_shared/rpm-ipc.c b/platform/msm_shared/rpm-ipc.c
index 2bd3c51..a8649db 100644
--- a/platform/msm_shared/rpm-ipc.c
+++ b/platform/msm_shared/rpm-ipc.c
@@ -30,11 +30,22 @@
#include <arch/defines.h>
#include <stdint.h>
#include <sys/types.h>
+#include <platform.h>
#include <rpm-ipc.h>
#include <rpm-glink.h>
#include <rpm-smd.h>
#include <string.h>
+__WEAK glink_err_type rpm_glink_send_data(uint32_t *data, uint32_t len, msg_type type)
+{
+ return GLINK_STATUS_API_NOT_SUPPORTED;
+}
+
+__WEAK int rpm_smd_send_data(uint32_t *data, uint32_t len, msg_type type)
+{
+ return -1;
+}
+
void fill_kvp_object(kvp_data **kdata, uint32_t *data, uint32_t len)
{
*kdata = (kvp_data *) memalign(CACHE_LINE, ROUNDUP(len, CACHE_LINE));
@@ -52,11 +63,13 @@
int rpm_send_data(uint32_t *data, uint32_t len, msg_type type)
{
int ret = 0;
-#ifdef GLINK_SUPPORT
- ret = rpm_glink_send_data(data, len, type);
-#else
- ret = rpm_smd_send_data(data, len, type);
-#endif
+
+ /* Runtime select to call glink or smd */
+ if (platform_is_glink_enabled())
+ ret = rpm_glink_send_data(data, len, type);
+ else
+ ret = rpm_smd_send_data(data, len, type);
+
return ret;
}
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 7a9e688..e18a014 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -62,7 +62,6 @@
ifeq ($(ENABLE_GLINK_SUPPORT),1)
OBJS += \
- $(LOCAL_DIR)/rpm-ipc.o \
$(LOCAL_DIR)/glink/glink_api.o \
$(LOCAL_DIR)/glink/glink_core_if.o \
$(LOCAL_DIR)/glink/glink_core_internal.o \
@@ -76,6 +75,11 @@
$(LOCAL_DIR)/rpm-glink.o
endif
+ifneq ($(ENABLE_SMD_SUPPORT),1)
+OBJS += \
+ $(LOCAL_DIR)/rpm-ipc.o
+endif
+
ifeq ($(PLATFORM),msm8x60)
OBJS += $(LOCAL_DIR)/mipi_dsi.o \
$(LOCAL_DIR)/i2c_qup.o \
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index b34bfd5..3f6d460 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -812,9 +812,12 @@
/* Change the driver type & rerun tuning */
while(++drv_type <= MX_DRV_SUPPORTED_HS200)
{
+ /* Marking driver type changed if we try to change it */
+ if(!drv_type_changed)
+ drv_type_changed = true;
+
if (mmc_set_drv_type(host, card, drv_type))
goto retry_tuning;
- drv_type_changed = true;
}
}
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 4da7b31..fc2fc8f 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -2,7 +2,7 @@
* Copyright (c) 2009, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -459,7 +459,8 @@
MSM8996AU = 310,
APQ8096AU = 311,
APQ8096SG = 312,
- SDXHEDGEHOG = 314
+ SDXHEDGEHOG1 = 314,
+ SDXHEDGEHOG2 = 333
};
enum platform {
diff --git a/platform/msm_shared/usb30_udc.c b/platform/msm_shared/usb30_udc.c
index a2923f1..1e378bf 100644
--- a/platform/msm_shared/usb30_udc.c
+++ b/platform/msm_shared/usb30_udc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -230,10 +230,6 @@
/* section 4.4.2: Initialization and configuration sequences */
- /* 1. UTMI Mux configuration */
- if (dev_info->t_usb_if->mux_config)
- dev_info->t_usb_if->mux_config();
-
/* 2. Put controller in reset */
dwc_reset(dwc, 1);
@@ -243,6 +239,10 @@
/* 3. Reset PHY */
phy_reset(wrapper, dev_info);
+ /* 3.1 UTMI Mux configuration */
+ if (dev_info->t_usb_if->mux_config)
+ dev_info->t_usb_if->mux_config();
+
/* 4. SS phy config */
if (!use_hsonly_mode())
usb_wrapper_ss_phy_configure(wrapper);
diff --git a/project/mdm9640.mk b/project/mdm9640.mk
index d72ee16..997f92c 100644
--- a/project/mdm9640.mk
+++ b/project/mdm9640.mk
@@ -50,6 +50,11 @@
DEFINES += SMD_SUPPORT=1
endif
+ENABLE_GLINK_SUPPORT := 1
+ifeq ($(ENABLE_GLINK_SUPPORT),1)
+DEFINES += GLINK_SUPPORT=1
+endif
+
# Reset USB clock from target code
DEFINES += USB_RESET_FROM_CLK=1
diff --git a/target/mdm9607/init.c b/target/mdm9607/init.c
index b59b7b9..4145588 100644
--- a/target/mdm9607/init.c
+++ b/target/mdm9607/init.c
@@ -257,6 +257,11 @@
int system_ptn_index = -1;
uint32_t buflen = strlen(UBI_CMDLINE) + strlen(" root=ubi0:rootfs ubi.mtd=") + sizeof(int) + 1; /* 1 byte for null character*/
+ if (!cmdline || !part ) {
+ dprintf(CRITICAL, "WARN: Invalid input param\n");
+ return -1;
+ }
+
*buf = (char *)malloc(buflen);
if(!(*buf)) {
dprintf(CRITICAL,"Unable to allocate memory for boot params\n");
diff --git a/target/mdm9640/init.c b/target/mdm9640/init.c
index b335731..803bef0 100644
--- a/target/mdm9640/init.c
+++ b/target/mdm9640/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -56,6 +56,7 @@
#include <boot_device.h>
#include <qmp_phy.h>
#include <crypto5_wrapper.h>
+#include <rpm-glink.h>
extern void smem_ptable_init(void);
extern void smem_add_modem_partitions(struct ptable *flash_ptable);
@@ -151,7 +152,14 @@
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
if(!platform_is_sdxhedgehog())
+ {
rpm_smd_init();
+ }
+ else
+ {
+ /* Initialize Glink */
+ rpm_glink_init();
+ }
if (platform_boot_dev_isemmc()) {
target_sdc_init();
@@ -421,7 +429,41 @@
crypto_eng_cleanup();
if(!platform_is_sdxhedgehog())
+ {
rpm_smd_uninit();
+ }
+ else
+ {
+ /* Tear down glink channels */
+ rpm_glink_uninit();
+ }
+}
+void target_mux_configure(void)
+{
+ uint32_t val;
+ //USB30_GENERAL_CFG_PIPE_UTMI_CLK_DIS
+ val = readl(USB30_GENERAL_CFG_PIPE);
+ val = val | 0x100;
+ writel(val, USB30_GENERAL_CFG_PIPE);
+ udelay(100);
+
+ //USB30_GENERAL_CFG_PIPE_UTMI_CLK_SEL
+ val = readl(USB30_GENERAL_CFG_PIPE);
+ val = val | 0x1;
+ writel(val, USB30_GENERAL_CFG_PIPE);
+ udelay(100);
+
+ //USB30_GENERAL_CFG_PIPE3_PHYSTATUS_SW
+ val = readl(USB30_GENERAL_CFG_PIPE);
+ val = val | 0x8;
+ writel(val, USB30_GENERAL_CFG_PIPE);
+ udelay(100);
+
+ //USB30_GENERAL_CFG_PIPE_UTMI_CLK_ENABLE
+ val = readl(USB30_GENERAL_CFG_PIPE);
+ val = val & 0xfffffeff;
+ writel(val, USB30_GENERAL_CFG_PIPE);
+ udelay(100);
}
void target_usb_phy_reset(void)
@@ -445,8 +487,10 @@
ASSERT(t_usb_iface);
t_usb_iface->mux_config = NULL;
- if (platform_is_sdxhedgehog())
+ if (platform_is_sdxhedgehog()){
+ t_usb_iface->mux_config = target_mux_configure;
t_usb_iface->phy_init = NULL;
+ }
else
t_usb_iface->phy_init = usb30_qmp_phy_init;
t_usb_iface->phy_reset = target_usb_phy_reset;
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index bcbf1be..ee001bc 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -51,6 +51,13 @@
#include "include/display_resource.h"
#include "gcdb_display.h"
+#define TRULY_720P_VID_PANEL "truly_720p_video"
+#define TRULY_720P_CMD_PANEL "truly_720p_cmd"
+
+#define HDMI_ADV_PANEL_STRING "1:dsi:0:qcom,mdss_dsi_adv7533_1080p:1:none:cfg:single_dsi"
+#define TRULY_VID_PANEL_STRING "1:dsi:0:qcom,mdss_dsi_truly_720p_video:1:none:cfg:single_dsi"
+#define TRULY_CMD_PANEL_STRING "1:dsi:0:qcom,mdss_dsi_truly_720p_cmd:1:none:cfg:single_dsi"
+
/*---------------------------------------------------------------------------*/
/* GPIO configuration */
/*---------------------------------------------------------------------------*/
@@ -569,7 +576,55 @@
bool target_display_panel_node(char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(pbuf, buf_size);
+ int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
+ bool ret = true;
+ struct oem_panel_data oem = mdss_dsi_get_oem_data();
+ uint32_t platform_subtype = board_hardware_subtype();
+
+ /* default to hdmi for apq iot */
+ if ((HW_PLATFORM_SUBTYPE_SNAP == platform_subtype) ||
+ (HW_PLATFORM_SUBTYPE_SNAP_NOPMI == platform_subtype)) {
+ if (!strcmp(oem.panel, "")) {
+ if (buf_size < (prefix_string_len +
+ strlen(HDMI_ADV_PANEL_STRING))) {
+ dprintf(CRITICAL, "HDMI command line argument \
+ is greater than buffer size\n");
+ return false;
+ }
+ strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+ buf_size -= prefix_string_len;
+ pbuf += prefix_string_len;
+ strlcpy(pbuf, HDMI_ADV_PANEL_STRING, buf_size);
+ } else if (!strcmp(oem.panel, TRULY_720P_VID_PANEL)) {
+ if (buf_size < (prefix_string_len +
+ strlen(TRULY_VID_PANEL_STRING))) {
+ dprintf(CRITICAL, "TRULY VIDEO command line \
+ argument is greater than \
+ buffer size\n");
+ return false;
+ }
+ strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+ buf_size -= prefix_string_len;
+ pbuf += prefix_string_len;
+ strlcpy(pbuf, TRULY_VID_PANEL_STRING, buf_size);
+ } else if (!strcmp(oem.panel, TRULY_720P_CMD_PANEL)) {
+ if (buf_size < (prefix_string_len +
+ strlen(TRULY_CMD_PANEL_STRING))) {
+ dprintf(CRITICAL, "TRULY CMD command line argument \
+ argument is greater than \
+ buffer size\n");
+ return false;
+ }
+ strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+ buf_size -= prefix_string_len;
+ pbuf += prefix_string_len;
+ strlcpy(pbuf, TRULY_CMD_PANEL_STRING, buf_size);
+ }
+ } else {
+ ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+ }
+
+ return ret;
}
void target_display_init(const char *panel_name)
@@ -577,6 +632,7 @@
struct oem_panel_data oem;
int32_t ret = 0;
uint32_t panel_loop = 0;
+ uint32_t platform_subtype = board_hardware_subtype();
set_panel_cmd_string(panel_name);
oem = mdss_dsi_get_oem_data();
@@ -590,6 +646,13 @@
return;
}
+ if ((HW_PLATFORM_SUBTYPE_SNAP == platform_subtype) ||
+ (HW_PLATFORM_SUBTYPE_SNAP_NOPMI == platform_subtype)) {
+ dprintf(INFO, "%s: Platform subtype %d\n",
+ __func__, platform_subtype);
+ return;
+ }
+
do {
target_force_cont_splash_disable(false);
ret = gcdb_display_init(oem.panel, MDP_REV_50, (void *)MIPI_FB_ADDR);