platform: msmtitanium: Add clock config for Peripherals.
Adding Clock configuration needed to enable UART, USB, SDCC and Cypto.
Change-Id: I845d4cc7f06cb8d3f0954f5133f808acbc1be79e
diff --git a/platform/msmtitanium/acpuclock.c b/platform/msmtitanium/acpuclock.c
index 25c1eff..58fc686 100755
--- a/platform/msmtitanium/acpuclock.c
+++ b/platform/msmtitanium/acpuclock.c
@@ -38,25 +38,171 @@
#define MAX_LOOPS 500
-void hsusb_clock_init(void)
+/*
+ * Disable power collapse using GDSCR:
+ * Globally Distributed Switch Controller Register
+ */
+void clock_usb30_gdsc_enable(void)
{
+ uint32_t reg = readl(GCC_USB30_GDSCR);
+
+ reg &= ~(0x1);
+
+ writel(reg, GCC_USB30_GDSCR);
+}
+
+/* enables usb30 clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ clock_usb30_gdsc_enable();
+
+ ret = clk_get_set_enable("usb30_master_clk", 133330000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_aux_clk", 19200000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_aux_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_sleep_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_phy_cfg_ahb_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_phy_cfg_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
void clock_init_mmc(uint32_t interface)
{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
+ int ret = 1;
char clk_name[64];
snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else if(freq == MMC_CLK_177MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 177770000, 1);
+ }
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
+ }
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
+ ASSERT(0);
+ }
+}
+
+void clock_bumpup_pipe3_clk()
+{
+ int ret =0;
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, true);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret);
+ ASSERT(0);
+ }
}
/* Function to asynchronously reset CE.
@@ -64,14 +210,90 @@
*/
static void ce_async_reset(uint8_t instance)
{
+ /* Start the block reset for CE */
+ writel(1, GCC_CRYPTO_BCR);
+
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CRYPTO_BCR);
+
+ udelay(2);
}
void clock_ce_enable(uint8_t instance)
{
+ int ret;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ ret = clk_get_set_enable(clk_name, 160000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_src_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_core_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_ahb_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_axi_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ /* Wait for 48 * #pipes cycles.
+ * This is necessary as immediately after an access control reset (boot up)
+ * or a debug re-enable, the Crypto core sequentially clears its internal
+ * pipe key storage memory. If pipe key initialization writes are attempted
+ * during this time, they may be overwritten by the internal clearing logic.
+ */
+ udelay(1);
}
void clock_ce_disable(uint8_t instance)
{
+ struct clk *ahb_clk;
+ struct clk *cclk;
+ struct clk *axi_clk;
+ struct clk *src_clk;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ src_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ahb_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ axi_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ cclk = clk_get(clk_name);
+
+ clk_disable(ahb_clk);
+ clk_disable(axi_clk);
+ clk_disable(cclk);
+ clk_disable(src_clk);
+
+ /* Some delay for the clocks to stabalize. */
+ udelay(1);
}
void clock_config_ce(uint8_t instance)
@@ -88,3 +310,73 @@
clock_ce_enable(instance);
}
+
+
+void clock_reset_usb_phy()
+{
+ int ret;
+
+ struct clk *phy_reset_clk = NULL;
+ struct clk *pipe_reset_clk = NULL;
+ struct clk *master_clk = NULL;
+
+ master_clk = clk_get("usb30_master_clk");
+ ASSERT(master_clk);
+
+ /* Look if phy com clock is present */
+ phy_reset_clk = clk_get("usb30_phy_reset");
+ ASSERT(phy_reset_clk);
+
+ pipe_reset_clk = clk_get("usb30_pipe_clk");
+ ASSERT(pipe_reset_clk);
+
+ /* ASSERT */
+ ret = clk_reset(master_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_master_reset clk\n");
+ return;
+ }
+ ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n");
+ goto deassert_master_clk;
+ }
+
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n");
+ goto deassert_phy_clk;
+ }
+
+ udelay(100);
+
+ /* DEASSERT */
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n");
+ return;
+ }
+
+deassert_phy_clk:
+
+ ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n");
+ return;
+ }
+
+deassert_master_clk:
+
+ ret = clk_reset(master_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_master clk\n");
+ return;
+ }
+}