platform: msmtitanium: Add clock config for Peripherals.
Adding Clock configuration needed to enable UART, USB, SDCC and Cypto.
Change-Id: I845d4cc7f06cb8d3f0954f5133f808acbc1be79e
diff --git a/platform/msmtitanium/msmtitanium-clock.c b/platform/msmtitanium/msmtitanium-clock.c
old mode 100644
new mode 100755
index ee831b2..ff1e313
--- a/platform/msmtitanium/msmtitanium-clock.c
+++ b/platform/msmtitanium/msmtitanium-clock.c
@@ -40,6 +40,8 @@
#define cxo_source_val 0
#define gpll0_source_val 1
#define gpll4_source_val 2
+#define gpll6_source_val 1
+#define gpll0_out_main_div2_source_val 4
#define cxo_mm_source_val 0
#define gpll0_mm_source_val 6
#define gpll6_mm_source_val 3
@@ -48,6 +50,12 @@
/* Clock Operations */
+
+static struct clk_ops clk_ops_reset =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
static struct clk_ops clk_ops_branch =
{
.enable = clock_lib2_branch_clk_enable,
@@ -112,6 +120,21 @@
},
};
+static struct pll_vote_clk gpll0_out_main_div2_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 400000000,
+ .dbg_name = "gpll0_out_main_div2_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
static struct pll_vote_clk gpll4_clk_src =
{
.en_reg = (void *) APCS_GPLL_ENA_VOTE,
@@ -127,17 +150,32 @@
},
};
+static struct pll_vote_clk gpll6_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(7),
+ .status_reg = (void *) GPLL6_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1080000000,
+ .dbg_name = "gpll6_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
/* SDCC Clocks */
static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] =
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
- F( 20000000, gpll0, 10, 1, 4),
- F( 25000000, gpll0, 16, 1, 2),
+ F( 20000000, gpll0_out_main_div2, 5, 1, 2),
+ F( 25000000, gpll0_out_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F(100000000, gpll0, 8, 0, 0),
F(177770000, gpll0, 4.5, 0, 0),
- F(200000000, gpll0, 4, 0, 0),
+ F(192000000, gpll4, 6, 0, 0),
F(384000000, gpll4, 3, 0, 0),
F_END
};
@@ -186,12 +224,12 @@
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
- F( 20000000, gpll0, 10, 1, 4),
- F( 25000000, gpll0, 16, 1, 2),
+ F( 20000000, gpll0_out_main_div2, 5, 1, 2),
+ F( 25000000, gpll0_out_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F(100000000, gpll0, 8, 0, 0),
F(177770000, gpll0, 4.5, 0, 0),
- F(200000000, gpll0, 4, 0, 0),
+ F(192000000, gpll4, 6, 0, 0),
F_END
};
@@ -238,10 +276,10 @@
/* UART Clocks */
static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] =
{
- F( 3686400, gpll0, 1, 72, 15625),
- F( 7372800, gpll0, 1, 144, 15625),
- F(14745600, gpll0, 1, 288, 15625),
- F(16000000, gpll0, 10, 1, 5),
+ F( 3686400, gpll0_out_main_div2, 1, 144, 15625),
+ F( 7372800, gpll0_out_main_div2, 1, 288, 15625),
+ F(14745600, gpll0_out_main_div2, 1, 576, 15625),
+ F(16000000, gpll0_out_main_div2, 5, 1, 5),
F(19200000, cxo, 1, 0, 0),
F(24000000, gpll0, 1, 3, 100),
F(25000000, gpll0, 16, 1, 2),
@@ -253,9 +291,39 @@
F(56000000, gpll0, 1, 7, 100),
F(58982400, gpll0, 1,1152, 15625),
F(60000000, gpll0, 1, 3, 40),
+ F(64000000, gpll0, 12, 1, 2),
F_END
};
+static struct rcg_clk blsp1_uart1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART1_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART1_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART1_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart1_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR,
+ .parent = &blsp1_uart1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct rcg_clk blsp1_uart2_apps_clk_src =
{
.cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
@@ -297,50 +365,117 @@
};
/* USB Clocks */
-static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+static struct branch_clk gcc_pc_noc_usb30_axi_clk =
{
- F(100000000, gpll0, 10, 0, 0),
- F(133330000, gpll0, 6, 0, 0),
+ .cbcr_reg = (uint32_t *) PC_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_pc_noc_usb3_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_phy_cfg_ahb_clk = {
+ .cbcr_reg = (uint32_t *) USB_PHY_CFG_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_phy_cfg_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
+{
+ F(100000000, gpll0, 8, 0, 0),
+ F(133330000, gpll0, 6, 0, 0),
F_END
};
-static struct rcg_clk usb_hs_system_clk_src =
-{
- .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
- .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+static struct rcg_clk usb30_master_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) USB30_MASTER_M,
+ .n_reg = (uint32_t *) USB30_MASTER_N,
+ .d_reg = (uint32_t *) USB30_MASTER_D,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "usb_hs_system_clk",
+ .dbg_name = "usb30_master_clk_src",
.ops = &clk_ops_rcg,
},
};
-static struct branch_clk gcc_usb_hs_system_clk =
+static struct branch_clk gcc_usb30_master_clk =
{
- .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
- .parent = &usb_hs_system_clk_src.c,
+ .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR,
+ .bcr_reg = (uint32_t *) USB_30_BCR,
+ .parent = &usb30_master_clk_src.c,
.c = {
- .dbg_name = "gcc_usb_hs_system_clk",
+ .dbg_name = "gcc_usb30_master_clk",
.ops = &clk_ops_branch,
},
};
-static struct branch_clk gcc_usb_hs_ahb_clk =
-{
- .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+
+static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) USB3PHY_PHY_BCR,
+ .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
.has_sibling = 1,
+ .halt_check = 0,
.c = {
- .dbg_name = "gcc_usb_hs_ahb_clk",
+ .dbg_name = "usb30_pipe_clk",
.ops = &clk_ops_branch,
},
};
+static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = {
+ F( 19200000, cxo, 0, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_aux_clk_src = {
+ .cmd_reg = (uint32_t *) USB3_AUX_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB3_AUX_CFG_RCGR,
+ .m_reg = (uint32_t *) USB3_AUX_M,
+ .n_reg = (uint32_t *) USB3_AUX_N,
+ .d_reg = (uint32_t *) USB3_AUX_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_aux_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_aux_clk_src",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_usb30_aux_clk = {
+ .cbcr_reg = (uint32_t *) USB3_AUX_CBCR,
+ .parent = &usb30_aux_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb30_aux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t) USB3_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_reset,
+ },
+};
+
static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
F(160000000, gpll0, 5, 0, 0),
F_END
@@ -370,6 +505,54 @@
},
};
+static struct reset_clk gcc_usb2a_phy_sleep_clk = {
+ .bcr_reg = (uint32_t) GCC_QUSB2_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb2b_phy_sleep_clk",
+ .ops = &clk_ops_reset,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+ F( 19200000, cxo, 0, 0, 0),
+ F( 60000000, gpll6, 6, 1, 3),
+ F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+ .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_mock_utmi_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+ .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
static struct vote_clk gcc_ce1_ahb_clk = {
.cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR,
.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
@@ -401,11 +584,21 @@
CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+ CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c),
+
CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
- CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
- CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+ CLK_LOOKUP("usb30_iface_clk", gcc_pc_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
+ CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c),
+ CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+ CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
+ CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
+ CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),