Merge "dev: gcdb: display: update auto refresh specific params" into lk.lnx.1.0-dev.1.0
diff --git a/dev/fbcon/fbcon.c b/dev/fbcon/fbcon.c
index f2296a4..5bce3c2 100644
--- a/dev/fbcon/fbcon.c
+++ b/dev/fbcon/fbcon.c
@@ -109,6 +109,8 @@
[FBCON_SELECT_MSG_BG_COLOR] = {RGB888_WHITE, RGB888_BLUE}};
+static void fbcon_flush(void);
+
static void fbcon_drawglyph(char *pixels, uint32_t paint, unsigned stride,
unsigned bpp, unsigned *glyph, unsigned scale_factor)
{
@@ -211,6 +213,7 @@
pixels += config->bpp / 8;
}
}
+ fbcon_flush();
}
static void fbcon_flush(void)
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index e7c9ace..1457877 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -163,6 +163,29 @@
int pll_type;
};
+struct ssc_params {
+ uint32_t kdiv;
+ uint64_t triang_inc_7_0;
+ uint64_t triang_inc_9_8;
+ uint64_t triang_steps;
+ uint64_t dc_offset;
+ uint64_t freq_seed_7_0;
+ uint64_t freq_seed_15_8;
+};
+
+struct mdss_dsi_vco_calc {
+ uint64_t sdm_cfg0;
+ uint64_t sdm_cfg1;
+ uint64_t sdm_cfg2;
+ uint64_t sdm_cfg3;
+ uint64_t cal_cfg10;
+ uint64_t cal_cfg11;
+ uint64_t refclk_cfg;
+ uint64_t gen_vco_clk;
+ uint32_t lpfr_lut_res;
+ struct ssc_params ssc;
+};
+
struct mdss_dsi_pll_config {
uint32_t pixel_clock;
uint32_t pixel_clock_mhz;
@@ -181,6 +204,12 @@
uint8_t pclk_n;
uint8_t pclk_d;
+ /* SSC related params */
+ bool ssc_en;
+ bool is_center_spread;
+ uint32_t ssc_freq;
+ uint32_t ssc_ppm;
+
/* pll 20nm */
uint32_t dec_start;
uint32_t frac_start;
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index 69bd7a1..1adb31b 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -81,16 +81,19 @@
udelay(1);
}
-int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base,
- struct mdss_dsi_pll_config *pd)
+uint64_t div_round_closest_unsigned(uint64_t dividend, uint64_t divisor)
{
- uint32_t rem, divider;
- uint32_t refclk_cfg = 0, frac_n_mode = 0, ref_doubler_en_b = 0;
- uint64_t vco_clock, div_fbx;
- uint32_t ref_clk_to_pll = 0, frac_n_value = 0;
- uint32_t sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
- uint32_t gen_vco_clk, cal_cfg10, cal_cfg11;
- uint8_t i, rc = NO_ERROR;
+ return ((dividend + (divisor / 2)) / divisor);
+}
+
+static int32_t mdss_dsi_pll_vco_rate_calc(struct mdss_dsi_pll_config *pd,
+ struct mdss_dsi_vco_calc *vco_calc)
+{
+ uint8_t i;
+ int8_t rc = NO_ERROR;
+ uint32_t rem;
+ uint64_t frac_n_mode = 0, ref_doubler_en_b = 0;
+ uint64_t div_fb = 0, frac_n_value = 0, ref_clk_to_pll = 0;
/* Configure the Loop filter resistance */
for (i = 0; i < LPFR_LUT_SIZE; i++)
@@ -102,11 +105,83 @@
rc = ERROR;
return rc;
}
+ vco_calc->lpfr_lut_res = lpfr_lut[i].resistance;
- mdss_dsi_phy_sw_reset(ctl_base);
+ rem = pd->vco_clock % VCO_REF_CLOCK_RATE;
+ if (rem) {
+ vco_calc->refclk_cfg = 0x1;
+ frac_n_mode = 1;
+ ref_doubler_en_b = 0;
+ } else {
+ vco_calc->refclk_cfg = 0x0;
+ frac_n_mode = 0;
+ ref_doubler_en_b = 1;
+ }
+ ref_clk_to_pll = (VCO_REF_CLOCK_RATE * 2 * vco_calc->refclk_cfg)
+ + (ref_doubler_en_b * VCO_REF_CLOCK_RATE);
+ div_fb = div_s64(pd->vco_clock, ref_clk_to_pll, &rem);
+ frac_n_value = ((uint64_t) rem * (1 << 16)) / ref_clk_to_pll;
+ vco_calc->gen_vco_clk = pd->vco_clock;
+
+ if (frac_n_mode) {
+ vco_calc->sdm_cfg0 = 0x0;
+ vco_calc->sdm_cfg1 = (div_fb & 0x3f) - 1;
+ vco_calc->sdm_cfg3 = frac_n_value / 256;
+ vco_calc->sdm_cfg2 = frac_n_value % 256;
+ } else {
+ vco_calc->sdm_cfg0 = (0x1 << 5);
+ vco_calc->sdm_cfg0 |= (div_fb & 0x3f) - 1;
+ vco_calc->sdm_cfg1 = 0x0;
+ vco_calc->sdm_cfg2 = 0;
+ vco_calc->sdm_cfg3 = 0;
+ }
+
+ vco_calc->cal_cfg11 = vco_calc->gen_vco_clk / 256000000;
+ vco_calc->cal_cfg10 = (vco_calc->gen_vco_clk % 256000000) / 1000000;
+
+ return NO_ERROR;
+
+}
+
+static void mdss_dsi_ssc_param_calc(struct mdss_dsi_pll_config *pd,
+ struct mdss_dsi_vco_calc *vco_calc)
+{
+ uint64_t ppm_freq, incr, spread_freq, div_rf, frac_n_value;
+ uint32_t rem;
+
+ vco_calc->ssc.kdiv = div_round_closest_unsigned(VCO_REF_CLOCK_RATE,
+ 1000000) - 1;
+ vco_calc->ssc.triang_steps = div_round_closest_unsigned(
+ VCO_REF_CLOCK_RATE, pd->ssc_freq * (vco_calc->ssc.kdiv + 1));
+ ppm_freq = (vco_calc->gen_vco_clk * pd->ssc_ppm) / 1000000;
+ incr = (ppm_freq * 65536) / (VCO_REF_CLOCK_RATE * 2 *
+ vco_calc->ssc.triang_steps);
+
+ vco_calc->ssc.triang_inc_7_0 = incr & 0xff;
+ vco_calc->ssc.triang_inc_9_8 = (incr >> 8) & 0x3;
+
+ if (!pd->is_center_spread)
+ spread_freq = vco_calc->gen_vco_clk - ppm_freq;
+ else
+ spread_freq = vco_calc->gen_vco_clk - (ppm_freq / 2);
+
+ div_rf = spread_freq / (2 * VCO_REF_CLOCK_RATE);
+ vco_calc->ssc.dc_offset = (div_rf - 1);
+
+ div_s64(spread_freq, 2 * VCO_REF_CLOCK_RATE, &rem);
+ frac_n_value = ((uint64_t) rem * 65536) / (2 * VCO_REF_CLOCK_RATE);
+
+ vco_calc->ssc.freq_seed_7_0 = frac_n_value & 0xff;
+ vco_calc->ssc.freq_seed_15_8 = (frac_n_value >> 8) & 0xff;
+
+}
+
+static void mdss_dsi_pll_vco_config(uint32_t pll_base, struct mdss_dsi_pll_config *pd,
+ struct mdss_dsi_vco_calc *vco_calc)
+{
/* Loop filter resistance value */
- writel(lpfr_lut[i].resistance, pll_base + 0x002c);
+ writel(vco_calc->lpfr_lut_res, pll_base + 0x002c);
/* Loop filter capacitance values : c1 and c2 */
writel(0x70, pll_base + 0x0030);
writel(0x15, pll_base + 0x0034);
@@ -123,51 +198,20 @@
writel(0x66, pll_base + 0x007c); /* Cal CFG4 */
writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
- rem = pd->vco_clock % VCO_REF_CLOCK_RATE;
- if (rem) {
- refclk_cfg = 0x1;
- frac_n_mode = 1;
- ref_doubler_en_b = 0;
+ if (!pd->ssc_en) {
+ writel(vco_calc->sdm_cfg1 , pll_base + 0x003c); /* SDM CFG1 */
+ writel(vco_calc->sdm_cfg2 , pll_base + 0x0040); /* SDM CFG2 */
+ writel(vco_calc->sdm_cfg3 , pll_base + 0x0044); /* SDM CFG3 */
} else {
- refclk_cfg = 0x0;
- frac_n_mode = 0;
- ref_doubler_en_b = 1;
+ writel(vco_calc->ssc.dc_offset , pll_base + 0x003c); /* SDM CFG1 */
+ writel(vco_calc->ssc.freq_seed_7_0, pll_base + 0x0040); /* SDM CFG2 */
+ writel(vco_calc->ssc.freq_seed_15_8 , pll_base + 0x0044); /* SDM CFG3 */
+ writel(vco_calc->ssc.kdiv, pll_base + 0x4c); /* SSC CFG0 */
+ writel(vco_calc->ssc.triang_inc_7_0, pll_base + 0x50); /* SSC CFG1 */
+ writel(vco_calc->ssc.triang_inc_9_8, pll_base + 0x54); /* SSC CFG2 */
+ writel(vco_calc->ssc.triang_steps, pll_base + 0x58); /* SSC CFG3 */
}
- ref_clk_to_pll = (VCO_REF_CLOCK_RATE * 2 * refclk_cfg)
- + (ref_doubler_en_b * VCO_REF_CLOCK_RATE);
-
- vco_clock = ((uint64_t) pd->vco_clock) * FRAC_DIVIDER;
-
- div_fbx = vco_clock / ref_clk_to_pll;
-
- rem = (uint32_t) (div_fbx % FRAC_DIVIDER);
- rem = rem * (1 << 16);
- frac_n_value = rem / FRAC_DIVIDER;
-
- divider = pd->vco_clock / ref_clk_to_pll;
- div_fbx *= ref_clk_to_pll;
- gen_vco_clk = div_fbx / FRAC_DIVIDER;
-
- if (frac_n_mode) {
- sdm_cfg0 = 0x0;
- sdm_cfg1 = (divider & 0x3f) - 1;
- sdm_cfg3 = frac_n_value / 256;
- sdm_cfg2 = frac_n_value % 256;
- } else {
- sdm_cfg0 = (0x1 << 5);
- sdm_cfg0 |= (divider & 0x3f) - 1;
- sdm_cfg1 = 0x0;
- sdm_cfg2 = 0;
- sdm_cfg3 = 0;
- }
-
- cal_cfg11 = gen_vco_clk / 256000000;
- cal_cfg10 = (gen_vco_clk % 256000000) / 1000000;
-
- writel(sdm_cfg1 , pll_base + 0x003c); /* SDM CFG1 */
- writel(sdm_cfg2 , pll_base + 0x0040); /* SDM CFG2 */
- writel(sdm_cfg3 , pll_base + 0x0044); /* SDM CFG3 */
writel(0x00, pll_base + 0x0048); /* SDM CFG4 */
if (pd->vco_delay)
@@ -175,19 +219,38 @@
else
udelay(10);
- writel(refclk_cfg, pll_base + 0x0000); /* REFCLK CFG */
+ writel(vco_calc->refclk_cfg, pll_base + 0x0000); /* REFCLK CFG */
writel(0x00, pll_base + 0x0014); /* PWRGEN CFG */
writel(0x71, pll_base + 0x000c); /* VCOLPF CFG */
writel(pd->directpath, pll_base + 0x0010); /* VREG CFG */
- writel(sdm_cfg0, pll_base + 0x0038); /* SDM CFG0 */
+ writel(vco_calc->sdm_cfg0, pll_base + 0x0038); /* SDM CFG0 */
writel(0x0a, pll_base + 0x006c); /* CAL CFG0 */
writel(0x30, pll_base + 0x0084); /* CAL CFG6 */
writel(0x00, pll_base + 0x0088); /* CAL CFG7 */
writel(0x60, pll_base + 0x008c); /* CAL CFG8 */
writel(0x00, pll_base + 0x0090); /* CAL CFG9 */
- writel(cal_cfg10, pll_base + 0x0094); /* CAL CFG10 */
- writel(cal_cfg11, pll_base + 0x0098); /* CAL CFG11 */
+ writel(vco_calc->cal_cfg10, pll_base + 0x0094); /* CAL CFG10 */
+ writel(vco_calc->cal_cfg11, pll_base + 0x0098); /* CAL CFG11 */
writel(0x20, pll_base + 0x009c); /* EFUSE CFG */
+}
+
+int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd)
+{
+ int rc = NO_ERROR;
+ struct mdss_dsi_vco_calc vco_calc;
+
+
+ rc = mdss_dsi_pll_vco_rate_calc(pd, &vco_calc);
+ if (rc)
+ return rc;
+
+ mdss_dsi_ssc_param_calc(pd, &vco_calc);
+
+ mdss_dsi_phy_sw_reset(ctl_base);
+
+ mdss_dsi_pll_vco_config(pll_base, pd, &vco_calc);
+
return rc;
}
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
old mode 100644
new mode 100755
index bce48b9..2bfc931
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -632,7 +632,16 @@
$(LOCAL_DIR)/scm.o \
$(LOCAL_DIR)/qseecom_lk.o \
$(LOCAL_DIR)/dev_tree.o \
- $(LOCAL_DIR)/gpio.o
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/dload_util.o \
+ $(LOCAL_DIR)/shutdown_detect.o \
+ $(LOCAL_DIR)/certificate.o \
+ $(LOCAL_DIR)/image_verify.o \
+ $(LOCAL_DIR)/crypto_hash.o \
+ $(LOCAL_DIR)/crypto5_eng.o \
+ $(LOCAL_DIR)/qmp_usb30_phy.o \
+ $(LOCAL_DIR)/qusb2_phy.o \
+ $(LOCAL_DIR)/crypto5_wrapper.o
endif
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index c883fa2..05e9ede 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -447,6 +447,7 @@
MSMTITANIUM = 293,
MSM8937 = 294,
APQ8037 = 295,
+ APQTITANIUM = 304,
};
enum platform {
diff --git a/platform/msmtitanium/acpuclock.c b/platform/msmtitanium/acpuclock.c
index 25c1eff..58fc686 100755
--- a/platform/msmtitanium/acpuclock.c
+++ b/platform/msmtitanium/acpuclock.c
@@ -38,25 +38,171 @@
#define MAX_LOOPS 500
-void hsusb_clock_init(void)
+/*
+ * Disable power collapse using GDSCR:
+ * Globally Distributed Switch Controller Register
+ */
+void clock_usb30_gdsc_enable(void)
{
+ uint32_t reg = readl(GCC_USB30_GDSCR);
+
+ reg &= ~(0x1);
+
+ writel(reg, GCC_USB30_GDSCR);
+}
+
+/* enables usb30 clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ clock_usb30_gdsc_enable();
+
+ ret = clk_get_set_enable("usb30_master_clk", 133330000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_aux_clk", 19200000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_aux_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_sleep_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_phy_cfg_ahb_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_phy_cfg_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
void clock_init_mmc(uint32_t interface)
{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
+ int ret = 1;
char clk_name[64];
snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else if(freq == MMC_CLK_177MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 177770000, 1);
+ }
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
+ }
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
+ ASSERT(0);
+ }
+}
+
+void clock_bumpup_pipe3_clk()
+{
+ int ret =0;
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, true);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret);
+ ASSERT(0);
+ }
}
/* Function to asynchronously reset CE.
@@ -64,14 +210,90 @@
*/
static void ce_async_reset(uint8_t instance)
{
+ /* Start the block reset for CE */
+ writel(1, GCC_CRYPTO_BCR);
+
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CRYPTO_BCR);
+
+ udelay(2);
}
void clock_ce_enable(uint8_t instance)
{
+ int ret;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ ret = clk_get_set_enable(clk_name, 160000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_src_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_core_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_ahb_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_axi_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ /* Wait for 48 * #pipes cycles.
+ * This is necessary as immediately after an access control reset (boot up)
+ * or a debug re-enable, the Crypto core sequentially clears its internal
+ * pipe key storage memory. If pipe key initialization writes are attempted
+ * during this time, they may be overwritten by the internal clearing logic.
+ */
+ udelay(1);
}
void clock_ce_disable(uint8_t instance)
{
+ struct clk *ahb_clk;
+ struct clk *cclk;
+ struct clk *axi_clk;
+ struct clk *src_clk;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ src_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ahb_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ axi_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ cclk = clk_get(clk_name);
+
+ clk_disable(ahb_clk);
+ clk_disable(axi_clk);
+ clk_disable(cclk);
+ clk_disable(src_clk);
+
+ /* Some delay for the clocks to stabalize. */
+ udelay(1);
}
void clock_config_ce(uint8_t instance)
@@ -88,3 +310,73 @@
clock_ce_enable(instance);
}
+
+
+void clock_reset_usb_phy()
+{
+ int ret;
+
+ struct clk *phy_reset_clk = NULL;
+ struct clk *pipe_reset_clk = NULL;
+ struct clk *master_clk = NULL;
+
+ master_clk = clk_get("usb30_master_clk");
+ ASSERT(master_clk);
+
+ /* Look if phy com clock is present */
+ phy_reset_clk = clk_get("usb30_phy_reset");
+ ASSERT(phy_reset_clk);
+
+ pipe_reset_clk = clk_get("usb30_pipe_clk");
+ ASSERT(pipe_reset_clk);
+
+ /* ASSERT */
+ ret = clk_reset(master_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_master_reset clk\n");
+ return;
+ }
+ ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n");
+ goto deassert_master_clk;
+ }
+
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n");
+ goto deassert_phy_clk;
+ }
+
+ udelay(100);
+
+ /* DEASSERT */
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n");
+ return;
+ }
+
+deassert_phy_clk:
+
+ ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n");
+ return;
+ }
+
+deassert_master_clk:
+
+ ret = clk_reset(master_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_master clk\n");
+ return;
+ }
+}
diff --git a/platform/msmtitanium/include/platform/clock.h b/platform/msmtitanium/include/platform/clock.h
old mode 100644
new mode 100755
index 4174744..86d1f9b
--- a/platform/msmtitanium/include/platform/clock.h
+++ b/platform/msmtitanium/include/platform/clock.h
@@ -41,4 +41,8 @@
void clock_config_uart_dm(uint8_t id);
void hsusb_clock_init(void);
void clock_config_ce(uint8_t instance);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
+void clock_reset_usb_phy();
#endif
diff --git a/platform/msmtitanium/include/platform/iomap.h b/platform/msmtitanium/include/platform/iomap.h
index a57769b..64779cb 100755
--- a/platform/msmtitanium/include/platform/iomap.h
+++ b/platform/msmtitanium/include/platform/iomap.h
@@ -93,7 +93,7 @@
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
-#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
+#define GPLL6_STATUS (CLK_CTL_BASE + 0x37024)
/* SDCC */
#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
@@ -127,6 +127,12 @@
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
+#define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x203C)
+#define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2044)
+#define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x2048)
+#define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x204C)
+#define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x2050)
+#define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x2054)
#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
@@ -140,9 +146,56 @@
#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
-#define MSM_USB30_QSCRATCH_BASE 0x070F8800
-#define MSM_USB30_BASE 0x7000000
-#define USB2_PHY_SEL 0x01937000
+#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x4103C)
+#define MSM_USB30_QSCRATCH_BASE 0x070F8800
+#define MSM_USB30_BASE 0x7000000
+#define USB2_PHY_SEL 0x01937000
+#define QUSB2_PHY_BASE 0X79000
+
+/* SS QMP (Qulacomm Multi Protocol) */
+#define QMP_PHY_BASE 0x78000
+
+#define AHB2_PHY_BASE 0x0007e000
+#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
+
+ /* USB3 clocks */
+#define USB_30_BCR (CLK_CTL_BASE + 0x3F070)
+#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x3F078)
+#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0x3F000)
+#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x3F004)
+#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x3F008)
+#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x3F00C)
+#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x3F010)
+#define USB30_MASTER_M (CLK_CTL_BASE + 0x3F014)
+#define USB30_MASTER_N (CLK_CTL_BASE + 0x3F018)
+#define USB30_MASTER_D (CLK_CTL_BASE + 0x3F01C)
+#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x3F020)
+#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x3F024)
+#define PC_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x3F038)
+
+#define USB3_AUX_CMD_RCGR (CLK_CTL_BASE + 0x3F05C)
+#define USB3_AUX_CFG_RCGR (CLK_CTL_BASE + 0x3F060)
+#define USB3_AUX_CBCR (CLK_CTL_BASE + 0x3F044)
+#define USB3_AUX_M (CLK_CTL_BASE + 0x3F064)
+#define USB3_AUX_N (CLK_CTL_BASE + 0x3F068)
+#define USB3_AUX_D (CLK_CTL_BASE + 0x3F06C)
+#define USB3_PIPE_CBCR (CLK_CTL_BASE + 0x3F040)
+#define USB3_PHY_BCR (CLK_CTL_BASE + 0x3F034)
+#define USB3PHY_PHY_BCR (CLK_CTL_BASE + 0x3F03C)
+#define USB_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x3F080)
+
+/* QMP rev registers */
+#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x988)
+#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x98C)
+#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x990)
+#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x994)
+
+/* Dummy macro needed for compilation only */
+#define PLATFORM_QMP_OFFSET 0x0
+
+#define USB3_PHY_STATUS 0x78974
+/* Register for finding out if single ended or differential clock enablement */
+#define TCSR_PHY_CLK_SCHEME_SEL 0x0193F044
/* RPMB send receive buffer needs to be mapped
* as device memory, define the start address
diff --git a/platform/msmtitanium/include/platform/irqs.h b/platform/msmtitanium/include/platform/irqs.h
index db33501..6c0aebf 100755
--- a/platform/msmtitanium/include/platform/irqs.h
+++ b/platform/msmtitanium/include/platform/irqs.h
@@ -44,14 +44,14 @@
#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 257)
-#define USB30_EE1_IRQ (GIC_SPI_START + 134)
+#define USB30_EE1_IRQ (GIC_SPI_START + 140)
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
#define USB1_HS_IRQ (GIC_SPI_START + 134)
#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
/* Retrofit universal macro names */
-#define INT_USB_HS USB1_HS_IRQ
+#define INT_USB_HS USB30_EE1_IRQ
#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 190)
diff --git a/platform/msmtitanium/msmtitanium-clock.c b/platform/msmtitanium/msmtitanium-clock.c
old mode 100644
new mode 100755
index ee831b2..ff1e313
--- a/platform/msmtitanium/msmtitanium-clock.c
+++ b/platform/msmtitanium/msmtitanium-clock.c
@@ -40,6 +40,8 @@
#define cxo_source_val 0
#define gpll0_source_val 1
#define gpll4_source_val 2
+#define gpll6_source_val 1
+#define gpll0_out_main_div2_source_val 4
#define cxo_mm_source_val 0
#define gpll0_mm_source_val 6
#define gpll6_mm_source_val 3
@@ -48,6 +50,12 @@
/* Clock Operations */
+
+static struct clk_ops clk_ops_reset =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
static struct clk_ops clk_ops_branch =
{
.enable = clock_lib2_branch_clk_enable,
@@ -112,6 +120,21 @@
},
};
+static struct pll_vote_clk gpll0_out_main_div2_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 400000000,
+ .dbg_name = "gpll0_out_main_div2_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
static struct pll_vote_clk gpll4_clk_src =
{
.en_reg = (void *) APCS_GPLL_ENA_VOTE,
@@ -127,17 +150,32 @@
},
};
+static struct pll_vote_clk gpll6_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(7),
+ .status_reg = (void *) GPLL6_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1080000000,
+ .dbg_name = "gpll6_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
/* SDCC Clocks */
static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] =
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
- F( 20000000, gpll0, 10, 1, 4),
- F( 25000000, gpll0, 16, 1, 2),
+ F( 20000000, gpll0_out_main_div2, 5, 1, 2),
+ F( 25000000, gpll0_out_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F(100000000, gpll0, 8, 0, 0),
F(177770000, gpll0, 4.5, 0, 0),
- F(200000000, gpll0, 4, 0, 0),
+ F(192000000, gpll4, 6, 0, 0),
F(384000000, gpll4, 3, 0, 0),
F_END
};
@@ -186,12 +224,12 @@
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
- F( 20000000, gpll0, 10, 1, 4),
- F( 25000000, gpll0, 16, 1, 2),
+ F( 20000000, gpll0_out_main_div2, 5, 1, 2),
+ F( 25000000, gpll0_out_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F(100000000, gpll0, 8, 0, 0),
F(177770000, gpll0, 4.5, 0, 0),
- F(200000000, gpll0, 4, 0, 0),
+ F(192000000, gpll4, 6, 0, 0),
F_END
};
@@ -238,10 +276,10 @@
/* UART Clocks */
static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] =
{
- F( 3686400, gpll0, 1, 72, 15625),
- F( 7372800, gpll0, 1, 144, 15625),
- F(14745600, gpll0, 1, 288, 15625),
- F(16000000, gpll0, 10, 1, 5),
+ F( 3686400, gpll0_out_main_div2, 1, 144, 15625),
+ F( 7372800, gpll0_out_main_div2, 1, 288, 15625),
+ F(14745600, gpll0_out_main_div2, 1, 576, 15625),
+ F(16000000, gpll0_out_main_div2, 5, 1, 5),
F(19200000, cxo, 1, 0, 0),
F(24000000, gpll0, 1, 3, 100),
F(25000000, gpll0, 16, 1, 2),
@@ -253,9 +291,39 @@
F(56000000, gpll0, 1, 7, 100),
F(58982400, gpll0, 1,1152, 15625),
F(60000000, gpll0, 1, 3, 40),
+ F(64000000, gpll0, 12, 1, 2),
F_END
};
+static struct rcg_clk blsp1_uart1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART1_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART1_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART1_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart1_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR,
+ .parent = &blsp1_uart1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct rcg_clk blsp1_uart2_apps_clk_src =
{
.cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
@@ -297,50 +365,117 @@
};
/* USB Clocks */
-static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+static struct branch_clk gcc_pc_noc_usb30_axi_clk =
{
- F(100000000, gpll0, 10, 0, 0),
- F(133330000, gpll0, 6, 0, 0),
+ .cbcr_reg = (uint32_t *) PC_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_pc_noc_usb3_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_phy_cfg_ahb_clk = {
+ .cbcr_reg = (uint32_t *) USB_PHY_CFG_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_phy_cfg_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
+{
+ F(100000000, gpll0, 8, 0, 0),
+ F(133330000, gpll0, 6, 0, 0),
F_END
};
-static struct rcg_clk usb_hs_system_clk_src =
-{
- .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
- .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+static struct rcg_clk usb30_master_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) USB30_MASTER_M,
+ .n_reg = (uint32_t *) USB30_MASTER_N,
+ .d_reg = (uint32_t *) USB30_MASTER_D,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "usb_hs_system_clk",
+ .dbg_name = "usb30_master_clk_src",
.ops = &clk_ops_rcg,
},
};
-static struct branch_clk gcc_usb_hs_system_clk =
+static struct branch_clk gcc_usb30_master_clk =
{
- .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
- .parent = &usb_hs_system_clk_src.c,
+ .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR,
+ .bcr_reg = (uint32_t *) USB_30_BCR,
+ .parent = &usb30_master_clk_src.c,
.c = {
- .dbg_name = "gcc_usb_hs_system_clk",
+ .dbg_name = "gcc_usb30_master_clk",
.ops = &clk_ops_branch,
},
};
-static struct branch_clk gcc_usb_hs_ahb_clk =
-{
- .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+
+static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) USB3PHY_PHY_BCR,
+ .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
.has_sibling = 1,
+ .halt_check = 0,
.c = {
- .dbg_name = "gcc_usb_hs_ahb_clk",
+ .dbg_name = "usb30_pipe_clk",
.ops = &clk_ops_branch,
},
};
+static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = {
+ F( 19200000, cxo, 0, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_aux_clk_src = {
+ .cmd_reg = (uint32_t *) USB3_AUX_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB3_AUX_CFG_RCGR,
+ .m_reg = (uint32_t *) USB3_AUX_M,
+ .n_reg = (uint32_t *) USB3_AUX_N,
+ .d_reg = (uint32_t *) USB3_AUX_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_aux_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_aux_clk_src",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_usb30_aux_clk = {
+ .cbcr_reg = (uint32_t *) USB3_AUX_CBCR,
+ .parent = &usb30_aux_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb30_aux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t) USB3_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_reset,
+ },
+};
+
static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
F(160000000, gpll0, 5, 0, 0),
F_END
@@ -370,6 +505,54 @@
},
};
+static struct reset_clk gcc_usb2a_phy_sleep_clk = {
+ .bcr_reg = (uint32_t) GCC_QUSB2_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb2b_phy_sleep_clk",
+ .ops = &clk_ops_reset,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+ F( 19200000, cxo, 0, 0, 0),
+ F( 60000000, gpll6, 6, 1, 3),
+ F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+ .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_mock_utmi_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+ .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
static struct vote_clk gcc_ce1_ahb_clk = {
.cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR,
.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
@@ -401,11 +584,21 @@
CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+ CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c),
+
CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
- CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
- CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+ CLK_LOOKUP("usb30_iface_clk", gcc_pc_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
+ CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c),
+ CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+ CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
+ CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
+ CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
diff --git a/platform/msmtitanium/platform.c b/platform/msmtitanium/platform.c
index 2168570..83d0b3b 100755
--- a/platform/msmtitanium/platform.c
+++ b/platform/msmtitanium/platform.c
@@ -66,6 +66,7 @@
{ APPS_SS_BASE, APPS_SS_BASE, APPS_SS_SIZE, IOMAP_MEMORY},
{ MSM_SHARED_IMEM_BASE, MSM_SHARED_IMEM_BASE, 1, COMMON_MEMORY},
{ SCRATCH_ADDR, SCRATCH_ADDR, 512, SCRATCH_MEMORY},
+ { RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF_SZ, IOMAP_MEMORY},
};
void platform_early_init(void)
@@ -168,3 +169,9 @@
else
return MSM_SHARED_BASE;
}
+
+uint32_t platform_get_qmp_rev()
+{
+ return readl(USB3_PHY_REVISION_ID3) << 24 | readl(USB3_PHY_REVISION_ID2) << 16 |
+ readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
+}
diff --git a/project/msm8952.mk b/project/msm8952.mk
index bb2ef5d..f0896ec 100644
--- a/project/msm8952.mk
+++ b/project/msm8952.mk
@@ -100,6 +100,9 @@
CFLAGS += -Werror
+#enable user force reset feature
+DEFINES += USER_FORCE_RESET_SUPPORT=1
+
DEFINES += USE_TARGET_HS200_DELAY=1
#enable battery voltage check
diff --git a/project/msmtitanium.mk b/project/msmtitanium.mk
index d1449a5..6cc2ada 100755
--- a/project/msmtitanium.mk
+++ b/project/msmtitanium.mk
@@ -67,6 +67,11 @@
CFLAGS += -Werror
+# Reset USB clock from target code
+DEFINES += USB_RESET_FROM_CLK=1
+
+DEFINES += USE_TARGET_QMP_SETTINGS=1
+
DEFINES += USE_TARGET_HS200_DELAY=1
#Enable the external reboot functions
diff --git a/target/msm8952/oem_panel.c b/target/msm8952/oem_panel.c
index 60ade48..d045a22 100755
--- a/target/msm8952/oem_panel.c
+++ b/target/msm8952/oem_panel.c
@@ -59,6 +59,7 @@
#include "include/panel_r69006_1080p_cmd.h"
#include "include/panel_r69006_1080p_video.h"
#include "include/panel_hx8394f_720p_video.h"
+#include "include/panel_truly_720p_video.h"
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -78,6 +79,7 @@
R69006_1080P_CMD_PANEL,
R69006_1080P_VIDEO_PANEL,
HX8394F_720P_VIDEO_PANEL,
+ TRULY_720P_VIDEO_PANEL,
UNKNOWN_PANEL
};
@@ -103,7 +105,8 @@
{"byd_1200p_video", BYD_1200P_VIDEO_PANEL},
{"r69006_1080p_cmd",R69006_1080P_CMD_PANEL},
{"r69006_1080p_video",R69006_1080P_VIDEO_PANEL},
- {"hx8394f_720p_video", HX8394F_720P_VIDEO_PANEL}
+ {"hx8394f_720p_video", HX8394F_720P_VIDEO_PANEL},
+ {"truly_720p_video", TRULY_720P_VIDEO_PANEL}
};
static uint32_t panel_id;
@@ -589,6 +592,33 @@
pinfo->mipi.signature = BYD_1200P_VIDEO_SIGNATURE;
phy_db->regulator_mode = DSI_PHY_REGULATOR_LDO_MODE;
break;
+ case TRULY_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &truly_720p_video_panel_data;
+ panelstruct->paneldata->panel_with_enable_gpio = 1;
+ panelstruct->panelres = &truly_720p_video_panel_res;
+ panelstruct->color = &truly_720p_video_color;
+ panelstruct->videopanel = &truly_720p_video_video_panel;
+ panelstruct->commandpanel = &truly_720p_video_command_panel;
+ panelstruct->state = &truly_720p_video_state;
+ panelstruct->laneconfig = &truly_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &truly_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &truly_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &truly_720p_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = truly_720p_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = TRULY_720P_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = truly_720p_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = TRULY_720P_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ truly_720p_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = TRULY_720P_VIDEO_SIGNATURE;
+ pinfo->mipi.tx_eot_append = true;
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index f202509..7d3c0d6 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -310,6 +310,14 @@
pll_data = pinfo->mipi.dsi_pll_config;
pll_data->vco_delay = VCO_DELAY_USEC;
+ /* SSC parameters */
+ if (platform_is_msm8937()) {
+ pll_data->ssc_en = true;
+ pll_data->is_center_spread = false;
+ pll_data->ssc_freq = 30000;
+ pll_data->ssc_ppm = 5000;
+ }
+
if (enable) {
mdp_gdsc_ctrl(enable);
mdss_bus_clocks_enable();
diff --git a/target/msmtitanium/init.c b/target/msmtitanium/init.c
index 8a80a8c..06d63ce 100755
--- a/target/msmtitanium/init.c
+++ b/target/msmtitanium/init.c
@@ -52,6 +52,12 @@
#include <spmi.h>
#include <sdhci_msm.h>
#include <clock.h>
+#include <boot_device.h>
+#include <secapp_loader.h>
+#include <rpmb.h>
+#include <smem.h>
+#include <qmp_phy.h>
+#include <qusb2_phy.h>
#if LONG_PRESS_POWER_ON
#include <shutdown_detect.h>
@@ -62,8 +68,18 @@
#define TLMM_VOL_UP_BTN_GPIO 85
#define FASTBOOT_MODE 0x77665500
+#define RECOVERY_MODE 0x77665502
#define PON_SOFT_RB_SPARE 0x88F
+#define CE1_INSTANCE 1
+#define CE_EE 1
+#define CE_FIFO_SIZE 64
+#define CE_READ_PIPE 3
+#define CE_WRITE_PIPE 2
+#define CE_READ_PIPE_LOCK_GRP 0
+#define CE_WRITE_PIPE_LOCK_GRP 0
+#define CE_ARRAY_SIZE 20
+
struct mmc_device *dev;
static uint32_t mmc_pwrctl_base[] =
@@ -78,7 +94,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(1, 0, BLSP1_UART1_BASE);
+ uart_dm_init(1, 0, BLSP1_UART0_BASE);
#endif
}
@@ -160,7 +176,7 @@
status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
/* Active high signal. */
- return status;
+ return !status;
}
/* Return 1 if vol_down pressed */
@@ -170,6 +186,15 @@
return pm8x41_resin_status();
}
+uint32_t target_is_pwrkey_pon_reason()
+{
+ uint8_t pon_reason = pm8950_get_pon_reason();
+ if (pm8x41_get_is_cold_boot() && ((pon_reason == KPDPWR_N) || (pon_reason == (KPDPWR_N|PON1))))
+ return 1;
+ else
+ return 0;
+}
+
static void target_keystatus()
{
keys_init();
@@ -183,6 +208,11 @@
void target_init(void)
{
+#if VERIFIED_BOOT
+#if !VBOOT_MOTA
+ int ret = 0;
+#endif
+#endif
dprintf(INFO, "target_init()\n");
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
@@ -199,6 +229,53 @@
#if LONG_PRESS_POWER_ON
shutdown_detect();
#endif
+
+
+ if (target_use_signed_kernel())
+ target_crypto_init_params();
+
+#if VERIFIED_BOOT
+#if !VBOOT_MOTA
+ clock_ce_enable(CE1_INSTANCE);
+
+ /* Initialize Qseecom */
+ ret = qseecom_init();
+
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed to initialize qseecom, error: %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Start Qseecom */
+ ret = qseecom_tz_init();
+
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed to start qseecom, error: %d\n", ret);
+ ASSERT(0);
+ }
+
+ if (rpmb_init() < 0)
+ {
+ dprintf(CRITICAL, "RPMB init failed\n");
+ ASSERT(0);
+ }
+
+ /*
+ * Load the sec app for first time
+ */
+ if (load_sec_app() < 0)
+ {
+ dprintf(CRITICAL, "Failed to load App for verified\n");
+ ASSERT(0);
+ }
+#endif
+#endif
+
+#if SMD_SUPPORT
+ rpm_smd_init();
+#endif
}
void target_serialno(unsigned char *buf)
@@ -221,6 +298,7 @@
/* This is already filled as part of board.c */
}
+/* Detect the modem type */
void target_baseband_detect(struct board_data *board)
{
uint32_t platform;
@@ -231,12 +309,19 @@
case MSMTITANIUM:
board->baseband = BASEBAND_MSM;
break;
+ case APQTITANIUM:
+ board->baseband = BASEBAND_APQ;
+ break;
default:
dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
ASSERT(0);
};
}
+unsigned target_baseband()
+{
+ return board_baseband();
+}
int set_download_mode(enum dload_mode mode)
{
int ret = 0;
@@ -272,6 +357,42 @@
return 0;
}
+void target_uninit(void)
+{
+ mmc_put_card_to_sleep(dev);
+ sdhci_mode_disable(&dev->host);
+ if (crypto_initialized())
+ crypto_eng_cleanup();
+
+ if (target_is_ssd_enabled())
+ clock_ce_disable(CE1_INSTANCE);
+
+#if VERIFIED_BOOT
+#if !VBOOT_MOTA
+ if (is_sec_app_loaded())
+ {
+ if (send_milestone_call_to_tz() < 0)
+ {
+ dprintf(CRITICAL, "Failed to unload App for rpmb\n");
+ ASSERT(0);
+ }
+ }
+
+ if (rpmb_uninit() < 0)
+ {
+ dprintf(CRITICAL, "RPMB uninit failed\n");
+ ASSERT(0);
+ }
+
+ clock_ce_disable(CE1_INSTANCE);
+#endif
+#endif
+
+#if SMD_SUPPORT
+ rpm_smd_uninit();
+#endif
+}
+
/* UTMI MUX configuration to connect PHY to SNPS controller:
* Configure primary HS phy mux to use UTMI interface
* (connected to usb30 controller).
@@ -294,16 +415,26 @@
}
}
+void target_usb_phy_reset()
+{
+
+ usb30_qmp_phy_reset();
+ qusb2_phy_reset();
+}
+
/* Initialize target specific USB handlers */
target_usb_iface_t* target_usb30_init()
{
target_usb_iface_t *t_usb_iface;
- t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
+ t_usb_iface = (target_usb_iface_t *) calloc(1, sizeof(target_usb_iface_t));
ASSERT(t_usb_iface);
- t_usb_iface->mux_config = target_usb_phy_mux_configure;
- //t_usb_iface->clock_init = clock_usb30_init;
+ t_usb_iface->mux_config = NULL;
+ t_usb_iface->phy_init = usb30_qmp_phy_init;
+ t_usb_iface->phy_reset = target_usb_phy_reset;
+ t_usb_iface->clock_init = clock_usb30_init;
+ t_usb_iface->vbus_override = 1;
return t_usb_iface;
}
@@ -314,14 +445,200 @@
return "dwc";
}
+/* Do any target specific intialization needed before entering fastboot mode */
+void target_fastboot_init(void)
+{
+ if (target_is_ssd_enabled()) {
+ clock_ce_enable(CE1_INSTANCE);
+ target_load_ssd_keystore();
+ }
+}
+
+void target_load_ssd_keystore(void)
+{
+ uint64_t ptn;
+ int index;
+ uint64_t size;
+ uint32_t *buffer = NULL;
+
+ if (!target_is_ssd_enabled())
+ return;
+
+ index = partition_get_index("ssd");
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0){
+ dprintf(CRITICAL, "Error: ssd partition not found\n");
+ return;
+ }
+
+ size = partition_get_size(index);
+ if (size == 0) {
+ dprintf(CRITICAL, "Error: invalid ssd partition size\n");
+ return;
+ }
+
+ buffer = memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
+ if (!buffer) {
+ dprintf(CRITICAL, "Error: allocating memory for ssd buffer\n");
+ return;
+ }
+
+ if (mmc_read(ptn, buffer, size)) {
+ dprintf(CRITICAL, "Error: cannot read data\n");
+ free(buffer);
+ return;
+ }
+
+ clock_ce_enable(CE1_INSTANCE);
+ scm_protect_keystore(buffer, size);
+ clock_ce_disable(CE1_INSTANCE);
+ free(buffer);
+}
crypto_engine_type board_ce_type(void)
{
return CRYPTO_ENGINE_TYPE_HW;
}
+/* Set up params for h/w CE. */
+void target_crypto_init_params()
+{
+ struct crypto_init_params ce_params;
+
+ /* Set up base addresses and instance. */
+ ce_params.crypto_instance = CE1_INSTANCE;
+ ce_params.crypto_base = MSM_CE1_BASE;
+ ce_params.bam_base = MSM_CE1_BAM_BASE;
+
+ /* Set up BAM config. */
+ ce_params.bam_ee = CE_EE;
+ ce_params.pipes.read_pipe = CE_READ_PIPE;
+ ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
+
+ /* Assign buffer sizes. */
+ ce_params.num_ce = CE_ARRAY_SIZE;
+ ce_params.read_fifo_size = CE_FIFO_SIZE;
+ ce_params.write_fifo_size = CE_FIFO_SIZE;
+
+ /* BAM is initialized by TZ for this platform.
+ * Do not do it again as the initialization address space
+ * is locked.
+ */
+ ce_params.do_bam_init = 0;
+
+ crypto_init_params(&ce_params);
+}
void pmic_reset_configure(uint8_t reset_type)
{
pm8x41_reset_configure(reset_type);
}
+
+uint32_t target_get_pmic()
+{
+ return PMIC_IS_PMI8950;
+}
+
+struct qmp_reg qmp_settings[] =
+{
+ {0x804, 0x01}, /*USB3PHY_PCIE_USB3_PCS_POWER_DOWN_CONTROL */
+ {0xAC, 0x14}, /* QSERDES_COM_SYSCLK_EN_SEL */
+ {0x34, 0x08}, /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
+ {0x174, 0x30}, /* QSERDES_COM_CLK_SELECT */
+ {0x3C, 0x06}, /* QSERDES_COM_SYS_CLK_CTRL */
+ {0xB4, 0x00}, /* QSERDES_COM_RESETSM_CNTRL */
+ {0xB8, 0x08}, /* QSERDES_COM_RESETSM_CNTRL2 */
+ {0x194, 0x06}, /* QSERDES_COM_CMN_CONFIG */
+ {0x19c, 0x01}, /* QSERDES_COM_SVS_MODE_CLK_SEL */
+ {0x178, 0x00}, /* QSERDES_COM_HSCLK_SEL */
+ {0xd0, 0x82}, /* QSERDES_COM_DEC_START_MODE0 */
+ {0xdc, 0x55}, /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
+ {0xe0, 0x55}, /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
+ {0xe4, 0x03}, /* QSERDES_COM_DIV_FRAC_START3_MODE0 */
+ {0x78, 0x0b}, /* QSERDES_COM_CP_CTRL_MODE0 */
+ {0x84, 0x16}, /* QSERDES_COM_PLL_RCTRL_MODE0 */
+ {0x90, 0x28}, /* QSERDES_COM_PLL_CCTRL_MODE0 */
+ {0x108, 0x80}, /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
+ {0x10C, 0x00}, /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
+ {0x184, 0x0A}, /* QSERDES_COM_CORECLK_DIV */
+ {0x4c, 0x15}, /* QSERDES_COM_LOCK_CMP1_MODE0 */
+ {0x50, 0x34}, /* QSERDES_COM_LOCK_CMP2_MODE0 */
+ {0x54, 0x00}, /* QSERDES_COM_LOCK_CMP3_MODE0 */
+ {0xC8, 0x00}, /* QSERDES_COM_LOCK_CMP_EN */
+ {0x18c, 0x00}, /* QSERDES_COM_CORE_CLK_EN */
+ {0xcc, 0x00}, /* QSERDES_COM_LOCK_CMP_CFG */
+ {0x128, 0x00}, /* QSERDES_COM_VCO_TUNE_MAP */
+ {0x0C, 0x0A}, /* QSERDES_COM_BG_TIMER */
+ {0x10, 0x01}, /* QSERDES_COM_SSC_EN_CENTER */
+ {0x1c, 0x31}, /* QSERDES_COM_SSC_PER1 */
+ {0x20, 0x01}, /* QSERDES_COM_SSC_PER2 */
+ {0x14, 0x00}, /* QSERDES_COM_SSC_ADJ_PER1 */
+ {0x18, 0x00}, /* QSERDES_COM_SSC_ADJ_PER2 */
+ {0x24, 0xde}, /* QSERDES_COM_SSC_STEP_SIZE1 */
+ {0x28, 0x07}, /* QSERDES_COM_SSC_STEP_SIZE2 */
+ {0x48, 0x0F}, /* USB3PHY_QSERDES_COM_PLL_IVCO */
+ {0x70, 0x0F}, /* USB3PHY_QSERDES_COM_BG_TRIM */
+ {0x100, 0x80}, /* QSERDES_COM_INTEGLOOP_INITVAL */
+
+ /* Rx Settings */
+ {0x440, 0x0b}, /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
+ {0x4d8, 0x02}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
+ {0x4dc, 0x6c}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
+ {0x4e0, 0xbb}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
+ {0x508, 0x77}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
+ {0x50c, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */
+ {0x514, 0x03}, /* QSERDES_RX_SIGDET_CNTRL */
+ {0x51c, 0x16}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+ {0x448, 0x75}, /* QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE */
+ {0x450, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW */
+ {0x454, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH */
+ {0x40C, 0x0a}, /* QSERDES_RX_UCDR_FO_GAIN */
+ {0x41C, 0x06}, /* QSERDES_RX_UCDR_SO_GAIN */
+ {0x510, 0x00}, /*QSERDES_RX_SIGDET_ENABLES */
+
+ /* Tx settings */
+ {0x268, 0x45}, /* QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN */
+ {0x2ac, 0x12}, /* QSERDES_TX_RCV_DETECT_LVL_2 */
+ {0x294, 0x06}, /* QSERDES_TX_LANE_MODE */
+ {0x254, 0x00}, /* QSERDES_TX_RES_CODE_LANE_OFFSET */
+
+ /* FLL settings */
+ {0x8c8, 0x83}, /* PCIE_USB3_PCS_FLL_CNTRL2 */
+ {0x8c4, 0x02}, /* PCIE_USB3_PCS_FLL_CNTRL1 */
+ {0x8cc, 0x09}, /* PCIE_USB3_PCS_FLL_CNT_VAL_L */
+ {0x8D0, 0xA2}, /* PCIE_USB3_PCS_FLL_CNT_VAL_H_TOL */
+ {0x8D4, 0x85}, /* PCIE_USB3_PCS_FLL_MAN_CODE */
+
+ /* PCS Settings */
+ {0x880, 0xD1}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG1 */
+ {0x884, 0x1F}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG2 */
+ {0x888, 0x47}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG3 */
+ {0x80C, 0x9F}, /* PCIE_USB3_PCS_TXMGN_V0 */
+ {0x824, 0x17}, /* PCIE_USB3_PCS_TXDEEMPH_M6DB_V0 */
+ {0x828, 0x0F}, /* PCIE_USB3_PCS_TXDEEMPH_M3P5DB_V0 */
+ {0x8B8, 0x75}, /* PCIE_USB3_PCS_RXEQTRAINING_WAIT_TIME */
+ {0x8BC, 0x13}, /* PCIE_USB3_PCS_RXEQTRAINING_RUN_TIME */
+ {0x8B0, 0x86}, /* PCIE_USB3_PCS_LFPS_TX_ECSTART_EQTLOCK */
+ {0x8A0, 0x04}, /* PCIE_USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
+ {0x88C, 0x44}, /* PCIE_USB3_PCS_TSYNC_RSYNC_TIME */
+ {0x870, 0xE7}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_L */
+ {0x874, 0x03}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_H */
+ {0x878, 0x40}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_L */
+ {0x87c, 0x00}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_H */
+ {0x9D8, 0x88}, /* PCIE_USB3_PCS_RX_SIGDET_LVL */
+ {0x808, 0x03}, /* PCIE_USB3_PCS_START_CONTROL */
+ {0x800, 0x00}, /* PCIE_USB3_PCS_SW_RESET */
+};
+
+struct qmp_reg *target_get_qmp_settings()
+{
+ return qmp_settings;
+}
+
+int target_get_qmp_regsize()
+{
+ return ARRAY_SIZE(qmp_settings);
+}