platform/target: thulium: Fix for bring up
- Update the freq plan for sdcc & usb
- Fix the gpio number for vol+ key
- Enable boot KPI logging
- Fix BLSP instance for UART
- Remove rpm message ram mapping as cacheable memory
Change-Id: I65a37bd2aa613dfa7db23c9c3b991195ae907f97
diff --git a/platform/thulium/platform.c b/platform/thulium/platform.c
index 315d05e..4b70f63 100644
--- a/platform/thulium/platform.c
+++ b/platform/thulium/platform.c
@@ -44,9 +44,6 @@
#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE)
-/* RPM MSG RAM memory - cacheable, write through */
-#define MSG_RAM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
- MMU_MEMORY_AP_READ_WRITE)
/* Peripherals - non-shared device */
#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
@@ -62,7 +59,6 @@
{ KERNEL_ADDR, KERNEL_ADDR, KERNEL_SIZE, SCRATCH_MEMORY},
{ SCRATCH_ADDR, SCRATCH_ADDR, SCRATCH_SIZE, SCRATCH_MEMORY},
{ MSM_SHARED_BASE, MSM_SHARED_BASE, MSM_SHARED_SIZE, SCRATCH_MEMORY},
- { RPM_SS_MSG_RAM_START_ADDRESS_BASE, RPM_SS_MSG_RAM_START_ADDRESS_BASE, RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE, MSG_RAM_MEMORY},
};
void platform_early_init(void)
@@ -134,3 +130,8 @@
{
return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
}
+
+addr_t get_bs_info_addr()
+{
+ return BS_INFO_ADDR;
+}