commit 9b794580a0e79c3a254f5b4e1f438d7469c9605b
author Ajay Dudani <adudani@codeaurora.org> Tue Oct 19 19:56:17 2010 -0700
committer Ajay Dudani <adudani@codeaurora.org> Tue Oct 19 19:56:17 2010 -0700
tree 0a64317be244d41f1a78657e57a53a99ceeaf846
parent 4cc2973db72eb8ccf6e843309a9481586c8e004b

[msm7630] Bug fix to not overwrite r3 value when checking for halcyon v1

We check for halcyon v1 we use r3; same register is used later to pass
on cache settings.  Use r4 instead when checking for processor version
so we dont overwrite the cache setting value in r3.

Change-Id: I22430f0bb766b49ee0431f0a6b7fe413fc23ca56

platform/msm7x30/arch_init.S

diff --git a/platform/msm7x30/arch_init.S b/platform/msm7x30/arch_init.S
index e0a0053..8093152 100644
--- a/platform/msm7x30/arch_init.S
+++ b/platform/msm7x30/arch_init.S
@@ -194,8 +194,8 @@
         // (Raptor V2 and earlier, or Halcyon V1)
         MRC    p15, 0, r1, c0, c0, 0      //; MIDR
         BIC    r2, r1, #0xf0              //; check for Halcyon V1
-        LDR    r3, =0x511f0000
-        CMP    r2, r3
+        LDR    r4, =0x511f0000
+        CMP    r2, r4
         BNE    PVR2F1
 
 DPRC: