Merge "pm8x41: Choose the right SPMI register offsets for the target"
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S
index 974fb9b..e67dc65 100644
--- a/arch/arm/cache-ops.S
+++ b/arch/arm/cache-ops.S
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -338,7 +338,7 @@
bhs 0b
mov r0, #0
- mcr p15, 0, r0, c7, c10, 4 // data sync barrier (formerly drain write buffer)
+ dsb
bx lr
@@ -351,7 +351,7 @@
bhs 0b
mov r0, #0
- mcr p15, 0, r0, c7, c10, 4 // data sync barrier (formerly drain write buffer)
+ dsb
bx lr
@@ -364,8 +364,7 @@
subs r1, r1, #CACHE_LINE
bhs 0b
mov r0, #0
- /* data sync barrier (formerly drain write buffer*/
- mcr p15, 0, r0, c7, c10, 4
+ dsb
bx lr
/* void arch_sync_cache_range(addr_t start, size_t len); */
diff --git a/platform/msm8610/include/platform/iomap.h b/platform/msm8610/include/platform/iomap.h
index b9b28f9..ce0eb26 100644
--- a/platform/msm8610/include/platform/iomap.h
+++ b/platform/msm8610/include/platform/iomap.h
@@ -195,7 +195,7 @@
#define INT_CTRL 0x10C
#define CMD_MODE_DMA_SW_TRIGGER 0x08C
-#define EOT_PACKET_CTRL 0x0CC
+#define EOT_PACKET_CTRL 0x0C8
#define MISR_CMD_CTRL 0x09C
#define MISR_VIDEO_CTRL 0x0A0
#define VIDEO_MODE_CTRL 0x00C
diff --git a/platform/msm_shared/image_verify.c b/platform/msm_shared/image_verify.c
index cf1253f..edca3bc 100644
--- a/platform/msm_shared/image_verify.c
+++ b/platform/msm_shared/image_verify.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011,2013 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011,2013-2014 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -99,6 +99,23 @@
goto cleanup;
}
+ /*
+ * Calculate hash of image and save calculated hash on TZ.
+ */
+ hash_size =
+ (hash_type == CRYPTO_AUTH_ALG_SHA256) ? SHA256_SIZE : SHA1_SIZE;
+ hash_find(image_ptr, image_size, (unsigned char *)&digest, hash_type);
+#ifdef TZ_SAVE_KERNEL_HASH
+ if (hash_type == CRYPTO_AUTH_ALG_SHA256) {
+ save_kernel_hash_cmd(digest);
+ dprintf(INFO, "Image hash saved.\n");
+ } else
+ dprintf(INFO, "image_verify: hash is not SHA-256.\n");
+#endif
+
+ /*
+ * Decrypt the pre-calculated expected image hash.
+ */
ret = image_decrypt_signature(signature_ptr, plain_text);
if (ret == -1) {
dprintf(CRITICAL, "ERROR: Image Invalid! Decryption failed!\n");
@@ -106,17 +123,8 @@
}
/*
- * Calculate hash of image for comparison
+ * Compare the expected hash with the calculated hash.
*/
- hash_size =
- (hash_type == CRYPTO_AUTH_ALG_SHA256) ? SHA256_SIZE : SHA1_SIZE;
- hash_find(image_ptr, image_size, (unsigned char *)&digest, hash_type);
-#ifdef TZ_SAVE_KERNEL_HASH
- if (hash_type == CRYPTO_AUTH_ALG_SHA256)
- save_kernel_hash_cmd(digest);
- else
- dprintf(INFO, "image_verify: hash is not SHA-256.\n");
-#endif
if (memcmp(plain_text, digest, hash_size) != 0) {
dprintf(CRITICAL,
"ERROR: Image Invalid! Please use another image!\n");
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 50e1cd5..73294f5 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -515,8 +515,8 @@
int mdp_dsi_video_on(void)
{
int ret = NO_ERROR;
- writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(0x32090, MDP_CTL_1_BASE + CTL_FLUSH);
+ writel(0x22048, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(0x24090, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return ret;
}
@@ -553,8 +553,8 @@
int mdp_dma_on(void)
{
- writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(0x32090, MDP_CTL_1_BASE + CTL_FLUSH);
+ writel(0x22048, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(0x24090, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_CTL_0_BASE + CTL_START);
return NO_ERROR;
}
@@ -566,7 +566,7 @@
int mdp_edp_on(void)
{
- writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(0x22048, MDP_CTL_0_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return NO_ERROR;
}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index d67061f..18bb1c4 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -1209,8 +1209,8 @@
ctl_base + CTRL);
writel(0x10000000, ctl_base + COMMAND_MODE_DMA_CTRL);
writel(0x10000000, ctl_base + MISR_CMD_CTRL);
+ writel(0x1, ctl_base + EOT_PACKET_CTRL);
#endif
-
return 0;
}
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index 74ec4ba..127505c 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -844,9 +844,15 @@
/* Run the clock @ 400 Mhz */
if (host->caps.hs400_support && mmc_card_supports_hs400_mode(card))
{
- clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
/* Save the timing value, before changing the clock */
MMC_SAVE_TIMING(host, MMC_HS400_TIMING);
+ /*
+ * Set the MCI_CLK divider before changing the sdcc core
+ * core clk to ensure card receives no more than 200 MHZ
+ * clock frequency
+ */
+ sdhci_msm_set_mci_clk(host);
+ clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
}
else
{
@@ -993,6 +999,10 @@
/* Save the timing value, before changing the clock */
MMC_SAVE_TIMING(host, MMC_HS400_TIMING);
sdhci_set_uhs_mode(host, SDHCI_SDR104_MODE);
+ /*
+ * Enable HS400 mode
+ */
+ sdhci_msm_set_mci_clk(host);
/* 7. Execute Tuning for hs400 mode */
if ((mmc_ret = sdhci_msm_execute_tuning(host, width)))
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index 29eeaee..d9c9ff2 100644
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -275,32 +275,31 @@
static uint32_t mmc_zero_out(struct mmc_device* dev, uint32_t blk_addr, uint32_t num_blks)
{
uint32_t *out;
- uint32_t block_size;
- int i;
+ uint32_t block_size = mmc_get_device_blocksize();
+ uint32_t erase_size = (block_size * num_blks);
+ uint32_t scratch_size = target_get_max_flash_size();
dprintf(INFO, "erasing 0x%x:0x%x\n", blk_addr, num_blks);
- block_size = mmc_get_device_blocksize();
- /* Assume there are at least block_size bytes available in the heap */
- out = memalign(CACHE_LINE, ROUNDUP(block_size, CACHE_LINE));
-
- if (!out)
+ if (erase_size <= scratch_size)
{
- dprintf(CRITICAL, "Error allocating memory\n");
+ /* Use scratch address if the unaligned blocks */
+ out = (uint32_t *) target_get_scratch_address();
+ }
+ else
+ {
+ dprintf(CRITICAL, "Erase Fail: Erase size: %u is bigger than scratch region:%u\n", scratch_size);
return 1;
}
- memset((void *)out, 0, ROUNDUP(block_size, CACHE_LINE));
- for (i = 0; i < num_blks; i++)
+ memset((void *)out, 0, erase_size);
+
+ if (mmc_sdhci_write(dev, out, blk_addr, num_blks))
{
- if (mmc_sdhci_write(dev, out, blk_addr + i, 1))
- {
- dprintf(CRITICAL, "failed to erase the partition: %x\n", blk_addr);
- free(out);
- return 1;
- }
+ dprintf(CRITICAL, "failed to erase the partition: %x\n", blk_addr);
+ return 1;
}
- free(out);
+
return 0;
}
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 1efce5d..eeb47fc 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -264,13 +264,6 @@
REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG);
- /*
- * SDHC spec does not have matching UHS mode
- * So we use Vendor specific registers to enable
- * HS400 mode
- */
- sdhci_msm_set_mci_clk(host);
-
/* Run the clock back */
sdhci_clk_supply(host, clk_val);
}
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index 47db659..87daf47 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -141,6 +141,7 @@
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.hs400_support = 0;
if (!(dev = mmc_init(&config)))
{
@@ -446,17 +447,12 @@
uint8_t data_hdrv = 0;
uint32_t platform = board_platform_id();
- if (platform == MSM8510 || platform == MSM8512)
- data_hdrv = TLMM_CUR_VAL_6MA;
- else
- data_hdrv = TLMM_CUR_VAL_10MA;
-
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
{ SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_DATA_HDRV_CTL_OFF, data_hdrv, TLMM_HDRV_MASK },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
};
/* Pull configs for sdc pins */
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index 3dea314..9f081f7 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -229,6 +229,7 @@
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.hs400_support = 1;
if (!(dev = mmc_init(&config))) {
/* Trying Slot 2 next */