target: msm8996: improve DSI PLL's performance
To improve performance margin for DSI's PLL at cold
temperature case, the value of DSIPHY_PLL_PLL_ICPMSET
should be changed from 0x24 to 0x3f for DSI0 and DSI1.
Change-Id: I9d8353b0217b53877a80e6a1432eb0c4e3eb772c
Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
Signed-off-by: Sivasri Kumar Vanka <sivasri@codeaurora.org>
diff --git a/platform/msm_shared/mipi_dsi_autopll_thulium.c b/platform/msm_shared/mipi_dsi_autopll_thulium.c
index 4b2bfb0..e3c4497 100644
--- a/platform/msm_shared/mipi_dsi_autopll_thulium.c
+++ b/platform/msm_shared/mipi_dsi_autopll_thulium.c
@@ -71,8 +71,8 @@
pdb->in.pll_ip_trim = 4; /* 4, reg: 0x0404 */
pdb->in.pll_cpcset_cur = 1; /* 1, reg: 0x04f0, bit 0 - 2 */
pdb->in.pll_cpmset_cur = 1; /* 1, reg: 0x04f0, bit 3 - 5 */
- pdb->in.pll_icpmset = 4; /* 4, reg: 0x04fc, bit 3 - 5 */
- pdb->in.pll_icpcset = 4; /* 4, reg: 0x04fc, bit 0 - 2 */
+ pdb->in.pll_icpmset = 7; /* 7, reg: 0x04fc, bit 3 - 5 */
+ pdb->in.pll_icpcset = 7; /* 7, reg: 0x04fc, bit 0 - 2 */
pdb->in.pll_icpmset_p = 0; /* 0, reg: 0x04f4, bit 0 - 2 */
pdb->in.pll_icpmset_m = 0; /* 0, reg: 0x04f4, bit 3 - 5 */
pdb->in.pll_icpcset_p = 0; /* 0, reg: 0x04f8, bit 0 - 2 */