Merge "platform: msm8994: Remove MDP lut clock from 8994"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index c7522d6..119ec4e 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -98,6 +98,7 @@
#define RECOVERY_MODE 0x77665502
#define FASTBOOT_MODE 0x77665500
+#define ALARM_BOOT 0x77665503
/* make 4096 as default size to ensure EFS,EXT4's erasing */
#define DEFAULT_ERASE_SIZE 4096
@@ -119,6 +120,7 @@
#endif
static const char *usb_sn_cmdline = " androidboot.serialno=";
static const char *androidboot_mode = " androidboot.mode=";
+static const char *alarmboot_cmdline = " androidboot.alarmboot=true";
static const char *loglevel = " quiet";
static const char *battchg_pause = " androidboot.mode=charger";
static const char *auth_kernel = " androidboot.authorized_kernel=true";
@@ -141,6 +143,7 @@
static char ffbm_mode_string[FFBM_MODE_BUF_SIZE];
static bool boot_into_ffbm;
static char target_boot_params[64];
+static bool boot_reason_alarm;
/* Assuming unauthorized kernel image by default */
static int auth_kernel_img = 0;
@@ -252,6 +255,8 @@
cmdline_len += strlen(ffbm_mode_string);
/* reduce kernel console messages to speed-up boot */
cmdline_len += strlen(loglevel);
+ } else if (boot_reason_alarm) {
+ cmdline_len += strlen(alarmboot_cmdline);
} else if (device.charger_screen_enabled &&
target_pause_for_battery_charge()) {
pause_at_bootup = 1;
@@ -383,6 +388,10 @@
src = loglevel;
if (have_cmdline) --dst;
while ((*dst++ = *src++));
+ } else if (boot_reason_alarm) {
+ src = alarmboot_cmdline;
+ if (have_cmdline) --dst;
+ while ((*dst++ = *src++));
} else if (pause_at_bootup) {
src = battchg_pause;
if (have_cmdline) --dst;
@@ -1462,7 +1471,12 @@
if (memcmp(info->magic, DEVICE_MAGIC, DEVICE_MAGIC_SIZE))
{
memcpy(info->magic, DEVICE_MAGIC, DEVICE_MAGIC_SIZE);
+#if DEFAULT_UNLOCK
+ info->is_unlocked = 1;
+#else
info->is_unlocked = 0;
+#endif
+ info->is_verified = 0;
info->is_tampered = 0;
info->charger_screen_enabled = 0;
@@ -2669,6 +2683,8 @@
boot_into_recovery = 1;
} else if(reboot_mode == FASTBOOT_MODE) {
boot_into_fastboot = true;
+ } else if(reboot_mode == ALARM_BOOT) {
+ boot_reason_alarm = true;
}
normal_boot:
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index 38ba3b4..e2e497f 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -43,7 +43,10 @@
uint32_t width = pinfo->xres;
if (pinfo->mipi.dual_dsi)
- width = pinfo->xres / 2;
+ width /= 2;
+
+ if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio)
+ width /= pinfo->fbc.comp_ratio;
h_period = width + pinfo->lcdc.h_back_porch +
pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width +
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index dd77668..5a060c4 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -219,15 +219,14 @@
dsi_id_len = strlen(dsi_id);
panel_node_len = strlen(panel_node);
- if (slave_panel_node)
- slave_panel_node_len = strlen(slave_panel_node);
+ if (!slave_panel_node)
+ slave_panel_node = NO_PANEL_CONFIG;
+ slave_panel_node_len = strlen(slave_panel_node);
arg_size = prefix_string_len + dsi_id_len + panel_node_len +
LK_OVERRIDE_PANEL_LEN + 1;
- /* For dual pipe or split display */
- if (panel_mode)
- arg_size += DSI_1_STRING_LEN + slave_panel_node_len;
+ arg_size += DSI_1_STRING_LEN + slave_panel_node_len;
if (buf_size < arg_size) {
dprintf(CRITICAL, "display command line buffer is small\n");
@@ -247,18 +246,13 @@
strlcpy(pbuf, panel_node, buf_size);
- /* Return string for single dsi */
- if (!panel_mode)
- goto end;
-
pbuf += panel_node_len;
buf_size -= panel_node_len;
strlcpy(pbuf, DSI_1_STRING, buf_size);
pbuf += DSI_1_STRING_LEN;
buf_size -= DSI_1_STRING_LEN;
- if (slave_panel_node)
- strlcpy(pbuf, slave_panel_node, buf_size);
+ strlcpy(pbuf, slave_panel_node, buf_size);
}
end:
return ret;
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index 1a328f5..c21383e 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -178,4 +178,24 @@
char *bl_pmic_model;
};
+typedef struct fb_compression {
+ uint32_t enabled;
+ uint32_t comp_ratio;
+ uint32_t comp_mode;
+ uint32_t qerr_enable;
+ uint32_t cd_bias;
+ uint32_t pat_enable;
+ uint32_t vlc_enable;
+ uint32_t bflc_enable;
+
+ uint32_t line_x_budget;
+ uint32_t block_x_budget;
+ uint32_t block_budget;
+
+ uint32_t lossless_mode_thd;
+ uint32_t lossy_mode_thd;
+ uint32_t lossy_rgb_thd;
+ uint32_t lossy_mode_idx;
+};
+
#endif /*_PANEL_H_ */
diff --git a/dev/gcdb/display/include/panel_nt35521_wxga_video.h b/dev/gcdb/display/include/panel_nt35521_wxga_video.h
new file mode 100644
index 0000000..bdac711
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35521_wxga_video.h
@@ -0,0 +1,1033 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_NT35521_WXGA_VIDEO_H_
+#define _PANEL_NT35521_WXGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config nt35521_wxga_video_panel_data = {
+ "qcom,mdss_dsi_nt35521_wxga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35521_wxga_video_panel_res = {
+ 800, 1280, 44, 55, 11, 0, 14, 15, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35521_wxga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char nt35521_wxga_video_on_cmd0[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xFF, 0xAA, 0x55, 0xA5,
+ 0x80, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd1[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0x6F, 0x11, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd2[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xF7, 0x20, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd3[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd4[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xF7, 0xA0, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd5[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x19, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd6[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xF7, 0x12, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd7[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x08, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd8[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xFA, 0x40, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd9[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x11, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd10[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xF3, 0x01, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd11[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd12[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC8, 0x80, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd13[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x6C, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd14[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB6, 0x08, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd15[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x02, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd16[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB8, 0x08, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd17[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBB, 0x74, 0x44, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd18[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBC, 0x00, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd19[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xBD, 0x02, 0xB0, 0x0C,
+ 0x0A, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd20[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x01, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd21[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB0, 0x05, 0x05, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd22[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x05, 0x05, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd23[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBC, 0x90, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd24[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBD, 0x90, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd25[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCA, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd26[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC0, 0x04, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd27[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB2, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd28[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBE, 0x29, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd29[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB3, 0x37, 0x37, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd30[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB4, 0x19, 0x19, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd31[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB9, 0x44, 0x44, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd32[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBA, 0x24, 0x24, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd33[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x02, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd34[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xEE, 0x01, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd35[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xEF, 0x09, 0x06, 0x15,
+ 0x18, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd36[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0x00, 0x00,
+ 0x25, 0x00, 0x43, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd37[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd38[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0x54, 0x00,
+ 0x68, 0x00, 0xA0, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd39[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x0C, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd40[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0xC0, 0x01,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd41[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB1, 0x01, 0x30, 0x01,
+ 0x78, 0x01, 0xAE, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd42[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd43[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB1, 0x02, 0x08, 0x02,
+ 0x52, 0x02, 0x54, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd44[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x0C, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd45[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xB1, 0x02, 0x99, 0x02,
+ 0xF0, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd46[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB2, 0x03, 0x20, 0x03,
+ 0x56, 0x03, 0x76, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd47[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd48[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB2, 0x03, 0x93, 0x03,
+ 0xA4, 0x03, 0xB9, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd49[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x0C, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd50[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xB2, 0x03, 0xC9, 0x03,
+ 0xE3, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd51[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xB3, 0x03, 0xFC, 0x03,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd52[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd53[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0x10, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd54[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x12, 0x14, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd55[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB2, 0x16, 0x18, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd56[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB3, 0x1A, 0x29, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd57[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB4, 0x2A, 0x08, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd58[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB5, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd59[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB6, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd60[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB7, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd61[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB8, 0x31, 0x0A, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd62[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB9, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd63[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBA, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd64[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBB, 0x0B, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd65[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBC, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd66[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBD, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd67[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBE, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd68[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBF, 0x09, 0x2A, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd69[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC0, 0x29, 0x1B, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd70[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC1, 0x19, 0x17, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd71[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC2, 0x15, 0x13, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd72[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC3, 0x11, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd73[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xE5, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd74[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC4, 0x09, 0x1B, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd75[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC5, 0x19, 0x17, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd76[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC6, 0x15, 0x13, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd77[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC7, 0x11, 0x29, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd78[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC8, 0x2A, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd79[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC9, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd80[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCA, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd81[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCB, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd82[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCC, 0x31, 0x0B, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd83[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCD, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd84[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCE, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd85[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCF, 0x0A, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd86[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD0, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd87[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD1, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd88[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD2, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd89[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD3, 0x00, 0x2A, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd90[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD4, 0x29, 0x10, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd91[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD5, 0x12, 0x14, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd92[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD6, 0x16, 0x18, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd93[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD7, 0x1A, 0x08, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd94[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xE6, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd95[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD8, 0x00, 0x00, 0x00,
+ 0x54, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd96[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD9, 0x00, 0x15, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd97[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE7, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd98[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x03, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd99[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB0, 0x20, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd100[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x20, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd101[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xB2, 0x05, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd102[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xB6, 0x05, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd103[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xB7, 0x05, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd104[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xBA, 0x57, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd105[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xBB, 0x57, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd106[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xC0, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd107[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xC1, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd108[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC4, 0x60, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd109[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC5, 0x40, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd110[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x05, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd111[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xBD, 0x03, 0x01, 0x03,
+ 0x03, 0x03, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd112[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB0, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd113[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd114[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB2, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd115[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB3, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd116[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB4, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd117[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB5, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd118[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB8, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd119[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB9, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd120[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBA, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd121[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBB, 0x02, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd122[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBC, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd123[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC0, 0x07, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd124[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC4, 0x80, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd125[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC5, 0xA4, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd126[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC8, 0x05, 0x30, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd127[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC9, 0x01, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd128[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xCC, 0x00, 0x00, 0x3C,
+};
+
+static char nt35521_wxga_video_on_cmd129[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xCD, 0x00, 0x00, 0x3C,
+};
+
+static char nt35521_wxga_video_on_cmd130[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD1, 0x00, 0x04, 0xFD,
+ 0x07, 0x10, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd131[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD2, 0x00, 0x05, 0x02,
+ 0x07, 0x10, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd132[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE5, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd133[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE6, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd134[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE7, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd135[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE8, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd136[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE9, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd137[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xEA, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd138[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xED, 0x30, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd139[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x11, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd140[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xF3, 0x01, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd141[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x35, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd142[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char nt35521_wxga_video_on_cmd143[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35521_wxga_video_on_command[] = {
+ {0xc, nt35521_wxga_video_on_cmd0, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd1, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd2, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd3, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd4, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd5, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd6, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd7, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd8, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd9, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd10, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd11, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd12, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd13, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd14, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd15, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd16, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd17, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd18, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd19, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd20, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd21, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd22, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd23, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd24, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd25, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd26, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd27, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd28, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd29, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd30, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd31, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd32, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd33, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd34, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd35, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd36, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd37, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd38, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd39, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd40, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd41, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd42, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd43, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd44, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd45, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd46, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd47, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd48, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd49, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd50, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd51, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd52, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd53, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd54, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd55, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd56, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd57, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd58, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd59, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd60, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd61, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd62, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd63, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd64, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd65, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd66, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd67, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd68, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd69, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd70, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd71, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd72, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd73, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd74, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd75, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd76, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd77, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd78, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd79, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd80, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd81, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd82, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd83, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd84, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd85, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd86, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd87, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd88, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd89, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd90, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd91, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd92, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd93, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd94, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd95, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd96, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd97, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd98, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd99, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd100, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd101, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd102, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd103, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd104, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd105, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd106, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd107, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd108, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd109, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd110, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd111, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd112, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd113, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd114, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd115, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd116, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd117, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd118, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd119, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd120, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd121, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd122, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd123, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd124, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd125, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd126, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd127, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd128, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd129, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd130, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd131, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd132, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd133, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd134, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd135, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd136, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd137, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd138, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd139, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd140, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd141, 0x00},
+ {0x4, nt35521_wxga_video_on_cmd142, 0x00},
+ {0x4, nt35521_wxga_video_on_cmd143, 0x00}
+};
+
+#define NT35521_WXGA_VIDEO_ON_COMMAND 144
+
+
+static char nt35521_wxga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char nt35521_wxga_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35521_wxga_video_off_command[] = {
+ {0x4, nt35521_wxga_videooff_cmd0, 0x32},
+ {0x4, nt35521_wxga_videooff_cmd1, 0x78}
+};
+
+#define NT35521_WXGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state nt35521_wxga_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info nt35521_wxga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info nt35521_wxga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration nt35521_wxga_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t nt35521_wxga_video_timings[] = {
+ 0x93, 0x1F, 0x17, 0x00, 0x2F, 0x2E, 0x1C, 0x21, 0x26, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing nt35521_wxga_video_timing_info = {
+ 0, 4, 0x20, 0x2D
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence nt35521_wxga_video_reset_seq = {
+ {1, 0, 1, }, {20, 1, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight nt35521_wxga_video_backlight = {
+ 0, 1, 255, 2, 0, "PMIC_8941"
+};
+
+#endif /*_PANEL_NT35521_WXGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
old mode 100644
new mode 100755
index 427a548..9734574
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -153,6 +153,27 @@
pinfo->mipi.mdp_trigger = pstruct->paneltiminginfo->dsi_mdp_trigger;
pinfo->mipi.dma_trigger = pstruct->paneltiminginfo->dsi_dma_trigger;
+ pinfo->fbc.enabled = pstruct->fbcinfo.enabled;
+ if (pinfo->fbc.enabled) {
+ pinfo->fbc.enabled = pstruct->fbcinfo.enabled;
+ pinfo->fbc.comp_ratio= pstruct->fbcinfo.comp_ratio;
+ pinfo->fbc.comp_mode = pstruct->fbcinfo.comp_mode;
+ pinfo->fbc.qerr_enable = pstruct->fbcinfo.qerr_enable;
+ pinfo->fbc.cd_bias = pstruct->fbcinfo.cd_bias;
+ pinfo->fbc.pat_enable = pstruct->fbcinfo.pat_enable;
+ pinfo->fbc.vlc_enable = pstruct->fbcinfo.vlc_enable;
+ pinfo->fbc.bflc_enable = pstruct->fbcinfo.bflc_enable;
+ pinfo->fbc.line_x_budget = pstruct->fbcinfo.line_x_budget;
+ pinfo->fbc.block_x_budget = pstruct->fbcinfo.block_x_budget;
+ pinfo->fbc.block_budget = pstruct->fbcinfo.block_budget;
+ pinfo->fbc.lossless_mode_thd = pstruct->fbcinfo.lossless_mode_thd;
+ pinfo->fbc.lossy_mode_thd = pstruct->fbcinfo.lossy_mode_thd;
+ pinfo->fbc.lossy_rgb_thd = pstruct->fbcinfo.lossy_rgb_thd;
+ pinfo->fbc.lossy_mode_idx = pstruct->fbcinfo.lossy_mode_idx;
+ } else {
+ pinfo->fbc.comp_ratio = 1;
+ }
+
pinfo->pre_on = dsi_panel_pre_on;
pinfo->pre_off = dsi_panel_pre_off;
pinfo->on = dsi_panel_post_on;
@@ -211,6 +232,9 @@
int ret = NO_ERROR;
uint8_t lane_enable = 0;
uint32_t panel_width = pinfo->xres;
+ uint32_t final_xres, final_yres, final_width;
+ uint32_t final_height, final_hbp, final_hfp,final_vbp;
+ uint32_t final_vfp, final_hpw, final_vpw;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
@@ -224,16 +248,29 @@
if (pinfo->mipi.data_lane3)
lane_enable |= (1 << 3);
- ret = mdss_dsi_video_mode_config((panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- (panel_width),
- (pinfo->yres),
- (plcdc->h_front_porch),
- (plcdc->h_back_porch + plcdc->h_pulse_width),
- (plcdc->v_front_porch),
- (plcdc->v_back_porch + plcdc->v_pulse_width),
- (plcdc->h_pulse_width),
- (plcdc->v_pulse_width),
+ final_xres = panel_width;
+ final_width = panel_width + pinfo->lcdc.xres_pad;
+
+ if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
+ final_xres /= pinfo->fbc.comp_ratio;
+ final_width /= pinfo->fbc.comp_ratio;
+ dprintf(SPEW, "DSI xres =%d final_width=%d\n", final_xres,
+ final_width);
+ }
+ final_yres = pinfo->yres;
+ final_height = pinfo->yres + pinfo->lcdc.yres_pad;
+ final_hbp = pinfo->lcdc.h_back_porch;
+ final_hfp = pinfo->lcdc.h_front_porch;
+ final_vbp = pinfo->lcdc.v_back_porch;
+ final_vfp = pinfo->lcdc.v_front_porch;
+ final_hpw = pinfo->lcdc.h_pulse_width;
+ final_vpw = pinfo->lcdc.v_pulse_width;
+
+ ret = mdss_dsi_video_mode_config(final_width, final_height,
+ final_xres, final_yres,
+ final_hfp, final_hbp + final_hpw,
+ final_vfp, final_vbp + final_vpw,
+ final_hpw, final_vpw,
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
@@ -243,24 +280,18 @@
MIPI_DSI0_BASE);
if (pinfo->mipi.dual_dsi)
- ret = mdss_dsi_video_mode_config(
- (panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- (panel_width),
- (pinfo->yres),
- (plcdc->h_front_porch),
- (plcdc->h_back_porch + plcdc->h_pulse_width),
- (plcdc->v_front_porch),
- (plcdc->v_back_porch + plcdc->v_pulse_width),
- (plcdc->h_pulse_width),
- (plcdc->v_pulse_width),
- pinfo->mipi.dst_format,
- pinfo->mipi.traffic_mode,
- lane_enable,
- pinfo->mipi.hsa_power_stop,
- pinfo->mipi.eof_bllp_power,
- pinfo->mipi.interleave_mode,
- MIPI_DSI1_BASE);
+ ret = mdss_dsi_video_mode_config(final_width, final_height,
+ final_xres, final_yres,
+ final_hfp, final_hbp + final_hpw,
+ final_vfp, final_vbp + final_vpw,
+ final_hpw, final_vpw,
+ pinfo->mipi.dst_format,
+ pinfo->mipi.traffic_mode,
+ lane_enable,
+ pinfo->mipi.hsa_power_stop,
+ pinfo->mipi.eof_bllp_power,
+ pinfo->mipi.interleave_mode,
+ MIPI_DSI1_BASE);
return ret;
}
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index a6843ce..dcc5631 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -47,6 +47,7 @@
#define DST_SPLIT_FLAG 0x10
#define MAX_PANEL_ID_LEN 64
+#include "panel.h"
/*---------------------------------------------------------------------------*/
/* struct definition */
/*---------------------------------------------------------------------------*/
@@ -61,6 +62,7 @@
struct panel_timing *paneltiminginfo;
struct panel_reset_sequence *panelresetseq;
struct backlight *backlightinfo;
+ struct fb_compression fbcinfo;
};
struct panel_list {
diff --git a/include/target.h b/include/target.h
index ba95cbb..16a4268 100644
--- a/include/target.h
+++ b/include/target.h
@@ -75,4 +75,5 @@
bool target_is_cdp_qvga();
uint32_t target_hw_interposer();
uint32_t target_override_pll();
+uint32_t target_ddr_cfg_val();
#endif
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index c8a7991..67a6f5b 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -259,6 +259,16 @@
#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3A00)
#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3E00)
+#ifdef MDP_PP_0_BASE
+#undef MDP_PP_0_BASE
+#endif
+#define MDP_PP_0_BASE REG_MDP(0x12F00)
+
+#ifdef MDP_PP_1_BASE
+#undef MDP_PP_1_BASE
+#endif
+#define MDP_PP_1_BASE REG_MDP(0x13000)
+
#define DMA_CMD_OFFSET 0x048
#define DMA_CMD_LENGTH 0x04C
diff --git a/platform/msm8909/gpio.c b/platform/msm8909/gpio.c
index 8d7355d..70d4dc4 100644
--- a/platform/msm8909/gpio.c
+++ b/platform/msm8909/gpio.c
@@ -55,10 +55,16 @@
void gpio_config_uart_dm(uint8_t id)
{
/* configure rx gpio */
- gpio_tlmm_config(21, 2, GPIO_INPUT, GPIO_NO_PULL,
+ gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
/* configure tx gpio */
- gpio_tlmm_config(20, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
}
+
+uint32_t gpio_status(uint32_t gpio)
+{
+ return readl(GPIO_IN_OUT_ADDR(gpio)) & GPIO_IN;
+}
+
diff --git a/platform/msm8909/include/platform/gpio.h b/platform/msm8909/include/platform/gpio.h
index d970f47..da40c1e 100644
--- a/platform/msm8909/include/platform/gpio.h
+++ b/platform/msm8909/include/platform/gpio.h
@@ -29,6 +29,8 @@
#ifndef __PLATFORM_MSM8909_GPIO_H
#define __PLATFORM_MSM8909_GPIO_H
+#include <bits.h>
+#include <gpio.h>
/* GPIO TLMM: Direction */
#define GPIO_INPUT 0
@@ -54,6 +56,9 @@
#define GPIO_ENABLE 0
#define GPIO_DISABLE 1
+/* GPIO_IN_OUT register shifts. */
+#define GPIO_IN BIT(0)
+#define GPIO_OUT BIT(1)
void gpio_config_uart_dm(uint8_t id);
#endif
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index f3629e7..bbe731c 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -32,9 +32,23 @@
#define MSM_IOMAP_BASE 0x00000000
#define MSM_IOMAP_END 0x08000000
+#define A7_SS_BASE 0x0B000000
+#define A7_SS_END 0x0B200000
+
+#define SYSTEM_IMEM_BASE 0x08600000
+#define MSM_SHARED_IMEM_BASE 0x08600000
+
+#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+#define BS_INFO_OFFSET (0x6B0)
+#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
+
#define SDRAM_START_ADDR 0x80000000
-#define MSM_SHARED_BASE 0x86300000
+#define MSM_SHARED_BASE 0x87D00000
+
+#define MSM_NAND_BASE 0x79B0000
+/* NAND BAM */
+#define MSM_NAND_BAM_BASE 0x7984000
#define APPS_SS_BASE 0x0B000000
@@ -42,6 +56,7 @@
#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
+#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00011008)
#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
#define PERIPH_SS_BASE 0x07800000
@@ -74,14 +89,27 @@
#define MPM2_MPM_CTRL_BASE 0x004A0000
#define MPM2_MPM_PS_HOLD 0x004AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
/* CRYPTO ENGINE */
#define MSM_CE1_BASE 0x073A000
#define MSM_CE1_BAM_BASE 0x0704000
+#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
+#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
+#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
+#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
+#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
+#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
+
+/* I2C */
+#define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010)
+#define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3018)
+#define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3014)
/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x21024)
+#define GPLL1_STATUS (CLK_CTL_BASE + 0x2001C)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
@@ -96,6 +124,14 @@
#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
+#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
@@ -114,4 +150,92 @@
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
+
+/* MDSS */
+#define MIPI_DSI_BASE (0x1AC8000)
+#define MIPI_DSI0_BASE MIPI_DSI_BASE
+#define MIPI_DSI1_BASE MIPI_DSI_BASE
+#define DSI0_PHY_BASE (0x1AC8500)
+#define DSI1_PHY_BASE DSI0_PHY_BASE
+#define DSI0_PLL_BASE (0x1AC8300)
+#define DSI1_PLL_BASE DSI0_PLL_BASE
+#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+
+
+/* MDP */
+#define MDP_BASE 0x1A00000
+#define REG_MDP(off) (MDP_BASE + (off))
+
+#define MDP_DMA_P_CONFIG REG_MDP(0x90000)
+#define MDP_DMA_P_OUT_XY REG_MDP(0x90010)
+#define MDP_DMA_P_SIZE REG_MDP(0x90004)
+#define MDP_DMA_P_BUF_ADDR REG_MDP(0x90008)
+#define MDP_DMA_P_BUF_Y_STRIDE REG_MDP(0x9000C)
+
+#define MDP_DSI_VIDEO_EN REG_MDP(0xF0000)
+#define MDP_DSI_VIDEO_HSYNC_CTL REG_MDP(0xF0004)
+#define MDP_DSI_VIDEO_VSYNC_PERIOD REG_MDP(0xF0008)
+#define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH REG_MDP(0xF000C)
+#define MDP_DSI_VIDEO_DISPLAY_HCTL REG_MDP(0xF0010)
+#define MDP_DSI_VIDEO_DISPLAY_V_START REG_MDP(0xF0014)
+#define MDP_DSI_VIDEO_DISPLAY_V_END REG_MDP(0xF0018)
+#define MDP_DSI_VIDEO_BORDER_CLR REG_MDP(0xF0028)
+#define MDP_DSI_VIDEO_HSYNC_SKEW REG_MDP(0xF0030)
+#define MDP_DSI_VIDEO_CTL_POLARITY REG_MDP(0xF0038)
+#define MDP_DSI_VIDEO_TEST_CTL REG_MDP(0xF0034)
+
+#define MDP_DMA_P_START REG_MDP(0x00044)
+#define MDP_DMA_S_START REG_MDP(0x00048)
+#define MDP_DISP_INTF_SEL REG_MDP(0x00038)
+#define MDP_MAX_RD_PENDING_CMD_CONFIG REG_MDP(0x0004C)
+#define MDP_INTR_ENABLE REG_MDP(0x00020)
+#define MDP_INTR_CLEAR REG_MDP(0x00028)
+#define MDP_DSI_CMD_MODE_ID_MAP REG_MDP(0xF1000)
+#define MDP_DSI_CMD_MODE_TRIGGER_EN REG_MDP(0XF1004)
+
+#define MDP_TEST_MODE_CLK REG_MDP(0xF0000)
+#define MDP_INTR_STATUS REG_MDP(0x00054)
+
+#define SOFT_RESET 0x118
+#define CLK_CTRL 0x11C
+#define TRIG_CTRL 0x084
+#define CTRL 0x004
+#define COMMAND_MODE_DMA_CTRL 0x03C
+#define COMMAND_MODE_MDP_CTRL 0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
+#define ERR_INT_MASK0 0x10C
+
+#define LANE_SWAP_CTL 0x0B0
+#define TIMING_CTL 0x0C4
+
+#define VIDEO_MODE_ACTIVE_H 0x024
+#define VIDEO_MODE_ACTIVE_V 0x028
+#define VIDEO_MODE_TOTAL 0x02C
+#define VIDEO_MODE_HSYNC 0x030
+#define VIDEO_MODE_VSYNC 0x034
+#define VIDEO_MODE_VSYNC_VPOS 0x038
+
+#define DMA_CMD_OFFSET 0x048
+#define DMA_CMD_LENGTH 0x04C
+
+#define INT_CTRL 0x110
+#define CMD_MODE_DMA_SW_TRIGGER 0x090
+
+#define EOT_PACKET_CTRL 0x0CC
+#define MISR_CMD_CTRL 0x0A0
+#define MISR_VIDEO_CTRL 0x0A4
+#define VIDEO_MODE_CTRL 0x010
+#define HS_TIMER_CTRL 0x0BC
+
+#define TCSR_TZ_WONCE 0x193D000
+
+/* Boot config */
+#define SEC_CTRL_CORE_BASE 0x00058000
+#define BOOT_CONFIG_OFFSET 0x0000602C
+#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
+
#endif
diff --git a/platform/msm8909/include/platform/irqs.h b/platform/msm8909/include/platform/irqs.h
index 1875b8a..3ef97b1 100644
--- a/platform/msm8909/include/platform/irqs.h
+++ b/platform/msm8909/include/platform/irqs.h
@@ -50,6 +50,8 @@
#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+#define SMD_IRQ (GIC_SPI_START + 168)
+
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
diff --git a/platform/msm8909/msm8909-clock.c b/platform/msm8909/msm8909-clock.c
index eff91e7..a2af96d 100644
--- a/platform/msm8909/msm8909-clock.c
+++ b/platform/msm8909/msm8909-clock.c
@@ -41,6 +41,8 @@
#define gpll0_source_val 1
#define cxo_mm_source_val 0
#define gpll0_mm_source_val 1
+#define gpll1_mm_source_val 3
+
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -109,6 +111,21 @@
},
};
+static struct pll_vote_clk gpll1_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(1),
+ .status_reg = (void *) GPLL1_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 614400000,
+ .dbg_name = "gpll1_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
/* SDCC Clocks */
static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
{
@@ -321,115 +338,6 @@
},
};
-/* Display clocks */
-static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
- F_MM(19200000, cxo, 1, 0, 0),
- F_END
-};
-
-static struct clk_freq_tbl ftbl_mdp_clk[] = {
- F_MM( 80000000, gpll0, 10, 0, 0),
- F_MM( 100000000, gpll0, 8, 0, 0),
- F_MM( 200000000, gpll0, 4, 0, 0),
- F_MM( 320000000, gpll0, 2.5, 0, 0),
- F_END
-};
-
-static struct rcg_clk dsi_esc0_clk_src = {
- .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR,
- .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_mdss_esc0_1_clk,
-
- .c = {
- .dbg_name = "dsi_esc0_clk_src",
- .ops = &clk_ops_rcg,
- },
-};
-
-static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
- F_MM(19200000, cxo, 1, 0, 0),
- F_END
-};
-
-static struct rcg_clk vsync_clk_src = {
- .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR,
- .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_mdss_vsync_clk,
-
- .c = {
- .dbg_name = "vsync_clk_src",
- .ops = &clk_ops_rcg,
- },
-};
-
-static struct branch_clk mdss_esc0_clk = {
- .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR,
- .parent = &dsi_esc0_clk_src.c,
- .has_sibling = 0,
-
- .c = {
- .dbg_name = "mdss_esc0_clk",
- .ops = &clk_ops_branch,
- },
-};
-
-static struct branch_clk mdss_axi_clk = {
- .cbcr_reg = (uint32_t *) MDP_AXI_CBCR,
- .has_sibling = 1,
-
- .c = {
- .dbg_name = "mdss_axi_clk",
- .ops = &clk_ops_branch,
- },
-};
-
-static struct branch_clk mdp_ahb_clk = {
- .cbcr_reg = (uint32_t *) MDP_AHB_CBCR,
- .has_sibling = 1,
-
- .c = {
- .dbg_name = "mdp_ahb_clk",
- .ops = &clk_ops_branch,
- },
-};
-
-static struct rcg_clk mdss_mdp_clk_src = {
- .cmd_reg = (uint32_t *) MDP_CMD_RCGR,
- .cfg_reg = (uint32_t *) MDP_CFG_RCGR,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_mdp_clk,
- .current_freq = &rcg_dummy_freq,
-
- .c = {
- .dbg_name = "mdss_mdp_clk_src",
- .ops = &clk_ops_rcg,
- },
-};
-
-static struct branch_clk mdss_mdp_clk = {
- .cbcr_reg = (uint32_t *) MDP_CBCR,
- .parent = &mdss_mdp_clk_src.c,
- .has_sibling = 0,
-
- .c = {
- .dbg_name = "mdss_mdp_clk",
- .ops = &clk_ops_branch,
- },
-};
-
-static struct branch_clk mdss_vsync_clk = {
- .cbcr_reg = MDSS_VSYNC_CBCR,
- .parent = &vsync_clk_src.c,
- .has_sibling = 0,
-
- .c = {
- .dbg_name = "mdss_vsync_clk",
- .ops = &clk_ops_branch,
- },
-};
-
static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
F(160000000, gpll0, 5, 0, 0),
F_END
@@ -520,13 +428,6 @@
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
- CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
- CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
- CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c),
- CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c),
- CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
- CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
-
CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
diff --git a/platform/msm8909/platform.c b/platform/msm8909/platform.c
index 3765be4..1ea030a 100644
--- a/platform/msm8909/platform.c
+++ b/platform/msm8909/platform.c
@@ -35,9 +35,37 @@
#include <arch/arm/mmu.h>
#include <smem.h>
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+#define A7_SS_SIZE ((A7_SS_END - A7_SS_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ { A7_SS_BASE, A7_SS_BASE, A7_SS_SIZE, IOMAP_MEMORY},
+ { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+};
+
+static struct smem_ram_ptable ram_ptable;
+
void platform_early_init(void)
{
board_init();
+ platform_clock_init();
qgic_init();
qtimer_init();
}
@@ -50,4 +78,109 @@
void platform_uninit(void)
{
qtimer_uninit();
+ if (!platform_boot_dev_isemmc())
+ qpic_nand_uninit();
}
+
+uint32_t platform_get_sclk_count(void)
+{
+ return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+addr_t get_bs_info_addr()
+{
+ return ((addr_t)BS_INFO_ADDR);
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ ram_partition ptn_entry;
+ uint32_t len = 0;
+
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Configure the MMU page entries for SDRAM and IMEM memory read
+ from the smem ram table*/
+ for(i = 0; i < len; i++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, i);
+ if(ptn_entry.type == SYS_MEMORY)
+ {
+ if((ptn_entry.category == SDRAM) ||
+ (ptn_entry.category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ptn_entry.start & (MB-1)) == 0);
+
+ sections = (ptn_entry.size) / MB;
+ while(sections--)
+ {
+ arm_mmu_map_section(ptn_entry.start +
+ sections * MB,
+ ptn_entry.start +
+ sections * MB,
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+ }
+ }
+ }
+ }
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
+
+/* DYNAMIC SMEM REGION feature enables LK to dynamically
+ * read the SMEM addr info from TCSR_TZ_WONCE register.
+ * The first word read, if indicates a MAGIC number, then
+ * Dynamic SMEM is assumed to be enabled. Read the remaining
+ * SMEM info for SMEM Size and Phy_addr from the other bytes.
+ */
+uint32_t platform_get_smem_base_addr()
+{
+ struct smem_addr_info *smem_info = NULL;
+
+ smem_info = (struct smem_addr_info *)readl(TCSR_TZ_WONCE);
+ if(smem_info && (smem_info->identifier == SMEM_TARGET_INFO_IDENTIFIER))
+ return smem_info->phy_addr;
+ else
+ return MSM_SHARED_BASE;
+}
+
diff --git a/platform/msm8909/rules.mk b/platform/msm8909/rules.mk
index da6f955..4da135e 100644
--- a/platform/msm8909/rules.mk
+++ b/platform/msm8909/rules.mk
@@ -1,7 +1,6 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
ARCH := arm
-#Compiling this as cortex-a8 until the compiler supports krait
ARM_CPU := cortex-a8
CPU := generic
@@ -11,13 +10,15 @@
DEFINES += PERIPH_BLK_BLSP=1
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
- MMC_SLOT=$(MMC_SLOT)
+ MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
OBJS += \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/msm8909-clock.o \
$(LOCAL_DIR)/gpio.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index 9596622..c815bd0 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -43,9 +43,14 @@
#define SDRAM_START_ADDR 0x80000000
#define MSM_SHARED_BASE 0x86300000
-
#define APPS_SS_BASE 0x0B000000
+#define DDR_START get_ddr_start()
+#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
+#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
+#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
+#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
+
#define MSM_GIC_DIST_BASE APPS_SS_BASE
#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
diff --git a/platform/msm8916/platform.c b/platform/msm8916/platform.c
index 4deaa1b..4e896ce 100644
--- a/platform/msm8916/platform.c
+++ b/platform/msm8916/platform.c
@@ -52,7 +52,7 @@
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
/* IMEM memory - cacheable, write through */
-#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
static mmu_section_t mmu_section_table[] = {
@@ -60,7 +60,10 @@
{ MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
{ MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
{ A53_SS_BASE, A53_SS_BASE, A53_SS_SIZE, IOMAP_MEMORY},
- { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+ { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, COMMON_MEMORY},
+ { MSM_SHARED_BASE, MSM_SHARED_BASE, 1, COMMON_MEMORY},
+ { BASE_ADDR, BASE_ADDR, 90, COMMON_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, 256, COMMON_MEMORY},
};
static struct smem_ram_ptable ram_ptable;
@@ -73,6 +76,7 @@
platform_clock_init();
qgic_init();
qtimer_init();
+ scm_init();
}
int qtmr_irq()
@@ -114,39 +118,6 @@
uint32_t i;
uint32_t sections;
uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- ram_partition ptn_entry;
- uint32_t len = 0;
-
- ASSERT(smem_ram_ptable_init_v1());
-
- len = smem_get_ram_ptable_len();
-
- /* Configure the MMU page entries for SDRAM and IMEM memory read
- from the smem ram table*/
- for(i = 0; i < len; i++)
- {
- smem_get_ram_ptable_entry(&ptn_entry, i);
- if(ptn_entry.type == SYS_MEMORY)
- {
- if((ptn_entry.category == SDRAM) ||
- (ptn_entry.category == IMEM))
- {
- /* Check to ensure that start address is 1MB aligned */
- ASSERT((ptn_entry.start & (MB-1)) == 0);
-
- sections = (ptn_entry.size) / MB;
- while(sections--)
- {
- arm_mmu_map_section(ptn_entry.start +
- sections * MB,
- ptn_entry.start +
- sections * MB,
- (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
- MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
- }
- }
- }
- }
/* Configure the MMU page entries for memory read from the
mmu_section_table */
@@ -216,3 +187,30 @@
else
return MSM_SHARED_BASE;
}
+uint32_t get_ddr_start()
+{
+ uint32_t i;
+ ram_partition ptn_entry;
+ uint32_t len = 0;
+
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Determine the Start addr of the DDR RAM */
+ for(i = 0; i < len; i++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, i);
+ if(ptn_entry.type == SYS_MEMORY)
+ {
+ if((ptn_entry.category == SDRAM) ||
+ (ptn_entry.category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ptn_entry.start & (MB-1)) == 0);
+ return ptn_entry.start;
+ }
+ }
+ }
+ ASSERT("DDR Start Mem Not found\n");
+}
diff --git a/platform/msm8916/rules.mk b/platform/msm8916/rules.mk
index 1b737e7..b0a2070 100644
--- a/platform/msm8916/rules.mk
+++ b/platform/msm8916/rules.mk
@@ -13,8 +13,6 @@
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
-DEFINES += TZ_SAVE_KERNEL_HASH
-
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
DEVS += fbcon
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index 33f535f..5e2d5a6 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -328,7 +328,7 @@
ASSERT(0);
}
- ret = clk_get_set_enable("mdss_mdp_clk_src", 240000000, 1);
+ ret = clk_get_set_enable("mdss_mdp_clk_src", 300000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
@@ -363,7 +363,7 @@
{
int ret;
/* Configure MMSSNOC AXI clock */
- ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+ ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 300000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
@@ -371,7 +371,7 @@
}
/* Configure S0 AXI clock */
- ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+ ret = clk_get_set_enable("mmss_s0_axi_clk", 300000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
@@ -379,7 +379,7 @@
}
/* Configure AXI clock */
- ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+ ret = clk_get_set_enable("mdss_axi_clk", 300000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index fd654cb..341c0a6 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -243,6 +243,17 @@
#define MDP_BASE (0xfd900000)
+
+#ifdef MDP_PP_0_BASE
+#undef MDP_PP_0_BASE
+#endif
+#define MDP_PP_0_BASE REG_MDP(0x71000)
+
+#ifdef MDP_PP_1_BASE
+#undef MDP_PP_1_BASE
+#endif
+#define MDP_PP_1_BASE REG_MDP(0x71800)
+
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_HW_REV REG_MDP(0x1000)
#define MDP_INTR_EN REG_MDP(0x1010)
@@ -285,8 +296,8 @@
#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
-#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x13d8)
-#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x13dc)
+#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
+#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
diff --git a/platform/msm8994/msm8994-clock.c b/platform/msm8994/msm8994-clock.c
index a28291a..5ee2d5c 100644
--- a/platform/msm8994/msm8994-clock.c
+++ b/platform/msm8994/msm8994-clock.c
@@ -554,12 +554,14 @@
static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
F_MM(19200000, cxo, 1, 0, 0),
F_MM(100000000, gpll0, 6, 0, 0),
+ F_MM(300000000, gpll0, 2, 0, 0),
F_END
};
static struct clk_freq_tbl ftbl_mdp_clk[] = {
F_MM( 75000000, gpll0, 8, 0, 0),
F_MM( 240000000, gpll0, 2.5, 0, 0),
+ F_MM(300000000, gpll0, 2, 0, 0),
F_END
};
diff --git a/platform/msm_shared/bam.c b/platform/msm_shared/bam.c
index f9593a4..00abeda 100644
--- a/platform/msm_shared/bam.c
+++ b/platform/msm_shared/bam.c
@@ -90,14 +90,6 @@
/* Flush out the right most global interrupt bit */
} while (!((val & 0x7FFF) & (1 << bam->pipe[pipe_num].pipe_num)));
- /* Check the reason for this BAM interrupt */
- bamsts = readl(BAM_IRQ_STTS(bam->base));
- if (bamsts)
- {
- dprintf(CRITICAL,"ERROR:BAM_IRQ_STTS %u \n", bamsts);
- goto bam_wait_int_error;
- }
-
/* Check the interrupt type */
/* Read interrupt status register */
val = readl(BAM_P_IRQ_STTSn(bam->pipe[pipe_num].pipe_num, bam->base));
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index fdc8553..fbbe62b 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -150,11 +150,11 @@
}
/* HLOS subtype
- * bit no |31 16 | 15 8 | 7 0|
- * board.platform_hlos_subtype = |reserved | DDR detection | subtype|
- * | bits | bits | |
+ * bit no |31 20 | 19 16| 15 8 | 7 0|
+ * board.platform_hlos_subtype = |reserved | Boot device | DDR detection | subtype|
+ * | bits | | bits |
*/
- board.platform_hlos_subtype = board_get_ddr_subtype() << 8;
+ board.platform_hlos_subtype = (board_get_ddr_subtype() << 8) | (platform_get_boot_dev() << 16);
}
else
{
diff --git a/platform/msm_shared/boot_device.c b/platform/msm_shared/boot_device.c
index a5e6131..c120b6c 100644
--- a/platform/msm_shared/boot_device.c
+++ b/platform/msm_shared/boot_device.c
@@ -53,7 +53,12 @@
boot_dev_type = platform_get_boot_dev();
+#if USE_MDM_BOOT_CFG
+ /* For MDM default boot device is NAND */
+ if (boot_dev_type == BOOT_EMMC)
+#else
if (boot_dev_type == BOOT_EMMC || boot_dev_type == BOOT_DEFAULT)
+#endif
boot_dev_type = 1;
else
boot_dev_type = 0;
@@ -71,15 +76,16 @@
val = platform_get_boot_dev();
switch(val)
{
+#if !USE_MDM_BOOT_CFG
case BOOT_DEFAULT:
- case BOOT_EMMC:
sprintf(buf, "%x.sdhci", ((struct mmc_device *)dev)->host.base);
break;
case BOOT_UFS:
sprintf(buf, "%x.ufshc", ((struct ufs_dev *)dev)->base);
break;
- case BOOT_NAND:
- sprintf(buf, "%x.nandc", nand_device_base());
+#endif
+ case BOOT_EMMC:
+ sprintf(buf, "%x.sdhci", ((struct mmc_device *)dev)->host.base);
break;
default:
dprintf(CRITICAL,"ERROR: Unexpected boot_device val=%x",val);
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index 849b294..9681de0 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -78,7 +78,8 @@
dprintf(INFO, "Config MIPI_VIDEO_PANEL.\n");
mdp_rev = mdp_get_revision();
- if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304)
+ if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304 ||
+ mdp_rev == MDP_REV_305)
ret = mdss_dsi_config(panel);
else
ret = mipi_config(panel);
@@ -96,7 +97,8 @@
case MIPI_CMD_PANEL:
dprintf(INFO, "Config MIPI_CMD_PANEL.\n");
mdp_rev = mdp_get_revision();
- if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304)
+ if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304 ||
+ mdp_rev == MDP_REV_305)
ret = mdss_dsi_config(panel);
else
ret = mipi_config(panel);
@@ -180,7 +182,8 @@
if (ret)
goto msm_display_on_out;
mdp_rev = mdp_get_revision();
- if (mdp_rev != MDP_REV_50 && mdp_rev != MDP_REV_304) {
+ if (mdp_rev != MDP_REV_50 && mdp_rev != MDP_REV_304 &&
+ mdp_rev != MDP_REV_305) {
ret = mipi_cmd_trigger();
if (ret)
goto msm_display_on_out;
diff --git a/platform/msm_shared/dme.c b/platform/msm_shared/dme.c
index 670d344..2571763 100644
--- a/platform/msm_shared/dme.c
+++ b/platform/msm_shared/dme.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -151,6 +151,51 @@
return ret;
}
+int dme_set_fpoweronwpen(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
+ uint32_t try_again = DME_FPOWERONWPEN_RETRIES;
+ struct utp_query_req_upiu_type read_query = {UPIU_QUERY_OP_READ_FLAG,
+ UFS_IDX_fPowerOnWPEn,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+ struct utp_query_req_upiu_type set_query = {UPIU_QUERY_OP_SET_FLAG,
+ UFS_IDX_fPowerOnWPEn,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+
+
+ if (dme_send_query_upiu(dev, &read_query))
+ return -UFS_FAILURE;
+
+ arch_invalidate_cache_range((addr_t) result, sizeof(uint32_t));
+
+ if (*result == 1)
+ goto utp_set_fpoweronwpen_done;
+
+ do
+ {
+ try_again--;
+ dprintf(CRITICAL, "Power on Write Protect request failed. Retrying again.\n");
+
+ if (dme_send_query_upiu(dev, &set_query))
+ return -UFS_FAILURE;
+ if (dme_send_query_upiu(dev, &read_query))
+ return -UFS_FAILURE;
+
+ if (*result == 1)
+ break;
+ } while (try_again);
+
+utp_set_fpoweronwpen_done:
+ dprintf(INFO,"Power on Write Protect status: %u\n", *result);
+ return UFS_SUCCESS;
+}
+
int dme_set_fdeviceinit(struct ufs_dev *dev)
{
STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
diff --git a/platform/msm_shared/include/boot_device.h b/platform/msm_shared/include/boot_device.h
index b393afd..1f195b9 100644
--- a/platform/msm_shared/include/boot_device.h
+++ b/platform/msm_shared/include/boot_device.h
@@ -31,16 +31,27 @@
#include <sys/types.h>
+#if USE_MDM_BOOT_CFG
+#define BOOT_DEVICE_MASK(val) ((val & 0x1E) >> 1)
+#else
#define BOOT_DEVICE_MASK(val) ((val & 0x3E) >> 1)
+#endif
/* Boot device */
+#if USE_MDM_BOOT_CFG
enum boot_device
{
- BOOT_DEFAULT=0,
+ BOOT_DEFAULT=0, /* NAND */
+ BOOT_EMMC=3,
+};
+#else
+enum boot_device
+{
+ BOOT_DEFAULT=0, /* EMMC */
BOOT_EMMC=2,
BOOT_UFS=4,
- BOOT_NAND=5,
};
+#endif
void platform_read_boot_config();
uint32_t platform_get_boot_dev();
diff --git a/platform/msm_shared/include/dme.h b/platform/msm_shared/include/dme.h
index 31be6c5..c9ac677 100644
--- a/platform/msm_shared/include/dme.h
+++ b/platform/msm_shared/include/dme.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -50,6 +50,7 @@
/* Retry value for commands. */
#define DME_NOP_NUM_RETRIES 20
#define DME_FDEVICEINIT_RETRIES 20
+#define DME_FPOWERONWPEN_RETRIES 20
/* Timeout value for commands. */
#define DME_NOP_QUERY_TIMEOUT 10
@@ -221,6 +222,7 @@
struct upiu_req_build_type *upiu_data);
int dme_send_nop_query(struct ufs_dev *dev);
int dme_set_fdeviceinit(struct ufs_dev *dev);
+int dme_set_fpoweronwpen(struct ufs_dev *dev);
int dme_read_unit_desc(struct ufs_dev *dev, uint8_t index);
#endif
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 5f2fa0e..8e17def 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -81,6 +81,7 @@
#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */
#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
+#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */
#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
#define MDSS_MAX_LINE_BUF_WIDTH 2048
@@ -102,6 +103,9 @@
#define MDP_CTL_0_BASE REG_MDP(0x600)
#define MDP_CTL_1_BASE REG_MDP(0x700)
+#define MDP_PP_0_BASE REG_MDP(0x12D00)
+#define MDP_PP_1_BASE REG_MDP(0x12E00)
+
#define CTL_LAYER_0 0x00
#define CTL_LAYER_1 0x04
#define CTL_TOP 0x14
@@ -120,6 +124,7 @@
#define MDP_INTF_2_BASE REG_MDP(0x12900)
#define MDP_INTF_3_BASE REG_MDP(0x12B00)
+#define MDP_INTF_CONFIG 0x04
#define MDP_HSYNC_CTL 0x08
#define MDP_VSYNC_PERIOD_F0 0x0C
#define MDP_VSYNC_PERIOD_F1 0x10
@@ -137,6 +142,7 @@
#define MDP_ACTIVE_V_END_F1 0x38
#define MDP_UNDERFFLOW_COLOR 0x48
#define MDP_PANEL_FORMAT 0x90
+#define MDP_PROG_FETCH_START 0x170
#define MDP_CLK_CTRL0 REG_MDP(0x03AC)
#define MDP_CLK_CTRL1 REG_MDP(0x03B4)
@@ -178,6 +184,10 @@
#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0x24074)
#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0x240A8)
+#define MDSS_MDP_REG_PP_FBC_MODE 0x034
+#define MDSS_MDP_REG_PP_FBC_BUDGET_CTL 0x038
+#define MDSS_MDP_REG_PP_FBC_LOSSY_MODE 0x03C
+
void mdp_set_revision(int rev);
int mdp_get_revision();
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index d7c19ce..0098c0e 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -305,6 +305,7 @@
uint16_t bus_width; /* Bus width used */
uint32_t max_clk_rate; /* Max clock rate supported */
uint8_t hs400_support; /* SDHC HS400 mode supported or not */
+ uint8_t use_io_switch; /* IO pad switch flag for shared sdc controller */
};
/* mmc device structure */
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 6befefd..651cc53 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -63,6 +63,7 @@
MDP_REV_30,
MDP_REV_303,
MDP_REV_304,
+ MDP_REV_305,
MDP_REV_31,
MDP_REV_40,
MDP_REV_41,
@@ -113,6 +114,45 @@
uint8_t dst_split;
};
+struct fbc_panel_info {
+ uint32_t enabled;
+ uint32_t comp_ratio;
+ uint32_t comp_mode;
+ uint32_t qerr_enable;
+ uint32_t cd_bias;
+ uint32_t pat_enable;
+ uint32_t vlc_enable;
+ uint32_t bflc_enable;
+
+ uint32_t line_x_budget;
+ uint32_t block_x_budget;
+ uint32_t block_budget;
+
+ uint32_t lossless_mode_thd;
+ uint32_t lossy_mode_thd;
+ uint32_t lossy_rgb_thd;
+ uint32_t lossy_mode_idx;
+};
+
+/* intf timing settings */
+struct intf_timing_params {
+ uint32_t width;
+ uint32_t height;
+ uint32_t xres;
+ uint32_t yres;
+
+ uint32_t h_back_porch;
+ uint32_t h_front_porch;
+ uint32_t v_back_porch;
+ uint32_t v_front_porch;
+ uint32_t hsync_pulse_width;
+ uint32_t vsync_pulse_width;
+
+ uint32_t border_clr;
+ uint32_t underflow_clr;
+ uint32_t hsync_skew;
+};
+
struct mipi_panel_info {
char mode; /* video/cmd */
char interleave_mode;
@@ -203,6 +243,7 @@
struct lcd_panel_info lcd;
struct lcdc_panel_info lcdc;
+ struct fbc_panel_info fbc;
struct mipi_panel_info mipi;
struct lvds_panel_info lvds;
struct hdmi_panel_info hdmi;
diff --git a/platform/msm_shared/include/oem_keystore.h b/platform/msm_shared/include/oem_keystore.h
index 47b3a4f..39d5ae2 100644
--- a/platform/msm_shared/include/oem_keystore.h
+++ b/platform/msm_shared/include/oem_keystore.h
@@ -29,55 +29,55 @@
#ifndef _OEM_KEYSTORE_H
#define _OEM_KEYSTORE_H
const unsigned char OEM_KEYSTORE[] = {
- 0x30, 0x82, 0x02, 0x4c, 0x02, 0x01, 0x00, 0x30, 0x82, 0x01, 0x1d, 0x30,
- 0x82, 0x01, 0x19, 0x30, 0x0b, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7,
- 0x0d, 0x01, 0x01, 0x0b, 0x30, 0x82, 0x01, 0x08, 0x02, 0x82, 0x01, 0x01,
- 0x00, 0xc8, 0x82, 0x09, 0x43, 0x84, 0x33, 0x91, 0xfa, 0xca, 0xa1, 0x43,
- 0xc1, 0x92, 0xa9, 0x26, 0x0c, 0xe2, 0x15, 0xab, 0x71, 0xfa, 0x85, 0x97,
- 0x5f, 0xf0, 0xcd, 0x66, 0xeb, 0x7f, 0x0b, 0xc1, 0x01, 0x8e, 0x8e, 0x1b,
- 0xfa, 0xaa, 0x82, 0x21, 0xd3, 0x1d, 0x3b, 0x0a, 0x91, 0x0e, 0xcd, 0x85,
- 0xa0, 0x4d, 0xd7, 0xed, 0x27, 0x72, 0xa6, 0xb1, 0x26, 0x8e, 0xe9, 0x5f,
- 0x57, 0x77, 0x3d, 0x93, 0x79, 0x38, 0xde, 0xac, 0xa1, 0xc9, 0xd1, 0xcc,
- 0x42, 0x04, 0x53, 0x88, 0x64, 0xac, 0xaa, 0xab, 0xfc, 0xb7, 0xf0, 0x32,
- 0x2d, 0xb0, 0xf4, 0xe1, 0x35, 0x58, 0xdf, 0x5e, 0x8a, 0x47, 0x28, 0x2b,
- 0xa9, 0xda, 0x54, 0xd3, 0xbc, 0x0a, 0x12, 0x5f, 0x76, 0x5e, 0x16, 0xab,
- 0xf5, 0x9d, 0x11, 0x8f, 0x36, 0x99, 0x3a, 0x1c, 0x76, 0x95, 0x31, 0xa9,
- 0x92, 0x86, 0x81, 0xcc, 0x56, 0x56, 0x52, 0xe2, 0x70, 0xf4, 0xb3, 0x99,
- 0xe7, 0x2e, 0xdd, 0x9d, 0x33, 0xad, 0x22, 0x8a, 0x10, 0x17, 0x53, 0xf2,
- 0x6a, 0x85, 0x80, 0xad, 0x14, 0xd3, 0xa2, 0xd3, 0xe2, 0x37, 0x8a, 0x4c,
- 0xdd, 0xa2, 0xdb, 0x46, 0x32, 0xa9, 0x23, 0x46, 0x1a, 0xd5, 0x86, 0xec,
- 0x39, 0x98, 0x06, 0xd0, 0x4f, 0xe8, 0x6f, 0x02, 0x90, 0x05, 0x76, 0x3b,
- 0x8b, 0xfc, 0x86, 0x8d, 0xa1, 0x3d, 0x58, 0x80, 0xc7, 0x9e, 0x53, 0xd0,
- 0xa2, 0xb8, 0xbb, 0xc7, 0x13, 0x35, 0xcd, 0x6f, 0xc2, 0x07, 0xad, 0xa2,
- 0xe1, 0x82, 0x12, 0xf1, 0xbc, 0x4f, 0x19, 0x00, 0x0f, 0x9d, 0x9f, 0x9d,
- 0x01, 0x43, 0x24, 0xac, 0xe6, 0x30, 0x11, 0x38, 0xae, 0xa6, 0xb7, 0x47,
- 0xb3, 0x71, 0x8b, 0x79, 0x46, 0xd4, 0x3b, 0x7d, 0xf0, 0x6c, 0x84, 0xa2,
- 0x58, 0xb4, 0xe3, 0x86, 0x8f, 0xb8, 0xfc, 0xf9, 0xcb, 0x1c, 0x30, 0x17,
- 0x1e, 0x34, 0xc3, 0x98, 0xa3, 0x02, 0x01, 0x03, 0x30, 0x82, 0x01, 0x24,
- 0x02, 0x01, 0x00, 0x30, 0x0b, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7,
- 0x0d, 0x01, 0x01, 0x0b, 0x30, 0x0e, 0x13, 0x08, 0x6b, 0x65, 0x79, 0x73,
- 0x74, 0x6f, 0x72, 0x65, 0x02, 0x02, 0x01, 0x28, 0x04, 0x82, 0x01, 0x00,
- 0x96, 0x5e, 0x50, 0x0f, 0x17, 0x97, 0xed, 0x8b, 0xfe, 0x92, 0x21, 0x79,
- 0xc9, 0x55, 0x1b, 0x20, 0xb6, 0xb6, 0x8a, 0xac, 0xbc, 0xb0, 0x77, 0x8c,
- 0x46, 0xf5, 0x73, 0xc3, 0x6e, 0xf8, 0xac, 0x67, 0x48, 0x7f, 0xb0, 0x5b,
- 0xc0, 0x37, 0x4b, 0xea, 0x77, 0xcb, 0x9b, 0x8e, 0x37, 0x4a, 0x76, 0x3c,
- 0xef, 0x18, 0x42, 0x17, 0x5f, 0xa0, 0x50, 0x38, 0xdd, 0xc3, 0x19, 0xd3,
- 0x72, 0x65, 0xa5, 0x81, 0x51, 0x9e, 0x6a, 0xc6, 0x98, 0xfc, 0xba, 0x82,
- 0x8a, 0x3b, 0xc7, 0x78, 0xbc, 0x0c, 0x75, 0x70, 0x25, 0x42, 0x0c, 0xd1,
- 0xba, 0xbb, 0x8d, 0x5c, 0x34, 0xd7, 0x90, 0x08, 0xf8, 0x0a, 0x31, 0x86,
- 0xc6, 0x0a, 0x47, 0xd4, 0x69, 0x62, 0xf0, 0x03, 0x89, 0x56, 0xca, 0x42,
- 0x75, 0xf3, 0x30, 0x24, 0x6c, 0xda, 0xb0, 0x4f, 0xf4, 0xdc, 0x0c, 0xd0,
- 0x20, 0xf8, 0xb9, 0x0f, 0x16, 0x84, 0xc7, 0xca, 0xc5, 0x7b, 0x66, 0x46,
- 0x76, 0x38, 0x11, 0x2d, 0x30, 0x88, 0xc3, 0x93, 0x14, 0x91, 0xad, 0x80,
- 0x94, 0xc9, 0xab, 0x75, 0x80, 0x07, 0xde, 0xed, 0x7e, 0xfe, 0x18, 0x5c,
- 0x16, 0xfa, 0x92, 0x45, 0xf4, 0x2b, 0x59, 0xcf, 0x2b, 0xf0, 0x7b, 0x2d,
- 0xfe, 0xf4, 0x07, 0x34, 0xb4, 0xad, 0x7d, 0x1f, 0x34, 0xc1, 0x48, 0x09,
- 0xf5, 0xf8, 0x26, 0xd9, 0x3b, 0x32, 0x25, 0xb1, 0x8f, 0x48, 0x08, 0xcf,
- 0x21, 0x14, 0x16, 0x15, 0x7e, 0x58, 0x89, 0x8b, 0x2a, 0x97, 0x89, 0xa7,
- 0x3a, 0x45, 0x13, 0x3b, 0x49, 0x86, 0xfb, 0xa2, 0x2d, 0x50, 0x92, 0x44,
- 0x57, 0x89, 0x6a, 0xcc, 0xe5, 0x1c, 0xae, 0xc1, 0x84, 0xf9, 0x3b, 0x38,
- 0x0b, 0x48, 0xb3, 0x24, 0x99, 0x46, 0x4e, 0xf8, 0xe5, 0x9f, 0x01, 0xd1,
- 0xf7, 0x62, 0x1f, 0xb8, 0xb5, 0x19, 0x30, 0x7f, 0x9f, 0x2d, 0x67, 0x3c,
- 0xc6, 0x0a, 0x5c, 0x3c
+ 0x30, 0x82, 0x02, 0x4e, 0x02, 0x01, 0x00, 0x30, 0x82, 0x01, 0x1f, 0x30,
+ 0x82, 0x01, 0x1b, 0x30, 0x0b, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7,
+ 0x0d, 0x01, 0x01, 0x0b, 0x30, 0x82, 0x01, 0x0a, 0x02, 0x82, 0x01, 0x01,
+ 0x00, 0xd0, 0xc5, 0xd5, 0x6b, 0x1f, 0x64, 0x41, 0xd5, 0xe8, 0x39, 0xd7,
+ 0xbf, 0xe0, 0x06, 0x62, 0xf3, 0x5b, 0x50, 0xec, 0xd7, 0x44, 0x46, 0xe9,
+ 0xcb, 0x4d, 0x64, 0xc8, 0x71, 0xa6, 0x93, 0x0e, 0x2e, 0x71, 0x19, 0x56,
+ 0x22, 0x86, 0xbf, 0x55, 0x4d, 0x46, 0x1c, 0x6a, 0x2b, 0xf2, 0x4a, 0x4e,
+ 0xfd, 0x94, 0xba, 0x38, 0x19, 0xf7, 0x84, 0x89, 0x70, 0x3b, 0x9b, 0x1b,
+ 0xe0, 0xf0, 0x03, 0x06, 0x86, 0x64, 0xa4, 0x2a, 0x0d, 0x85, 0x1a, 0xd1,
+ 0x55, 0x36, 0x72, 0x78, 0x3c, 0x4d, 0x83, 0xdc, 0x9d, 0x81, 0x8f, 0x74,
+ 0x9e, 0xd4, 0xb1, 0xc9, 0x29, 0xea, 0xd7, 0x60, 0xeb, 0x8b, 0xe7, 0xb3,
+ 0xb7, 0xbe, 0x55, 0x57, 0xf4, 0x74, 0xec, 0x84, 0xa2, 0xf4, 0x7e, 0x27,
+ 0x27, 0x98, 0x53, 0x3d, 0x39, 0x3a, 0x15, 0x0c, 0x60, 0xff, 0x71, 0x24,
+ 0x88, 0x69, 0x03, 0x65, 0xe7, 0x5d, 0xee, 0x44, 0x91, 0xbf, 0x62, 0x4c,
+ 0x54, 0x98, 0xa3, 0xdb, 0x81, 0xa6, 0x85, 0xc3, 0x0f, 0x82, 0x18, 0xed,
+ 0xa3, 0xaa, 0x53, 0x14, 0x9b, 0xbf, 0xdc, 0x0c, 0xb7, 0x22, 0x29, 0x76,
+ 0x5f, 0xa8, 0x4e, 0x6d, 0x3e, 0x92, 0xa4, 0x51, 0x8b, 0x82, 0xa8, 0xc4,
+ 0x61, 0xd5, 0xd0, 0x2c, 0xc3, 0xb1, 0xe1, 0x14, 0xb9, 0x61, 0xbf, 0x2a,
+ 0x9f, 0xfb, 0x69, 0x51, 0x7d, 0x4a, 0x0e, 0x39, 0x35, 0xc0, 0xba, 0x29,
+ 0x8b, 0xeb, 0x1b, 0x2b, 0x14, 0x28, 0x0f, 0x81, 0xb7, 0x4f, 0x4e, 0x7d,
+ 0xe0, 0xe7, 0xfc, 0x74, 0x69, 0x4f, 0xd4, 0x9f, 0x44, 0x49, 0x49, 0x6b,
+ 0x90, 0xd1, 0x9a, 0xcd, 0xf7, 0x50, 0x15, 0x2d, 0x9e, 0x89, 0xb5, 0xe4,
+ 0x5e, 0x32, 0x77, 0x8b, 0xef, 0x16, 0x0b, 0x9b, 0x07, 0x49, 0xe4, 0x3c,
+ 0xe5, 0x2e, 0xc1, 0xf6, 0x61, 0x4c, 0x57, 0xe0, 0x7a, 0xe6, 0x38, 0x1f,
+ 0x66, 0xc7, 0x92, 0x32, 0x9b, 0x02, 0x03, 0x01, 0x00, 0x01, 0x30, 0x82,
+ 0x01, 0x24, 0x02, 0x01, 0x00, 0x30, 0x0b, 0x06, 0x09, 0x2a, 0x86, 0x48,
+ 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x30, 0x0e, 0x13, 0x08, 0x6b, 0x65,
+ 0x79, 0x73, 0x74, 0x6f, 0x72, 0x65, 0x02, 0x02, 0x01, 0x2a, 0x04, 0x82,
+ 0x01, 0x00, 0x86, 0xae, 0xa7, 0xb2, 0xa3, 0x13, 0xd4, 0x6e, 0x38, 0xde,
+ 0x0b, 0x26, 0x9a, 0x17, 0x4a, 0xda, 0x55, 0x11, 0x8a, 0xeb, 0x4c, 0xc4,
+ 0xeb, 0xcf, 0x17, 0xf0, 0x94, 0x3d, 0x5e, 0x26, 0x7c, 0xf2, 0xce, 0x66,
+ 0x05, 0x6d, 0xdf, 0xad, 0x4c, 0x90, 0xbc, 0x39, 0xf4, 0x0c, 0x61, 0x31,
+ 0xe9, 0xa7, 0x4c, 0x51, 0x2c, 0x6c, 0x47, 0x98, 0x97, 0xbe, 0xe2, 0x78,
+ 0xb8, 0x46, 0x97, 0x35, 0x2f, 0xbb, 0x1a, 0xa5, 0x99, 0x97, 0x20, 0x96,
+ 0x35, 0x2c, 0xf9, 0xd7, 0x94, 0x84, 0x56, 0x3b, 0xc4, 0xe1, 0x45, 0x6d,
+ 0x09, 0x79, 0x2d, 0x0d, 0x9b, 0x46, 0x27, 0x23, 0xb7, 0xcb, 0xb5, 0x6b,
+ 0x44, 0x29, 0x0f, 0xd5, 0x38, 0x54, 0x58, 0x20, 0x9e, 0xbe, 0xc6, 0x06,
+ 0x9b, 0x3f, 0xe0, 0xea, 0xd5, 0xae, 0x50, 0x64, 0xfb, 0xc2, 0x82, 0xca,
+ 0xf5, 0x43, 0x70, 0x91, 0x41, 0xc5, 0x47, 0x36, 0x03, 0xf0, 0xba, 0x08,
+ 0x5e, 0xd4, 0xf2, 0x4b, 0x7d, 0xaa, 0xcc, 0x11, 0xaa, 0xfe, 0x4a, 0xbd,
+ 0xa8, 0x4d, 0x52, 0xb2, 0x33, 0xaf, 0x48, 0x5d, 0x67, 0x09, 0xe7, 0xa0,
+ 0x86, 0xf6, 0x18, 0xb3, 0x10, 0xae, 0x6c, 0x48, 0xce, 0xb5, 0x30, 0x86,
+ 0x39, 0xff, 0xab, 0x7b, 0x9e, 0x81, 0xd0, 0x20, 0xea, 0xa9, 0xfa, 0x86,
+ 0xb9, 0x22, 0x4a, 0x95, 0x21, 0x32, 0x56, 0x9c, 0x27, 0xd2, 0x9e, 0xd7,
+ 0x39, 0xb7, 0x6f, 0xd8, 0xec, 0x57, 0xa6, 0xaf, 0x7b, 0xf5, 0x55, 0x1a,
+ 0x65, 0x1c, 0x4e, 0x98, 0x82, 0x00, 0x84, 0x36, 0xdd, 0xa6, 0x4d, 0xcb,
+ 0xa9, 0xb8, 0x70, 0x98, 0xbe, 0xb8, 0x38, 0xa0, 0x53, 0x2b, 0xb0, 0x88,
+ 0x00, 0x33, 0xff, 0x91, 0x5a, 0x6a, 0x27, 0x5d, 0x84, 0x44, 0xe2, 0x17,
+ 0x6e, 0xb4, 0xf0, 0x68, 0xfd, 0x68, 0x9b, 0x6a, 0x0c, 0x7e, 0x98, 0x48,
+ 0x62, 0x0c, 0xa9, 0x82, 0x34, 0x33
};
#endif
diff --git a/platform/msm_shared/include/qgic.h b/platform/msm_shared/include/qgic.h
index 45607ff..30abec5 100644
--- a/platform/msm_shared/include/qgic.h
+++ b/platform/msm_shared/include/qgic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011, 2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -56,11 +56,17 @@
#define GIC_DIST_CONFIG GIC_DIST_REG(0xc00)
#define GIC_DIST_SOFTINT GIC_DIST_REG(0xf00)
+#define INTERRUPT_LVL_N_TO_N 0x0
+#define INTERRUPT_LVL_1_TO_N 0x1
+#define INTERRUPT_EDGE_N_TO_N 0x2
+#define INTERRUPT_EDGE_1_TO_N 0x3
+
struct ihandler {
int_handler func;
void *arg;
};
void qgic_init(void);
+void qgic_change_interrupt_cfg(uint32_t spi_number, uint8_t type);
#endif
diff --git a/platform/msm_shared/include/sdhci_msm.h b/platform/msm_shared/include/sdhci_msm.h
index 79ae142..4682694 100644
--- a/platform/msm_shared/include/sdhci_msm.h
+++ b/platform/msm_shared/include/sdhci_msm.h
@@ -118,6 +118,9 @@
#define SDHCI_DLL_TIMEOUT 50
#define CDC_STATUS_TIMEOUT 50
+#define HC_IO_PAD_PWR_SWITCH_EN BIT(15)
+#define HC_IO_PAD_PWR_SWITCH BIT(16)
+
struct sdhci_msm_data
{
uint32_t pwrctl_base;
@@ -126,6 +129,7 @@
uint8_t calibration_done;
uint8_t saved_phase;
uint8_t slot;
+ uint8_t use_io_switch;
event_t* sdhc_event;
};
diff --git a/platform/msm_shared/include/ufs.h b/platform/msm_shared/include/ufs.h
index bbe9a40..b5c76fc 100644
--- a/platform/msm_shared/include/ufs.h
+++ b/platform/msm_shared/include/ufs.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -120,5 +120,6 @@
uint32_t ufs_get_serial_num(struct ufs_dev* dev);
uint8_t ufs_get_num_of_luns(struct ufs_dev* dev);
uint32_t ufs_get_erase_blk_size(struct ufs_dev* dev);
+void ufs_dump_is_register(struct ufs_dev* dev);
void ufs_dump_hc_registers(struct ufs_dev* dev);
#endif
diff --git a/platform/msm_shared/include/utp.h b/platform/msm_shared/include/utp.h
index 042c002..ff55f22 100644
--- a/platform/msm_shared/include/utp.h
+++ b/platform/msm_shared/include/utp.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -47,6 +47,7 @@
#define UTP_MUTEX_ACQUIRE_TIMEOUT 0x100000
#define UTP_GENERIC_CMD_TIMEOUT 40000
+#define UTP_MAX_COMMAND_RETRY 5000000
struct utp_prdt_entry
{
@@ -145,5 +146,5 @@
int utp_enqueue_upiu(struct ufs_dev *dev, struct upiu_req_build_type *upiu_data);
void utp_process_req_completion(struct ufs_req_irq_type *irq);
-
+int utp_poll_utrd_complete(struct ufs_dev *dev);
#endif
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index b53b3d8..f466d26 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -60,7 +60,7 @@
lcdc->h_back_porch + 1;
vsync_period_intmd = pinfo->yres + lcdc->v_front_porch + \
lcdc->v_back_porch + 1;
- if (mdp_rev == MDP_REV_304) {
+ if (mdp_rev == MDP_REV_304 || mdp_rev == MDP_REV_305) {
hsync_period += lcdc->h_pulse_width - 1;
vsync_period_intmd += lcdc->v_pulse_width - 1;
}
@@ -78,7 +78,7 @@
writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
writel(lcdc->v_pulse_width * hsync_period, \
MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
- if (mdp_rev == MDP_REV_304) {
+ if (mdp_rev == MDP_REV_304 || mdp_rev == MDP_REV_305) {
writel((pinfo->xres + lcdc->h_back_porch + \
lcdc->h_pulse_width - 1) << 16 | \
lcdc->h_back_porch + lcdc->h_pulse_width, \
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
old mode 100644
new mode 100755
index 1c0f1aa..ff0709e
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -40,6 +40,9 @@
#include <clock.h>
#include <scm.h>
+#define MDP_MIN_FETCH 9
+#define MDSS_MDP_MAX_FETCH 12
+
int restore_secure_cfg(uint32_t id);
static int mdp_rev;
@@ -121,11 +124,15 @@
*ctl1_reg_val = 0x24082;
break;
}
- /* For 8916/8939, MDP INTF registers are double buffered */
+ /* For targets from MDP v1.5, MDP INTF registers are double buffered */
if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_108)) {
*ctl0_reg_val |= BIT(30);
- *ctl1_reg_val |= BIT(30);
+ *ctl1_reg_val |= BIT(31);
+ } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) ||
+ (mdss_mdp_rev == MDSS_MDP_HW_REV_109)) {
+ *ctl0_reg_val |= BIT(30);
+ *ctl1_reg_val |= BIT(29);
}
}
@@ -356,11 +363,12 @@
{
uint32_t hsync_period, vsync_period;
uint32_t hsync_start_x, hsync_end_x;
- uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend;
+ uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
uint32_t mdss_mdp_intf_off;
uint32_t adjust_xres = 0;
struct lcdc_panel_info *lcdc = NULL;
+ struct intf_timing_params itp = {0};
if (pinfo == NULL)
return ERR_INVALID_ARGS;
@@ -384,41 +392,58 @@
writel(BIT(5), MDP_REG_PPB0_CNTL);
}
+ if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
+ pinfo->fbc.comp_ratio = 1;
+
+ itp.xres = (adjust_xres / pinfo->fbc.comp_ratio);
+ itp.yres = pinfo->yres;
+ itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio);
+ itp.height = pinfo->yres + pinfo->lcdc.yres_pad;
+ itp.h_back_porch = pinfo->lcdc.h_back_porch;
+ itp.h_front_porch = pinfo->lcdc.h_front_porch;
+ itp.v_back_porch = pinfo->lcdc.v_back_porch;
+ itp.v_front_porch = pinfo->lcdc.v_front_porch;
+ itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width;
+ itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width;
+
+ itp.border_clr = pinfo->lcdc.border_clr;
+ itp.underflow_clr = pinfo->lcdc.underflow_clr;
+ itp.hsync_skew = pinfo->lcdc.hsync_skew;
+
+
mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
- hsync_period = lcdc->h_pulse_width +
- lcdc->h_back_porch +
- adjust_xres + lcdc->xres_pad + lcdc->h_front_porch;
- vsync_period = (lcdc->v_pulse_width +
- lcdc->v_back_porch +
- pinfo->yres + lcdc->yres_pad +
- lcdc->v_front_porch);
+ hsync_period = itp.hsync_pulse_width + itp.h_back_porch +
+ itp.width + itp.h_front_porch;
+
+ vsync_period = itp.vsync_pulse_width + itp.v_back_porch +
+ itp.height + itp.v_front_porch;
hsync_start_x =
- lcdc->h_pulse_width +
- lcdc->h_back_porch;
+ itp.hsync_pulse_width +
+ itp.h_back_porch;
hsync_end_x =
- hsync_period - lcdc->h_front_porch - 1;
+ hsync_period - itp.h_front_porch - 1;
- display_vstart = (lcdc->v_pulse_width +
- lcdc->v_back_porch)
- * hsync_period + lcdc->hsync_skew;
- display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period)
- +lcdc->hsync_skew - 1;
+ display_vstart = (itp.vsync_pulse_width +
+ itp.v_back_porch)
+ * hsync_period + itp.hsync_skew;
+ display_vend = ((vsync_period - itp.v_front_porch) * hsync_period)
+ + itp.hsync_skew - 1;
if (intf_base == MDP_INTF_0_BASE) { /* eDP */
- display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch;
- display_vend -= lcdc->h_front_porch;
+ display_vstart += itp.hsync_pulse_width + itp.h_back_porch;
+ display_vend -= itp.h_front_porch;
}
- hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
+ hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off);
writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
- writel(lcdc->v_pulse_width*hsync_period,
+ writel(itp.vsync_pulse_width*hsync_period,
MDP_VSYNC_PULSE_WIDTH_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
@@ -442,6 +467,63 @@
writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
}
+void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo,
+ uint32_t intf_base)
+{
+ uint32_t mdp_hw_rev = readl(MDP_HW_REV);
+ uint32_t mdss_mdp_intf_off;
+ uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines;
+ uint32_t adjust_xres = 0;
+
+ struct lcdc_panel_info *lcdc = NULL;
+
+ if (pinfo == NULL)
+ return;
+
+ lcdc = &(pinfo->lcdc);
+ if (lcdc == NULL)
+ return;
+
+ /*
+ * MDP programmable fetch is for MDP with rev >= 1.05.
+ * Programmable fetch is not needed if vertical back porch
+ * is >= 9.
+ */
+ if (mdp_hw_rev < MDSS_MDP_HW_REV_105 ||
+ lcdc->v_back_porch >= MDP_MIN_FETCH)
+ return;
+
+ mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
+
+ adjust_xres = pinfo->xres;
+ if (pinfo->lcdc.split_display)
+ adjust_xres /= 2;
+
+ /*
+ * Fetch should always be outside the active lines. If the fetching
+ * is programmed within active region, hardware behavior is unknown.
+ */
+ v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres +
+ lcdc->v_front_porch;
+ h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres +
+ lcdc->h_front_porch;
+ vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres;
+
+ fetch_lines = v_total - vfp_start;
+
+ /*
+ * In some cases, vertical front porch is too high. In such cases limit
+ * the mdp fetch lines as the last 12 lines of vertical front porch.
+ */
+ if (fetch_lines > MDSS_MDP_MAX_FETCH)
+ fetch_lines = MDSS_MDP_MAX_FETCH;
+
+ fetch_start = (v_total - fetch_lines) * h_total + 1;
+
+ writel(fetch_start, MDP_PROG_FETCH_START + mdss_mdp_intf_off);
+ writel(BIT(31), MDP_INTF_CONFIG + mdss_mdp_intf_off);
+}
+
void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
*pinfo)
{
@@ -507,6 +589,57 @@
}
}
+void mdss_fbc_cfg(struct msm_panel_info *pinfo)
+{
+ uint32_t mode = 0;
+ uint32_t budget_ctl = 0;
+ uint32_t lossy_mode = 0;
+ uint32_t xres;
+ struct fbc_panel_info *fbc;
+ uint32_t enc_mode;
+
+ fbc = &pinfo->fbc;
+ xres = pinfo->xres;
+
+ if (!pinfo->fbc.enabled)
+ return;
+
+ if (pinfo->mipi.dual_dsi)
+ xres /= 2;
+
+ /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */
+ enc_mode = (fbc->comp_ratio == 2) ? 0 : 1;
+
+ mode = ((xres) << 16) | (enc_mode) << 9 | ((fbc->comp_mode) << 8) |
+ ((fbc->qerr_enable) << 7) | ((fbc->cd_bias) << 4) |
+ ((fbc->pat_enable) << 3) | ((fbc->vlc_enable) << 2) |
+ ((fbc->bflc_enable) << 1) | 1;
+
+ dprintf(SPEW, "xres = %d, comp_mode %d, qerr_enable = %d, cd_bias = %d\n",
+ xres, fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias);
+ dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable\n",
+ fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable);
+
+ budget_ctl = ((fbc->line_x_budget) << 12) |
+ ((fbc->block_x_budget) << 8) | fbc->block_budget;
+
+ lossy_mode = ((fbc->lossless_mode_thd) << 16) |
+ ((fbc->lossy_mode_thd) << 8) |
+ ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx;
+
+ writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE);
+ writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
+ writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
+
+ if (pinfo->mipi.dual_dsi) {
+ writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE);
+ writel(budget_ctl, MDP_PP_1_BASE +
+ MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
+ writel(lossy_mode, MDP_PP_1_BASE +
+ MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
+ }
+}
+
void mdss_qos_remapper_setup(void)
{
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
@@ -522,12 +655,15 @@
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_106) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_108) ||
- MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_105))
+ MDSS_MDP_HW_REV_108))
map = 0xE4;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_103))
+ MDSS_MDP_HW_REV_105) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_109))
+ map = 0xA4;
+ else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_103))
map = 0xFA;
else
return;
@@ -551,11 +687,12 @@
vbif_qos[1] = 2;
vbif_qos[2] = 2;
vbif_qos[3] = 2;
- } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105)) {
- vbif_qos[0] = 2;
+ } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109)) {
+ vbif_qos[0] = 1;
vbif_qos[1] = 2;
vbif_qos[2] = 2;
- vbif_qos[3] = 1;
+ vbif_qos[3] = 2;
} else {
return;
}
@@ -601,9 +738,12 @@
uint32_t reg;
mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE);
+ mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE);
- if (pinfo->mipi.dual_dsi)
+ if (pinfo->mipi.dual_dsi) {
mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE);
+ mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE);
+ }
mdp_clk_gating_ctrl();
@@ -627,6 +767,8 @@
/*If dst_split is enabled only intf 2 needs to be enabled.
CTL_1 path should not be set since CTL_0 itself is going
to split after DSPP block*/
+ if (pinfo->fbc.enabled)
+ mdss_fbc_cfg(pinfo);
if (pinfo->mipi.dual_dsi) {
if (!pinfo->lcdc.dst_split) {
@@ -745,6 +887,11 @@
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
+ if (pinfo->lcdc.dst_split) {
+ writel(BIT(16), MDP_REG_PPB0_CONFIG);
+ writel(BIT(5), MDP_REG_PPB0_CNTL);
+ }
+
mdss_mdp_intf_off = mdss_mdp_intf_offset();
mdp_clk_gating_ctrl();
@@ -771,10 +918,15 @@
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
writel(reg, MDP_CTL_0_BASE + CTL_TOP);
+ if (pinfo->fbc.enabled)
+ mdss_fbc_cfg(pinfo);
+
if (pinfo->mipi.dual_dsi) {
writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
- reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
- writel(reg, MDP_CTL_1_BASE + CTL_TOP);
+ if (!pinfo->lcdc.dst_split) {
+ reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
+ writel(reg, MDP_CTL_1_BASE + CTL_TOP);
+ }
}
return ret;
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 3878be3..2a29a7f 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -607,7 +607,8 @@
ctl_base + VIDEO_MODE_ACTIVE_V);
if (mdp_get_revision() >= MDP_REV_41 ||
- mdp_get_revision() == MDP_REV_304) {
+ mdp_get_revision() == MDP_REV_304 ||
+ mdp_get_revision() == MDP_REV_305) {
writel(((disp_height + vsync_porch0_fp
+ vsync_porch0_bp - 1) << 16)
| (disp_width + hsync_porch0_fp
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index a31cf87..411f22c 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -1091,6 +1091,7 @@
data->pwrctl_base = cfg->pwrctl_base;
data->pwr_irq = cfg->pwr_irq;
data->slot = cfg->slot;
+ data->use_io_switch = cfg->use_io_switch;
host->msm_host = data;
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index 276840b..c660a5f 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -357,6 +357,15 @@
blk_addr += unaligned_blks;
blk_count -= unaligned_blks;
+
+ head_unit = blk_addr / erase_unit_sz;
+ tail_unit = (blk_addr + blk_count - 1) / erase_unit_sz;
+
+ if (tail_unit - head_unit <= 1)
+ {
+ dprintf(INFO, "SDHCI unit erase not required\n");
+ return mmc_zero_out(dev, blk_addr, blk_count);
+ }
}
unaligned_blks = blk_count % erase_unit_sz;
diff --git a/platform/msm_shared/qgic.c b/platform/msm_shared/qgic.c
index 48e846d..49299e7 100644
--- a/platform/msm_shared/qgic.c
+++ b/platform/msm_shared/qgic.c
@@ -32,6 +32,7 @@
*/
#include <reg.h>
+#include <bits.h>
#include <debug.h>
#include <arch/arm.h>
#include <kernel/thread.h>
@@ -179,3 +180,24 @@
handler[vector].arg = arg;
exit_critical_section();
}
+
+void qgic_change_interrupt_cfg(uint32_t spi_number, uint8_t type)
+{
+ uint32_t register_number, register_address, bit_number, value;
+ register_number = spi_number >> 4; // r = n DIV 16
+ bit_number = (spi_number % 16) << 1; // b = (n MOD 16) * 2
+ value = readl(GIC_DIST_CONFIG + (register_number << 2));
+ // there are two bits per register to indicate the level
+ if (type == INTERRUPT_LVL_N_TO_N)
+ value &= ~(BIT(bit_number)|BIT(bit_number+1)); // 0x0 0x0
+ else if (type == INTERRUPT_LVL_1_TO_N)
+ value = (value & ~BIT(bit_number+1)) | BIT(bit_number); // 0x0 0x1
+ else if (type == INTERRUPT_EDGE_N_TO_N)
+ value = BIT(bit_number+1) | (value & ~BIT(bit_number));// 0x1 0x0
+ else if (type == INTERRUPT_EDGE_1_TO_N)
+ value |= (BIT(bit_number)|BIT(bit_number+1)); // 0x1 0x1
+ else
+ dprintf(CRITICAL, "Invalid interrupt type change requested\n");
+ register_address = GIC_DIST_CONFIG + (register_number << 2);
+ writel(value, register_address);
+}
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index f21e032..ecb5bbb 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -68,6 +68,7 @@
{0x2690AC2C, 0xFFFFFFFF, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
{0x1590ACAD, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x80, 0},
{0x9590DC2C, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0x40, 0},
+ {0x1590aa98, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0x80, 1},
/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
};
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index 6675d67..fce33f2 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -31,6 +31,11 @@
#include <bits.h>
#include <debug.h>
+__WEAK int platform_is_msm8994()
+{
+ return 0;
+}
+
void qusb2_phy_reset(void)
{
uint32_t val;
@@ -61,7 +66,8 @@
/* Disable the PHY */
writel(0x23, QUSB2PHY_PORT_POWERDOWN);
/* Enable ULPI mode */
- writel(0x0, QUSB2PHY_PORT_UTMI_CTRL2);
+ if (platform_is_msm8994())
+ writel(0x0, QUSB2PHY_PORT_UTMI_CTRL2);
/* Enable PHY */
/* set CLAMP_N_EN and USB PHY is enabled*/
writel(0x22, QUSB2PHY_PORT_POWERDOWN);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index dd9d160..9d9196c 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -471,7 +471,12 @@
$(LOCAL_DIR)/shutdown_detect.o \
$(LOCAL_DIR)/certificate.o \
$(LOCAL_DIR)/image_verify.o \
- $(LOCAL_DIR)/i2c_qup.o
+ $(LOCAL_DIR)/i2c_qup.o \
+ $(LOCAL_DIR)/mdp3.o \
+ $(LOCAL_DIR)/display.o \
+ $(LOCAL_DIR)/mipi_dsi.o \
+ $(LOCAL_DIR)/mipi_dsi_phy.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll.o
endif
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index 5a7795f..d72d90d 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -142,6 +142,8 @@
*/
void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *config)
{
+ uint32_t io_switch;
+
/* Disable HC mode */
RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, 0);
@@ -163,6 +165,19 @@
sdhci_reset(host, SDHCI_SOFT_RESET);
/*
+ * Some platforms have same SDC instance shared between emmc & sd card.
+ * For such platforms the emmc IO voltage has to be switched from 3.3 to
+ * 1.8 for the contoller to work with emmc.
+ */
+
+ if(config->use_io_switch)
+ {
+ io_switch = REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC);
+ io_switch |= HC_IO_PAD_PWR_SWITCH | HC_IO_PAD_PWR_SWITCH_EN;
+ REG_WRITE32(host, io_switch, SDCC_VENDOR_SPECIFIC_FUNC);
+ }
+
+ /*
* CORE_SW_RST may trigger power irq if previous status of PWRCTL
* was either BUS_ON or IO_HIGH. So before we enable the power irq
* interrupt in GIC (by registering the interrupt handler), we need to
@@ -478,8 +493,8 @@
DBG("\n CM_DLL_SDC4 Calibration Start\n");
- /*1.Write the default value to SDCC_HC_REG_DDR_CONFIG register*/
- REG_WRITE32(host, DDR_CONFIG_VAL, SDCC_HC_REG_DDR_CONFIG);
+ /*1.Write the DDR config value to SDCC_HC_REG_DDR_CONFIG register*/
+ REG_WRITE32(host, target_ddr_cfg_val(), SDCC_HC_REG_DDR_CONFIG);
/*2. Write DDR_CAL_EN to '1' */
REG_WRITE32(host, (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) | DDR_CAL_EN), SDCC_HC_REG_DLL_CONFIG_2);
diff --git a/platform/msm_shared/ufs.c b/platform/msm_shared/ufs.c
index 8244576..1fd26b4 100644
--- a/platform/msm_shared/ufs.c
+++ b/platform/msm_shared/ufs.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -34,8 +34,10 @@
#include <uic.h>
#include <ucs.h>
#include <dme.h>
+#include <qgic.h>
#include <string.h>
#include <platform/iomap.h>
+#include <platform/irqs.h>
#include <kernel/mutex.h>
static int ufs_dev_init(struct ufs_dev *dev)
@@ -81,8 +83,10 @@
writel(1, UFS_UTRLRSR(dev->base));
/* Enable the required irqs. */
- val = UFS_IE_UTRCE | UFS_IE_UEE | UFS_IE_UTMRCE | UFS_IE_UCCE ;
+ val = UFS_IE_UEE | UFS_IE_UCCE ;
ufs_irq_enable(dev, val);
+ // Change UFS_IRQ to level based
+ qgic_change_interrupt_cfg(UFS_IRQ, INTERRUPT_LVL_N_TO_N);
}
int ufs_read(struct ufs_dev* dev, uint64_t start_lba, addr_t buffer, uint32_t num_blocks)
@@ -266,6 +270,12 @@
return ret;
}
+void ufs_dump_is_register(struct ufs_dev *dev)
+{
+ uint32_t base = dev->base;
+ dprintf(CRITICAL,"UFS_IS 0x%x\n",readl(UFS_IS(base)));
+}
+
void ufs_dump_hc_registers(struct ufs_dev *dev)
{
uint32_t base = dev->base;
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
index ccaa3b5..d8858b9 100644
--- a/platform/msm_shared/usb30_dwc.c
+++ b/platform/msm_shared/usb30_dwc.c
@@ -456,6 +456,7 @@
for (uint8_t ep_index = 2; ep_index < DWC_MAX_NUM_OF_EP; ep_index++)
{
dwc_ep_t *ep = &dev->ep[ep_index];
+ ASSERT(ep != NULL);
DBG("\n RESET on EP = %d while state = %s", ep_index,
ep_state_lookup[ep->state]);
@@ -489,7 +490,7 @@
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -573,7 +574,11 @@
uint8_t status = 0;
uint8_t trb_updated = 0;
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[index];
+ ASSERT(ep != NULL);
+
dwc_trb_t *trb = ep->trb;
uint32_t num_of_trb = ep->trb_queued;
uint32_t bytes_remaining = 0;
@@ -641,7 +646,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -756,7 +761,7 @@
uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -930,6 +935,8 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
+
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1011,7 +1018,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1085,7 +1092,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1164,7 +1171,7 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1239,7 +1246,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1289,7 +1296,7 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1373,7 +1380,7 @@
uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
#endif
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1433,6 +1440,7 @@
*/
static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index)
{
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
uint8_t ep_phy_num = dev->ep[index].phy_num;
dwc_ep_cmd_set_config(dev, index, SET_CONFIG_ACTION_INIT);
@@ -1455,6 +1463,7 @@
/* Control OUT */
index = DWC_EP_INDEX(0, DWC_EP_DIRECTION_OUT);
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dev->ep[index].number = 0;
dev->ep[index].dir = DWC_EP_DIRECTION_OUT;
@@ -1525,7 +1534,9 @@
/* entry function into inactive state for data transfer fsm */
static void dwc_ep_bulk_state_inactive_enter(dwc_dev_t *dev, uint8_t ep_phy_num)
{
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+ ASSERT(ep != NULL);
/* queue request to receive the first setup pkt from host */
ep->req.data = NULL;
@@ -1605,7 +1616,9 @@
{
uint8_t index = DWC_EP_INDEX(new_ep->number, new_ep->dir);
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[index];
+ ASSERT(ep != NULL);
memset(ep, 0, sizeof(ep));
@@ -1691,7 +1704,9 @@
uint8_t ep_phy_num,
dwc_request_t *req)
{
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+ ASSERT(ep != NULL);
dwc_trb_t *trb = ep->trb;
uint8_t *data_ptr = req->data;
diff --git a/platform/msm_shared/utp.c b/platform/msm_shared/utp.c
index c7d30ff..317cd69 100644
--- a/platform/msm_shared/utp.c
+++ b/platform/msm_shared/utp.c
Binary files differ
diff --git a/platform/msmzirc/gpio.c b/platform/msmzirc/gpio.c
index 98ff2e4..b285906 100644
--- a/platform/msmzirc/gpio.c
+++ b/platform/msmzirc/gpio.c
@@ -64,13 +64,13 @@
void gpio_config_uart_dm(uint8_t id)
{
- if (id == 2)
+ if (id == 3)
{
/* configure rx gpio. */
- gpio_tlmm_config(9, 1, GPIO_INPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(9, 3, GPIO_INPUT, GPIO_NO_PULL, GPIO_6MA, GPIO_DISABLE);
/* configure tx gpio. */
- gpio_tlmm_config(8, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(8, 3, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_6MA, GPIO_DISABLE);
}
else
{
diff --git a/platform/msmzirc/include/platform/iomap.h b/platform/msmzirc/include/platform/iomap.h
index be34590..5aefde8 100644
--- a/platform/msmzirc/include/platform/iomap.h
+++ b/platform/msmzirc/include/platform/iomap.h
@@ -36,8 +36,8 @@
#define APPS_SS_BASE 0x0B000000
-#define MSM_IOMAP_BASE 0x0078000
-#define MSM_IOMAP_END 0x0BFFFFFF
+#define MSM_IOMAP_BASE 0x00000000
+#define MSM_IOMAP_END 0x80000000
#define SYSTEM_IMEM_BASE 0x08600000
#define MSM_SHARED_IMEM_BASE 0x08600000
@@ -68,6 +68,7 @@
#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
+#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x000B1000)
#define MSM_USB30_BASE 0x08A00000
#define MSM_USB30_QSCRATCH_BASE 0x08AF8800
@@ -127,8 +128,8 @@
#define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x403C)
#define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x4044)
-#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x4848)
-#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x484C)
+#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x4048)
+#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x404C)
#define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x4050)
#define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x4054)
@@ -156,6 +157,7 @@
#define USB3_PIPE_CFG_RCGR (CLK_CTL_BASE + 0x5E04C)
#define USB_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x5E080)
#define USB3_PIPE_CBCR (CLK_CTL_BASE + 0x5E040)
+#define USB3_PIPE_BCR (CLK_CTL_BASE + 0x5E03C)
#define USB3_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5E05C)
#define USB3_AUX_CFG_RCGR (CLK_CTL_BASE + 0x5E060)
diff --git a/platform/msmzirc/msmzirc-clock.c b/platform/msmzirc/msmzirc-clock.c
index ca97cb0..497ed35 100644
--- a/platform/msmzirc/msmzirc-clock.c
+++ b/platform/msmzirc/msmzirc-clock.c
@@ -55,6 +55,7 @@
.enable = clock_lib2_branch_clk_enable,
.disable = clock_lib2_branch_clk_disable,
.set_rate = clock_lib2_branch_set_rate,
+ .reset = clock_lib2_branch_clk_reset,
};
static struct clk_ops clk_ops_rcg_mnd =
@@ -188,31 +189,31 @@
F_END
};
-static struct rcg_clk blsp1_uart2_apps_clk_src =
+static struct rcg_clk blsp1_uart3_apps_clk_src =
{
- .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+ .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART3_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART3_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART3_APPS_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "blsp1_uart2_apps_clk",
+ .dbg_name = "blsp1_uart3_apps_clk",
.ops = &clk_ops_rcg_mnd,
},
};
-static struct branch_clk gcc_blsp1_uart2_apps_clk =
+static struct branch_clk gcc_blsp1_uart3_apps_clk =
{
- .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
+ .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR,
+ .parent = &blsp1_uart3_apps_clk_src.c,
.c = {
- .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .dbg_name = "gcc_blsp1_uart3_apps_clk",
.ops = &clk_ops_branch,
},
};
@@ -307,6 +308,7 @@
static struct branch_clk gcc_usb30_pipe_clk = {
.cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
+ .bcr_reg = (uint32_t *) USB3_PIPE_BCR,
.parent = &usb30_pipe_clk_src.c,
.has_sibling = 0,
@@ -371,8 +373,8 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
- CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
- CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+ CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c),
CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
diff --git a/platform/msmzirc/platform.c b/platform/msmzirc/platform.c
index bed6f22..7b9c115 100644
--- a/platform/msmzirc/platform.c
+++ b/platform/msmzirc/platform.c
@@ -50,17 +50,12 @@
#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE)
/* Scratch memory - Strongly ordered, non-executable */
-#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL | \
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
/* Peripherals - shared device */
#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
-#define SCRATCH_REGION1_VIRT_START SCRATCH_REGION1
-#define SCRATCH_REGION2_VIRT_START SCRATCH_REGION2
-
-#define SDRAM_BANK0_LAST_FIXED_ADDR (SCRATCH_REGION2 + SCRATCH_REGION2_SIZE)
-
/* Map all the accesssible memory according to the following rules:
* 1. Map 1MB from MSM_SHARED_BASE with 1 -1 mapping.
* 2. Map MEMBASE - MEMSIZE with 1 -1 mapping.
@@ -74,12 +69,16 @@
{MSM_SHARED_BASE, MSM_SHARED_BASE, 1, SCRATCH_MEMORY},
{MEMBASE, MEMBASE, MEMSIZE / MB, LK_MEMORY},
{MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
- {SCRATCH_REGION1, SCRATCH_REGION1_VIRT_START, SCRATCH_REGION1_SIZE / MB, SCRATCH_MEMORY},
- {SCRATCH_REGION2, SCRATCH_REGION2_VIRT_START, SCRATCH_REGION2_SIZE / MB, SCRATCH_MEMORY},
+ {SCRATCH_REGION1, SCRATCH_REGION1, SCRATCH_REGION1_SIZE / MB, SCRATCH_MEMORY},
+ {SCRATCH_REGION2, SCRATCH_REGION2, SCRATCH_REGION2_SIZE / MB, SCRATCH_MEMORY},
+ {KERNEL_REGION, KERNEL_REGION, KERNEL_REGION_SIZE / MB, SCRATCH_MEMORY},
};
void platform_early_init(void)
{
+ /* Read boot config for identifying boot device */
+ platform_read_boot_config();
+
/* Initialize board identifier data */
board_init();
@@ -126,41 +125,7 @@
{
uint32_t i;
uint32_t sections;
- ram_partition ptn_entry;
uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- uint32_t len = 0;
-
- ASSERT(smem_ram_ptable_init_v1());
-
- len = smem_get_ram_ptable_len();
-
- /* Configure the MMU page entries for SDRAM and IMEM memory read
- from the smem ram table*/
- for(i = 0; i < len; i++)
- {
- smem_get_ram_ptable_entry(&ptn_entry, i);
- if(ptn_entry.type == SYS_MEMORY)
- {
- if((ptn_entry.category == SDRAM) ||
- (ptn_entry.category == IMEM))
- {
- /* Check to ensure that start address is 1MB aligned */
- ASSERT((ptn_entry.start & (MB-1)) == 0);
-
- sections = (ptn_entry.size) / MB;
- while(sections--)
- {
- arm_mmu_map_section(ptn_entry.start +
- sections * MB,
- ptn_entry.start +
- sections * MB,
- (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH |
- MMU_MEMORY_AP_READ_WRITE |
- MMU_MEMORY_XN));
- }
- }
- }
- }
/* Configure the MMU page entries for memory read from the
mmu_section_table */
@@ -181,50 +146,12 @@
addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
{
- uint32_t paddr;
- uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- uint32_t limit;
-
- for (uint32_t i = 0; i < table_size; i++)
- {
- limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
-
- if (virt_addr >= mmu_section_table[i].vaddress &&
- virt_addr <= (mmu_section_table[i].vaddress + limit))
- {
- paddr = mmu_section_table[i].paddress + (virt_addr - mmu_section_table[i].vaddress);
- return paddr;
- }
- }
- /* No special mapping found.
- * Assume 1-1 mapping.
- */
- paddr = virt_addr;
- return paddr;
+ /* Fixed 1-1 mapping */
+ return virt_addr;
}
addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
{
- uint32_t vaddr;
- uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- uint32_t limit;
-
- for (uint32_t i = 0; i < table_size; i++)
- {
- limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
-
- if (phys_addr >= mmu_section_table[i].paddress &&
- phys_addr <= (mmu_section_table[i].paddress + limit))
- {
- vaddr = mmu_section_table[i].vaddress + (phys_addr - mmu_section_table[i].paddress);
- return vaddr;
- }
- }
-
- /* No special mapping found.
- * Assume 1-1 mapping.
- */
- vaddr = phys_addr;
-
- return vaddr;
+ /* Fixed 1-1 mapping */
+ return phys_addr;
}
diff --git a/project/msm8909.mk b/project/msm8909.mk
index 1f013f1..0ffce48 100644
--- a/project/msm8909.mk
+++ b/project/msm8909.mk
@@ -9,6 +9,9 @@
DEBUG := 1
EMMC_BOOT := 1
+ENABLE_SMD_SUPPORT := 1
+ENABLE_BOOT_CONFIG_SUPPORT := 1
+
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
#DEFINES += WITH_DEBUG_FBCON=1
@@ -22,6 +25,11 @@
DEFINES += ABOOT_FORCE_TAGS_ADDR=0x81E00000
DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x00080000
+DEFINES += BAM_V170=1
+
+#Enable the feature of long press power on
+DEFINES += LONG_PRESS_POWER_ON=1
+
#Disable thumb mode
ENABLE_THUMB := false
@@ -31,6 +39,17 @@
DEFINES += MMC_SDHCI_SUPPORT=1
endif
+#enable power on vibrator feature
+ENABLE_PON_VIB_SUPPORT := true
+
ifeq ($(EMMC_BOOT),1)
DEFINES += _EMMC_BOOT=1
endif
+
+ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
+DEFINES += PON_VIB_SUPPORT=1
+endif
+
+ifeq ($(ENABLE_SMD_SUPPORT),1)
+DEFINES += SMD_SUPPORT=1
+endif
diff --git a/project/msm8916.mk b/project/msm8916.mk
index 1984ab2..5f51f80 100644
--- a/project/msm8916.mk
+++ b/project/msm8916.mk
@@ -25,11 +25,6 @@
DEFINES += BAM_V170=1
DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
-DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80008000
-DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x80080000
-DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82000000
-DEFINES += ABOOT_FORCE_TAGS_ADDR=0x81E00000
-
#Enable the feature of long press power on
DEFINES += LONG_PRESS_POWER_ON=1
diff --git a/project/msmzirc.mk b/project/msmzirc.mk
index f021b26..3cec784 100644
--- a/project/msmzirc.mk
+++ b/project/msmzirc.mk
@@ -18,6 +18,7 @@
DEFINES += SPMI_CORE_V2=1
DEFINES += BAM_V170=1
DEFINES += USE_BOOTDEV_CMDLINE=1
+DEFINES += USE_MDM_BOOT_CFG=1
ifeq ($(ENABLE_USB30_SUPPORT),1)
DEFINES += USB30_SUPPORT=1
diff --git a/target/init.c b/target/init.c
index 78feeea..79e0466 100644
--- a/target/init.c
+++ b/target/init.c
@@ -25,6 +25,7 @@
#include <target.h>
#include <compiler.h>
#include <dload_util.h>
+#include <sdhci_msm.h>
#define EXPAND(NAME) #NAME
#define TARGET(NAME) EXPAND(NAME)
@@ -197,3 +198,9 @@
__WEAK void target_crypto_init_params()
{
}
+
+/* Default CFG delay value */
+__WEAK uint32_t target_ddr_cfg_val()
+{
+ return DDR_CONFIG_VAL;
+}
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index aec33ec..81ee581 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -450,6 +450,9 @@
if (target_is_ssd_enabled())
clock_ce_disable(SSD_CE_INSTANCE);
+
+ /* Disable HC mode before jumping to kernel */
+ sdhci_mode_disable(&dev->host);
}
void target_usb_init(void)
diff --git a/target/msm8909/include/target/display.h b/target/msm8909/include/target/display.h
new file mode 100644
index 0000000..74613c0
--- /dev/null
+++ b/target/msm8909/include/target/display.h
@@ -0,0 +1,111 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_MSM8909_DISPLAY_H
+#define _TARGET_MSM8909_DISPLAY_H
+
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
+
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 25, 3, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {
+ "msmgpio", 97, 3, 1, 0, 1
+};
+
+static struct gpio_pin bkl_gpio = {
+ "msmgpio", 98, 3, 1, 0, 1
+};
+
+static struct gpio_pin enp_gpio = {
+ "msmgpio", 97, 3, 1, 0, 1
+};
+
+static struct gpio_pin enn_gpio = {
+ "msmgpio", 32, 3, 1, 0, 1
+};
+
+static struct gpio_pin te_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+static struct gpio_pin pwm_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0xff, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x00, 0x00, 0xb1, 0xff, 0x00, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01
+};
+
+static const char panel_lane_config[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x5f, 0x00, 0x00, 0x10
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+#define DISPLAY_CMDLINE_PREFIX " mdss_mdp.panel="
+
+#define MIPI_FB_ADDR 0x83200000
+
+#define MIPI_HSYNC_PULSE_WIDTH 12
+#define MIPI_HSYNC_BACK_PORCH_DCLK 32
+#define MIPI_HSYNC_FRONT_PORCH_DCLK 144
+
+#define MIPI_VSYNC_PULSE_WIDTH 4
+#define MIPI_VSYNC_BACK_PORCH_LINES 3
+#define MIPI_VSYNC_FRONT_PORCH_LINES 9
+
+#endif
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 604e0ba..b0eed95 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -47,10 +47,61 @@
#include <partition_parser.h>
#include <stdlib.h>
#include <gpio.h>
+#include <rpm-smd.h>
+#include <qpic_nand.h>
+
+#if LONG_PRESS_POWER_ON
+#include <shutdown_detect.h>
+#endif
+
+#if PON_VIB_SUPPORT
+#include <vibrator.h>
+#endif
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
+#define TLMM_VOL_UP_BTN_GPIO 90
+#if PON_VIB_SUPPORT
+#define VIBRATE_TIME 250
+#endif
+
+#define FASTBOOT_MODE 0x77665500
+
+#define CE1_INSTANCE 1
+#define CE_EE 1
+#define CE_FIFO_SIZE 64
+#define CE_READ_PIPE 3
+#define CE_WRITE_PIPE 2
+#define CE_READ_PIPE_LOCK_GRP 0
+#define CE_WRITE_PIPE_LOCK_GRP 0
+#define CE_ARRAY_SIZE 20
+
+extern void smem_ptable_init(void);
+extern void smem_add_modem_partitions(struct ptable *flash_ptable);
+void target_sdc_init();
+
+static struct ptable flash_ptable;
+
+/* NANDc BAM pipe numbers */
+#define DATA_CONSUMER_PIPE 0
+#define DATA_PRODUCER_PIPE 1
+#define CMD_PIPE 2
+
+/* NANDc BAM pipe groups */
+#define DATA_PRODUCER_PIPE_GRP 0
+#define DATA_CONSUMER_PIPE_GRP 0
+#define CMD_PIPE_GRP 1
+
+/* NANDc EE */
+#define QPIC_NAND_EE 0
+
+/* NANDc max desc length. */
+#define QPIC_NAND_MAX_DESC_LEN 0x7FFF
+
+#define LAST_NAND_PTN_LEN_PATTERN 0xFFFFFFFF
+
+struct qpic_nand_init_config config;
struct mmc_device *dev;
@@ -65,13 +116,49 @@
static void set_sdc_power_ctrl(void);
+void update_ptable_names(void)
+{
+ uint32_t ptn_index;
+ struct ptentry *ptentry_ptr = flash_ptable.parts;
+ struct ptentry *boot_ptn;
+ unsigned i;
+ uint32_t len;
+
+ /* Change all names to lower case. */
+ for (ptn_index = 0; ptn_index != (uint32_t)flash_ptable.count; ptn_index++)
+ {
+ len = strlen(ptentry_ptr[ptn_index].name);
+
+ for (i = 0; i < len; i++)
+ {
+ if (isupper(ptentry_ptr[ptn_index].name[i]))
+ {
+ ptentry_ptr[ptn_index].name[i] = tolower(ptentry_ptr[ptn_index].name[i]);
+ }
+ }
+
+ /* SBL fills in the last partition length as 0xFFFFFFFF.
+ * Update the length field based on the number of blocks on the flash.
+ */
+ if ((uint32_t)(ptentry_ptr[ptn_index].length) == LAST_NAND_PTN_LEN_PATTERN)
+ {
+ ptentry_ptr[ptn_index].length = flash_num_blocks() - ptentry_ptr[ptn_index].start;
+ }
+ }
+}
+
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(1, 0, BLSP1_UART1_BASE);
+ uart_dm_init(1, 0, BLSP1_UART0_BASE);
#endif
}
+int target_is_emmc_boot(void)
+{
+ return platform_boot_dev_isemmc();
+}
+
void target_sdc_init()
{
struct mmc_config_data config;
@@ -109,8 +196,40 @@
return (void *) dev;
}
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ uint8_t status = 0;
+
+ gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE);
+
+ /* Wait for the gpio config to take effect - debounce time */
+ thread_sleep(10);
+
+ /* Get status of GPIO */
+ status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
+
+ /* Active low signal. */
+ return !status;
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ /* Volume down button tied in with PMIC RESIN. */
+ return pm8x41_resin_status();
+}
+
static void target_keystatus()
{
+ keys_init();
+
+ if(target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if(target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
+
}
static void set_sdc_power_ctrl()
@@ -147,14 +266,54 @@
target_keystatus();
- target_sdc_init();
+ platform_read_boot_config();
- if (partition_read_table())
- {
- dprintf(CRITICAL, "Error reading the partition table info\n");
- ASSERT(0);
+ if (platform_boot_dev_isemmc()) {
+ target_sdc_init();
+ if (partition_read_table())
+ {
+ dprintf(CRITICAL, "Error reading the partition table info\n");
+ ASSERT(0);
+ }
+
+ } else {
+ config.pipes.read_pipe = DATA_PRODUCER_PIPE;
+ config.pipes.write_pipe = DATA_CONSUMER_PIPE;
+ config.pipes.cmd_pipe = CMD_PIPE;
+
+ config.pipes.read_pipe_grp = DATA_PRODUCER_PIPE_GRP;
+ config.pipes.write_pipe_grp = DATA_CONSUMER_PIPE_GRP;
+ config.pipes.cmd_pipe_grp = CMD_PIPE_GRP;
+
+ config.bam_base = MSM_NAND_BAM_BASE;
+ config.nand_base = MSM_NAND_BASE;
+ config.ee = QPIC_NAND_EE;
+ config.max_desc_len = QPIC_NAND_MAX_DESC_LEN;
+
+ qpic_nand_init(&config);
+
+ ptable_init(&flash_ptable);
+ smem_ptable_init();
+ smem_add_modem_partitions(&flash_ptable);
+
+ update_ptable_names();
+ flash_set_ptable(&flash_ptable);
}
+#if LONG_PRESS_POWER_ON
+ shutdown_detect();
+#endif
+
+#if PON_VIB_SUPPORT
+
+ /* turn on vibrator to indicate that phone is booting up to end user */
+ vib_timed_turn_on(VIBRATE_TIME);
+#endif
+
+ if (target_use_signed_kernel())
+ target_crypto_init_params();
+
+ rpm_smd_init();
}
void target_serialno(unsigned char *buf)
@@ -168,6 +327,93 @@
unsigned board_machtype(void)
{
+ return LINUX_MACHTYPE_UNKNOWN;
+}
+
+unsigned check_reboot_mode(void)
+{
+ uint32_t restart_reason = 0;
+
+ /* Read reboot reason and scrub it */
+ restart_reason = readl(RESTART_REASON_ADDR);
+ writel(0x00, RESTART_REASON_ADDR);
+
+ return restart_reason;
+}
+
+static int scm_dload_mode(int mode)
+{
+ int ret = 0;
+ uint32_t dload_type;
+
+ dprintf(SPEW, "DLOAD mode: %d\n", mode);
+ if (mode == NORMAL_DLOAD)
+ dload_type = SCM_DLOAD_MODE;
+ else if(mode == EMERGENCY_DLOAD)
+ dload_type = SCM_EDLOAD_MODE;
+ else
+ dload_type = 0;
+
+ ret = scm_call_atomic2(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0);
+ if (ret)
+ dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret);
+
+ ret = scm_call_atomic2(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
+ if (ret)
+ dprintf(CRITICAL, "Failed to disable the wdog debug \n");
+
+ return ret;
+}
+
+/* Configure PMIC and Drop PS_HOLD for shutdown */
+void shutdown_device()
+{
+ dprintf(CRITICAL, "Going down for shutdown.\n");
+
+ /* Configure PMIC for shutdown */
+ pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+ uint8_t reset_type = 0;
+ uint32_t ret = 0;
+
+ /* Need to clear the SW_RESET_ENTRY register and
+ * write to the BOOT_MISC_REG for known reset cases
+ */
+ if(reboot_reason != DLOAD)
+ scm_dload_mode(NORMAL_MODE);
+
+ writel(reboot_reason, RESTART_REASON_ADDR);
+
+ /* For Reboot-bootloader and Dload cases do a warm reset
+ * For Reboot cases do a hard reset
+ */
+ if((reboot_reason == FASTBOOT_MODE) || (reboot_reason == DLOAD))
+ reset_type = PON_PSHOLD_WARM_RESET;
+ else
+ reset_type = PON_PSHOLD_HARD_RESET;
+
+ pm8x41_reset_configure(reset_type);
+
+ ret = scm_halt_pmic_arbiter();
+
+ if (ret)
+ dprintf(CRITICAL , "Failed to halt pmic arbiter: %d\n", ret);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "Rebooting failed\n");
}
/* Detect the target type */
@@ -202,4 +448,256 @@
ASSERT(0);
};
}
+uint8_t target_panel_auto_detect_enabled()
+{
+ uint8_t ret = 0;
+ switch(board_hardware_id()) {
+ default:
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+
+static uint8_t splash_override;
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+ uint8_t splash_screen = 0;
+ if (!splash_override) {
+ switch (board_hardware_id()) {
+ default:
+ splash_screen = 0;
+ break;
+ }
+ dprintf(SPEW, "Target_cont_splash=%d\n", splash_screen);
+ }
+ return splash_screen;
+}
+
+void target_force_cont_splash_disable(uint8_t override)
+{
+ splash_override = override;
+}
+
+int get_target_boot_params(const char *cmdline, const char *part, char *buf,
+ int buflen)
+{
+ struct ptable *ptable;
+ int system_ptn_index = -1;
+
+ if (!target_is_emmc_boot()) {
+ if (!cmdline || !part || !buf || buflen < 0) {
+ dprintf(CRITICAL, "WARN: Invalid input param\n");
+ return -1;
+ }
+
+ ptable = flash_get_ptable();
+ if (!ptable) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get flash partition table\n");
+ return -1;
+ }
+
+ system_ptn_index = ptable_get_index(ptable, part);
+ if (system_ptn_index < 0) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get partition index for %s\n", part);
+ return -1;
+ }
+
+ /*
+ * check if cmdline contains "root=" at the beginning of buffer or
+ * " root=" in the middle of buffer.
+ */
+ if (((!strncmp(cmdline, "root=", strlen("root="))) ||
+ (strstr(cmdline, " root="))))
+ dprintf(DEBUG, "DEBUG: cmdline has root=\n");
+ else
+ snprintf(buf, buflen, " root=/dev/mtdblock%d",
+ system_ptn_index);
+ }
+
+ return 0;
+}
+
+unsigned target_baseband()
+{
+ return board_baseband();
+}
+
+int emmc_recovery_init(void)
+{
+ return _emmc_recovery_init();
+}
+
+void target_usb_init(void)
+{
+ uint32_t val;
+
+ /* Select and enable external configuration with USB PHY */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
+
+ /* Enable sess_vld */
+ val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
+ writel(val, USB_GENCONFIG_2);
+
+ /* Enable external vbus configuration in the LINK */
+ val = readl(USB_USBCMD);
+ val |= SESS_VLD_CTRL;
+ writel(val, USB_USBCMD);
+}
+
+unsigned target_pause_for_battery_charge(void)
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+ uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /* In case of fastboot reboot,adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ return 1;
+ else
+ return 0;
+}
+
+void target_usb_stop(void)
+{
+ /* Disable VBUS mimicing in the controller. */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
+}
+
+
+void target_uninit(void)
+{
+#if PON_VIB_SUPPORT
+ /* wait for the vibrator timer is expried */
+ wait_vib_timeout();
+#endif
+
+ if (platform_boot_dev_isemmc())
+ {
+ mmc_put_card_to_sleep(dev);
+ sdhci_mode_disable(&dev->host);
+ }
+
+ if (crypto_initialized())
+ crypto_eng_cleanup();
+
+ if (target_is_ssd_enabled())
+ clock_ce_disable(CE1_INSTANCE);
+
+ rpm_smd_uninit();
+}
+
+/* Do any target specific intialization needed before entering fastboot mode */
+void target_fastboot_init(void)
+{
+ /* Set the BOOT_DONE flag in PM8916 */
+ pm8x41_set_boot_done();
+
+ if (target_is_ssd_enabled()) {
+ clock_ce_enable(CE1_INSTANCE);
+ target_load_ssd_keystore();
+ }
+}
+
+int set_download_mode(enum dload_mode mode)
+{
+ int ret = 0;
+ ret = scm_dload_mode(mode);
+
+ pm8x41_clear_pmic_watchdog();
+
+ return ret;
+}
+
+void target_load_ssd_keystore(void)
+{
+ uint64_t ptn;
+ int index;
+ uint64_t size;
+ uint32_t *buffer = NULL;
+
+ if (!target_is_ssd_enabled())
+ return;
+
+ index = partition_get_index("ssd");
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0){
+ dprintf(CRITICAL, "Error: ssd partition not found\n");
+ return;
+ }
+
+ size = partition_get_size(index);
+ if (size == 0) {
+ dprintf(CRITICAL, "Error: invalid ssd partition size\n");
+ return;
+ }
+
+ buffer = memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
+ if (!buffer) {
+ dprintf(CRITICAL, "Error: allocating memory for ssd buffer\n");
+ return;
+ }
+ if (mmc_read(ptn, buffer, size)) {
+ dprintf(CRITICAL, "Error: cannot read data\n");
+ free(buffer);
+ return;
+ }
+
+ clock_ce_enable(CE1_INSTANCE);
+ scm_protect_keystore(buffer, size);
+ clock_ce_disable(CE1_INSTANCE);
+ free(buffer);
+}
+
+crypto_engine_type board_ce_type(void)
+{
+ return CRYPTO_ENGINE_TYPE_HW;
+}
+
+/* Set up params for h/w CE. */
+void target_crypto_init_params()
+{
+ struct crypto_init_params ce_params;
+
+ /* Set up base addresses and instance. */
+ ce_params.crypto_instance = CE1_INSTANCE;
+ ce_params.crypto_base = MSM_CE1_BASE;
+ ce_params.bam_base = MSM_CE1_BAM_BASE;
+
+ /* Set up BAM config. */
+ ce_params.bam_ee = CE_EE;
+ ce_params.pipes.read_pipe = CE_READ_PIPE;
+ ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
+
+ /* Assign buffer sizes. */
+ ce_params.num_ce = CE_ARRAY_SIZE;
+ ce_params.read_fifo_size = CE_FIFO_SIZE;
+ ce_params.write_fifo_size = CE_FIFO_SIZE;
+
+ /* BAM is initialized by TZ for this platform.
+ * Do not do it again as the initialization address space
+ * is locked.
+ */
+ ce_params.do_bam_init = 0;
+
+ crypto_init_params(&ce_params);
+}
+
+uint32_t target_get_hlos_subtype()
+{
+ return board_hlos_subtype();
+}
diff --git a/target/msm8909/oem_panel.c b/target/msm8909/oem_panel.c
new file mode 100644
index 0000000..b18c74a
--- /dev/null
+++ b/target/msm8909/oem_panel.c
@@ -0,0 +1,168 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+#include <target/display.h>
+#include "include/panel.h"
+#include "panel_display.h"
+
+#include "include/panel_hx8394d_720p_video.h"
+
+#define DISPLAY_MAX_PANEL_DETECTION 0
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+static uint32_t auto_pan_loop = 0;
+
+enum {
+ HX8394D_720P_VIDEO_PANEL,
+ UNKNOWN_PANEL
+};
+
+/*
+ * The list of panels that are supported on this target.
+ * Any panel in this list can be selected using fastboot oem command.
+ */
+static struct panel_list supp_panels[] = {
+ {"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL}
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ return NO_ERROR;
+}
+
+int oem_panel_on()
+{
+ /*
+ * OEM can keep there panel specific on instructions in this
+ * function
+ */
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /*
+ * OEM can keep their panel specific off instructions
+ * in this function
+ */
+ return NO_ERROR;
+}
+
+static int init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ int pan_type = PANEL_TYPE_DSI;
+
+ switch (panel_id) {
+ case HX8394D_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8394d_720p_video_panel_data;
+ panelstruct->panelres = &hx8394d_720p_video_panel_res;
+ panelstruct->color = &hx8394d_720p_video_color;
+ panelstruct->videopanel = &hx8394d_720p_video_video_panel;
+ panelstruct->commandpanel = &hx8394d_720p_video_command_panel;
+ panelstruct->state = &hx8394d_720p_video_state;
+ panelstruct->laneconfig = &hx8394d_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8394d_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8394d_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &hx8394d_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = hx8394d_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = HX8394D_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ hx8394d_720p_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = HX8394D_720P_VIDEO_SIGNATURE;
+ break;
+ case UNKNOWN_PANEL:
+ default:
+ memset(panelstruct, 0, sizeof(struct panel_struct));
+ memset(pinfo->mipi.panel_cmds, 0, sizeof(struct mipi_dsi_cmd));
+ pinfo->mipi.num_of_panel_cmds = 0;
+ memset(phy_db->timing, 0, TIMING_SIZE);
+ pan_type = PANEL_TYPE_UNKNOWN;
+ break;
+ }
+ return pan_type;
+}
+
+uint32_t oem_panel_max_auto_detect_panels()
+{
+ return target_panel_auto_detect_enabled() ?
+ DISPLAY_MAX_PANEL_DETECTION : 0;
+}
+
+int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ int32_t panel_override_id;
+
+ if (panel_name) {
+ panel_override_id = panel_name_to_id(supp_panels,
+ ARRAY_SIZE(supp_panels), panel_name);
+
+ if (panel_override_id < 0) {
+ dprintf(CRITICAL, "Not able to search the panel:%s\n",
+ panel_name + strspn(panel_name, " "));
+ } else if (panel_override_id < UNKNOWN_PANEL) {
+ /* panel override using fastboot oem command */
+ panel_id = panel_override_id;
+
+ dprintf(INFO, "OEM panel override:%s\n",
+ panel_name + strspn(panel_name, " "));
+ goto panel_init;
+ }
+ }
+ switch (hw_id) {
+ case HW_PLATFORM_SURF:
+ panel_id = HX8394D_720P_VIDEO_PANEL;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n",
+ hw_id);
+ return PANEL_TYPE_UNKNOWN;
+ }
+
+panel_init:
+ return init_panel_data(panelstruct, pinfo, phy_db);
+}
diff --git a/target/msm8909/rules.mk b/target/msm8909/rules.mk
index 9b6f73b..58d841a 100644
--- a/target/msm8909/rules.mk
+++ b/target/msm8909/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8909
@@ -10,10 +11,15 @@
BASE_ADDR := 0x80000000
SCRATCH_ADDR := 0x90000000
+DEFINES += DISPLAY_SPLASH_SCREEN=0
+DEFINES += DISPLAY_TYPE_MIPI=1
+DEFINES += DISPLAY_TYPE_DSI6G=1
+
MODULES += \
dev/keys \
dev/vib \
lib/ptable \
+ dev/gcdb/display \
dev/pmic/pm8x41 \
lib/libfdt
@@ -26,4 +32,6 @@
OBJS += \
$(LOCAL_DIR)/init.o \
- $(LOCAL_DIR)/meminfo.o
+ $(LOCAL_DIR)/meminfo.o \
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8909/target_display.c b/target/msm8909/target_display.c
new file mode 100755
index 0000000..338c5da
--- /dev/null
+++ b/target/msm8909/target_display.c
@@ -0,0 +1,249 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <smem.h>
+#include <err.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <pm8x41.h>
+#include <board.h>
+#include <mdp3.h>
+#include <scm.h>
+#include <platform/gpio.h>
+#include <platform/iomap.h>
+#include <target/display.h>
+
+#include "include/panel.h"
+#include "include/display_resource.h"
+
+#define VCO_DELAY_USEC 1000
+#define GPIO_STATE_LOW 0
+#define GPIO_STATE_HIGH 2
+#define RESET_GPIO_SEQ_LEN 3
+#define PWM_DUTY_US 13
+#define PWM_PERIOD_US 27
+
+static void mdss_dsi_uniphy_pll_sw_reset_8909(uint32_t pll_base)
+{
+ writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
+ mdelay(1);
+ writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
+ mdelay(1);
+}
+
+static uint32_t dsi_pll_enable_seq_8909(uint32_t pll_base)
+{
+ uint32_t pll_locked = 0;
+
+ writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
+ udelay(1);
+ writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x34, pll_base + 0x0070); /* CAL CFG1*/
+ udelay(1);
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
+ udelay(1);
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ udelay(1);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(1);
+
+ writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */
+ udelay(1);
+ writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
+ udelay(512);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
+
+ return pll_locked;
+}
+
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
+{
+ struct pm8x41_mpp mpp;
+ int rc;
+
+ if (bl->bl_interface_type == BL_DCS)
+ return 0;
+
+ mpp.base = PM8x41_MMP4_BASE;
+ mpp.vin = MPP_VIN0;
+ if (enable) {
+ pm_pwm_enable(false);
+ rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
+ if (rc < 0)
+ mpp.mode = MPP_HIGH;
+ else {
+ mpp.mode = MPP_DTEST1;
+ pm_pwm_enable(true);
+ }
+ pm8x41_config_output_mpp(&mpp);
+ pm8x41_enable_mpp(&mpp, MPP_ENABLE);
+ } else {
+ pm_pwm_enable(false);
+ pm8x41_enable_mpp(&mpp, MPP_DISABLE);
+ }
+ mdelay(20);
+ return 0;
+}
+
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ int32_t ret = 0;
+ struct mdss_dsi_pll_config *pll_data;
+ dprintf(SPEW, "target_panel_clock\n");
+
+ pll_data = pinfo->mipi.dsi_pll_config;
+ pll_data->vco_delay = VCO_DELAY_USEC;
+
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mdss_bus_clocks_enable();
+ mdp_clock_enable();
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ mdp_clock_disable();
+ mdss_bus_clocks_disable();
+ mdp_gdsc_ctrl(0);
+ return ret;
+ }
+ mdss_dsi_uniphy_pll_sw_reset_8909(DSI0_PLL_BASE);
+ mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
+ MIPI_DSI0_BASE, pll_data);
+ if (!dsi_pll_enable_seq_8909(DSI0_PLL_BASE))
+ dprintf(CRITICAL, "Not able to enable the pll\n");
+ gcc_dsi_clocks_enable(pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
+ } else if(!target_cont_splash_screen()) {
+ gcc_dsi_clocks_disable();
+ mdp_clock_disable();
+ mdss_bus_clocks_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return 0;
+}
+
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ uint32_t hw_id = board_hardware_id();
+ uint32_t hw_subtype = board_hardware_subtype();
+
+ if (enable) {
+ if (pinfo->mipi.use_enable_gpio) {
+ gpio_tlmm_config(enable_gpio.pin_id, 0,
+ enable_gpio.pin_direction, enable_gpio.pin_pull,
+ enable_gpio.pin_strength,
+ enable_gpio.pin_state);
+
+ gpio_set_dir(enable_gpio.pin_id, 2);
+ }
+
+ if (hw_id == HW_PLATFORM_SURF) {
+ /* configure backlight gpio for CDP */
+ gpio_tlmm_config(bkl_gpio.pin_id, 0,
+ bkl_gpio.pin_direction, bkl_gpio.pin_pull,
+ bkl_gpio.pin_strength, bkl_gpio.pin_state);
+ gpio_set_dir(bkl_gpio.pin_id, 2);
+ }
+
+ gpio_tlmm_config(reset_gpio.pin_id, 0,
+ reset_gpio.pin_direction, reset_gpio.pin_pull,
+ reset_gpio.pin_strength, reset_gpio.pin_state);
+
+ gpio_set_dir(reset_gpio.pin_id, 2);
+
+ /* reset */
+ for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
+ if (resetseq->pin_state[i] == GPIO_STATE_LOW)
+ gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW);
+ else
+ gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH);
+ mdelay(resetseq->sleep[i]);
+ }
+ } else if(!target_cont_splash_screen()) {
+ gpio_set_dir(reset_gpio.pin_id, 0);
+ if (pinfo->mipi.use_enable_gpio)
+ gpio_set_dir(enable_gpio.pin_id, 0);
+ }
+
+ return ret;
+}
+
+int target_ldo_ctrl(uint8_t enable)
+{
+ /*
+ * The PMIC regulators needed for display are enabled in SBL.
+ * There is no access to the regulators is LK.
+ */
+ return NO_ERROR;
+}
+
+bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
+{
+ return gcdb_display_cmdline_arg(pbuf, buf_size);
+}
+
+void target_display_init(const char *panel_name)
+{
+ uint32_t panel_loop = 0;
+ uint32_t ret = 0;
+
+ if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
+ dprintf(INFO, "Skip panel configuration\n");
+ return;
+ }
+
+ do {
+ target_force_cont_splash_disable(false);
+ ret = gcdb_display_init(panel_name, MDP_REV_305, MIPI_FB_ADDR);
+ if (!ret || ret == ERR_NOT_SUPPORTED) {
+ break;
+ } else {
+ target_force_cont_splash_disable(true);
+ msm_display_off();
+ }
+ } while (++panel_loop <= oem_panel_max_auto_detect_panels());
+}
+
+void target_display_shutdown(void)
+{
+ gcdb_display_shutdown();
+}
diff --git a/target/msm8916/include/target/display.h b/target/msm8916/include/target/display.h
old mode 100644
new mode 100755
index 0faf033..d904966
--- a/target/msm8916/include/target/display.h
+++ b/target/msm8916/include/target/display.h
@@ -77,6 +77,10 @@
"msmgpio", 98, 3, 1, 0, 1
};
+static struct gpio_pin enable_gpio_skut1 = {
+ "msmgpio", 8, 3, 1, 0, 1
+};
+
/*---------------------------------------------------------------------------*/
/* Target Physical configuration */
/*---------------------------------------------------------------------------*/
@@ -126,6 +130,7 @@
HW_PLATFORM_SUBTYPE_SKUH = 4,
HW_PLATFORM_SUBTYPE_SKUI = 5, /* msm8916 */
HW_PLATFORM_SUBTYPE_SKUK = 5, /* msm8939 */
+ HW_PLATFORM_SUBTYPE_SKUT1 = 0x40, /* msm8916 */
};
#endif
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
old mode 100644
new mode 100755
index 25344d0..82bcdad
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -52,6 +52,7 @@
#include "include/panel_jdi_fhd_video.h"
#include "include/panel_hx8379a_fwvga_video.h"
#include "include/panel_hx8394d_720p_video.h"
+#include "include/panel_nt35521_wxga_video.h"
#define DISPLAY_MAX_PANEL_DETECTION 2
#define OTM8019A_FWVGA_VIDEO_PANEL_ON_DELAY 50
@@ -74,6 +75,7 @@
JDI_FHD_VIDEO_PANEL,
HX8379A_FWVGA_VIDEO_PANEL,
HX8394D_720P_VIDEO_PANEL,
+NT35521_WXGA_VIDEO_PANEL,
UNKNOWN_PANEL
};
@@ -92,7 +94,8 @@
{"sharp_wqxga_dualdsi_video",SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
{"jdi_fhd_video", JDI_FHD_VIDEO_PANEL},
{"hx8379a_wvga_video", HX8379A_FWVGA_VIDEO_PANEL},
- {"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL}
+ {"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL},
+ {"nt35521_wxga_video", NT35521_WXGA_VIDEO_PANEL}
};
static uint32_t panel_id;
@@ -359,6 +362,26 @@
hx8394d_720p_video_timings, TIMING_SIZE);
pinfo->mipi.signature = HX8394D_720P_VIDEO_SIGNATURE;
break;
+ case NT35521_WXGA_VIDEO_PANEL:
+ panelstruct->paneldata = &nt35521_wxga_video_panel_data;
+ panelstruct->panelres = &nt35521_wxga_video_panel_res;
+ panelstruct->color = &nt35521_wxga_video_color;
+ panelstruct->videopanel = &nt35521_wxga_video_video_panel;
+ panelstruct->commandpanel = &nt35521_wxga_video_command_panel;
+ panelstruct->state = &nt35521_wxga_video_state;
+ panelstruct->laneconfig = &nt35521_wxga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35521_wxga_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35521_wxga_video_reset_seq;
+ panelstruct->backlightinfo = &nt35521_wxga_video_backlight;
+ pinfo->mipi.panel_cmds
+ = nt35521_wxga_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = NT35521_WXGA_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ nt35521_wxga_video_timings, TIMING_SIZE);
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -448,10 +471,14 @@
break;
case HW_PLATFORM_SUBTYPE_SKUI:
/* qrd SKUIC */
- if ((plat_hw_ver_major >> 4) == 0x1)
- panel_id = HX8379A_FWVGA_VIDEO_PANEL;
- else
+ if ((plat_hw_ver_major >> 4) == 0)
panel_id = OTM8019A_FWVGA_VIDEO_PANEL;
+ else
+ panel_id = HX8379A_FWVGA_VIDEO_PANEL;
+ break;
+ case HW_PLATFORM_SUBTYPE_SKUT1:
+ /* qrd SKUT1 */
+ panel_id = NT35521_WXGA_VIDEO_PANEL;
break;
default:
dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
old mode 100644
new mode 100755
index 0cd12df..b47f1e0
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -293,6 +293,10 @@
if (enable) {
if (pinfo->mipi.use_enable_gpio) {
+ /* set enable gpio pin for SKUT1 */
+ if ((hw_id == HW_PLATFORM_QRD) &&
+ (hw_subtype == HW_PLATFORM_SUBTYPE_SKUT1))
+ enable_gpio = enable_gpio_skut1;
gpio_tlmm_config(enable_gpio.pin_id, 0,
enable_gpio.pin_direction, enable_gpio.pin_pull,
enable_gpio.pin_strength,
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 0780268..18c6ab9 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -76,6 +76,7 @@
#define FASTBOOT_MODE 0x77665500
#define PMIC_WLED_SLAVE_ID 3
+#define DDR_CFG_DLY_VAL 0x80040870
static void set_sdc_power_ctrl(uint8_t slot);
static uint32_t mmc_pwrctl_base[] =
@@ -182,6 +183,26 @@
{
}
+unsigned target_pause_for_battery_charge(void)
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+ uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /* In case of fastboot reboot,adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ return 1;
+ else
+ return 0;
+}
+
static void set_sdc_power_ctrl(uint8_t slot)
{
uint32_t reg = 0;
@@ -539,3 +560,8 @@
/* We are entering fastboot mode, so read partition table */
mmc_read_partition_table(1);
}
+
+uint32_t target_ddr_cfg_val()
+{
+ return DDR_CFG_DLY_VAL;
+}
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index edf1ceb..2463515 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -351,8 +351,6 @@
int target_display_pre_on()
{
- writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0);
- writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1);
writel(0xC0000CCC, MDP_CLK_CTRL0);
writel(0xC0000CCC, MDP_CLK_CTRL1);
writel(0x00CCCCCC, MDP_CLK_CTRL2);
diff --git a/target/msmzirc/init.c b/target/msmzirc/init.c
index a94ef0d..22e03df 100644
--- a/target/msmzirc/init.c
+++ b/target/msmzirc/init.c
@@ -75,6 +75,9 @@
#define LAST_NAND_PTN_LEN_PATTERN 0xFFFFFFFF
+#define EXT4_CMDLINE " rootfstype=ext4 root=/dev/mmcblk0p"
+#define UBI_CMDLINE " rootfstype=ubifs rootflags=bulk_read ubi.fm_autoconvert=1"
+
struct qpic_nand_init_config config;
void update_ptable_names(void)
@@ -111,7 +114,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(2, 0, BLSP1_UART1_BASE);
+ uart_dm_init(3, 0, BLSP1_UART2_BASE);
#endif
}
@@ -127,8 +130,6 @@
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
- platform_read_boot_config();
-
if (platform_boot_dev_isemmc()) {
target_sdc_init();
if (partition_read_table()) {
@@ -217,39 +218,45 @@
struct ptable *ptable;
int system_ptn_index = -1;
- if (!target_is_emmc_boot()) {
- if (!cmdline || !part || !buf || buflen < 0) {
- dprintf(CRITICAL, "WARN: Invalid input param\n");
- return -1;
- }
-
- ptable = flash_get_ptable();
- if (!ptable) {
- dprintf(CRITICAL,
- "WARN: Cannot get flash partition table\n");
- return -1;
- }
-
- system_ptn_index = ptable_get_index(ptable, part);
- if (system_ptn_index < 0) {
- dprintf(CRITICAL,
- "WARN: Cannot get partition index for %s\n", part);
- return -1;
- }
-
- /*
- * check if cmdline contains "root=" at the beginning of buffer or
- * " root=" in the middle of buffer.
- */
- if (((!strncmp(cmdline, "root=", strlen("root="))) ||
- (strstr(cmdline, " root="))))
- dprintf(DEBUG, "DEBUG: cmdline has root=\n");
- else
- snprintf(buf, buflen, " root=/dev/mtdblock%d",
- system_ptn_index);
+ if (!cmdline || !part || !buf || buflen < 0) {
+ dprintf(CRITICAL, "WARN: Invalid input param\n");
+ return -1;
}
- return 0;
+ if (!strstr(cmdline, "root=/dev/ram")) /* This check is to handle kdev boot */
+ {
+ if (!target_is_emmc_boot()) {
+ /* Below is for NAND boot */
+ ptable = flash_get_ptable();
+ if (!ptable) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get flash partition table\n");
+ return -1;
+ }
+
+ system_ptn_index = ptable_get_index(ptable, part);
+ if (system_ptn_index < 0) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get partition index for %s\n", part);
+ return -1;
+ }
+ /* Adding command line parameters according to target boot type */
+ snprintf(buf, buflen, UBI_CMDLINE);
+ snprintf(buf+strlen(buf), buflen, " root=ubi0:rootfs ubi.mtd=%d", system_ptn_index);
+ }
+ else {
+ /* Below is for emmc boot */
+ system_ptn_index = partition_get_index(part);
+ if (system_ptn_index < 0) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get partition index for %s\n", part);
+ return -1;
+ }
+ snprintf(buf, buflen, EXT4_CMDLINE"%d", system_ptn_index);
+ }
+
+ return 0;
+ }
}
const char * target_usb_controller()
@@ -301,6 +308,7 @@
config.pwrctl_base = MSM_SDC1_BASE;
config.pwr_irq = SDCC1_PWRCTL_IRQ;
config.hs400_support = 0;
+ config.use_io_switch = 1;
if (!(dev = mmc_init(&config))) {
dprintf(CRITICAL, "mmc init failed!");
@@ -319,8 +327,8 @@
void target_usb_phy_reset(void)
{
- qusb2_phy_reset();
usb30_qmp_phy_reset();
+ qusb2_phy_reset();
}
target_usb_iface_t* target_usb30_init()
@@ -338,3 +346,13 @@
return t_usb_iface;
}
+
+uint32_t target_override_pll()
+{
+ return 1;
+}
+
+uint32_t target_get_hlos_subtype()
+{
+ return board_hlos_subtype();
+}
diff --git a/target/msmzirc/keypad.c b/target/msmzirc/keypad.c
index 569ea66..11ba6e8 100644
--- a/target/msmzirc/keypad.c
+++ b/target/msmzirc/keypad.c
@@ -33,7 +33,7 @@
/* GPIO that controls the button
* for FASTBOOT.
*/
-#define FASTBOOT_KEY_GPIO_ID 17
+#define FASTBOOT_KEY_GPIO_ID 92
/*
* Returns fastboot button state.
diff --git a/target/msmzirc/meminfo.c b/target/msmzirc/meminfo.c
index 7516b42..d71630c 100644
--- a/target/msmzirc/meminfo.c
+++ b/target/msmzirc/meminfo.c
@@ -77,10 +77,10 @@
void *target_get_scratch_address(void)
{
- return ((void *) VA((addr_t)SCRATCH_REGION2));
+ return ((void *) VA((addr_t)SCRATCH_REGION1));
}
unsigned target_get_max_flash_size(void)
{
- return (SCRATCH_REGION2_SIZE);
+ return (SCRATCH_REGION1_SIZE);
}
diff --git a/target/msmzirc/rules.mk b/target/msmzirc/rules.mk
index c0831cc..7a19970 100644
--- a/target/msmzirc/rules.mk
+++ b/target/msmzirc/rules.mk
@@ -4,14 +4,17 @@
PLATFORM := msmzirc
-MEMBASE := 0x87C00000
+MEMBASE := 0x81200000
MEMSIZE := 0x00100000 # 1MB
BASE_ADDR := 0x80000000
SCRATCH_ADDR := 0x80000000
-SCRATCH_REGION1 := 0x80000000
-SCRATCH_REGION1_SIZE := 0x07C00000 # 124MB
+SCRATCH_REGION1 := 0x81300000
+SCRATCH_REGION1_SIZE := 0x06900000 # 105MB
SCRATCH_REGION2 := 0x88000000
SCRATCH_REGION2_SIZE := 0x08000000 # 128MB
+KERNEL_REGION := 0x80000000
+KERNEL_REGION_SIZE := 0x01200000 # 18MB
+
DEFINES += NO_KEYPAD_DRIVER=1
DEFINES += PERIPH_BLK_BLSP=1
@@ -31,6 +34,9 @@
MEMSIZE=$(MEMSIZE) \
SCRATCH_REGION1_SIZE=$(SCRATCH_REGION1_SIZE) \
SCRATCH_REGION2_SIZE=$(SCRATCH_REGION2_SIZE) \
+ KERNEL_REGION=$(KERNEL_REGION) \
+ KERNEL_REGION_SIZE=$(KERNEL_REGION_SIZE) \
+
OBJS += \
$(LOCAL_DIR)/init.o \